JP2005268438A - Field effect transistor and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor and its manufacturing method for simplifying circuit configurations, and for reducing the chip size. <P>SOLUTION: In this vertical field effect transistor laminated in its thickness direction, at least either an NOR circuit or an NAND circuit among logical circuits is realized according to the arrangement positions of a semiconductor layer and a gate electrode 4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof, and relates to a technique applied to a vertical field effect transistor.

  BACKGROUND ART Field effect transistors (abbreviated as MOSFETs) have been conventionally developed on a semiconductor substrate on a flat surface by using photolithography technology, enabling mass production, and have achieved great development as an industry. Also, the size of the MOSFET itself has been reduced by increasing the integration of the MOSFET.

  In recent years, a technique for making a MOSFET a vertical type has been proposed (see, for example, Patent Documents 1 and 2). Patent Document 1 discloses a technique for producing a C-MOS inverter logic using a vertical MOSFET. FIG. 9 is a cross-sectional view of a conventional vertical field effect transistor. The vertical MOSFET of Patent Document 2 includes a semiconductor substrate 60, an N-type diffusion layer 61, a gate electrode 62, a P-type semiconductor layer 63, and a drain electrode 62. With this configuration, a NAND circuit can be realized.

JP-A-6-21467 JP-A-10-93083

  In the conventional MOSFET, the leakage current between the drain and source electrodes increases as the MOSFET size is reduced. Further, when the C-MOS circuit is developed on a plane, it is necessary to produce and arrange an N-type MOSFET and a P-type MOSFET that operate with different power sources. Therefore, since the well structure and the like become complicated, the process becomes long and the yield decreases.

  The technology of Patent Document 1 merely discloses a vertical MOSFET, and does not disclose or suggest a NAND circuit and a NOR circuit that are basic logic circuits. In other words, none of the techniques of Patent Document 1 corresponds to a configuration for realizing a logic circuit.

  In the technique of Patent Document 2, although the structure of the NAND circuit is disclosed, the NOR circuit is not disclosed or suggested. According to such a circuit configuration, all circuit configurations can be realized using the Domorgan rule, but there are the following problems. In other words, when an integrated circuit using a vertical MOSFET is manufactured, one logic circuit can be realized by one vertical transistor. Therefore, when a logic circuit is developed using a NAND circuit and the Domorgan rule, the number of circuits is reduced. To increase. That is, since the number of vertical transistors increases, the circuit scale increases. Therefore, the chip size increases.

  An object of the present invention is to provide a field effect transistor and a manufacturing method thereof that can simplify a circuit structure and reduce a chip size.

The present invention provides a columnar semiconductor layer in which semiconductor layers of different conductivity types are stacked in the thickness direction of a semiconductor substrate;
A plurality of gate electrodes disposed on the side wall of the columnar semiconductor layer,
The columnar semiconductor layer and the plurality of gate electrodes form a stacked body stacked in the thickness direction.

  According to the present invention, semiconductor layers having different conductivity types are stacked on the columnar semiconductor layer in the thickness direction of the semiconductor substrate. A plurality of gate electrodes are disposed on the side wall of the columnar semiconductor layer. These columnar semiconductor layers and the plurality of gate electrodes form a stacked body that is stacked in the thickness direction.

  In the invention, it is preferable that the gate electrode is electrically arranged between the source electrode and the drain electrode in parallel.

  According to the present invention, since the source and drain electrodes are electrically arranged in parallel, a NOR circuit among the logic circuits can be realized.

  In the invention, it is preferable that the gate electrode is electrically arranged in series between the source electrode and the drain electrode.

  According to the present invention, since the source and drain electrodes are electrically arranged in series, a NAND circuit among the logic circuits can be realized.

  According to the present invention, among the field effect transistors, a gate electrode of an N-channel field effect transistor and a gate electrode of a P-channel field effect transistor are electrically connected, and a drain electrode of the N-channel field effect transistor. And a C-MOS type logic device in which a drain electrode of a P-channel field effect transistor is electrically connected.

  According to the present invention, the gate electrode of the N-channel field effect transistor and the gate electrode of the P-channel field effect transistor are electrically connected. In addition, the drain electrode of the N-channel field effect transistor and the drain electrode of the P-channel field effect transistor are electrically connected. In this way, a C-MOS type logic device can be realized.

The present invention also includes a first step of forming a diffusion layer on a semiconductor substrate,
After the first step, a second step of epitaxially growing the semiconductor layer along the thickness direction of the semiconductor substrate;
And a third step of forming a gate insulating film on the semiconductor substrate and the epitaxially grown semiconductor layer and then patterning the gate electrode.

  According to the present invention, in the first step, a diffusion layer is formed on the semiconductor substrate. In the second step after the first step, the semiconductor layer is epitaxially grown along the thickness direction of the semiconductor substrate. In the third step, a gate insulating film is formed on the semiconductor substrate and the epitaxially grown semiconductor layer, and then the gate electrode is patterned.

The present invention also includes a fourth step of forming an insulator layer on the patterned gate electrode and further epitaxially growing a semiconductor layer along the thickness direction,
A fifth step of removing a layer facing the gate insulating film and the insulator layer from the epitaxially grown layer epitaxially grown in the fourth step;
A sixth step of forming a gate insulating film on the gate insulating film, the insulator layer, and the epitaxial growth layer, and then forming a contact for conducting electrical connection between the gate electrode patterned in the third step and another gate electrode When,
And a seventh step of forming another gate electrode.

  According to the present invention, in the fourth step, an insulator layer is formed on the patterned gate electrode, and the semiconductor layer is further epitaxially grown. In the fifth step, the layers facing the gate insulating film and the insulator layer are removed from the epitaxial growth layer. In the sixth step, a gate insulating film is formed on the gate insulating film, the insulator layer, and the epitaxial growth layer, and then a contact is formed. In the seventh step, another gate electrode is formed.

  According to the present invention, semiconductor layers having different conductivity types are stacked on the columnar semiconductor layer in the thickness direction of the semiconductor substrate. A plurality of gate electrodes are disposed on the side wall of the columnar semiconductor layer. These columnar semiconductor layers and the plurality of gate electrodes form a stacked body that is stacked in the thickness direction. Such a configuration provides the following effects. That is, by providing a plurality of gate electrodes on the side wall of the columnar semiconductor layer, the source and drain electrodes of the columnar semiconductor layer can be arranged in parallel. By stacking the columnar semiconductor layer and the plurality of gate electrodes in the thickness direction, the source and drain electrodes can be arranged in series.

  Therefore, in the vertical field effect transistor stacked in the thickness direction, it is possible to realize at least one of the NOR circuit and the NAND circuit among the logic circuits depending on the arrangement position of the semiconductor layer and the gate electrode. In other words, a vertical field effect transistor can be selectively used as a NOR circuit or a NAND circuit depending on how the gate electrodes are connected. Therefore, not only all logic circuits can be realized, but also the circuit structure can be simplified and the circuit scale can be reduced as compared with the prior art. As a result, the chip size can be reduced.

  Further, according to the present invention, the source and drain electrodes are electrically arranged in parallel, so that a NOR circuit among the logic circuits can be realized.

  Further, according to the present invention, since the source and drain electrodes are arranged in series electrically, a NAND circuit among the logic circuits can be realized.

  According to the present invention, the gate electrode of the N-channel field effect transistor and the gate electrode of the P-channel field effect transistor are electrically connected. In addition, the drain electrode of the N-channel field effect transistor and the drain electrode of the P-channel field effect transistor are electrically connected. In this way, a C-MOS type logic device can be realized. Therefore, in the state of the semiconductor substrate, since only one power source exists, a short circuit between power sources due to well insulation failure can be eliminated. Furthermore, since there is no parasitic thyristor due to the well, problems such as latch-up can be solved.

  According to the invention, after the diffusion layer is formed on the semiconductor substrate in the first step, the semiconductor layer is epitaxially grown along the thickness direction of the semiconductor substrate in the second step. In the third step, a gate insulating film is formed on the semiconductor substrate and the epitaxially grown semiconductor layer, and then the gate electrode is patterned. In this way, it is possible to define the arrangement positions of the semiconductor layer and the gate electrode. In other words, the vertical field effect transistor can be selectively used as one of the logic circuits depending on how the gate electrodes are connected. Therefore, not only can the logic circuit be realized, but also the circuit structure can be simplified and the circuit scale can be reduced as compared with the prior art.

  According to the invention, in the fourth step, an insulator layer is formed on the patterned gate electrode, and the semiconductor layer is further epitaxially grown. In the fifth step, the layers facing the gate insulating film and the insulator layer are removed from the epitaxial growth layer. In the sixth step, a gate insulating film is formed on the gate insulating film, the insulator layer, and the epitaxial growth layer, and then a contact is formed. In the seventh step, another gate electrode is formed. By defining the arrangement position of the gate electrode in this manner, the vertical field effect transistor can be selectively used as one of the logic circuits.

  FIG. 1 is a perspective view schematically showing a vertical field effect transistor 1 according to an embodiment of the present invention. A vertical field effect transistor 1 (abbreviation: vertical MOSFET) includes a semiconductor substrate 2, a columnar body 3 formed by epitaxial growth, a gate electrode 4, a channel 5, a gate oxide film and an interlayer insulating film not shown. A semiconductor substrate 2 is placed and supported, and a pillar 3 that is a stacked body is erected on one surface portion of the semiconductor substrate 2. The column 3 is synonymous with a “vertical MOSFET column” described later. The column 3 is a hexahedron and is formed so as to extend substantially perpendicular to the one surface portion. The “substantially vertical” direction includes a vertical direction. Hereinafter, the extending direction of the column 3 is defined as the z direction, the direction parallel to one side of the column 3 is defined as the x direction, and the direction parallel to the other side of the column 3 is defined as the y direction. The z direction may be referred to as the vertical direction.

  In the column 3, channels 5 are formed at regular intervals in the z direction. Gate electrodes 4 protrude from the four side surfaces of the column 3 and the four side surfaces covering the channel layer. In addition, four gate electrodes 4 are arranged at the same stage in the z direction of the column 3, and four gate electrodes 4 (that is, a total of 16 gate electrodes 4) along the z direction of the column 3. ) Is arranged. In this way, the number of gate electrodes formed at each stage of the column 3 is configured to match the number of stages at which the gate electrode 4 is disposed.

  In the present embodiment, the gate electrodes 4 are arranged on all the side surfaces of the column 3, but the present invention is not necessarily limited to this configuration. One gate electrode 4 is disposed on one side surface covering one channel layer, but the configuration is not necessarily limited to this. For example, a plurality of gate electrodes 4 may be arranged on one side surface covering one channel layer.

  By a process for manufacturing the vertical MOSFET 1 described later, for example, a two-input NAND circuit can be realized with the transistor portion using two gate electrodes 4a and 4b adjacent in the z direction as logic circuit inputs. Further, using two gate electrodes 4a and 4c adjacent in the x and y directions as logic circuit inputs, a two-input NOR circuit can be realized by the transistor portion.

  FIG. 2 is a perspective view showing an example of a gate electrode connection method in the case of configuring a NAND circuit. FIG. 3 is a perspective view showing an example of a gate electrode connection method when a NOR circuit is configured. Here, a method for forming the same column 3 into a NAND circuit and a NOR circuit in cooperation with the gate electrode 4 will be schematically described. However, the same members as those of the vertical MOSFET 1 are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 2, for example, when configuring a NAND circuit, all the gate electrodes constituting the NOR circuit are connected in one stage 4A in the same stage, that is, the same stage in the z direction. Also in each stage, all the gate electrodes constituting the NOR circuit are connected in the same manner as described above to provide one input 4B (4C, 4D). With such a configuration, the input of the NAND circuit can be realized.

  As shown in FIG. 3, for example, when configuring a NOR circuit, all gate electrodes formed on the same side surface portion of the column 3 are connected. Thereby, gate connections 4α and 4β of different systems can be realized. The input of the NOR circuit can be realized by the gate electrodes adjacent to each other in the x and y directions and different types of gate electrodes. In the present embodiment, the gate electrodes formed on the same side surface portion are selected and connected, but the present invention is not necessarily limited to this configuration. For example, it is possible to select and connect gate electrodes formed on different side surfaces.

  FIG. 4 is a flowchart showing a method for manufacturing a vertical field effect transistor according to this embodiment. This flow is started at step s0, and a diffusion layer is formed at step s1. Next, it transfers to step s2 and makes a semiconductor layer grow epitaxially. Next, in step s3, a gate insulating film is formed on the semiconductor substrate and the epitaxially grown semiconductor layer, and then the gate electrode is patterned. Next, the process proceeds to step s4, and the layers facing the gate insulating film and the insulator layer are removed from the epitaxially grown epitaxially grown layers. Thereafter, the process proceeds to step s5. In step s5, a gate insulating film is formed on the gate insulating film, the insulator layer, and the epitaxial growth layer, and then a contact for establishing electrical connection between the gate electrode patterned in step s3 and another gate electrode is formed. . Thereafter, in step s7, another gate electrode is formed.

5, FIG. 6 and FIG. 7 are diagrams for explaining the formation process of the vertical field effect transistor step by step in detail. In the present embodiment, for example, a semiconductor type in the case of an N-channel MOSFET is applied. As shown in FIG. 5A, first, an N-type diffusion layer 6 for supplying power (or ground) is formed on a P-type semiconductor substrate 2 by using, for example, a thermal diffusion method or an ion implantation method. Next, as shown in FIG. 5B, an epitaxial semiconductor film is formed in accordance with the underlying crystal orientation. That is, the N ⁺ semiconductor layer of the source electrode 7, the P ⁻ semiconductor layer of the channel 5, and the N ⁺ semiconductor layer of the drain electrode 8 are epitaxially grown in this order. The z-direction thickness of the P ⁻ semiconductor layer serving as the channel 5 corresponds to a so-called gate length (also referred to as channel length). An epitaxial film of 400 nm was formed as the N ⁺ semiconductor layer of the source electrode 7, 200 nm was formed as the P ⁻ semiconductor layer of the channel 5, and 250 nm was formed as the N ⁺ semiconductor layer of the drain electrode 8. Thus, the epitaxial growth for one stage of the vertical MOSFET 1 can be performed.

Next, as shown in FIG. 5 (3), the epitaxially grown epitaxially grown layer is finely processed into a columnar shape. Specifically, a resist mask is formed using photolithography, and finely processed using an etching method with strong anisotropy such as reactive anisotropic etching (abbreviation RIE). A parallel plate RIE using SF ₆ and O ₂ gas was used. Thereafter, a gate insulating film 9 is formed on the columnar epitaxial growth layer and the semiconductor substrate 2 as shown in FIG. The gate insulating film 9 is selected from a process capable of isotropically forming, for example, chemical vapor deposition (abbreviated as CVD). In this embodiment, the gate insulating film 9 is formed using a plasma CVD apparatus using tetraethyl orthosilicate (abbreviated as TEOS).

Next, as shown in FIG. 5 (5), the SiO ₂ film 10 and the polysilicon film 11 are formed by, eg, sputtering. A physical deposition method other than the sputtering method may be applied. By applying a physical deposition method including such a sputtering method, the SiO ₂ film 10 and the polysilicon film 11 can be sequentially deposited in a bottom-up manner. Therefore, a film can be formed so as to fill the recess 12. By interposing the SiO ₂ film 10, the height in the z direction between the channel layer and the polysilicon layer can be matched, and stray capacitance formed between one end in the z direction, that is, the lower power supply layer can be reduced. In the case of a MOSFET, the accuracy required for alignment between the channel layer and the gate electrode 4 is not high, so that the film is formed by controlling only the deposition rate of sputtering. The polysilicon film 11 of the gate electrode 4 is formed slightly thicker than the channel layer so as to completely cover the channel layer.

  Next, as shown in FIG. 6A, the gate electrode 4 is patterned by fine processing. Specifically, a resist mask is formed using photolithography and processed by a highly anisotropic etching method such as RIE. At this time, the gate electrode 4 is divided into a plurality of parts for forming a NOR circuit. The part to be a NAND circuit is left surrounding the columnar epitaxial growth film and only separated from the adjacent gate electrode 4.

Thereafter, as shown in FIG. 6B, the periphery of the patterned gate electrode 4 and the periphery of the gate electrode 4 facing outward is filled with an insulator 13. Thereby, the gate electrode 4 is separated. Specifically, first, the resist mask of the gate electrode 4 is left, and SiO ₂ is sputtered to fill the periphery of the gate electrode 4. Next, the resist mask is removed, and SiO ₂ is sputtered on one surface portion in the z direction, that is, the entire surface. Thereafter, SiO ₂ deposited on one surface portion in the z direction of the epitaxial layer is removed by etching.

  Next, as shown in FIG. 6C, a semiconductor layer for the next-stage MOSFET is epitaxially grown. That is, an epitaxial film 14 having a uniform crystal structure is formed on one side of the columnar semiconductor layer in the z direction. On the other hand, since the crystal structure is different on the oxide film, it grows as a polysilicon film 15 with a disordered crystal structure on one side in the z direction of the oxide film. The film thicknesses of the polysilicon films 15 are sequentially defined as 250 nm, 200 nm, and 250 nm from the base end in the z direction toward one side in the z direction. The transistor formed in the vertical direction, that is, the z direction is defined such that the drain electrode region is 500 nm with respect to the channel region of 200 nm. Thus, by forming the drain electrode region thick in the z direction with respect to the channel region, the operation of the NOR-connected transistor formed in the same stage of the vertical transistor column can be stabilized.

  Thereafter, as shown in FIG. 6D, the polysilicon film 15 having a disordered crystal structure is removed by etching. That is, a resist mask is formed using photolithography, and the polysilicon film 15 is removed by etching using a highly anisotropic etching method such as RIE. Next, as shown in FIG. 7A, a gate insulating film 16 is formed on the columnar epitaxial growth layer 14 and the insulator 13. The gate insulating film 16 is selected from a process capable of isotropically forming, for example, chemical vapor deposition (abbreviated as CVD). In this embodiment, the gate insulating film 16 is formed using tetraethylorthosilicate (abbreviated as TEOS) using a plasma CVD apparatus.

  Thereafter, as shown in FIG. 7B, a contact 17 with another gate electrode 4 is formed. That is, a resist mask is formed using photolithography, and the contact 17 is formed by a highly heterogeneous etching method such as RIE. Next, as shown in FIG. 7C, a polysilicon film which is the gate electrode 4 is formed by, for example, sputtering. That is, polysilicon is filled in the contact with the previously formed gate electrode 4, and the connection with the previously formed gate electrode 4 is simultaneously performed. A physical deposition method other than the sputtering method may be applied. Thereafter, the process shown in FIG. 6A is repeated to form a vertical MOSFET pillar on one surface of the semiconductor substrate.

  According to the vertical MOSFET 1 described above, the gate electrode 4 is patterned by microfabrication, particularly as shown in FIG. At this time, the gate electrode 4 is divided into a plurality of parts for forming a NOR circuit. A portion to be a NAND circuit is left surrounding the columnar epitaxial growth film 14 and only separated from the adjacent gate electrode 4. Therefore, in the vertical MOSFET 1, a NOR circuit and a NAND circuit among the logic circuits can be realized depending on the arrangement position of the semiconductor layer and the gate electrode 4. In other words, the vertical MOSFET 1 can be selectively used as a NOR circuit or a NAND circuit depending on how the gate electrodes 4 are connected. Therefore, not only all the logic circuits can be realized, but also the circuit structure can be simplified and the circuit scale can be reduced as compared with the prior art. As a result, the chip size can be reduced.

  The vertical MOSFET pillar 3 forms a hexahedron, and a gate electrode 4 is disposed on each side surface portion thereof. Since the cross-sectional shape of the vertical MOSFET pillar 3 forming the hexahedron cut by a virtual plane including the xy direction is rectangular, the following effects are obtained. That is, when the vertical MOSFET pillar 3 is disposed on the main surface of the semiconductor substrate, it can be efficiently disposed in a space. For example, when arranging a plurality of vertical MOSFET pillars 3 on the main surface of the semiconductor substrate, the distance between adjacent vertical MOSFET pillars 3 can be made as short as possible. In the present embodiment, a vertical MOSFET pillar having a hexahedron is applied, but the present invention is not necessarily limited to this form. For example, the vertical MOSFET pillar may be formed as a hexagonal pillar. Since the cross-sectional shape of the vertical MOSFET column formed on the hexagonal column cut by a virtual plane including the xy direction is a hexagonal shape, the vertical MOSFET column is formed on the main surface of the semiconductor substrate in the same manner as described above. Also when arrange | positioning, it can arrange | position efficiently in space.

  Further, according to the vertical MOSFET 1 according to the present embodiment, the number of gate electrodes formed at each stage in the z direction of the vertical MOSFET pillar 3 is made to coincide with the number of stages at which the gate electrode 4 is disposed. Therefore, the following effects are achieved. In the hexahedral vertical MOSFET pillar 3 having a rectangular cross-sectional shape, when one gate electrode 4 is formed on each of the four side surfaces, a 4-input NOR circuit is formed. At this time, by stacking four vertical MOSFETs 1 in the z direction, that is, in the vertical direction, four NAND circuits are configured. Therefore, by selecting a connection method of a total of 16 gate electrodes 4, a 4-input NOR circuit and a 4-input NAND circuit can be realized by the same vertical MOSFET pillar 3.

  8 shows a three-stage inverter according to an embodiment of the present invention, FIG. 8 (1) is a sectional view of a three-stage inverter circuit using a vertical field effect transistor, and FIG. 8 (2) is a three-stage inverter. It is the circuit diagram which made the inverter logic in series. The C-MOS type logic device according to this embodiment is configured by stacking vertical MOSFET pillars of different conductivity types formed on two semiconductor substrates. In FIG. 8, one vertical MOSFET column is a simplified view of two MOSFETs stacked. The C-MOS type logic device 20 has one and other vertical MOSFETs 21 and 22 and an interposer substrate 23. That is, one vertical MOSFET 21 is stacked on the other vertical MOSFET 22 via the interposer substrate 23. This stacking direction will be described below as the z direction.

  One vertical MOSFET 21 has an N-type semiconductor substrate 24, a P-channel vertical MOSFET pillar 25, and a gate electrode 26. A P-type diffusion layer 27 is formed on the surface portion on one side in the z direction of the N-type semiconductor substrate 24. The P-type diffusion layer 27 is formed using, for example, a thermal diffusion method or an ion implantation method. On one side in the z direction of the N-type semiconductor substrate 24, an epitaxially grown semiconductor layer, that is, a vertical MOSFET pillar 25 is formed. A gate electrode 26 is formed along the side surface of the vertical MOSFET pillar 25.

  The other vertical MOSFET 22 includes a P-type semiconductor substrate 28, an N-channel vertical MOSFET pillar 29, and a gate electrode 30. An N-type diffusion layer 31 is formed on the surface of the P-type semiconductor substrate 28 on the other side in the z direction. The N type diffusion layer 31 is formed using, for example, a thermal diffusion method or an ion implantation method. On the other side of the P-type semiconductor substrate 28 in the z direction, an epitaxially grown semiconductor layer, that is, a vertical MOSFET pillar 29 is formed. A gate electrode 30 is formed along the side surface of the vertical MOSFET pillar 29.

  On the interposer substrate 23, input and output terminals 32 and 33 of a three-stage inverter circuit, a connection terminal 34 between the inverters, and first and second wirings 35 and 36 are formed. Among these wirings, the first wiring 35 electrically connects the gate electrode 30 formed on the N-channel type vertical MOSFET column 29 and the gate electrode 26 formed on the P-channel type vertical MOSFET column 25. Has a function to connect. The second wiring 36 has a function of electrically connecting the drain electrode formed in the N-channel type vertical MOSFET column 29 and the drain electrode formed in the P-channel type vertical MOSFET column 25. In order to operate as an inverter, the gate electrodes 26 and 30 of all the vertical MOSFETs 21 and 22 of the N-channel type and the P-channel type are bundled as inputs. Furthermore, the portion where the drain electrodes of the N-channel type vertical MOSFET 21 and the P-channel type vertical MOSFET 22 are connected is the output.

  The interposer substrate 23 forms a metal film (Al) as a sacrificial layer on a silicon wafer, and then forms a copper polyimide multilayer film using a polyimide film. The polyimide uses a photosensitive polyimide material, and the contact between the layers is formed by exposing the polyimide to etching. For the Cu of the wiring, a lift-off method is used in which a pattern is formed by using a photoresist as a groove to form a groove, and when Cu is sputtered over the entire surface or when the resist is removed, excess Cu is removed at the same time. As a result, a 1 μm pitch Cu wiring substrate is formed and used as a wiring interposer, that is, an interposer substrate 23.

  For the connection, first, a wiring interposer 23 formed on a silicon wafer is connected to the semiconductor substrate 28 on which the N-channel MOSFET 22 is formed using a flip chip bonder, and the sacrificial layer is etched away. Next, the semiconductor substrate 24 on which the P-channel MOSFET 21 is formed and the N-channel semiconductor substrate 28 on which the wiring interposer 23 is mounted are connected. In any case, since silicon is used for the substrate, necessary and sufficient positioning accuracy at the time of connection can be obtained, and connection can be made with positioning accuracy of ± 0.5 μm or less by performing repeated pattern recognition. As the flip chip method, for example, a thermocompression bonding method is used.

  As described above, the vertical MOSFETs having different conductivity types are electrically connected by the first and second wirings 35 and 36 of the interposer substrate, thereby operating as a C-MOS logic circuit. When the above-described input terminal is part of a circuit for performing a desired operation, the input terminal is not connected from the outside but may be connected from another circuit. The output terminal may be connected to another circuit.

  Thus, a C-MOS type logic device is configured by connecting a semiconductor substrate on which an N-channel type vertical MOSFET is formed and a semiconductor substrate on which a P-channel type vertical MOSFET is formed via a wiring interposer. In this case, it is possible to eliminate a short circuit between power sources due to poor insulation of the well. Furthermore, since there is no parasitic thyristor due to the well, problems such as latch-up can be solved.

1 is a perspective view schematically showing a vertical field effect transistor 1 according to an embodiment of the present invention. It is a perspective view which shows an example of the contact method of the gate electrode in the case of comprising a NAND circuit. It is a perspective view which shows an example of the contact method of the gate electrode in the case of comprising a NOR circuit. 5 is a flowchart showing a method for manufacturing a vertical field effect transistor according to the embodiment. It is a figure explaining the formation process of a vertical field effect transistor in steps and in detail. It is a figure explaining the formation process of a vertical field effect transistor in steps and in detail. It is a figure explaining the formation process of a vertical field effect transistor in steps and in detail. FIG. 8A shows a three-stage inverter according to an embodiment of the present invention, FIG. 8A is a cross-sectional view of a three-stage inverter circuit using a vertical field effect transistor, and FIG. 8B is a series of three-stage inverter logic. FIG. It is sectional drawing of the conventional vertical field effect transistor.

Explanation of symbols

1 Vertical MOSFET
2 Semiconductor substrate 3 Vertical MOSFET pillar 4 Gate electrode 7 Source electrode 8 Drain electrode

Claims (6)

A columnar semiconductor layer in which semiconductor layers of different conductivity types are stacked in the thickness direction of the semiconductor substrate;
A plurality of gate electrodes disposed on the side wall of the columnar semiconductor layer,
A field effect transistor, characterized in that these columnar semiconductor layers and a plurality of gate electrodes form a laminated body laminated in the thickness direction.   The field effect transistor according to claim 1, wherein the gate electrode is electrically arranged in parallel between the source electrode and the drain electrode.   3. The field effect transistor according to claim 1, wherein the gate electrode is electrically arranged in series between the source electrode and the drain electrode.   Among the field effect transistors according to any one of claims 1 to 3, a gate electrode of an N-channel field effect transistor and a gate electrode of a P-channel field effect transistor are electrically connected, and the N-channel type A C-MOS type logic device formed by electrically connecting a drain electrode of a field effect transistor and a drain electrode of a P-channel type field effect transistor. A first step of forming a diffusion layer on a semiconductor substrate;
After the first step, a second step of epitaxially growing the semiconductor layer along the thickness direction of the semiconductor substrate;
And a third step of forming a gate insulating film on the semiconductor substrate and the epitaxially grown semiconductor layer, and then patterning the gate electrode. A fourth step of forming an insulator layer on the patterned gate electrode and further epitaxially growing a semiconductor layer along the thickness direction;
A fifth step of removing a layer facing the gate insulating film and the insulator layer from the epitaxially grown layer epitaxially grown in the fourth step;
A sixth step of forming a gate insulating film on the gate insulating film, the insulator layer, and the epitaxial growth layer, and then forming a contact for conducting electrical connection between the gate electrode patterned in the third step and another gate electrode When,
6. The method of manufacturing a field effect transistor according to claim 5, further comprising a seventh step of forming another gate electrode.

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