WO2018202097A1 - 一种编码方法及装置 - Google Patents

一种编码方法及装置 Download PDF

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Publication number
WO2018202097A1
WO2018202097A1 PCT/CN2018/085503 CN2018085503W WO2018202097A1 WO 2018202097 A1 WO2018202097 A1 WO 2018202097A1 CN 2018085503 W CN2018085503 W CN 2018085503W WO 2018202097 A1 WO2018202097 A1 WO 2018202097A1
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column
check
vector
bit
order
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PCT/CN2018/085503
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English (en)
French (fr)
Inventor
黄凌晨
张华滋
李榕
张公正
徐晨
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华为技术有限公司
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Priority to EP18794746.0A priority Critical patent/EP3614568B1/en
Publication of WO2018202097A1 publication Critical patent/WO2018202097A1/zh
Priority to US16/673,118 priority patent/US11063611B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to an encoding method and apparatus.
  • Cyclic Redundancy Check (CRC) coding is one of the most commonly used error checking codes in the field of data communication.
  • the feature of CRC coding is that the length of the information field and the check field can be arbitrarily selected. In communication systems, CRC coding is used to detect the correct transmission of data and to control the probability of occurrence of false alarms (English: False Alarm).
  • FIG. 1 shows a common way of shift register (referred to as register) to implement CRC encoding.
  • the feedback tap of the register is determined by the CRC polynomial [1 0 1 0 1], and the register contents are initialized to preset values.
  • the information to be encoded is shifted into the register bit by bit from side to side, and the feedback tap and the corresponding state of the register are subjected to bitwise exclusive OR operation, so that the state of the register changes.
  • the bit 0 of the number equal to the length of the CRC check is shifted, and then the register state is read, and the register state is used as the CRC check bit, which is attached to the information to be encoded as the CRC code code word. .
  • the transmitting end performs channel coding on the CRC code, and the receiving end performs corresponding channel decoding. After the channel decoding ends, the CRC check determines whether the decoding result is successfully decoded.
  • the embodiment of the present application provides an encoding method and device, which are used to solve the problem that the decoding process is complicated and wastes decoding resources by using the existing CRC encoding method.
  • an encoding method is provided.
  • the transmitting end interleaves the check bits of the information to be encoded into the information bits.
  • each parity bit is decoded, that is, Can be verified, if the verification does not pass, the decoding can be terminated early, which helps to avoid the problem of waste of decoding resources after the channel decoding is completed, shortening the time used for decoding, and improving the translation. The efficiency of the code.
  • the transmitting end performs check coding on the coded information to obtain a check codeword, where the check codeword includes information bits and check bits, and the length of the information bits is K, and the check bits are The length is J, the transmitting end performs an interleaving operation on the check codeword, wherein the interleaving sequence S used in the interleaving operation includes J subsequences, and the i th subsequence includes an intermediate result vector T i
  • V i is the column vector of the check partial matrix P
  • P is the sub-matrix of the matrix G of the check coding system form
  • ⁇ represents the bit-by-bit non-operation
  • & represents the bit-wise AND operation
  • - represents Bitwise operation;
  • the intermediate result vector T i can occupy a continuous storage space of the address.
  • the transmitting end acquires the interleaving sequence S in a dynamic computing manner or an offline storage manner. Specifically, before the transmitting end performs an interleaving operation on the encoded codeword, the interleaving sequence S is calculated; or the transmitting end calculates and stores the interleaving sequence S offline, and the encoding is performed at the transmitting end.
  • the transmitting end performs an interleaving operation on the encoded codeword according to the stored interleaving sequence S.
  • the order of values of i in the J subsequences may be in the order of i values from small to large, or in descending order of i values, or according to elements 1 of the column vector V i
  • the order of the numbers is from small to large, or in descending order of the number of elements 1 in the column vector V i .
  • an encoding method performs check encoding on the encoded information to obtain an encoded codeword, where the encoded codeword includes information bits and check bits, and the length of the information bits is K, and the length of the check bits
  • the transmitting end performs an interleaving operation on the encoded codeword
  • the transmitting end performs a Polar encoding on the check encoded codeword after the interleaving operation.
  • the interleaving sequence S used in the interleaving operation is obtained by calculating a generation matrix G of the check coding, extracting a parity part matrix P in the generation matrix G, and initializing the mask vector M and the intermediate result vector T.
  • T i and M are both 1 ⁇ K vectors.
  • the intermediate result vector T i can occupy a continuous storage space of the address.
  • the column vector V i of the check partial matrix is read column by column in a set order, by: reading the school column by column according to the order of the column index values from small to large column vector matrix V i posterior portion, or in the order of descending column index value, a column-by-column vector V i to read the check matrix portion.
  • an encoding method is provided.
  • the transmitting end stores the interleaving sequence S, and after receiving the information to be encoded, the transmitting end performs check and encoding on the information to be encoded, obtains an encoded codeword, and performs an interleaving operation on the encoded codeword by using the stored interleaving sequence S, where the sending The terminal performs Polar coding on the check codeword after the interleaving operation.
  • the receiving end uses the sequential decoding, the check bit can be verified every time the check bit is decoded, and if the check fails, the decoding can be terminated early, which helps to avoid the calibration after the channel decoding ends.
  • the test causes the problem of waste of decoding resources, shortens the time used for decoding, and improves the efficiency of decoding.
  • T i and M are both 1 ⁇ K vectors.
  • the intermediate result vector T i can occupy a continuous storage space of the address.
  • the column vector V i of the check partial matrix is read column by column in a set order, by: reading the school column by column according to the order of the column index values from small to large column vector matrix V i posterior portion, or in the order of descending column index value, a column-by-column vector V i to read the check matrix portion.
  • the check bit can be verified every time the check bit is decoded, and if the check fails, the decoding can be terminated early, which helps to avoid the calibration after the channel decoding ends.
  • the test causes the problem of waste of decoding resources, shortens the time used for decoding, and improves the efficiency of decoding.
  • the transmitting end reads the column vector V i of the check partial matrix P column by column in a set order, by implementing the following: the sending end is small to large according to the column index value.
  • the column vector V i of the check partial matrix is read column by column, or the transmitting end reads the column vector V i of the check partial matrix column by column in descending order of column index values.
  • the transmitting end reads the column vector V i of the check partial matrix column by column according to the order of the number of elements 1 in the column vector; or, the transmitting end follows the elements in the column vector
  • the order vector V i of the check partial matrix is read column by column in order of the number of ones.
  • a decoding method is provided.
  • the receiving end acquires a sequence to be decoded, and the receiving end performs a Polar code decoding on the sequence to be decoded, and performs a deinterleaving operation on the decoded sequence, assuming the length of the information bit.
  • the length of the check bit is J
  • the submatrices of the matrix G, ⁇ represents a bitwise bitwise operation, & represents a bitwise AND operation, and represents a bitwise OR operation.
  • T i and M are both 1 ⁇ K vectors.
  • the receiving end acquires the de-interleaving sequence S' in a dynamic calculation manner or an offline storage manner. Specifically, before the demodulating operation is performed on the decoded sequence, the receiving end calculates the deinterleaving sequence S′; or the receiving end calculates and stores the deinterleaving sequence S′ offline. When the receiving end performs the deinterleaving operation on the coded codeword, the receiving end performs a deinterleaving operation on the decoded sequence according to the stored deinterleaving sequence S'.
  • the order of values of i in the J subsequences may be in the order of i values from small to large, or in descending order of i values, or according to elements 1 of the column vector V i
  • the order of the numbers is from small to large, or in descending order of the number of elements 1 in the column vector V i .
  • a decoding method is provided.
  • the receiving end calculates the deinterleaving sequence S' offline by calculating a generation matrix G of the check coding, and extracting a parity part matrix P in the generation matrix G; an initialization mask.
  • the column vector V i of the check partial matrix is read column by column in a set order, by: reading the school column by column according to the order of the column index values from small to large column vector matrix V i posterior portion, or in the order of descending column index value, a column-by-column vector V i to read the check matrix portion.
  • an encoding apparatus having a function of implementing a sender behavior in any of the possible aspects of the first aspect and the first aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device comprises: an input interface circuit for acquiring information to be encoded; and a logic circuit for performing the first aspect and the first The behavior of the sender in any of the possible designs; the output interface circuit for outputting the Polar encoded bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the encoding device may implement the method as described in the first aspect and any of the possible designs of the first aspect.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • an encoding apparatus having a function of implementing a sender behavior in any of the possible aspects of the second aspect and the second aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device when part or all of the function is implemented by hardware, the encoding device comprises: an input interface circuit for acquiring information to be encoded; and a logic circuit for performing the second aspect and the second aspect described above The behavior of the sender in any of the possible designs; the output interface circuit for outputting the Polar encoded bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the encoding device can implement the method described in any of the possible aspects of the second aspect and the second aspect described above.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • an encoding apparatus having a function of implementing a sender-side behavior in any of the possible aspects of the third aspect and the third aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device when part or all of the function is implemented by hardware, the encoding device comprises: an input interface circuit for acquiring information to be encoded; and a logic circuit for performing the third aspect and the third aspect described above The behavior of the sender in any of the possible designs; the output interface circuit for outputting the Polar encoded bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the encoding device can implement the method described in any of the possible aspects of the third aspect and the third aspect described above.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • an encoding apparatus having a function of realizing a behavior of a transmitting end in any of the possible aspects of the fourth aspect and the fourth aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the encoding device comprises: an input interface circuit for acquiring an information vector U to be encoded; and a logic circuit for performing the above fourth aspect and The behavior of the transmitting end in any of the possible designs of the fourth aspect; the output interface circuit for outputting the Polar encoded bit sequence.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the function is implemented by software, the encoding device comprises: a memory for storing a program; a processor for executing the program stored by the memory, When the program is executed, the encoding apparatus can implement the method as described in any of the possible aspects of the fourth aspect and the fourth aspect described above.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the encoding device when some or all of the functions are implemented by software, the encoding device includes a processor.
  • a memory for storing a program is located outside the encoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • a decoding apparatus having the function of implementing the behavior of a receiving end in any of the possible aspects of the fifth aspect and the fifth aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the decoding apparatus when part or all of the function is implemented by hardware, includes: an input interface circuit for acquiring a sequence to be decoded; and a logic circuit for performing the fifth aspect described above And the behavior of the receiving end in any of the possible designs of the fifth aspect; the output interface circuit for outputting the bit sequence after the deinterleaving operation.
  • the decoding device may be a chip or an integrated circuit.
  • the decoding apparatus when part or all of the function is implemented by software, includes: a memory for storing a program; a processor for executing the program stored by the memory, when When the program is executed, the decoding apparatus may implement the method as described in any of the possible aspects of the fifth aspect and the fifth aspect described above.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the decoding device when some or all of the functionality is implemented in software, the decoding device includes a processor.
  • a memory for storing a program is located outside the decoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • a decoding apparatus having the function of realizing the behavior of a receiving end in any of the possible designs of the sixth aspect and the sixth aspect described above.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the decoding apparatus when part or all of the function is implemented by hardware, includes: an input interface circuit for acquiring a sequence to be decoded; and a logic circuit for performing the sixth aspect described above And the behavior of the receiving end in any of the possible designs of the sixth aspect; the output interface circuit for outputting the bit sequence after the deinterleaving operation.
  • the decoding device may be a chip or an integrated circuit.
  • the decoding apparatus when part or all of the function is implemented by software, includes: a memory for storing a program; a processor for executing the program stored by the memory, when When the program is executed, the decoding apparatus may implement the method as described in any of the possible aspects of the fifth aspect and the fifth aspect described above.
  • the above memory may be a physically separate unit or may be integrated with the processor.
  • the decoding device when some or all of the functionality is implemented in software, the decoding device includes a processor.
  • a memory for storing a program is located outside the decoding device, and the processor is connected to the memory through a circuit/wire for reading and executing a program stored in the memory.
  • a communication system comprising the apparatus of any of the seventh aspect to the tenth aspect, and the apparatus of the eleventh or twelfth aspect.
  • a fourteenth aspect a computer storage medium for storing a computer program, the computer program comprising: in any of the possible embodiments of the first to sixth aspects, the first to sixth aspects Method of instruction.
  • a computer program product comprising instructions for causing a computer to perform the method of the above aspects when executed on a computer is provided.
  • FIG. 1 is a schematic diagram of a CRC encoding method in the prior art
  • FIG. 2 is a schematic structural diagram of a communication system in an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a coding method in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of interleaving a coded codeword in the embodiment of the present application.
  • FIG. 5 is a second schematic flowchart of a coding method in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an encoding apparatus in an embodiment of the present application.
  • FIG. 7 is a second schematic structural diagram of an encoding apparatus according to an embodiment of the present application.
  • FIG. 8 is a third schematic structural diagram of an encoding apparatus according to an embodiment of the present application.
  • FIG. 9 is a fourth schematic structural diagram of an encoding apparatus according to an embodiment of the present application.
  • FIG. 10 is a fifth schematic structural diagram of an encoding apparatus according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present application.
  • FIG. 12 is a second schematic structural diagram of a decoding apparatus according to an embodiment of the present application.
  • FIG. 13 is a third schematic structural diagram of a decoding apparatus according to an embodiment of the present application.
  • An embodiment of the present invention provides an encoding method and apparatus, which interpolate check bits between information bits to be encoded by an interleaving manner.
  • each check bit can be verified. If the verification fails, the decoding can be terminated early, which helps to avoid the problem of waste of decoding resources after the channel decoding is completed, shortens the time used for decoding, and improves the decoding efficiency.
  • the communication system 200 to which the embodiment of the present application is applied includes a transmitting end 201 and a receiving end 202.
  • the transmitting end 201 can be a base station, and the receiving end 202 is a terminal; or the transmitting end 201 is a terminal, and the receiving end 202 is a base station.
  • a base station is a device deployed in a radio access network to provide wireless communication functions to a terminal.
  • the base station may include various forms of macro base stations, micro base stations, relay stations, access points, and the like. It can be applied in systems with different radio access technologies, such as in Long Term Evolution (LTE) systems, or in more possible communication systems such as 5th Generation (5G) communication systems.
  • LTE Long Term Evolution
  • 5G 5th Generation
  • the base station may also be another network device having a base station function, and in particular, may also be a terminal serving as a base station function in D2D communication.
  • the terminal may include various handheld devices having wireless communication functions, in-vehicle devices, wearable devices, computing devices, or other processing devices connected to the wireless modem, and various forms of User Equipment (UE), mobile stations (Mobile) Station, MS), etc.
  • UE User Equipment
  • MS Mobile Station
  • the transmitting end 201 performs check coding and Polar coding on the coded information, where the transmitting end 201 interleaves the check coded codeword, or the transmitting end 201 is in the school.
  • the check bit is interspersed between the information bits, and the transmitting end 201 sends the encoded Polar code to the receiving end 202, and the receiving end 202 performs decoding and deinterleaving.
  • Step 301 The sending end acquires information to be encoded.
  • Step 302 The transmitting end performs check coding to obtain a check codeword.
  • Step 303 The transmitting end performs an interleaving operation on the check codeword.
  • Step 304 The transmitting end performs Polar code encoding on the check codeword after the interleaving operation.
  • Step 305 The receiving end acquires a sequence to be decoded.
  • Step 306 The receiving end performs the Polar code decoding on the sequence to be decoded.
  • Step 307 The receiving end performs a deinterleaving operation on the decoded sequence.
  • the receiving end does not perform decoding and deinterleaving in the manner of steps 305 to 307.
  • the receiving end may perform a verification on a part of the information bits obtained by decoding according to a part of the parity bits obtained by decoding, and if the existing decoding result fails to pass the verification, Then the decoding is stopped immediately, and the feedback decoding fails, otherwise the decoding is continued.
  • the method for performing the check coding by the transmitting end may adopt any one of the prior art check coding methods, for example, adopting the existing CRC coding mode.
  • the check code code word obtained after the check code is sent by the transmitting end includes information bits and check bits. Assume that the information bit length is K and the check bit length is J.
  • the transmitting end performs an interleaving operation on the check coded codeword by using the interleaving sequence S.
  • the interleaving sequence S used by the transmitting end includes J subsequences, and the J subsequences are consecutive.
  • One subsequence includes a position index value of the element 1 in the intermediate result vector T i and a value of (K+i), 1 ⁇ i ⁇ J, i is an integer. i takes different values and the subsequences are different.
  • the order of the values of i may be in the order of i values from small to large, or in descending order of i values, or in descending order of the number of elements 1 in the column vector V i , or The order of the number of elements 1 in the column vector V i is not limited in this application.
  • the resulting vector T i is an all-zero vector of length K.
  • the transmitting end may dynamically calculate the foregoing interleaving sequence S before step 303, and may also calculate and store the interleaving sequence S offline. In step 303, the transmitting end performs an interleaving operation on the check encoded codeword by using the stored interleaving sequence S.
  • the following describes in detail how the transmitting end calculates the above-described interleaving sequence S. It should be noted that the transmitting end uses the same calculation method to calculate the above-mentioned interleaving sequence S offline and store it.
  • the transmitting end calculates the system form generation matrix G of the check code, extracts the check partial matrix P in the generator matrix G, initializes the mask vector M, the intermediate result vector T i and the interleaving sequence S, for example, an initialization mask.
  • the vector M and the intermediate result vector T i are all all 0 vectors of length K; the column vector V i of the check partial matrix P is read column by column in the set order, and 1 ⁇ i ⁇ J, i is an integer.
  • the column vector V i of the check partial matrix may be read column by column according to the order of the column index values from small to large, or may be read column by column according to the order of the column index values from large to small.
  • the column vector V i of the check partial matrix is read column by column in order of the number of elements 1 in the most.
  • the column vector V i of P can also be read in other set order.
  • the following takes the check code as the CRC code as an example, and details the steps of the transmitter to obtain the interleaving sequence.
  • G is a system form generation matrix of K rows and (K+J) columns
  • I is an identity matrix of K rows and K columns
  • P is a matrix of K rows and J columns
  • P may be called a check partial matrix
  • a check portion matrix P is extracted from G.
  • the mask vector M and the intermediate result vector T i initialize an all-zero vector of length K.
  • the length of the interleaving sequence S is (K+J).
  • the intermediate result vector T i can occupy a continuous storage space of the address.
  • the column vector is represented by V i , 1 ⁇ i ⁇ J, and i is an integer.
  • the transmitting end may sequentially read the column vector according to the column number from small to large or from large to small, that is, sequentially read the first to the Jth columns in P, or sequentially read the Jth to the first column.
  • the sender can also read the column vectors in order of the number of elements 1 contained in each column from the most to the least or from the least.
  • Steps (3.1) to (3.3) are performed each time a column vector is read until all column vectors of the check partial matrix P are read.
  • T i ( ⁇ M) & (Vi), where ⁇ is a bit-by-bit non-operation, and & is a bit-wise AND operation;
  • the location index value may be a sequence number of an element having a value of 1 in the intermediate result vector T i , or a difference between an address of the intermediate result vector T i having an element value of 1 and an address of the first element in the T i .
  • the receiving end performs a deinterleaving operation on the decoded sequence by using a deinterleaving sequence S'.
  • the method for obtaining the interleaving sequence S by the receiving end is the same as the method for obtaining the interleaving sequence S by the transmitting end, and the repeated portions are not described herein again.
  • the receiving end may also dynamically calculate the deinterleaving sequence S' before step 307, and may also calculate and store the deinterleaving sequence S' offline.
  • the receiving end uses the stored deinterleaving sequence S' to decode the decoded The sequence is deinterleaved.
  • the check code as the CRC code as an example.
  • the information bit length K is 10
  • the check bit length J of the CRC check code is 5.
  • the information vector to be encoded U [1,0,1,1,0,1,0,0,1,1]
  • the generator polynomial of the CRC code is [1 0 1 0 0 1], according to the existing CRC coding method
  • the check code word C 0 [ 1, 0, 1, 1, 0, 1, 0, 1, 1, 1, 0, 1, 0, 0 ] is obtained.
  • the step of the transmitting end acquiring the interleaving sequence S is as described in the following 1 to 5.
  • P is the check partial matrix.
  • Initialization mask vector M [0,0,0,0,0,0,0,0,0,0]
  • intermediate result vector T i [0,0,0,0,0,0,0,0 , 0, 0, 0] and the interleaving sequence S.
  • the column vector V i in the check partial matrix P is read column by column. Each time a column is read, a subsequence is obtained, and the obtained subsequence is recorded at the end of the interleaving sequence S.
  • the number of elements 1 in each column vector of the check partial matrix P is determined.
  • the column vector V i in P can be determined in other ways.
  • the third column V 3 is read, and steps 4.1 to 4.3 are performed.
  • V 3 [0,1,1,1,0,1,0,1,0,0]
  • (Vi), M M
  • (Vi) [0,1,1,1,0,1,0,1,0,0] .
  • the first, second, fourth, and fifth columns are sequentially read, and similarly, the recording interleaving sequence S is updated in accordance with the above steps.
  • the process of reading the first, second, fourth, and fifth columns of the check partial matrix P and the intermediate result vector T i , the interleaving sequence S, and the mask vector M are as follows, and the first column of the matrix P is read.
  • T 1 [0,0,0,0,1,0,1,0,1,0]
  • S [2,3,4,6,8,13,5,7,9,11]
  • M [0,1,1,1,1,1,1,1,0]
  • T 2 [0,0,0,0,0,0,0,0,1]
  • S [2,3,4,6,8,13,5,7,9,11,10,12]
  • M [0,1,1,1,1,1 ,1,1,1]
  • S [2,3 , 4, 6, 8, 13, 5, 7, 9, 11, 10, 12, 1, 14]
  • M [1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
  • Each element in S represents: the position index of C 0 in the position of the element in C is the element value of the element, for example, the first element in S is 2, indicating that C is placed in the first position in C.
  • the second element value in 0 the second element in S is 3, indicating that the third element value in C 0 is placed in the second position in C.
  • Step 501 The sender acquires the information vector U to be encoded.
  • Step 502 The transmitting end calculates a system form generation matrix G of the check code, and extracts a check part matrix P in the generation matrix G.
  • G is a system form generation matrix of K rows and (K+J) columns
  • I is an identity matrix of K rows and K columns
  • P is a matrix of K rows and J columns
  • P may be called a check partial matrix
  • a check portion matrix P is extracted from G.
  • Step 503 The sender initializes the mask vector M, the first intermediate result vector T1 i , the second intermediate result vector T2 i , and the check codeword C.
  • the mask vector M and the intermediate result vector T i initialize an all-zero vector of length K.
  • the first intermediate result vector T1 i may occupy a segment of the storage space of consecutive addresses.
  • the length of the check code word C is (K+J).
  • Step 504 The transmitting end reads the column vector V i of the check partial matrix P column by column in the set order, and 1 ⁇ i ⁇ J, i is an integer. Each time a column vector V i is read, the following operations are performed until all column vectors in P are read, and the final check code word C is obtained.
  • T1 i ( ⁇ M) & (V i ) calculation; U and V i perform bit-wise AND operation to obtain T2 i ; determine the position index of the element in T1 i is 1, and the element corresponding to the position index in T2 i
  • Step 505 The transmitting end performs Polar coding on the finally obtained check coded codeword C.
  • the transmitting end may read the column vector V i of the check partial matrix P column by column according to the column index value from small to large, or the transmitting end may be column by column according to the column index value from large to small. Reading the column vector V i of the check partial matrix P, or the transmitting end reads the column vector V i of the check partial matrix P column by column in descending order of the number of elements 1 in the column vector; or the transmitting end The column vector V i of the check partial matrix P is read column by column in the order of the number of elements 1 in the column vector.
  • the second encoding method shown in FIG. 5 will be exemplified below.
  • the check code as the CRC code as an example.
  • the length K of U is 10
  • the check bit length J of the CRC check code is 5.
  • U [1,0,1,1,0,1,0,0,1,1]
  • the generator polynomial of the CRC code is [1 0 1 0 0 1]
  • the step of obtaining the check code code word C is :
  • P is the check partial matrix.
  • the number of elements 1 in each column vector of the check partial matrix P is determined.
  • the column vector V i in P can be determined in other ways.
  • V 3 [0,1,1,1,0,1,0,1,0,0]
  • Vi [0,1,1,1,0,1,0,1,0,0]
  • T2 3 [0, 0, 1 , 1 , 0, 1 , 0, 0, 0, 0];
  • (Vi), M M
  • (Vi) [0,1,1,1,0,1,0,1,0,0] ;
  • T1 1 [0,0,0,0,1,0,1,0,1,0]
  • M [0,1,1,1,1,1,1,1,1,0]
  • T1 2 [0,0,0,0,0,0,0,0,1]
  • M [0,1 ,1,1,1,1,1,1,1,1,1]
  • T1 4 [1,0,0,0,0,0,0,0,0,0 ]
  • the embodiment of the present application may implement interleaving of the check codewords, and the check bits are interspersed between the information bits.
  • each decoding is performed.
  • the check bit can be verified. If the check fails, the decoding can be terminated early, which helps to avoid the problem of waste of decoding resources after the channel decoding is completed, and shortens the decoding.
  • the duration increases the efficiency of decoding.
  • the interleaving of the coded codewords can be implemented more simply, which effectively saves hardware overhead and helps improve the utilization of coding resources.
  • an embodiment of the present application further provides an encoding apparatus 600 for performing the encoding shown in FIG. 3 or FIG.
  • the method, the encoding device 600 includes:
  • the receiving unit 601 is configured to obtain information to be encoded.
  • the processing unit 602 is configured to perform check coding on the coded information to obtain a check codeword, and the check codeword includes information bits and check bits, the length of the information bits is K, and the length of the check bits is J;
  • the processing unit 602 is further configured to perform an interleaving operation on the check coded codeword.
  • the processing unit 602 is further configured to perform Polar coding on the check codeword after the interleaving operation.
  • the processing unit 602 is configured to: before the interleaving operation on the encoded codeword, calculate the interleaving sequence S; or calculate and store the interleaving sequence S offline, and perform an interleaving operation on the encoded codeword according to the stored interleaving sequence S.
  • the order of values of i in the J subsequences includes: in order from i to small, or in descending order of i values, or according to the number of elements 1 in the column vector V i In as little order as possible, or in descending order of the number of elements 1 in the column vector V i .
  • an embodiment of the present application further provides an encoding apparatus 700 for performing the encoding shown in FIG. 3 or FIG.
  • the method, the encoding device 700 includes:
  • the receiving unit 701 is configured to obtain an information vector U to be encoded
  • the processing unit 702 is configured to calculate a system format generation matrix G of the check code, and extract a check portion matrix P in the G;
  • the processing unit 702 is further configured to initialize a mask vector M, a first intermediate result vector T1 i , a second intermediate result vector T2 i , and a check coded code word C;
  • the processing unit 702 is further configured to perform Polar coding on the check coded codeword C.
  • processing unit 702 is configured to:
  • the column vector V i of the check partial matrix is read column by column in the order of the column index values from small to large, or
  • the column vector V i of the check partial matrix is read column by column according to the order of the column index values from large to small, or
  • the column vector V i of the check partial matrix is read column by column according to the order of the number of elements 1 in the column vector; or, column by column according to the order of the number of elements 1 in the column vector
  • the column vector V i of the check partial matrix is read.
  • an embodiment of the present application further provides an encoding apparatus 800 for performing the method shown in FIG. 3 or FIG. Coding method.
  • the encoding apparatus 800 includes: an input interface circuit 801 for acquiring information to be encoded; 802 is used to perform the coding method shown in FIG. 3 or FIG. 5 above.
  • the output interface circuit 803 is configured to output a Polar coded bit sequence.
  • the encoding device 800 may be a chip or an integrated circuit when implemented.
  • the encoding apparatus 800 includes: a memory 901 for storing a program; and a processor 902 for executing the memory 901.
  • the stored program when executed, causes the encoding device 800 to implement the encoding method provided by the above embodiments.
  • the foregoing memory 901 may be a physically independent unit, or as shown in FIG. 10, the memory 901 is integrated with the processor 902.
  • the encoding apparatus 800 may also include only the processor 902.
  • the memory 901 for storing programs is located outside the encoding device 800, and the processor 902 is connected to the memory 901 through circuits/wires for reading and executing programs stored in the memory 901.
  • the decoding device 1100 is further provided in the method shown in FIG. The method executed at the receiving end.
  • part or all of the receiving end execution method may be implemented by hardware or by software.
  • the decoding apparatus 1100 includes: an input interface circuit 1101, which is used to acquire The sequence of the decoding; the logic circuit 1102 is configured to perform the method performed by the receiving end in the method described in FIG. 3 above.
  • the output interface circuit 1103 is used for output. The bit sequence after the deinterleaving operation.
  • the decoding device 1100 may be a chip or an integrated circuit when implemented.
  • the decoding apparatus 1100 includes: a memory 1201 for storing a program; and a processor 1202, The program for executing the storage of the memory 1201, when the program is executed, causes the decoding device 1100 to implement the method of performing the receiving end in the method shown in FIG. 3 described above.
  • the foregoing memory 1201 may be a physically independent unit, or as shown in FIG. 13, the memory 1301 is integrated with the processor 1302.
  • the decoding apparatus 1100 may also include only the processor 1202.
  • the memory 1201 for storing programs is located outside the decoding device 1100, and the processor 1202 is connected to the memory 1201 through circuits/wires for reading and executing the programs stored in the memory 1201.
  • the embodiment of the present application provides a computer storage medium for storing a computer program, the computer program comprising the encoding method shown in FIG. 3 or FIG.
  • the embodiment of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to execute the encoding method shown in FIG. 3 or FIG. 5.
  • the coding apparatus shown in FIG. 8 to FIG. 10 may also be a system chip, and the decoding apparatus shown in FIG. 11 to FIG. 13 may be a system chip.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Abstract

一种编码方法及装置，用以提供一种新的校验编码方式。该方法为：发送端对待编码信息进行校验编码，获得校验编码码字，校验编码码字中信息比特的长度为K，校验比特的长度为J；发送端对校验编码码字进行交织操作；其中，交织操作所采用的交织序列S包括J个子序列，第i个子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；发送端对交织操作后的校验编码码字进行Polar编码。

Description

一种编码方法及装置
本申请要求在2018年5月5日提交中国专利局、申请号为201710314164.5、发明名称为“一种编码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信技术领域，尤其涉及一种编码方法及装置。
背景技术
循环冗余校验(Cyclic Redundancy Check，CRC)编码是数据通信领域中最常用的一种查错校验码，CRC编码的特征是信息字段和校验字段的长度可以任意选定。在通信系统中，CRC编码用于检测数据的传输是否正确，以及控制虚警(英文：False Alarm)的发生概率。
CRC编码的一种实现方式为移位寄存器形式。图1为一种常用的移位寄存器(简称寄存器)形式实现CRC编码的方式，寄存器的反馈抽头由CRC多项式[1 0 1 0 1]决定，寄存器内容初始化为预设值。编码时，待编码信息逐比特从一侧移入寄存器，反馈抽头与寄存器对应状态进行比特异或运算，从而寄存器状态发生变化。当所有待编码比特移入寄存器后，再移入与CRC校验长度相等位数的比特0，然后读取寄存器状态，将寄存器状态作为CRC校验比特，附在待编码信息之后，作为CRC编码码字。发送端对CRC编码进行信道编码，接收端进行对应的信道译码，在信道译码结束后，通过CRC校验判断译码结果是否译码成功。
但是，对于顺序译码(即串行译码)的译码方式，如果采用上述传统的CRC编码方式，在信道译码结束后才能进行CRC校验，使得译码过程复杂，占用时间较长，且浪费译码资源。
发明内容
本申请实施例提供一种编码方法及装置，用以解决采用现有CRC编码方式译码过程复杂从而浪费译码资源的问题。
本申请实施例提供的具体技术方案如下：
第一方面，提供一种编码方法，发送端采用交织的方式，将待编码信息的校验比特穿插在信息比特之间，当接收端采用顺序译码时，每译码出校验比特，即可进行校验，若校验不通过，可以提前结束译码，有助于避免在信道译码结束后再进行校验造成了译码资源浪费的问题，缩短了译码所用时长，提高了译码的效率。
在一个可能的设计中，发送端对待编码信息进行校验编码，获得校验编码码字，所述校验编码码字包括信息比特和校验比特，信息比特的长度为K，校验比特的长度为J，所述发送端对所述校验编码码字进行交织操作，其中，所述交织操作所采用的交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i) 的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；所述发送端对交织操作后的校验编码码字进行Polar编码。可选的，T i、M均为1×K的向量。
可选的，在硬件实现时，中间结果向量T i可占据地址连续的一段存储空间。
由此看出，交织序列的计算方式更加简单易实现，有效节省了硬件开销，有助于提高编码资源的利用率。
在一个可能的设计中，所述发送端采用动态计算的方式或者离线存储的方式获取所述交织序列S。具体地，所述发送端对所述编码码字进行交织操作之前，计算所述交织序列S；或者，所述发送端离线计算并存储所述交织序列S，在所述发送端对所述编码码字进行交织操作时，所述发送端按照存储的所述交织序列S对所述编码码字进行交织操作。
在一个可能的设计中，所述J个子序列中i取值的顺序可以按照i值从小到大的顺序，或者按照i值从大到小的顺序，或者按照列向量V i中元素1的个数从少到多的顺序，或者按照列向量V i中元素1的个数从多到少的顺序。
第二方面，提供一种编码方法，发送端对待编码信息进行校验编码，获得编码码字，所述编码码字包括信息比特和校验比特，信息比特的长度为K，校验比特的长度为J，所述发送端对所述编码码字进行交织操作，所述发送端对交织操作后的校验编码码字进行Polar编码。其中，所述交织操作所采用的交织序列S按照以下方式获取：计算校验编码的生成矩阵G，提取所述生成矩阵G中的校验部分矩阵P；初始化掩码向量M、中间结果向量T i和交织序列S；按照设定的顺序逐列读取所述校验部分矩阵P的列向量V i，每读取一个列向量V i：执行T i＝(～M)&(V i)计算，并将T i中元素为1的位置索引值以及(K+i)的值依次记录于S的尾部，i为V i在P中的列索引值，按照M＝M︱(V i)更新M。这样，当接收端采用顺序译码时，每译码出校验比特，即可进行校验，若校验不通过，可以提前结束译码，有助于避免在信道译码结束后再进行校验造成了译码资源浪费的问题，缩短了译码所用时长，提高了译码的效率。
可选的，T i、M均为1×K的向量。
可选的，在硬件实现时，中间结果向量T i可占据地址连续的一段存储空间。
由此看出，交织序列的计算方式更加简单易实现，有效节省了硬件开销，有助于提高编码资源的利用率。
在一个可能的设计中，按照设定的顺序逐列读取所述校验部分矩阵的列向量V i，通过以下方式实现：按照列索引值从小到大的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，按照列索引值从大到小的顺序，逐列读取所述校验部分矩阵的列向量V i。
第三方面，提供一种编码方法，发送端通过以下方式离线计算交织序列S：计算校验编码的生成矩阵G，提取所述生成矩阵G中的校验部分矩阵P；初始化掩码向量M、中间结果向量T i和交织序列S；按照设定的顺序逐列读取所述校验部分矩阵P的列向量V i，每读取一个列向量V i：执行T i＝(～M)&(V i)计算，并将T i中元素为1的位置索引值以及(K+i)的值依次记录于S的尾部，i为V i在P中的列索引值，按照M＝M︱(V i)更新M。发送端存储所述交织序列S，发送端在获取待编码信息后，对待编码信息进行校验编码，获得编码码字，采用存储的交织序列S对所述编码码字进行交织操作，所述发送端对交织操作后的校验编码码字进行Polar编码。这样，当接收端采用顺序译码时，每译码出校验 比特，即可进行校验，若校验不通过，可以提前结束译码，有助于避免在信道译码结束后再进行校验造成了译码资源浪费的问题，缩短了译码所用时长，提高了译码的效率。
可选的，T i、M均为1×K的向量。
可选的，在硬件实现时，中间结果向量T i可占据地址连续的一段存储空间。
由此看出，交织序列的计算方式更加简单易实现，有效节省了硬件开销，有助于提高编码资源的利用率。
在一个可能的设计中，按照设定的顺序逐列读取所述校验部分矩阵的列向量V i，通过以下方式实现：按照列索引值从小到大的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，按照列索引值从大到小的顺序，逐列读取所述校验部分矩阵的列向量V i。
第四方面，提供一种编码方法，发送端获取待编码信息向量U；所述发送端计算校验编码的系统形式生成矩阵G，并提取所述G中的校验部分矩阵P；所述发送端初始化掩码向量M、第一中间结果向量T1 i、第二中间结果向量T2 i和校验编码码字C；所述发送端按照设定的顺序逐列读取所述校验部分矩阵P的列向量V i，每读取一个列向量V i，执行以下操作：T1 i＝(～M)&(V i)计算；U和V i进行逐比特与运算，得到T2 i；确定T1 i中元素为1的位置索引，将T2 i中所述位置索引对应的元素、和T2 i中所有元素进行异或运算的结果记录于C的尾部，按照M＝M︱(V i)更新M，其中，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；所述发送端对所述校验编码码字C进行Polar编码。这样，当接收端采用顺序译码时，每译码出校验比特，即可进行校验，若校验不通过，可以提前结束译码，有助于避免在信道译码结束后再进行校验造成了译码资源浪费的问题，缩短了译码所用时长，提高了译码的效率。
在一个可能的设计中，所述发送端按照设定的顺序逐列读取所述校验部分矩阵P的列向量V i，通过以下方式实现：所述发送端按照列索引值从小到大的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，所述发送端按照列索引值从大到小的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，所述发送端按照列向量中元素1的个数从少到多的顺序，逐列读取所述校验部分矩阵的列向量V i；或者，所述发送端按照列向量中元素1的个数从多到少的顺序，逐列读取所述校验部分矩阵的列向量V i。
第五方面，提供一种译码方法，接收端获取待译码的序列，接收端对待译码的序列进行Polar码译码，并对译码后的序列进行解交织操作，假设信息比特的长度为K，校验比特的长度为J，所述解交织操作所用的解交织序列S’满足S’(S(j))＝j，1≤j≤(K+J)，j为整数，其中S为交织序列，交织序列S包括J个子序列，一个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
可选的，T i、M均为1×K的向量。
在一个可能的设计中，所述接收端采用动态计算的方式或者离线存储的方式获取所述解交织序列S’。具体地，所述接收端对所述译码后的序列进行解交织操作之前，计算所述解交织序列S’；或者，所述接收端离线计算并存储所述解交织序列S’，在所述接收端对所述编码码字进行解交织操作时，所述接收端按照存储的所述解交织序列S’对所述译码后的序列进行解交织操作。
在一个可能的设计中，所述J个子序列中i取值的顺序可以按照i值从小到大的顺序， 或者按照i值从大到小的顺序，或者按照列向量V i中元素1的个数从少到多的顺序，或者按照列向量V i中元素1的个数从多到少的顺序。
第六方面，提供一种译码方法，接收端通过以下方式离线计算解交织序列S’：计算校验编码的生成矩阵G，提取所述生成矩阵G中的校验部分矩阵P；初始化掩码向量M、中间结果向量T i和交织序列S；按照设定的顺序逐列读取所述校验部分矩阵P的列向量V i，每读取一个列向量V i：执行T i＝(～M)&(V i)计算，并将T i中元素为1的位置索引值以及(K+i)的值依次记录于S的尾部，i为V i在P中的列索引值，按照M＝M︱(V i)更新M；按照S’(S(j))＝j获取S’，1≤j≤(K+J)，j为整数；接收端存储所述解交织序列S’，接收端在获取待译码的序列后，对待译码的序列进行Polar码译码，并采用存储的解交织序列S’对译码后的序列进行解交织操作。
在一个可能的设计中，按照设定的顺序逐列读取所述校验部分矩阵的列向量V i，通过以下方式实现：按照列索引值从小到大的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，按照列索引值从大到小的顺序，逐列读取所述校验部分矩阵的列向量V i。
第七方面，提供一种编码装置，该装置具有实现上述第一方面和第一方面的任一种可能的设计中发送端行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述编码装置包括：输入接口电路，用于获取待编码信息；逻辑电路，用于执行上述第一方面和第一方面的任一种可能的设计中发送端的行为；输出接口电路，用于输出Polar编码后的比特序列。
可选的，所述编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述编码装置可以实现如上述第一方面和第一方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第八方面，提供一种编码装置，该装置具有实现上述第二方面和第二方面的任一种可能的设计中发送端行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述编码装置包括：输入接口电路，用于获取待编码信息；逻辑电路，用于执行上述第二方面和第二方面的任一种可能的设计中发送端的行为；输出接口电路，用于输出Polar编码后的比特序列。
可选的，所述编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述编码装置可以实现如上述第二方面和第二方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第九方面，提供一种编码装置，该装置具有实现上述第三方面和第三方面的任一种可能的设计中发送端行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述编码装置包括：输入接口电路，用于获取待编码信息；逻辑电路，用于执行上述第三方面和第三方面的任一种可能的设计中发送端的行为；输出接口电路，用于输出Polar编码后的比特序列。
可选的，所述编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述编码装置可以实现如上述第三方面和第三方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第十方面，提供一种编码装置，该装置具有实现上述第四方面和第四方面的任一种可能的设计中发送端行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述编码装置包括：输入接口电路，用于获取待编码信息向量U；逻辑电路，用于执行上述第四方面和第四方面的任一种可能的设计中发送端的行为；输出接口电路，用于输出Polar编码后的比特序列。
可选的，所述编码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述编码装置可以实现如上述第四方面和第四方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述编码装置包括处理器。用于存储程序的存储器位于所述编码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第十一方面，提供了一种译码装置，该装置具有实现上述第五方面和第五方面的任一种可能的设计中接收端行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述译码装置包括：输入接口电路，用于获取待译码的序列；逻辑电路，用于执行上述第五方面和第五方面的任一种可能的设计中接收端的行为；输出接口电路，用于输出解交织操作后的比特序列。
可选的，所述译码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述译码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述译码装置可以实现如上述第五方面和第五方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述译码装置包括处理器。用于存储程序的存储器位于所述译码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第十二方面，提供了一种译码装置，该装置具有实现上述第六方面和第六方面的任一种可能的设计中接收端行为的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的设计中，当所述功能的部分或全部通过硬件实现时，所述译码装置包括：输入接口电路，用于获取待译码的序列；逻辑电路，用于执行上述第六方面和第六方面的任一种可能的设计中接收端的行为；输出接口电路，用于输出解交织操作后的比特序列。
可选的，所述译码装置可以是芯片或者集成电路。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述译码装置包括：存储器，用于存储程序；处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述译码装置可以实现如上述第五方面和第五方面的任一种可能的设计中所述的方法。
可选的，上述存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一个可能的设计中，当所述功能的部分或全部通过软件实现时，所述译码装置包括处理器。用于存储程序的存储器位于所述译码装置之外，处理器通过电路/电线与存储器连接，用于读取并执行所述存储器中存储的程序。
第十三方面，提供了一种通信系统，该系统包括第七方面至第十方面任一方面所述的装置，和第十一方面或第十二方面所述的装置。
第十四方面，提供了一种计算机存储介质，用于存储计算机程序，该计算机程序包括用于执行第一方面至第六方面、第一方面至第六方面的任一可能的实施方式中的方法的指令。
第十五方面，提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
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图7为本申请实施例中编码装置结构示意图之二；
图8为本申请实施例中编码装置结构示意图之三；
图9为本申请实施例中编码装置结构示意图之四；
图10为本申请实施例中编码装置结构示意图之五；
图11为本申请实施例中译码装置结构示意图之一；
图12为本申请实施例中译码装置结构示意图之二；
图13为本申请实施例中译码装置结构示意图之三。
具体实施方式
下面将结合附图，对本申请实施例进行详细描述。
本申请实施例提供一种编码方法及装置，通过交织方式将校验比特穿插在待编码信息比特之间，当接收端采用顺序译码时，每译码出校验比特，即可进行校验，若校验不通过，可以提前结束译码，有助于避免在信道译码结束后再进行校验造成了译码资源浪费的问题，缩短了译码所用时长，提高了译码的效率。
如图2所示，本申请实施例应用的通信系统200中包括发送端201和接收端202。其中，发送端201可以为基站，接收端202为终端；或者，发送端201为终端，接收端202为基站。基站是一种部署在无线接入网中用以为终端提供无线通信功能的装置。基站可以包括各种形式的宏基站，微基站，中继站，接入点等等。可以应用在不同的无线接入技术的系统中，例如长期演进(Long Term Evolution，LTE)系统中，或者，第五代(5th Generation，5G)通信系统等更多可能的通信系统中。基站还可以是其他具有基站功能的网络设备，特别地，还可以是D2D通信中担任基站功能的终端。终端可以包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其他处理设备，以及各种形式的用户设备(User Equipment，UE)，移动台(Mobile Station，MS)等。
基于图2所示的通信系统架构，本申请实施例中，发送端201对待编码信息进行校验编码和Polar编码，其中，发送端201对校验编码码字进行交织，或者发送端201在校验编码过程中实现将校验比特穿插于信息比特之间，发送端201将编码后的Polar码发送给接收端202，接收端202进行译码和解交织。下面将结合图3和图5详细介绍一下本申请实施例基于同一发明构思提供的两种编码方法。
如图3所示，本申请实施例提供的编码方法之一的具体流程如下所述。
步骤301、发送端获取待编码信息；
步骤302、发送端进行校验编码，获得校验编码码字。
步骤303、发送端对校验编码码字进行交织操作。
步骤304、发送端对交织操作后的校验编码码字进行Polar码编码。
步骤305、接收端获取待译码的序列。
步骤306、接收端对待译码的序列进行Polar码译码。
步骤307、接收端对译码后的序列进行解交织操作。
或者，在步骤304之后，接收端不采用步骤305～步骤307的方式进行译码和解交织。例如，对顺序译码方式，接收端可以在译码过程中，根据译码得到的一部分校验比特对译码得到的一部分信息比特进行校验，若已有的译码结果无法通过校验，则立刻停止译码，并反馈译码失败，否则继续译码。
具体地，发送端进行检验编码的方法可以采用现有技术中的任意一种校验编码方法，例如采用现有的CRC编码方式。发送端进行校验编码后获得的校验编码码字中包括信息比特和校验比特。假设信息比特长度为K，校验比特长度为J。发送端采用交织序列S对校验编码码字进行交织操作。其中，发送端所采用的交织序列S包括J个子序列，J个子序列连续，一个子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数。i取不同的值，子序列不同。可选的，i的取值顺序可以按照i值从小到大的顺序，或者按照i值从大到小的顺序，或者按照列向量V i中元素1的个数从少到多的顺序，或者按照列向量V i中元素1的个数从多到少的顺序，本申请中不作限定。T i＝(～M)&(V i)，M＝M︱(V i)，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算，可选的，初始化掩码向量M、中间结果向量T i和交织序列S，例如，初始化掩码向量M和中间结果向量T i均为长度为K的全0向量。
发送端可以在步骤303之前动态计算上述交织序列S，也可以离线计算并存储上述交织序列S，在步骤303中发送端采用存储的交织序列S对校验编码码字进行交织操作。
以下详细说明一下发送端如何计算上述交织序列S。需要说明的是，发送端采用相同的计算方式离线计算上述交织序列S并存储下来。
为方便说明，假设信息比特长度为K，校验比特长度为J。简要来说，发送端计算校验编码的系统形式生成矩阵G，提取生成矩阵G中的校验部分矩阵P；初始化掩码向量M、中间结果向量T i和交织序列S，例如，初始化掩码向量M和中间结果向量T i均为长度为K的全0向量；按照设定的顺序逐列读取校验部分矩阵P的列向量V i，1≤i≤J，i为整数。具体地，可以是按照列索引值从小到大的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，按照列索引值从大到小的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，按照列向量中元素1的个数从少到多的顺序，逐列读取所述校验部分矩阵的列向量V i，也或者，按照列向量中元素1的个数从多到少的顺序，逐列读取所述校验部分矩阵的列向量V i。当然，还可以按照其他设定顺序读取P的列向量V i。每读取一个列向量V i，执行一次下述操作，直到读取完校验部分矩阵P中的所有列向量，具体地，执行T i＝(～M)&(V i)计算，并将T i中元素为1的位置索引值以及(K+i)的值依次记录于S的尾部，i为V i在P中的列索引值，按照M＝M︱(V i)更新M，其中，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算。
下面以校验编码为CRC编码为例，详细介绍一下发送端获取交织序列的步骤。
(1)根据CRC多项式，获取CRC系统形式生成矩阵G，G＝[I P]。
其中，G为K行、(K+J)列的系统形式生成矩阵，I为K行、K列的单位矩阵，P为K行、J列的矩阵，P可以称为校验部分矩阵，从G中提取出校验部分矩阵P。
(2)初始化掩码向量M、中间结果向量T i和交织序列S。
具体地，掩码向量M和中间结果向量T i初始化长度为K的全0向量。交织序列S的长度为(K+J)。其中，在硬件实现时，中间结果向量T i可占据地址连续的一段存储空间。
(3)按照设定顺序逐列读取矩阵P中的列向量。
列向量以V i表示，1≤i≤J，i为整数。具体地，发送端可以按照列序号从小到大或者从大到小的顺序依次读取列向量，即依次读取P中的第1到第J列，或者，依次读取第J到第1列。发送端还可以按照每列中包含元素1的个数从多到少或者从少到多的顺序依次读 取列向量。
每读取一个列向量执行步骤(3.1)～步骤(3.3)，直到读取完校验部分矩阵P的所有列向量。
(3.1)将读取的第i列向量Vi与掩码向量M进行逐比特运算，然后赋值给向量T i。
例如T i＝(～M)&(Vi)，其中～为逐比特取非运算，&为逐比特与运算；
(3.2)读取中间结果向量T i中元素值为1的位置索引值，将读取到的位置索引值和值(K+i)记录于交织序列S的尾部，记录的顺序可以按照数值从小到大、或从大到小的方式，本申请不作限定。其中，位置索引值可以是值为1的元素在中间结果向量T i中的序号，或中间结果向量T i中元素值为1的地址与T i中第一个元素的地址的差值。
(3.3)更新掩码向量M。
将掩码向量M与向量Vi进行逐比特或运算，将运算后的值更新掩码向量M，例如M＝M|(Vi)。
(4)获得交织序列S。
针对接收端来说，在步骤307中，若需要获取解交织序列，则按照解交织序列S’与交织序列S的关系获取，解交织序列S’与交织序列S的关系为：依次取j为1到(K+J)，S’(S(j))＝j。接收端采用解交织序列S’对译码后的序列进行解交织操作。其中，接收端获取交织序列S的方法与发送端获取交织序列S的方法相同，重复之处在此不再赘述。同样，接收端也可以在步骤307之前动态计算解交织序列S’，也可以离线计算并存储上述解交织序列S’，在步骤307中接收端采用存储的解交织序列S’对译码后的序列进行解交织操作。
下面举例说明获取交织序列的过程。仍以校验编码为CRC编码为例。例如，信息比特长度K为10，CRC校验编码的校验比特长度J为5。待编码的信息向量U＝[1,0,1,1,0,1,0,0,1,1]，CRC编码的生成多项式为[1 0 1 0 0 1]，按照现有CRC编码方式，得到校验编码码字C 0＝[1,0,1,1,0,1,0,0,1,1,1,0,1,0,0]。
那么，发送端获取交织序列S的步骤如下1～5所述。
1、计算CRC编码的系统形式生成矩阵G，如表1。可见，G为K行、(K+J)列的矩阵，即G为10×(10+5)矩阵，G＝[I P]，I为K行、K列的单位矩阵，即K为10×10的单位矩阵，P为K行、J列的矩阵，即P为10×5的矩阵。其中，P为校验部分矩阵。
表1
1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0 1 0 0 0 0 0 0 0 0 1 0 1 0 1
0 0 1 0 0 0 0 0 0 0 1 1 1 1 0
0 0 0 1 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 1 0 0 0 0 0 1 0 0 1 1
0 0 0 0 0 1 0 0 0 0 1 1 1 0 1
0 0 0 0 0 0 1 0 0 0 1 1 0 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 0 1
0 0 0 0 0 0 0 0 1 0 1 0 0 1 0
0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2、在G中取出校验部分矩阵P，如表2；
表2
0 0 0 1 1
1 0 1 0 1
1 1 1 1 0
0 1 1 1 1
1 0 0 1 1
1 1 1 0 1
1 1 0 1 0
0 1 1 0 1
1 0 0 1 0
0 1 0 0 1
3、初始化掩码向量M＝[0,0,0,0,0,0,0,0,0,0]、中间结果向量T i＝[0,0,0,0,0,0,0,0,0,0]和交织序列S。
4、逐列读取校验部分矩阵P中的列向量V i，每读取一列，计算获得一个子序列，将获得的子序列记录在交织序列S的尾部。
具体地，确定校验部分矩阵P的每个列向量中元素1的个数，即[6,6,5,6,7]。按照列向量中元素1的个数由少到多的顺序逐列读取校验部分矩阵P，即按照i＝[3,1,2,4,5]的顺序逐列读取校验部分矩阵P中的列向量V i。当然，读取列向量的顺序可以按照其他方式确定。
首先，读取第3列V 3，执行步骤4.1～步骤4.3。
4.1、读取第3列V 3，V 3＝[0,1,1,1,0,1,0,1,0,0]，将V 3与掩码向量M进行逐比特运算获得向量T 3，例如，T 3＝(～M)&(Vi)＝[0,1,1,1,0,1,0,1,0,0]；
4.2、读取T 3中元素1的序号[2,3,4,6,8]，并计算i+K的值，(i+K)＝(3+10)＝13，将T 3中元素为1的序号和(i+K)的值记录于交织序列S，例如，可以按照从小大到的顺序，依次记录于交织序列S，得到S＝[2,3,4,6,8,13]。
4.3、更新掩码向量M，例如，可以按照M＝M|(Vi)更新，M＝M|(Vi)＝[0,1,1,1,0,1,0,1,0,0]。
接着，依次读取第1、2、4、5列，类似地，按照上述步骤更新记录交织序列S。具体地，对校验部分矩阵P的第1、2、4、5列的读取及中间结果向量T i、交织序列S和掩码向量M的变化过程如下，读取矩阵P第1列，得到T 1＝[0,0,0,0,1,0,1,0,1,0]，S＝[2,3,4,6,8,13,5,7,9,11]，M＝[0,1,1,1,1,1,1,1,1,0]；读取矩阵P第2列，得到T 2＝[0,0,0,0,0,0,0,0,0,1]，S＝[2,3,4,6,8,13,5,7,9,11,10,12],M＝[0,1,1,1,1,1,1,1,1,1]；读取矩阵P第4列，得到T 4＝[1,0,0,0,0,0,0,0,0,0]，S＝[2,3,4,6,8,13,5,7,9,11,10,12,1,14]，M＝[1,1,1,1,1,1,1,1,1,1]；读取矩阵P第5列，得到T 5＝[0,0,0,0,0,0,0,0,0,0]，S＝[2,3,4,6,8,13,5,7,9,11,10,12,1,14,15]，M＝[1,1,1,1,1,1,1,1,1,1]。
5、获得交织序列S＝[2,3,4,6,8,13,5,7,9,11,10,12,1,14,15]
如图4所示，在获得交织序列S后，采用交织序列S对校验编码码字C 0＝[1,0,1,1,0,1,0,0,1,1,1,0,1,0,0]进行交织，得到码字C＝[0,1,1,1,0,1,0,0,1,1,1,0,1,0,0]。S中的每一个元素表示：在C中该元素的位置放置C 0中位置索引为该元素的元素值，例如，S中的第1个元素为2，表示在C中第1个位置放置C 0中第2个元素值，S中的第2个元素 为3，表示在C中第2个位置放置C 0中第3个元素值。
如图5所示，本申请实施例提供的编码方法之二的具体流程如下所述。
步骤501、发送端获取待编码信息向量U。
假设U的长度为K，预生成的校验比特的长度为J。
步骤502、发送端计算校验编码的系统形式生成矩阵G，并提取生成矩阵G中的校验部分矩阵P。
可选的，校验编码方式可以是CRC编码，根据CRC多项式，通过现有技术获取CRC系统形式生成矩阵G，G＝[I P]。其中，G为K行、(K+J)列的系统形式生成矩阵，I为K行、K列的单位矩阵，P为K行、J列的矩阵，P可以称为校验部分矩阵，从G中提取出校验部分矩阵P。
步骤503、发送端初始化掩码向量M、第一中间结果向量T1 i、第二中间结果向量T2 i和校验编码码字C。
具体地，掩码向量M和中间结果向量T i初始化长度为K的全0向量。其中，在硬件实现时，第一中间结果向量T1 i可占据地址连续的一段存储空间。校验编码码字C的长度为(K+J)。
步骤504、发送端按照设定的顺序逐列读取校验部分矩阵P的列向量V i，1≤i≤J，i为整数。每读取一个列向量V i，执行以下操作，直到读完P中所有列向量，获得最终的校验编码码字C。
T1 i＝(～M)&(V i)计算；U和V i进行逐比特与运算，得到T2 i；确定T1 i中元素为1的位置索引，将T2 i中所述位置索引对应的元素、和T2 i中所有元素进行异或运算的结果记录于C的尾部，按照M＝M︱(V i)更新M，其中，～表示取非运算，&表示与运算，︱表示或运算。
步骤505、发送端对最终获得的校验编码码字C进行Polar编码。
其中，步骤504中，发送端可以按照列索引值从小到大的顺序，逐列读取校验部分矩阵P的列向量V i，或者发送端按照列索引值从大到小的顺序，逐列读取校验部分矩阵P的列向量V i，或者发送端按照列向量中元素1的个数从少到多的顺序，逐列读取校验部分矩阵P的列向量V i；或者发送端按照列向量中元素1的个数从多到少的顺序，逐列读取校验部分矩阵P的列向量V i。
下面对图5所示的编码方法之二进行举例说明。仍以校验编码为CRC编码为例。例如，U的长度K为10，CRC校验编码的校验比特长度J为5。U＝[1,0,1,1,0,1,0,0,1,1]，CRC编码的生成多项式为[1 0 1 0 0 1]，则获取校验编码码字C的步骤为：
1)、计算CRC编码的系统形式生成矩阵G，如表3。可见，G为K行、(K+J)列的矩阵，即G为10×(10+5)矩阵，G＝[I P]，I为K行、K列的单位矩阵，即K为10×10的单位矩阵，P为K行、J列的矩阵，即P为10×5的矩阵。其中，P为校验部分矩阵。
表3
1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0 1 0 0 0 0 0 0 0 0 1 0 1 0 1
0 0 1 0 0 0 0 0 0 0 1 1 1 1 0
0 0 0 1 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 1 0 0 0 0 0 1 0 0 1 1
0 0 0 0 0 1 0 0 0 0 1 1 1 0 1
0 0 0 0 0 0 1 0 0 0 1 1 0 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 0 1
0 0 0 0 0 0 0 0 1 0 1 0 0 1 0
0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2)、在G中取出校验部分矩阵P，如表4；
表4
0 0 0 1 1
1 0 1 0 1
1 1 1 1 0
0 1 1 1 1
1 0 0 1 1
1 1 1 0 1
1 1 0 1 0
0 1 1 0 1
1 0 0 1 0
0 1 0 0 1
3)、初始化掩码向量M＝[0,0,0,0,0,0,0,0,0,0]、中间结果向量T1 i＝[0,0,0,0,0,0,0,0,0,0]、中间结果向量T2 i＝[0,0,0,0,0,0,0,0,0,0]和码字向量C。
4)、逐列读取校验部分矩阵P中的列向量V i，每读取一列，计算中间结果向量T1 i、中间结果向量T2 i、码字向量C和掩码向量M，直到读取完校验部分矩阵P中的所有列向量。
具体地，确定校验部分矩阵P的每个列向量中元素1的个数，即[6,6,5,6,7]。按照列向量中元素1的个数由少到多的顺序逐列读取校验部分矩阵P，即按照i＝[3,1,2,4,5]的顺序逐列读取校验部分矩阵P中的列向量V i。当然，读取列向量的顺序可以按照其他方式确定。
首先，读取第3列V 3，V 3＝[0,1,1,1,0,1,0,1,0,0]，将V 3与掩码向量M进行逐比特运算获得向量T1 3，T1 3＝(～M)&(Vi)＝[0,1,1,1,0,1,0,1,0,0]；
接着，将U与V3进行逐比特与运算，得到T2 3，T2 3＝[0,0,1,1,0,1,0,0,0,0]；
然后，确定T1 3中元素值为1的序号向量[2,3,5,6,7,9]，取出T2 3中这些序号的元素值[0,1,1,1,0]，确定T2 3的所有比特的异或结果[1]，将T2 3中取出的这些元素值[0,1,1,1,0]和上述异或结果[1]按照先后顺序放入码字向量C中，得到C＝[0,1,1,1,0,1]。
最后，更新掩码向量M，例如，可以按照M＝M|(Vi)更新，M＝M|(Vi)＝[0,1,1,1,0,1,0,1,0,0]；
对校验部分矩阵P的第1、2、4、5列的读取及中间结果向量T1 i、中间结果向量T2 i、码字向量C和掩码向量M的变化过程如下：
读取矩阵P第1列，得到T1 1＝[0,0,0,0,1,0,1,0,1,0]，T2 1＝[0,0,1,0,0,1,0,0,1,0]，C＝[0,1,1,1,0,1,0,0,1,1]，M＝[0,1,1,1,1,1,1,1,1,0]；读取矩阵P第2列，得到 T1 2＝[0,0,0,0,0,0,0,0,0,1]，T2 2＝[0,0,1,1,0,1,0,0,0,1]，C＝[0,1,1,1,0,1,0,0,1,1,1,0]，M＝[0,1,1,1,1,1,1,1,1,1]；读取矩阵P第4列，得到T1 4＝[1,0,0,0,0,0,0,0,0,0]，T2 4＝[1,0,1,1,0,0,0,0,1,0]，C＝[0,1,1,1,0,1,0,0,1,1,1,0,1,0]，M＝[1,1,1,1,1,1,1,1,1,1]；读取矩阵P第5列，得到T1 5＝[0,0,0,0,0,0,0,0,0,0]，T2 5＝[1,0,0,1,0,1,0,0,0,1]，C＝[0,1,1,1,0,1,0,0,1,1,1,0,1,0,0]，M＝[1,1,1,1,1,1,1,1,1,1]。
5)、获得校验编码码字C＝[0,1,1,1,0,1,0,0,1,1,1,0,1,0,0]。
通过上述图3和图5所示的编码方法，本申请实施例可以将校验编码码字实现交织，校验比特穿插于信息比特之间，当接收端采用顺序译码时，每译码出校验比特，即可进行校验，若校验不通过，可以提前结束译码，有助于避免在信道译码结束后再进行校验造成了译码资源浪费的问题，缩短了译码所用时长，提高了译码的效率。并且，采用本申请实施例提供的方法，可以更简单的实现校验编码码字的交织，有效的节省了硬件开销，有助于提高编码资源的利用率。
基于图3或图5所示的编码方法的同一发明构思，如图6所示，本申请实施例中还提供一种编码装置600，编码装置600用于执行图3或图5所示的编码方法，编码装置600包括：
接收单元601，用于获取待编码信息；
处理单元602，用于对待编码信息进行校验编码，获得校验编码码字，校验编码码字包括信息比特和校验比特，信息比特的长度为K，校验比特的长度为J；
处理单元602，还用于对校验编码码字进行交织操作；其中，交织操作所采用的交织序列S包括J个子序列，第i个子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；
处理单元602，还用于对交织操作后的校验编码码字进行Polar编码。
可选的，处理单元602用于：对编码码字进行交织操作之前，计算交织序列S；或者，离线计算并存储交织序列S，按照存储的交织序列S对编码码字进行交织操作。
可选的，J个子序列中i取值的顺序包括：按照i值从小到大的顺序，或者，按照i值从大到小的顺序，或者，按照列向量V i中元素1的个数从少到多的顺序，或者，按照列向量V i中元素1的个数从多到少的顺序。
基于图3或图5所示的编码方法的同一发明构思，如图7所示，本申请实施例中还提供一种编码装置700，编码装置700用于执行图3或图5所示的编码方法，编码装置700包括：
接收单元701，用于获取待编码信息向量U；
处理单元702，用于计算校验编码的系统形式生成矩阵G，并提取G中的校验部分矩阵P；
处理单元702，还用于初始化掩码向量M、第一中间结果向量T1 i、第二中间结果向量T2 i和校验编码码字C；
处理单元702，还用于按照设定的顺序逐列读取校验部分矩阵P的列向量V i，每读取一个列向量V i，执行以下操作：T1 i＝(～M)&(V i)计算；U和V i进行逐比特与运算，得到T2 i；确定T1中元素为1的位置索引，将T2 i中位置索引对应的元素、和T2 i中所有元 素进行异或运算的结果记录于C的尾部，按照M＝M︱(V i)更新M，其中，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；
处理单元702，还用于对校验编码码字C进行Polar编码。
可选的，处理单元702用于：
按照列索引值从小到大的顺序，逐列读取校验部分矩阵的列向量V i，或者，
按照列索引值从大到小的顺序，逐列读取校验部分矩阵的列向量V i，或者，
按照列向量中元素1的个数从少到多的顺序，逐列读取校验部分矩阵的列向量V i；或者，按照列向量中元素1的个数从多到少的顺序，逐列读取校验部分矩阵的列向量V i。
基于图3或图5所示的编码方法的同一发明构思，如图8所示，本申请实施例中还提供一种编码装置800，该编码装置800用于执行图3或图5所示的编码方法。上述实施例的编码方法中的部分或全部可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，所述编码装置800包括：输入接口电路801，用于获取待编码信息；逻辑电路802，用于执行上述图3或图5所示的编码方法，具体请见前面方法实施例中的描述，此处不再赘述；输出接口电路803，用于输出Polar编码后的比特序列。
可选的，编码装置800在具体实现时可以是芯片或者集成电路。
可选的，当上述实施例的编码方法中的部分或全部通过软件来实现时，如图9所示，编码装置800包括：存储器901，用于存储程序；处理器902，用于执行存储器901存储的程序，当程序被执行时，使得编码装置800可以实现上述实施例提供的编码方法。
可选的，上述存储器901可以是物理上独立的单元，也可以如图10所示，存储器901与处理器902集成在一起。
可选的，当上述实施例的编码方法中的部分或全部通过软件实现时，编码装置800也可以只包括处理器902。用于存储程序的存储器901位于编码装置800之外，处理器902通过电路/电线与存储器901连接，用于读取并执行存储器901中存储的程序。
基于图3所示方法中接收端执行方法的同一发明构思，如图11所示，本申请实施例中还提供一种译码装置1100，该译码装置1100用于执行图3所示方法中接收端所执行方法。图3所示方法中接收端执行方法中的部分或全部可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，所述译码装置1100包括：输入接口电路1101，用于获取待译码的序列；逻辑电路1102，用于执行上述图3所述方法中接收端所执行方法，具体请见前面方法实施例中的描述，此处不再赘述；输出接口电路1103，用于输出解交织操作后的比特序列。
可选的，译码装置1100在具体实现时可以是芯片或者集成电路。
可选的，当图3所示方法中接收端执行方法中的部分或全部通过软件来实现时，如图12所示，译码装置1100包括：存储器1201，用于存储程序；处理器1202，用于执行存储器1201存储的程序，当程序被执行时，使得译码装置1100可以实现上述图3所示方法中接收端执行方法。
可选的，上述存储器1201可以是物理上独立的单元，也可以如图13所示，存储器1301与处理器1302集成在一起。
可选的，当图3所示方法中接收端执行方法中的部分或全部通过软件实现时，译码装置1100也可以只包括处理器1202。用于存储程序的存储器1201位于译码装置1100之外，处理器1202通过电路/电线与存储器1201连接，用于读取并执行存储器1201中存储的程 序。
本申请实施例提供了一种计算机存储介质，用于存储计算机程序，该计算机程序包括用于执行图3或图5所示的编码方法。
本申请实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行图3或图5所示的编码方法。
本申请实施例图8～图10所示的编码装置还可以是一种系统芯片，图11～图13所示的译码装置也可以是一种系统芯片。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种编码方法，其特征在于，包括：
    发送端对待编码信息进行校验编码，获得校验编码码字，所述校验编码码字包括信息比特和校验比特，信息比特的长度为K，校验比特的长度为J；
    所述发送端对所述校验编码码字进行交织操作；
    其中，所述交织操作所采用的交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；
    所述发送端对交织操作后的校验编码码字进行Polar编码。
  2. 如权利要求1所述的方法，其特征在于，所述发送端对所述编码码字进行交织操作之前，计算所述交织序列S；或者，
    所述发送端离线计算并存储所述交织序列S，所述发送端对所述编码码字进行交织操作，包括：所述发送端按照存储的所述交织序列S对所述编码码字进行交织操作。
  3. 如权利要求1或2所述的方法，其特征在于，所述J个子序列中i取值的顺序包括：
    按照i值从小到大的顺序，或者，
    按照i值从大到小的顺序，或者，
    按照列向量V i中元素1的个数从少到多的顺序，或者，
    按照列向量V i中元素1的个数从多到少的顺序。
  4. 一种编码方法，其特征在于，包括：
    发送端获取待编码信息向量U；
    所述发送端计算校验编码的系统形式生成矩阵G，并提取所述G中的校验部分矩阵P；
    所述发送端初始化掩码向量M、第一中间结果向量T1 i、第二中间结果向量T2 i和校验编码码字C；
    所述发送端按照设定的顺序逐列读取所述校验部分矩阵P的列向量V i，每读取一个列向量V i，执行以下操作：
    T1 i＝(～M)&(V i)计算；U和V i进行逐比特与运算，得到T2 i；确定T1 i中元素为1的位置索引，将T2 i中所述位置索引对应的元素、和T2 i中所有元素进行异或运算的结果记录于C的尾部，按照M＝M︱(V i)更新M，其中，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；
    所述发送端对所述校验编码码字C进行Polar编码。
  5. 如权利要求4所述的方法，其特征在于，所述发送端按照设定的顺序逐列读取所述校验部分矩阵P的列向量V i，包括：
    所述发送端按照列索引值从小到大的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，
    所述发送端按照列索引值从大到小的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，
    所述发送端按照列向量中元素1的个数从少到多的顺序，逐列读取所述校验部分矩阵的列向量V i；或者，
    所述发送端按照列向量中元素1的个数从多到少的顺序，逐列读取所述校验部分矩阵的列向量V i。
  6. 一种编码装置，其特征在于，包括：
    接收单元，用于获取待编码信息；
    处理单元，用于对待编码信息进行校验编码，获得校验编码码字，所述校验编码码字包括信息比特和校验比特，信息比特的长度为K，校验比特的长度为J；
    所述处理单元，还用于对所述校验编码码字进行交织操作；
    其中，所述交织操作所采用的交织序列S包括J个子序列，第i个所述子序列包括中间结果向量T i中元素为1的位置索引值和(K+i)的值，1≤i≤J，i为整数，T i＝(～M)&(V i)，M＝M︱(V i)，M为掩码向量，V i为校验部分矩阵P的列向量，P为校验编码的系统形式生成矩阵G的子矩阵，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；
    所述处理单元，还用于对交织操作后的校验编码码字进行Polar编码。
  7. 如权利要求6所述的装置，其特征在于，所述处理单元用于：
    对所述编码码字进行交织操作之前，计算所述交织序列S；或者，
    离线计算并存储所述交织序列S，按照存储的所述交织序列S对所述编码码字进行交织操作。
  8. 如权利要求6或7所述的装置，其特征在于，所述J个子序列中i取值的顺序包括：
    按照i值从小到大的顺序，或者，
    按照i值从大到小的顺序，或者，
    按照列向量V i中元素1的个数从少到多的顺序，或者，
    按照列向量V i中元素1的个数从多到少的顺序。
  9. 一种编码装置，其特征在于，包括：
    接收单元，用于获取待编码信息向量U；
    处理单元，用于计算校验编码的系统形式生成矩阵G，并提取所述G中的校验部分矩阵P；
    所述处理单元，还用于初始化掩码向量M、第一中间结果向量T1 i、第二中间结果向量T2 i和校验编码码字C；
    所述处理单元，还用于按照设定的顺序逐列读取所述校验部分矩阵P的列向量V i，每读取一个列向量V i，执行以下操作：
    T1 i＝(～M)&(V i)计算；U和V i进行逐比特与运算，得到T2 i；确定T1 i中元素为1的位置索引，将T2 i中所述位置索引对应的元素、和T2 i中所有元素进行异或运算的结果记录于C的尾部，按照M＝M︱(V i)更新M，其中，～表示逐比特取非运算，&表示逐比特与运算，︱表示逐比特或运算；
    所述处理单元，还用于对所述校验编码码字C进行Polar编码。
  10. 如权利要求9所述的装置，其特征在于，所述处理单元用于：
    按照列索引值从小到大的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，
    按照列索引值从大到小的顺序，逐列读取所述校验部分矩阵的列向量V i，或者，
    按照列向量中元素1的个数从少到多的顺序，逐列读取所述校验部分矩阵的列向量V i；或者，
    按照列向量中元素1的个数从多到少的顺序，逐列读取所述校验部分矩阵的列向量V i。
  11. 一种编码方法及装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1～5任一项所述的方法。
  12. 如权利要求11所述的方法，其特征在于，所述装置为芯片。
  13. 一种芯片，其特征在于，包括：
    输入接口电路，用于获取待编码信息向量U；
    逻辑电路，用于执行上述如权利要求1～5任一项所述的方法；
    输出接口电路，输出Polar编码后的比特序列。
  14. 一种计算机可读存储介质，其特征在于，所述计算机存储介质中存储有计算机可读指令，当计算机读取并执行所述计算机可读指令时，使得计算机执行如权利要求1-5任意一项所述的方法。
  15. 一种计算机程序产品，其特征在于，当计算机读取并执行所述计算机程序产品时，使得计算机执行如权利要求1-5任意一项所述的方法。
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