WO2018198710A1

WO2018198710A1 - Liquid crystal display panel and electronic device

Info

Publication number: WO2018198710A1
Application number: PCT/JP2018/014584
Authority: WO
Inventors: 広大徳増; 信弥稲毛; 信彦小田; 昌宏甲斐田; 津野　仁志
Original assignee: ソニー株式会社; ソニーセミコンダクタソリューションズ株式会社
Priority date: 2017-04-27
Filing date: 2018-04-05
Publication date: 2018-11-01
Also published as: JPWO2018198710A1; JP7110182B2

Abstract

A liquid crystal display panel provided with: a liquid crystal layer; transistors for driving the liquid crystal layer in each pixel, the transistors having a semiconductor film in which a channel region is provided; a first electrode electrically connected to the semiconductor film, the first electrode covering the channel region of the semiconductor film; a second electrode facing the first electrode; a third electrode electrically connected to the first electrode, the third electrode facing the first electrode with the second electrode therebetween; a wiring facing the semiconductor film with the third electrode therebetween, the wiring being disposed in a position superposed on the third electrode in plan view; and a shielding electrode provided between the wiring and the third electrode and electrically connected to the second electrode.

Description

Liquid crystal display panel and electronic equipment

This technology relates to a liquid crystal display panel and an electronic device having a transistor and a storage capacitor.

For example, a liquid crystal display panel is used as a light modulation element (light valve) in a projector (projection display device) or the like. The liquid crystal display panel has a liquid crystal layer between the pixel electrode and the counter substrate, and the potential of the pixel electrode is temporarily held in a storage capacitor (for example, Patent Documents 1 and 2). ).

JP2013-80040A JP 2010-237687 A

In such a liquid crystal display panel, image quality may be deteriorated due to coupling between a plurality of wirings.

Therefore, it is desirable to provide a liquid crystal display panel and an electronic device that can suppress the occurrence of image quality defects.

A liquid crystal display panel according to an embodiment of the present technology includes a semiconductor film provided with a liquid crystal layer and a channel region, a transistor that drives the liquid crystal layer for each pixel, a channel region of the semiconductor film, and a semiconductor A first electrode electrically connected to the membrane; a second electrode opposed to the first electrode; and a second electrode opposed to the first electrode and electrically connected to the first electrode The three electrodes are arranged in a position overlapping the third electrode in plan view, and are provided between the wiring facing the semiconductor film with the third electrode interposed therebetween, and between the wiring and the third electrode. And a shielding electrode electrically connected to the.

An electronic apparatus according to an embodiment of the present technology includes the liquid crystal display panel according to the embodiment of the present technology.

In the liquid crystal display panel and the electronic device according to the embodiment of the present technology, a storage capacitor is configured by the first electrode, the second electrode, and the third electrode that are arranged at positions overlapping each other in plan view. Here, since the shielding electrode is provided between the wiring to which the predetermined potential is supplied and the third electrode constituting the storage capacitor, the influence of the coupling from the wiring to the third electrode can be suppressed.

According to the liquid crystal display panel and the electronic device according to the embodiment of the present technology, since the shielding electrode is provided between the third electrode and the wiring, the influence of the coupling from the wiring to the third electrode is suppressed. Can do. Therefore, it is possible to suppress the occurrence of image quality defects.

The above content is an example of the present disclosure. The effects of the present disclosure are not limited to those described above, and may be other different effects or may include other effects.

It is a cross-sectional schematic diagram showing the schematic structure of the liquid crystal display panel which concerns on one embodiment of this technique. FIG. 2 is a schematic plan view illustrating a schematic configuration of a drive substrate illustrated in FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line III-III shown in FIG. FIG. 4 is a schematic sectional view taken along line IV-IV shown in FIG. 2. FIG. 3 is a schematic plan view illustrating a planar configuration of the shielding electrode illustrated in FIG. 2 together with a signal line. 6 is a schematic cross-sectional view illustrating a schematic configuration of a drive substrate according to Comparative Example 1. FIG. 10 is a schematic cross-sectional view illustrating a schematic configuration of a drive substrate according to Comparative Example 2. FIG. FIG. 7 is a diagram illustrating a leakage current of the storage capacitor illustrated in FIG. 2 and the storage capacitor illustrated in FIG. 6. It is a figure showing the longitudinal crosstalk of the drive board | substrate shown in FIG. 2, and the drive board | substrate shown in FIG. It is a figure for demonstrating the crosstalk value shown to FIG. 9A. It is a figure showing the structure of the projection type display apparatus with which the liquid crystal display panel shown in FIG. 1 is applied. It is a schematic diagram showing the whole structure of the light modulation element shown in FIG. It is a figure showing an example of the pixel circuit of the pixel shown in FIG.

Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. The description will be given in the following order.
1. 1. Embodiment A liquid crystal panel having a shielding electrode between a third electrode and a signal line (wiring). Application example Projection display

Embodiment
(Constitution)
FIG. 1 illustrates a schematic cross-sectional configuration of a liquid crystal display panel 1 according to an embodiment of the present technology. The liquid crystal display panel 1 is used, for example, as a light modulation element of a projection display device (projection display device 200 in FIG. 10 described later). The liquid crystal display panel 1 includes a liquid crystal layer 30 between a drive substrate 10 and a counter substrate 20 facing each other.

Between the driving substrate 10 and the liquid crystal layer 30, a planarizing layer 10P, a pixel electrode 10E, a protective layer 10C, and an alignment film 10AF are provided in this order from a position close to the driving substrate 10. Between the counter substrate 20 and the liquid crystal layer 30, a counter electrode 20E and an alignment film 20AF are provided in this order from a position close to the counter substrate 20. Polarizing plates 10PZ and 20PZ are bonded to the surfaces of the drive substrate 10 and the counter substrate 20 opposite to the opposing surfaces, respectively.

2 shows a schematic plan configuration of the drive substrate 10. FIG. 3 shows a cross-sectional configuration along the line III-III shown in FIG. 2, and FIG. 4 shows an IV-type shown in FIG. Each of the cross-sectional configurations along line IV is shown. The drive substrate 10 has, for example, a scanning line WSL, a transistor Tr, a storage capacitor Cs, a light shielding film 17, a shielding electrode 18, and a signal line DTL (wiring) in this order on the support substrate 11. A first interlayer insulating film IA between the scanning line WSL and the transistor Tr, a second interlayer insulating film IB between the transistor Tr and the storage capacitor Cs, and a third interlayer insulating film between the storage capacitor Cs and the shielding electrode 18. A fourth interlayer insulating film ID is provided between the IC, the shielding electrode 18 and the signal line DTL. The support substrate 11 is composed of a plate-like member such as quartz, glass, silicon, or a plastic film.

The scanning line WSL provided on the support substrate 11 extends along a predetermined direction (for example, the X direction and the Y direction in FIG. 2). The scanning line WSL is made of a low reflectance material such as tungsten silicide (WSi). It is preferable to use a silicide-based semiconductor material having conductivity for the scan line WSL. The scanning line WSL may be composed of tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), tantalum (Ta), or a silicide compound thereof. The thickness of the scanning line WSL (the size in the Y direction in FIGS. 3 and 4) is, for example, 200 nm. The scanning line WSL has a thickness of 30 nm to 400 nm, for example.

The first interlayer insulating film IA covers the scanning line WSL and is provided over the entire surface of the support substrate 11. The first interlayer insulating film IA is preferably planarized by, for example, a CMP (Chemical Mechanical Polishing) process. Since the first interlayer insulating film IA is planarized, workability when forming an upper layer pattern is improved. Therefore, the yield can be improved. The first interlayer insulating film IA is made of, for example, silicon oxide (SiO ₂ ).

The transistor Tr has the semiconductor film 12, the gate insulating film 13, and the gate electrode 14 in this order on the first interlayer insulating film IA. The transistor Tr is, for example, a TFT element having an LDD (Lightly Doped Drain) structure. The liquid crystal layer 30 is driven for each pixel by the transistor Tr.

The semiconductor film 12 is provided in a selective region on the first interlayer insulating film IA and extends in a predetermined direction (for example, the Y direction in FIG. 2). The semiconductor film 12 has a channel region 12a facing the gate electrode 14, and a pair of LDD regions 12b disposed on both sides of the channel region 12a and adjacent to the channel region 12a. By providing the LDD region 12b, leakage current when the transistor Tr is turned off can be reduced. A source / drain region of the semiconductor film 12 is provided outside the pair of LDD regions 12b (on the side opposite to the channel region 12a). The source region of the semiconductor film 12 is electrically connected to the signal line DTL, and the drain region of the semiconductor film 12 is electrically connected to the storage capacitor Cs. The semiconductor film 12 is made of, for example, amorphous silicon or crystalline silicon. The LDD region 12b is doped with, for example, an n-type impurity at a low concentration. The source / drain region has a lower resistance value (lower resistance) than that of the channel region 12a, for example, by being doped with an n-type impurity having a higher concentration than that of the LDD region 12b. The channel region 12a and the pair of LDD regions 12b of the semiconductor film 12 are disposed at positions facing the scanning line WSL.

The gate insulating film 13 is for electrically insulating the semiconductor film 12 and the gate electrode 14, and is provided between the semiconductor film 12 and the gate electrode 14. The gate insulating film 13 is made of, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiN). Such a gate insulating film 13 is formed by, for example, a thermal oxidation method or a CVD (Chemical Vapor Deposition) method.

The gate electrode 14 is provided on the gate insulating film 13 in a predetermined pattern. The gate electrode 14 has, for example, an “H” shape in plan view so as to straddle the semiconductor film 12 in the width direction (X direction in FIG. 2). Specifically, the gate electrode 14 includes a portion that overlaps the channel region 12 a of the semiconductor film 12 and exposes the LDD region 12 b in a plan view, and portions that extend on both sides of the semiconductor film 12 in parallel with the semiconductor film 12. Has been. The gate electrode 14 faces the scanning line WSL and is electrically connected to the scanning line WSL via connection holes H3 and H4 provided in the first interlayer insulating film IA. The connection holes H3 and H4 are disposed on both sides of the semiconductor film 12 in a plan view, for example.

The gate electrode 14 has, for example, a stacked structure in which a first conductive film 14A and a second conductive film 14B are stacked in order from a position close to the gate insulating film 13. The first conductive film 14A is made of, for example, a polysilicon film to which an impurity such as phosphorus (P) is added. The second conductive film 14B is made of a low reflectance material such as a tungsten silicide film. The thickness of the first conductive film 14A is, for example, 40 nm to 1000 nm, and the thickness of the second conductive film 14B is, for example, 30 nm to 400 nm. Thus, by providing the first conductive film 14 A between the light-shielding second conductive film 14 B and the gate insulating film 13, the second conductive film 14 B can be fixed to the gate insulating film 13. It is sufficient that at least the second conductive film 14B is buried in the connection holes H3 and H4. By providing the second conductive film 14B in the connection holes H3 and H4, the incidence of light on the channel region 12a and the LDD region 12b of the semiconductor film 12 can be suppressed. The gate electrode 14 is formed as follows, for example. First, the first conductive film 14 A is formed at a position facing the channel region 12 a of the semiconductor film 12. Subsequently, connection holes H3 and H4 are formed in the first interlayer insulating film IA by dry etching. Thereafter, a second conductive film 14B is formed on the region including the inside of the connection holes H3 and H4 and on the first conductive film 14A. Thereby, the gate electrode 14 is formed.

The second interlayer insulating film IB is provided on the entire surface of the support substrate 11 so as to cover the gate electrode 14. The second interlayer insulating film IB is made of, for example, silicon oxide, like the first interlayer insulating film IA.

The storage capacitor Cs is provided in a predetermined region on the second interlayer insulating film IB and covers the transistor Tr. Specifically, the storage capacitor Cs is provided at a position overlapping the semiconductor film 12 and the gate electrode 14 in plan view, and covers at least the channel region 12 a and LDD region 12 b of the semiconductor film 12 and the gate electrode 14. The storage capacitor Cs has, for example, the same width as the scanning line WSL, and is disposed at a position overlapping a part of the scanning line WSL in plan view. The channel region 12a and LDD region 12b of the semiconductor film 12 and the gate electrode 14 have their lower surfaces covered with the scanning lines WSL and their upper surfaces covered with the storage capacitor Cs.

The storage capacitor Cs includes the first electrode 15A, the dielectric film DFA (first dielectric film), the second electrode 16, the dielectric film DFB (second dielectric film), and the second interlayer insulating film IB. Three electrodes 15B are provided in this order (FIGS. 3 and 4). The first electrode 15A, the second electrode 16, and the third electrode 15B are disposed at positions overlapping each other in plan view, and the first electrode 15A and the third electrode 15B are electrically connected. That is, the storage capacitor Cs is a stacked capacitor. Thereby, it is possible to secure a large storage capacity while suppressing the occupied area.

The first electrode 15A is electrically connected to the drain region of the semiconductor film 12 through a connection hole H1 provided in the second interlayer insulating film IB. Therefore, a pixel potential is supplied to the first electrode 15A. The second electrode 16 faces the first electrode 15A with the dielectric film DFA in between. The second electrode 16 is electrically connected to the shield electrode 18 and is supplied with, for example, a common potential (Vcom potential). The third electrode 15B faces the first electrode 15A with the second electrode 16 therebetween, and the dielectric film DFB is disposed between the third electrode 15B and the second electrode 16. For example, a pixel potential is supplied to the third electrode 15B electrically connected to the first electrode 15A. The first electrode 15A, the second electrode 16, and the third electrode 15B are made of a polysilicon film to which an impurity such as phosphorus (P) is added. The dielectric films DFA and DFB are made of, for example, a silicon nitride film. The dielectric films DFA and DFB are preferably made of an insulating film having a dielectric constant higher than that of the silicon oxide film. The dielectric film DFA has, for example, the same planar shape as that of the second electrode 16, and the dielectric film DFB has, for example, the same planar shape as that of the third electrode 15B.

The light shielding film 17 on the storage capacitor Cs is for preventing light irradiation to the transistor Tr. For example, the light shielding film 17 has the same planar shape as the third electrode 15B, and is provided at a position overlapping the third electrode 15B in plan view. That is, the light shielding film 17 covers at least the channel region 12 a and the LDD region 12 b of the semiconductor film 12 and the gate electrode 14. The light shielding film 17 is made of, for example, a light-shielding refractory metal or a refractory metal silicide. An example of the light-shielding refractory metal is tungsten, and an example of the light-shielding refractory metal silicide is tungsten silicide.

The third interlayer insulating film IC is provided over the entire surface of the support substrate 11 so as to cover the light shielding film 17 and the storage capacitor Cs. The third interlayer insulating film IC is made of, for example, silicon oxide, like the first interlayer insulating film IA and the second interlayer insulating film IB. Providing the third interlayer insulating film IC having a thickness of 90 nm or more can suppress the occurrence of a breakdown voltage failure.

The third interlayer insulating film IC may be formed of a silicon nitride film having a thickness of 20 nm to 30 nm, for example. For example, the capacitance is held between the third electrode 15B and the shielding electrode 18 by using the third interlayer insulating film IC having a higher dielectric constant than that of the silicon oxide film. That is, the third electrode 15B and the shielding electrode 18 constitute a capacitive element.

FIG. 5 is a schematic plan view showing the shape of the shielding electrode 18 together with the storage capacitor Cs and the signal line DTL. The shield electrode 18 on the third interlayer insulating film IC is disposed between the storage capacitor Cs and the signal line DTL. For example, a common potential is supplied to the shield electrode 18 electrically connected to the second electrode 16 of the storage capacitor Cs. Although details will be described later, in the present embodiment, since the shielding electrode 18 is provided, the influence of the coupling from the signal line DTL to the storage capacitor Cs (third electrode 15B) can be suppressed.

The shielding electrode 18 covers, for example, at least the channel region 12a and the LDD region 12b of the semiconductor film 12 and the gate electrode 14. Such a shielding electrode 18 is made of, for example, a light-shielding refractory metal or a refractory metal silicide. An example of the light-shielding refractory metal is tungsten, and an example of the light-shielding refractory metal silicide is tungsten silicide. Thereby, irradiation of light to the transistor Tr can be more effectively prevented. The thickness of the shielding electrode 18 is, for example, 75 nm to 125 nm. For example, the shielding electrode 18 has a thickness of 100 nm.

The fourth interlayer insulating film ID is provided over the entire surface of the support substrate 11 so as to cover the shielding electrode 18. The fourth interlayer insulating film ID is made of, for example, silicon oxide, like the first interlayer insulating film IA, the second interlayer insulating film IB, and the third interlayer insulating film IC.

The signal line DTL on the fourth interlayer insulating film ID is disposed at a position overlapping the third electrode 15B in plan view, and the shielding electrode 18 is provided between the signal line DTL and the storage capacitor Cs as described above. It has been. The signal line DTL extends, for example, in a direction parallel to the extending direction of the semiconductor film 12 (Y direction in FIG. 2), and is provided to face the semiconductor film 12 with the shielding electrode 18 therebetween. . The signal line DTL is electrically connected to the source region of the semiconductor film 12 through a connection hole H2 that penetrates the fourth interlayer insulating film ID, the third interlayer insulating film IC, and the second interlayer insulating film IB. A signal line potential is supplied to the signal line DTL. The signal line DTL is made of a metal material such as tungsten silicide (WSi), aluminum (Al), titanium (Ti), or copper (Cu). The signal line DTL may be configured by a laminated film including a plurality of metals. The thickness of the signal line DTL is, for example, 100 nm to 1000 nm.

On the fourth interlayer insulating film ID, for example, a first connection wiring 19A and a second connection wiring 19B are provided in the same layer as the signal line DTL. The first connection wiring 19A is for electrically connecting the first electrode 15A and the third electrode 15B of the storage capacitor Cs. The first connection wiring 19A is electrically connected to the first electrode 15A and the third electrode 15B through connection holes H5 and H6 provided in the fourth interlayer insulating film ID and the third interlayer insulating film IC. The second connection wiring 19 B is for electrically connecting the second electrode 16 and the shielding electrode 18. The second connection wiring 19B is electrically connected to the shielding electrode 18 through the connection hole H7 provided in the fourth interlayer insulating film ID, and is provided in the fourth interlayer insulating film ID and the third interlayer insulating film IC. The second electrode 16 is electrically connected through the connection hole H8. For example, the first connection wiring 19A and the second connection wiring 19B are formed in the same process as the signal line DTL, are made of the same material as the signal line DTL, and have the same thickness.

The planarization layer 10P is for planarizing the surface of the drive substrate 10, and is provided on the entire surface of the drive substrate 10, for example. The planarizing layer 10P is made of, for example, an epoxy resin or an acrylic resin.

The pixel electrode 10E on the planarization layer 10P is provided for each pixel (pixel 2 in FIG. 11 described later), and is electrically connected to, for example, the transistor Tr. The pixel electrode 10E is made of, for example, a transparent conductive film. Examples of the transparent conductive film include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium gallium zinc-containing oxide (IGZO).

The protective layer 10C that covers the pixel electrode 10E plays a role of preventing the corrosion of the pixel electrode 10E. The protective layer 10C is preferably made of an inorganic material that is chemically more stable than the constituent materials of the alignment films 10AF and 20AF. Specifically, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiN) can be used as a constituent material of the protective layer 10C. The thickness of the protective layer 10C is, for example, 30 nm to 70 nm. The protective layer 10C is preferably formed using a method that is chemically more stable than vapor deposition, and can be formed by, for example, CVD or sputtering.

The alignment film 10AF is provided between the protective layer 10C and the liquid crystal layer 30, and the alignment film 20AF is provided between the counter electrode 20E and the liquid crystal layer 30. The alignment films 10AF and 20AF are for controlling the alignment of the liquid crystal layer 30 and are made of an inorganic material such as silicon oxide. The thickness of the alignment films 10AF and 20AF is, for example, about 120 nm to 360 nm. The alignment films 10AF and 20AF can be formed using, for example, a vapor deposition method.

The liquid crystal layer 30 is provided between the alignment film 10AF and the alignment film 20AF. For example, it is composed of liquid crystal driven in VA (Vertical Alignment) mode, TN (Twisted Nematic) mode, ECB (Electrically controlled ring birefringence) mode, FFS (Fringe Field Switching) mode or IPS (In Plane Switching) mode. ing.

The counter electrode 20E is provided in common to all pixels, for example, and is held at a common potential. A video voltage is supplied to the liquid crystal layer 30 by the counter electrode 20E and the pixel electrode 10E. For the counter electrode 20E, for example, a transparent conductive material can be used in the same manner as the pixel electrode 10E.

The counter substrate 20 is made of a plate-like member such as quartz, glass, silicon, or a plastic film, for example, like the support substrate 11. A color filter layer, a black matrix layer, an overcoat layer, and the like may be provided between the counter substrate 20 and the counter electrode 20E.

The polarizing plates 10PZ and 20PZ are arranged in, for example, a crossed Nicols, so that only light (polarized light) in a predetermined vibration direction can pass through the polarizing plates 10PZ and 20PZ.

(Operation)
In the liquid crystal display panel 1, the light transmittance in the liquid crystal layer 30 is controlled for each pixel, and light having a contrast corresponding to the input image signal is emitted. The transistor Tr is electrically connected to the pixel electrode 10E, and performs switching control of the pixel electrode 10E.

(Action / Effect)
In the liquid crystal display panel 1 of the present embodiment, the shielding electrode 18 (common potential) is provided between the signal line DTL sharing the signal line potential and the third electrode 15B (pixel potential) constituting the storage capacitor Cs. Therefore, the influence of the coupling from the signal line DTL to the third electrode 15B is reduced. Hereinafter, this will be described in detail using comparative examples (Comparative Examples 1 and 2).

FIG. 6 illustrates a schematic cross-sectional configuration of a drive substrate (drive substrate 101) according to Comparative Example 1. The drive substrate 101 has a storage capacitor Cs in which the first electrode 115A, the second electrode 116, and the third electrode 115B are stacked in this order. The first electrode 115A and the third electrode 115B are electrically connected via the first connection wiring 119A, and are held at a common potential, for example. The second electrode 116 is electrically connected to the semiconductor film 12 through the connection hole H100, and the second connection wiring 119B for supplying a pixel potential is electrically connected to the second electrode 116.

In such a drive substrate 101, since the second electrode 116 on the first electrode 115A is electrically connected to the semiconductor film 12, the first electrode 115A is patterned before the connection hole H100 is formed. When the first electrode 115A is patterned, the dielectric film DFA is contaminated by the resist. Alternatively, when the hydrofluoric acid treatment or the like is performed to remove the oxide film formed on the dielectric film DFA, the surface of the dielectric film DFA is damaged. Due to the resist contamination and the damage on the surface of the dielectric film DFA, there is a possibility that leakage occurs in the storage capacitor Cs. In order to suppress the influence of resist contamination and damage to the surface of the dielectric film DFA, the second electrode 116 may be formed in two steps, but in this case, the number of steps increases.

FIG. 7 shows a schematic cross-sectional configuration of a drive substrate (drive substrate 102) according to Comparative Example 2. In the storage capacitor Cs of the drive substrate 102, the first electrode 15A is electrically connected to the semiconductor film 12 through the connection hole H1. In such a drive substrate 102, since the second electrode 16 and the semiconductor film 12 are not connected, resist contamination and surface damage of the dielectric film DFA do not occur. However, the third electrode 15B (pixel potential) electrically connected to the first electrode 15A is affected by a vertical electric field from the signal line DTL (signal line potential), and coupling is likely to occur between them. For this reason, image quality such as crosstalk may occur in the drive substrate 102.

In contrast, in the present embodiment, since the shielding electrode 18 (common potential) is provided between the signal line DTL and the third electrode 15B, a vertical electric field from the signal line DTL to the third electrode 15B is generated. It is shielded and the coupling between them is less likely to occur. Thereby, in the liquid crystal display panel 1, the occurrence of image quality defects such as crosstalk due to the coupling between the signal line DTL and the third electrode 15B can be suppressed.

FIG. 8 shows the leakage current of the storage capacitor Cs between the drive substrate 10 and the drive substrate 101. In the drive substrate 10, the first electrode 15 A is electrically connected to the semiconductor film 12, so that it is possible to suppress the occurrence of a leakage current of the storage capacitor Cs due to resist contamination and damage to the surface of the dielectric film DFA.

FIG. 9A shows the vertical crosstalk between the driving substrate 10 and the driving substrate 102. The vertical axis in FIG. 9A represents the crosstalk value CTK (%) obtained by the following equation (1). Wi and Wi ′ in Expression (1) represent the luminance of adjacent windows around the black window, as shown in FIG. 9B. In the drive substrate 10, since the shielding electrode 18 is provided, the influence of the vertical electric field from the signal line DTL to the third electrode 15B is reduced, and the occurrence of vertical crosstalk can be suppressed.

CTK (%) = {(Wi′−Wi) / Wi} × 100 (1)

As described above, in the present embodiment, since the shielding electrode 18 is provided between the third electrode 15B (pixel potential) and the signal line DTL (signal line potential), the third electrode from the signal line DTL is provided. The influence of coupling to 15B can be suppressed. Therefore, it is possible to suppress the occurrence of image quality defects.

Furthermore, by using a light shielding material for the shielding electrode 18, the incidence of light in the oblique direction to the semiconductor film 12 can be suppressed, and the occurrence of light leakage can be suppressed. In addition, by providing the light shielding film 17 that covers the third electrode 15B, it is possible to more effectively suppress the incidence of light in the oblique direction to the semiconductor film 12.

In addition, since the first storage electrode 15A, the second electrode 16, and the third electrode 15B form a stacked storage capacitor Cs, it is possible to maintain a large capacity while reducing the occupied area. Therefore, the aperture ratio of the liquid crystal display panel 1 can be increased or the pitch can be reduced.

[Application example]
The liquid crystal display panel 1 of the present technology can be applied to an electronic device such as a projection display device.

FIG. 10 is a diagram illustrating a configuration example of a projection display device (projection display device 200) to which the liquid crystal display panel 1 is applied as a light modulation element. The projection display device 200 is a display device that projects an image on a screen, for example. The projection display device 200 is connected to an external image supply device such as a computer such as a PC or various image players via an I / F (interface), and is based on an image signal input to the I / F. Projection onto a screen or the like. The configuration of the projection display device 200 described below is an example, and the projection display device according to the present technology is not limited to such a configuration.

The projection display device 200 includes a light source 211, a multi-lens array 212, a PbS array 213, a focus lens 214, a mirror 215,

dichroic mirrors

216 and 217, light modulation elements 218a to 218c, a dichroic prism 219, and a projection lens 220. For example, the liquid crystal display panel 1 of the above-described embodiment is used for the light modulation elements 218a to 218c.

The light source 211 emits the light emitted by the light emitting unit 211a to the multi-lens array 212 by the reflector 211b. The multi-lens array 212 has a structure in which a plurality of lens elements are provided in an array, and condenses light emitted from the light source 211. The PbS array 213 polarizes the light collected by the multi-lens array 212 into light having a predetermined polarization direction, for example, a P-polarized wave. The focus lens 214 condenses the light converted into light having a predetermined polarization direction by the PbS array 213.

The dichroic mirror 216 transmits red light R out of light incident through the focus lens 214 and the mirror 215 and reflects green light G and blue light B. The red light R transmitted by the dichroic mirror 216 is guided to the light modulation element 218a through the mirror 215.

The dichroic mirror 217 transmits the blue light B out of the light reflected by the dichroic mirror 216 and reflects the green light G. The green light G reflected by the dichroic mirror 217 is guided to the light modulation element 218b. On the other hand, the blue light B transmitted by the dichroic mirror 217 is guided to the light modulation element 218 c via the mirror 215.

Each of the light modulation elements 218a to 218c light-modulates each incident color light, and the light-modulated color light enters the dichroic prism 219. The dichroic prism 219 synthesizes each color light that has been incident after being light-modulated into one optical axis. Each synthesized color light is projected onto a screen or the like via the projection lens 220.

FIG. 11 shows an example of the overall configuration of the light modulation elements 218a to 218c of FIG. The light modulation elements 218a to 218c include, for example, the above-described liquid crystal display panel 1 and a drive circuit 40 that drives the liquid crystal display panel 1. The drive circuit 40 includes a display control unit 41, a data driver 42, and a gate driver 43.

The liquid crystal display panel 1 has a pixel portion 1A in which a plurality of pixels 2 are formed in a matrix and a peripheral portion 1B. The liquid crystal display panel 1 displays an image based on a video signal Din input from the outside by actively driving each pixel 2 by a data driver 42 and a gate driver 43.

The liquid crystal display panel 1 includes a plurality of scanning lines WSL extending in the row direction, a plurality of signal lines DTL extending in the column direction, and a plurality of common potential lines COM extending in the row direction. . Pixels 2 are provided corresponding to the intersections between the signal lines DTL and the scanning lines WSL. Each signal line DTL is connected to an output end (not shown) of the data driver 42. Each scanning line WSL is connected to an output terminal (not shown) of the gate driver 43. Each common potential line COM is connected to, for example, an output terminal (not shown) of a circuit that outputs a fixed potential.

The display controller 41 stores, for example, the supplied video signal Din in a frame memory for each screen (for each display of one frame). For example, the display control unit 41 has a function of controlling the data driver 42 and the gate driver 43 that drive the liquid crystal display panel 1 to operate in conjunction with each other. Specifically, the display control unit 41 supplies, for example, a scanning timing control signal to the data driver 42, and the data driver 42 receives an image signal for one horizontal line based on the image signal held in the frame memory. A display timing control signal is supplied.

The data driver 42 supplies, for example, a video signal Din for one horizontal line supplied from the display control unit 41 to each pixel 2 as a signal voltage. Specifically, the data driver 42 supplies, for example, a signal voltage corresponding to the video signal Din to each pixel 2 constituting one horizontal line selected by the gate driver 43 via the signal line DTL. It is.

The gate driver 43 has a function of selecting the pixel 2 to be driven according to a scanning timing control signal supplied from the display control unit 41, for example. Specifically, the gate driver 43 applies, for example, a selection pulse to the gate electrode 14 of the transistor Tr of the pixel 2 via the scanning line WSL, thereby the pixel 2 formed in a matrix in the pixel portion 1A. One row is selected as a drive target. In these pixels 2, one horizontal line is displayed according to the signal voltage supplied from the data driver 42. In this way, for example, the gate driver 43 sequentially scans one horizontal line at a time in a time-division manner, and performs display over the entire display area.

Next, the circuit configuration of the pixel 2 will be described. FIG. 12 illustrates an example of a circuit configuration of the pixel 2. Each pixel 2 is provided with a pixel circuit 4. Each pixel circuit 4 is provided corresponding to the intersection of the scanning line WSL and the signal line DTL. The pixel circuit 4 includes a transistor Tr that writes a signal voltage to the pixel 2 and a storage capacitor Cs that holds the voltage written to the pixel 2. One of the storage capacitors Cs (first electrode 15A and third electrode 15B) is connected to the drain region of the semiconductor film 12, and the other (second electrode 16) is connected to the common potential line COM.

In the projection display device 200, three light modulation elements 218a to 218c corresponding to the three primary colors red, green, and blue are combined to display all colors. That is, the projection display device 200 is a so-called three-plate projection display device.

In addition to the projection display device, the liquid crystal display panel 1 includes a television device, a desktop personal computer monitor, a notebook personal computer, an imaging device such as a video camera and a digital still camera, a PDA (Personal Digital Assistant), a mobile phone. The present invention can also be applied to electronic devices such as telephones and smartphones.

Although the present technology has been described with reference to the embodiment, the present technology is not limited to the above-described embodiment, and various modifications can be made. For example, the components, arrangement, number, and the like of the liquid crystal display panel exemplified in the above embodiment are merely examples, and it is not necessary to include all the components, and may further include other components. .

In the above embodiment, a display panel having a liquid crystal layer as a display layer has been described as an example. However, the present invention is not limited to this, and the present invention is applied to other display layers such as an organic EL (Electro Luminescence) layer or an electrophoretic layer. It is also possible to do.

Furthermore, the semiconductor film 12 may be made of a material other than crystalline silicon and amorphous silicon, for example, an oxide semiconductor material or an organic semiconductor material.

It should be noted that the effects described in the present specification are merely examples and are not limited to these, and other effects may be obtained.

Note that the present technology may be configured as follows.
(1)
A liquid crystal layer;
A transistor having a semiconductor film provided with a channel region and driving the liquid crystal layer for each pixel;
A first electrode that covers the channel region of the semiconductor film and is electrically connected to the semiconductor film;
A second electrode facing the first electrode;
A third electrode opposed to the first electrode with the second electrode in between and electrically connected to the first electrode;
In a plan view, the wiring is disposed at a position overlapping the third electrode, and the wiring is opposed to the semiconductor film with the third electrode in between.
A liquid crystal display panel, comprising: a shielding electrode provided between the wiring and the third electrode and electrically connected to the second electrode.
(2)
The liquid crystal display panel according to (1), wherein the shielding electrode is made of a light shielding material.
(3)
The liquid crystal display panel according to (1) or (2), further including a connection wiring that connects the shielding electrode and the second electrode.
(4)
The liquid crystal display panel according to (3), wherein the connection wiring is provided in the same layer as the wiring.
(5)
The wiring is held at the signal line potential,
The liquid crystal display panel according to (3) or (4), wherein a common potential is supplied to the connection wiring.
(6)
A gate electrode provided in the transistor;
The liquid crystal display panel according to any one of (1) to (5), including a scanning line facing the gate electrode with the semiconductor film interposed therebetween.
(7)
The liquid crystal display panel according to any one of (1) to (6), wherein the semiconductor film has an LDD (Lightly Doped Drain) region adjacent to the channel region.
(8)
The liquid crystal display panel according to (6), wherein the gate electrode includes, in order from a position close to the semiconductor film, a first conductive film containing polysilicon and a second conductive film having a light shielding property.
(9)
A first dielectric film between the first electrode and the second electrode;
The liquid crystal display panel according to any one of (1) to (8), including a second dielectric film between the second electrode and the third electrode.
(10)
The liquid crystal display panel according to any one of (1) to (9), further including a light shielding film that covers the third electrode.
(11)
The liquid crystal display panel according to any one of (1) to (10), wherein the first electrode, the second electrode, and the third electrode include polysilicon.
(12)
With a liquid crystal display panel,
The liquid crystal display panel is
A liquid crystal layer;
A transistor having a semiconductor film provided with a channel region and driving the liquid crystal layer for each pixel;
A first electrode that covers the channel region of the semiconductor film and is electrically connected to the semiconductor film;
A second electrode facing the first electrode;
A third electrode opposed to the first electrode with the second electrode in between and electrically connected to the first electrode;
In a plan view, the wiring is disposed at a position overlapping the third electrode, and the wiring is opposed to the semiconductor film with the third electrode in between.
An electronic device comprising: a shielding electrode provided between the wiring and the third electrode and electrically connected to the second electrode.
Solid-state imaging device.

This application claims priority on the basis of Japanese Patent Application No. 2017-87947 filed on April 27, 2017 at the Japan Patent Office. The entire contents of this application are incorporated herein by reference. This is incorporated into the application.

Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims

A liquid crystal layer;
A transistor having a semiconductor film provided with a channel region and driving the liquid crystal layer for each pixel;
A first electrode that covers the channel region of the semiconductor film and is electrically connected to the semiconductor film;
A second electrode facing the first electrode;
A third electrode opposed to the first electrode with the second electrode in between and electrically connected to the first electrode;
In a plan view, the wiring is disposed at a position overlapping the third electrode, and the wiring is opposed to the semiconductor film with the third electrode in between.
A liquid crystal display panel, comprising: a shielding electrode provided between the wiring and the third electrode and electrically connected to the second electrode.
The liquid crystal display panel according to claim 1, wherein the shielding electrode is made of a light shielding material.
The liquid crystal display panel according to claim 1, further comprising a connection wiring that connects the shielding electrode and the second electrode.
The liquid crystal display panel according to claim 3, wherein the connection wiring is provided in the same layer as the wiring.
The wiring is held at the signal line potential,
The liquid crystal display panel according to claim 3, wherein a common potential is supplied to the connection wiring.
A gate electrode provided in the transistor;
The liquid crystal display panel according to claim 1, further comprising a scanning line facing the gate electrode with the semiconductor film interposed therebetween.
The liquid crystal display panel according to claim 1, wherein the semiconductor film has an LDD (Lightly Doped Drain) region adjacent to the channel region.
The liquid crystal display panel according to claim 6, wherein the gate electrode includes, in order from a position close to the semiconductor film, a first conductive film containing polysilicon and a second conductive film having a light shielding property.
A first dielectric film between the first electrode and the second electrode;
The liquid crystal display panel according to claim 1, comprising a second dielectric film between the second electrode and the third electrode.
The liquid crystal display panel according to claim 1, further comprising a light-shielding film that covers the third electrode.
The liquid crystal display panel according to claim 1, wherein the first electrode, the second electrode, and the third electrode include polysilicon.
With a liquid crystal display panel,
The liquid crystal display panel is
A liquid crystal layer;
A transistor having a semiconductor film provided with a channel region and driving the liquid crystal layer for each pixel;
A first electrode that covers the channel region of the semiconductor film and is electrically connected to the semiconductor film;
A second electrode facing the first electrode;
A third electrode opposed to the first electrode with the second electrode in between and electrically connected to the first electrode;
In a plan view, the wiring is disposed at a position overlapping the third electrode, and the wiring is opposed to the semiconductor film with the third electrode in between.
An electronic device comprising: a shielding electrode provided between the wiring and the third electrode and electrically connected to the second electrode.