WO2018190166A1 - Dispositif d'imagerie à semi-conducteurs et appareil électronique - Google Patents

Dispositif d'imagerie à semi-conducteurs et appareil électronique Download PDF

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Publication number
WO2018190166A1
WO2018190166A1 PCT/JP2018/014066 JP2018014066W WO2018190166A1 WO 2018190166 A1 WO2018190166 A1 WO 2018190166A1 JP 2018014066 W JP2018014066 W JP 2018014066W WO 2018190166 A1 WO2018190166 A1 WO 2018190166A1
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WO
WIPO (PCT)
Prior art keywords
wiring
pixel
drain
source
transistor
Prior art date
Application number
PCT/JP2018/014066
Other languages
English (en)
Inventor
Yukio Tagawa
Koji Yoshikawa
Yuhi Yorikado
Koichi Baba
Original Assignee
Sony Semiconductor Solutions Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2017155550A external-priority patent/JP7055603B2/ja
Application filed by Sony Semiconductor Solutions Corporation filed Critical Sony Semiconductor Solutions Corporation
Priority to CN201880022655.5A priority Critical patent/CN110520995A/zh
Priority to US16/500,571 priority patent/US20200105808A1/en
Priority to EP18718532.7A priority patent/EP3610509A1/fr
Priority to KR1020197028826A priority patent/KR20190138785A/ko
Publication of WO2018190166A1 publication Critical patent/WO2018190166A1/fr

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    • H01L27/14636—
    • H01L27/14609—
    • H01L27/14643—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • an imaging device includes a plurality of pixels.
  • a pixel of the plurality of pixels includes: a first wiring coupled to a floating diffusion; a second wiring opposed to the first wiring such that a wiring capacitance is formed; a pixel amplifier with a feedback capacitance that is based on the wiring capacitance; a vertical signal line arranged to output a signal from the floating diffusion; a first transistor comprising a source and a drain; a second transistor comprising a source and a drain, wherein the source of the second transistor is coupled to an output of the pixel amplifier and the drain of the second transistor is coupled to the vertical signal line; and a third transistor comprising a source and a drain, wherein the source of the third transistor is coupled to the floating diffusion and the drain of the third transistor is coupled to a reset line.
  • the wiring capacitance is formed between the floating diffusion and the drain of the third transistor.
  • an amplifier that includes a transistor.
  • the transistor includes a gate and an asymmetric source-drain structure.
  • the asymmetric source-drain structure includes a source region comprising: a first region including an impurity with a first concentration; and a second region including an impurity with a second concentration larger than the first concentration.
  • the asymmetric source-drain structure also includes a drain region comprising: a third region including an impurity with a third concentration larger than the first concentration.
  • Fig. 1 is a diagram showing a configuration example of an embodiment of a solid-state imaging device to which the present technology is applied.
  • Fig. 2 is a diagram describing conversion efficiency of a pixel amplifier.
  • Fig. 3 is a diagram describing a feedback capacitance including a parasitic capacitance of an amplification transistor.
  • Fig. 4 is a diagram describing a relationship between conversion efficiency of a pixel to which a differential pixel amplifier is applied and output variation in a read signal (PRNU).
  • Fig. 5 is a circuit diagram showing a configuration example of a source-grounded inversion amplification pixel amplifier.
  • Fig. 6 is a circuit diagram showing a configuration example of a differential inversion amplification pixel amplifier.
  • Fig. 1 is a diagram showing a configuration example of an embodiment of a solid-state imaging device to which the present technology is applied.
  • Fig. 2 is a diagram describing conversion efficiency of a pixel amplifier.
  • Fig. 3 is
  • the input/output terminal 17 transmits/receives signals to/from the outside.
  • ⁇ V VSL and ⁇ V VSL respectively represent variation in the output signal ( ⁇ V VSL ) in the vertical signal line (VSL) and the standard deviation thereof, and ⁇ > represents the expected value.
  • Fig. 4 represents that as the gate width Wg of the amplification transistor (AMP-Tr) becomes narrower, the conversion efficiency increases and PRNU becomes larger. That is, there is a trade-off relationship between increasing the conversion efficiency and improving PRNU by narrowing the gate width Wg (narrowing Wg).
  • the reference pixel 300 is desirably a pixel in which the potential fluctuation of the terminal (FD terminal) of the floating diffusion 321 at the time of resetting is equivalent to the potential fluctuation of the terminal (FD terminal) of the floating diffusion 221 of the read pixel 200.
  • the reference pixel 300 an inactive effective pixel that has finished reading and is arranged in the vicinity of the read pixel 200 in the pixel array unit 11 (Fig. 1) can be used. In this case, the roles of the read pixel 200 and the reference pixel 300 in Fig. 6 are switched by the switched provided in the column signal processing circuit 13 (Fig. 1).
  • differential reading it is desirable to perform, for example, source-follower-type reading with a large dynamic range in the light state, because high conversion efficiency can be achieved. That is, in some cases, more appropriate reading can be performed by appropriately switching differential reading (hereinafter, referred to as the differential mode) and source-follower-type reading (hereinafter, referred to as the SF mode).
  • differential mode differential reading
  • SF mode source-follower-type reading
  • FIG. 8 is a circuit diagram showing a configuration example of a pixel amplifier that performs reading in the SF mode.
  • the switches SW1 to SW9 perform a switching operation in the pixel peripheral unit 400, and thus, the reading in the differential mode and the reading in the SF mode can be easily switched. For example, in the light state, it is possible to switch to the source-follower-type reading with a large dynamic range.
  • Fig. 12 is a circuit diagram showing a pixel to which the wiring capacitance between FD-VSL of the type 2 is added.
  • the LDD 114B-D on the drain side is formed by using ion species having small diffusion such as arsenic (As). Meanwhile, in the LDD 114B-S on the source side, phosphorous (P) is formed so as to cover arsenic (As) formed inside.
  • the following structures can be adopted as the structure of the amplification transistor 114, for example.
  • the amplification transistor to which an embodiment of the present technology is applied for example, in the case of assuming the current direction corresponding to the differential mode in a circuit system that realizes a plurality of functions by using the amplification transistor in which the current flowing direction is different, it is possible to cope with the variation in characteristics depending on the current flowing direction because the LDD region on the source side is formed to spread below the gate and to be wider than the LDD region on the drain side.
  • Fig. 34 is a block diagram showing an example of a schematic configuration of a vehicle control system, which is an example of a movable object control system to which the technology according to the present disclosure is applied.
  • a solid-state imaging device including: a pixel array unit, pixels being two-dimensionally arranged in the pixel array unit, the pixels each including a photoelectric conversion unit, in which the pixels each include a first wiring and a second wiring opposed to each other, the first wiring being connected to a floating diffusion, a charge detected by the photoelectric conversion unit being transferred to the floating diffusion, the second wiring being connected to a vertical signal line for outputting a signal from the floating diffusion, a feedback capacitance of a pixel amplifier being adjusted by capacitance addition by opposite wirings including the first wiring and the second wiring.
  • the pixel amplifier is a source-grounded inversion amplification pixel amplifier.
  • An electronic apparatus including: a solid-state imaging device including a pixel array unit, pixels being two-dimensionally arranged in the pixel array unit, the pixels each including a photoelectric conversion unit, in which the pixels each include a first wiring and a second wiring opposed to each other, the first wiring being connected to a floating diffusion, a charge detected by the photoelectric conversion unit being transferred to the floating diffusion, the second wiring being connected to a vertical signal line for outputting a signal from the floating diffusion, a feedback capacitance of a pixel amplifier being adjusted by capacitance addition by opposite wirings including the first wiring and the second wiring.
  • An imaging device including a plurality of pixels, a pixel of the plurality of pixels including: a first wiring coupled to a floating diffusion; a second wiring opposed to the first wiring such that a wiring capacitance is formed; a pixel amplifier with a feedback capacitance that is based on the wiring capacitance; a vertical signal line arranged to output a signal from the floating diffusion; a first transistor comprising a source and a drain; and a second transistor comprising a source and a drain, in which the source of the second transistor is coupled to an output of the pixel amplifier and the drain of the second transistor is coupled to the vertical signal line, in which the wiring capacitance is formed between the floating diffusion and the source of the second transistor.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

L'invention concerne un dispositif d'imagerie comprenant une pluralité de pixels (200-1). Un pixel (200-1) de la pluralité de pixels comprend : un premier câblage connecté à une diffusion flottante (221) ; un deuxième câblage opposé au premier câblage de telle sorte qu'une capacité de câblage (Cfd-vsl) est formée ; un amplificateur de pixel (214) ayant une capacité de rétroaction qui est basée sur la capacité de câblage ; et une ligne de signal verticale (22) disposée de manière à délivrer un signal à partir de la diffusion flottante. La capacité de câblage est formée entre la diffusion flottante et la ligne de signal verticale.
PCT/JP2018/014066 2017-04-11 2018-04-02 Dispositif d'imagerie à semi-conducteurs et appareil électronique WO2018190166A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201880022655.5A CN110520995A (zh) 2017-04-11 2018-04-02 固态摄像装置和电子设备
US16/500,571 US20200105808A1 (en) 2017-04-11 2018-04-02 Solid-state imaging device and electronic apparatus
EP18718532.7A EP3610509A1 (fr) 2017-04-11 2018-04-02 Dispositif d'imagerie à semi-conducteurs et appareil électronique
KR1020197028826A KR20190138785A (ko) 2017-04-11 2018-04-02 고체 촬상 장치 및 전자 기기

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2017078183 2017-04-11
JP2017-078183 2017-04-11
JP2017-155550 2017-08-10
JP2017155550A JP7055603B2 (ja) 2017-04-11 2017-08-10 固体撮像装置、及び、電子機器

Publications (1)

Publication Number Publication Date
WO2018190166A1 true WO2018190166A1 (fr) 2018-10-18

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Application Number Title Priority Date Filing Date
PCT/JP2018/014066 WO2018190166A1 (fr) 2017-04-11 2018-04-02 Dispositif d'imagerie à semi-conducteurs et appareil électronique

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WO (1) WO2018190166A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117631740A (zh) * 2024-01-25 2024-03-01 芯聚威科技(成都)有限公司 一种差分参考电压产生电路及电子设备

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US6445022B1 (en) * 1999-04-23 2002-09-03 Micron Technology, Inc. Increasing pixel conversion gain in CMOS image sensors
US20050121519A1 (en) * 2003-12-05 2005-06-09 Canon Kabushiki Kaisha Solid state image pickup device, method of driving solid state image pickup device, and camera using the solid state image pickup device
JP2005278041A (ja) 2004-03-26 2005-10-06 Sharp Corp 増幅型固体撮像装置
US20080258047A1 (en) * 2007-04-23 2008-10-23 Sony Corporation Solid-state image pickup device, a method of driving the same, a signal processing method for the same, and image pickup apparatus
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EP2333835A2 (fr) * 2008-09-29 2011-06-15 Crosstek Capital, LLC Transistor, capteur optique equipe d'un tel transistor et procede de fabrication associe
JP2013045878A (ja) 2011-08-24 2013-03-04 Sony Corp 固体撮像装置、固体撮像装置の製造方法、電子機器
JP2013069913A (ja) 2011-09-22 2013-04-18 Renesas Electronics Corp 半導体装置およびその製造方法
US20150076327A1 (en) * 2012-05-30 2015-03-19 Panasonic Intellectual Property Management Co., Ltd. Solid-state imaging apparatus, method for driving the same, and imaging apparatus
US20150380451A1 (en) * 2014-06-25 2015-12-31 Semiconductor Energy Laboratory Co., Ltd. Imaging device, monitoring device, and electronic appliance
WO2016030801A1 (fr) * 2014-08-29 2016-03-03 Semiconductor Energy Laboratory Co., Ltd. Dispositif d'imagerie et dispositif électronique
US20160191825A1 (en) * 2014-12-26 2016-06-30 Panasonic Intellectual Property Management Co., Ltd. Imaging device including unit pixel cell
US20160204159A1 (en) * 2009-11-30 2016-07-14 Sony Corporation Solid state imaging device and electronic apparatus
US20160268335A1 (en) * 2015-03-09 2016-09-15 Semiconductor Components Industries, Llc Image sensor with buried-channel drain (bcd) transistors

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6445022B1 (en) * 1999-04-23 2002-09-03 Micron Technology, Inc. Increasing pixel conversion gain in CMOS image sensors
US20050121519A1 (en) * 2003-12-05 2005-06-09 Canon Kabushiki Kaisha Solid state image pickup device, method of driving solid state image pickup device, and camera using the solid state image pickup device
JP2005278041A (ja) 2004-03-26 2005-10-06 Sharp Corp 増幅型固体撮像装置
US20080258047A1 (en) * 2007-04-23 2008-10-23 Sony Corporation Solid-state image pickup device, a method of driving the same, a signal processing method for the same, and image pickup apparatus
EP2065938A2 (fr) * 2007-11-30 2009-06-03 Sony Corporation Dispositif d'imagerie à l'état solide et caméra
EP2333835A2 (fr) * 2008-09-29 2011-06-15 Crosstek Capital, LLC Transistor, capteur optique equipe d'un tel transistor et procede de fabrication associe
US20160204159A1 (en) * 2009-11-30 2016-07-14 Sony Corporation Solid state imaging device and electronic apparatus
JP2013045878A (ja) 2011-08-24 2013-03-04 Sony Corp 固体撮像装置、固体撮像装置の製造方法、電子機器
JP2013069913A (ja) 2011-09-22 2013-04-18 Renesas Electronics Corp 半導体装置およびその製造方法
US20150076327A1 (en) * 2012-05-30 2015-03-19 Panasonic Intellectual Property Management Co., Ltd. Solid-state imaging apparatus, method for driving the same, and imaging apparatus
US20150380451A1 (en) * 2014-06-25 2015-12-31 Semiconductor Energy Laboratory Co., Ltd. Imaging device, monitoring device, and electronic appliance
WO2016030801A1 (fr) * 2014-08-29 2016-03-03 Semiconductor Energy Laboratory Co., Ltd. Dispositif d'imagerie et dispositif électronique
US20160191825A1 (en) * 2014-12-26 2016-06-30 Panasonic Intellectual Property Management Co., Ltd. Imaging device including unit pixel cell
US20160268335A1 (en) * 2015-03-09 2016-09-15 Semiconductor Components Industries, Llc Image sensor with buried-channel drain (bcd) transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117631740A (zh) * 2024-01-25 2024-03-01 芯聚威科技(成都)有限公司 一种差分参考电压产生电路及电子设备
CN117631740B (zh) * 2024-01-25 2024-05-10 芯聚威科技(成都)有限公司 一种差分参考电压产生电路及电子设备

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