WO2018188283A1 - 一种信息处理的方法及电子设备 - Google Patents

一种信息处理的方法及电子设备 Download PDF

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WO2018188283A1
WO2018188283A1 PCT/CN2017/104600 CN2017104600W WO2018188283A1 WO 2018188283 A1 WO2018188283 A1 WO 2018188283A1 CN 2017104600 W CN2017104600 W CN 2017104600W WO 2018188283 A1 WO2018188283 A1 WO 2018188283A1
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slot
backplane
bus
pci
interface
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French (fr)
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万超
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Lenovo Beijing Ltd
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Lenovo Beijing Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • the present disclosure relates to the field of computers, and in particular, to a method and an electronic device for information processing.
  • the embodiments of the present disclosure provide a method and an electronic device for processing information to implement management of an NVM e storage device.
  • the SAS interface is further disposed on the backplane, the method further includes: acquiring a second instruction, where the second instruction is used to obtain a bus slot number corresponding to the SAS interface on the backplane;
  • the second instruction is configured to send a second slot view signal to a RAID (Redundant Array of Independent Disk) controller, where the second slot view signal is used to instruct the RAID controller to acquire the SAS
  • the number of the corresponding slot number is determined according to the group label, and the number of the bus slot corresponding to the slot of the backplane where the SAS interface is located from the RAID controller is received, where
  • the bus slot number corresponding to the slot of the backplane of the SAS interface and the slot number corresponding to the slot of the backplane of the PCI-E bus interface are sequentially numbered.
  • the obtaining, according to the mapping relationship, the bus slot number corresponding to the slot of the backplane of the PCI-E bus interface including: obtaining the back of the slot of the backplane where the PCI-E bus interface is located The number of the slot number corresponding to the slot number of the backplane slot of the PCI-E bus interface is obtained according to the mapping relationship.
  • an embodiment of the present disclosure provides an electronic device, including: a processor, an FPGA, a backplane, and at least one PCI-E bus interface disposed on the backplane.
  • a processor configured to acquire a first instruction, where the first instruction is used to obtain a bus slot number corresponding to the PCI-E bus interface on the backplane; and execute the first instruction to send to the FPGA
  • the first slot view signal is further configured to receive a mapping relationship between the pre-stored bus slot number from the FPGA and the backplane slot number; and obtain the PCI-E bus interface according to the mapping relationship Number of the bus slot corresponding to the slot on the backplane.
  • An FPGA configured to receive the first slot view signal; and send the pre-stored mapping relationship to the processor in response to the first slot view signal sent by the processor.
  • the electronic device further includes: a RAID controller, and a SAS interface disposed on the backplane.
  • the processor is further configured to acquire a second instruction, where the second instruction is used to obtain a bus slot number corresponding to the SAS interface, and execute the second instruction to send a second slot view signal to the RAID controller.
  • a bus slot number corresponding to the slot of the backplane slot of the SAS interface where the slot number of the backplane slot of the SAS interface is corresponding to the PCI-
  • the bus slot number corresponding to the slot of the backplane of the E bus interface is sequentially numbered; the RAID controller is configured to receive the second slot view signal; and in response to the second slot view signal, the slave The backplane obtains the group number corresponding to the slot of the backplane where the SAS interface is located; determines the corresponding bus slot number according to the group label; and sends the group label to determine the corresponding bus slot number to the processor.
  • the processor is further configured to obtain a backplane slot number of a slot of the backplane where the PCI-E bus interface is located; and obtain, according to the mapping relationship, a backplane where the PCI-E bus interface is located Number of the bus slot corresponding to the slot number of the slot in the slot.
  • the PCI-E bus interface is connected to the NVMe storage device.
  • FIG. 1A schematically shows a schematic structural diagram of an electronic device according to an embodiment of the present disclosure
  • FIG. 1B is a schematic structural diagram of an electronic device according to another embodiment of the present disclosure.
  • FIG. 2 is a schematic flow chart showing a method of information processing according to an embodiment of the present disclosure
  • FIG. 4 schematically shows a flow chart of a processor side information processing method according to an embodiment of the present disclosure.
  • the techniques of this disclosure may be implemented in the form of hardware and/or software (including firmware, microcode, etc.). Additionally, the techniques of this disclosure may take the form of a computer program product on a computer readable medium storing instructions for use by or in connection with an instruction execution system.
  • a computer readable medium can be any medium that can contain, store, communicate, propagate or transport the instructions.
  • a computer readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium.
  • the computer readable medium include: a magnetic storage device such as a magnetic tape or a hard disk (HDD); an optical storage device such as a compact disk (CD-ROM); a memory such as a random access memory (RAM) or a flash memory; and/or a wired /Wireless communication link.
  • a magnetic storage device such as a magnetic tape or a hard disk (HDD)
  • an optical storage device such as a compact disk (CD-ROM)
  • a memory such as a random access memory (RAM) or a flash memory
  • RAM random access memory
  • the backplane when the backplane is simultaneously connected to the SATA/SAS storage device and the NVMe storage device, a fixed number is reserved for the NVMe storage device.
  • the backplane supports four SATA/SAS storage devices and two NVMes.
  • the first four Slot IDs are 0 to 3.
  • the last two Slot IDs are NVMe storage devices.
  • the reserved Slot ID is larger in order to ensure that the Slot ID does not conflict with the SATA/SAS storage device. It can be 64 to 65.
  • the Slot ID of the NVMe storage device is located in the middle of the Slot ID of the SATA/SAS storage device, causing the Slot ID to be discontinuous.
  • the Slot IDs of the devices on the backplane are Slot0, Slot1, Slot64, Slot65, Slot2, and Slot3.
  • the NVMe storage device may be a NVMe protocol storage device, such as an NVMe mechanical hard disk, an NVMe solid state hard disk, or the like;
  • the SATA/SAS storage device is a SATA/SAS interface storage device, such as a SATA/SAS mechanical hard disk. , SATA/SAS solid state drives, etc.
  • other devices may be used, and the embodiments of the present disclosure are not specifically limited.
  • FIG. 1A schematically shows a schematic structural view of an electronic device according to an embodiment of the present disclosure.
  • the electronic device 10 includes a processor 11, an FPGA 12, a backplane 13, and at least one PCI-E bus interface 14 disposed on the backplane 13.
  • the processor and the FPGA are disposed on a motherboard of the electronic device, and the backplane is provided with at least one backplane slot (Bay), and at least one PCI-E is disposed in each backplane slot.
  • FIG. 2 schematically shows a schematic flow chart of a method of information processing according to an embodiment of the present disclosure.
  • the method includes:
  • S201 The processor acquires the first instruction.
  • the first instruction is used to obtain a bus slot number corresponding to the PCI-E bus interface on the backplane.
  • the user may input an acquisition command on the NVMe management tool, and at this time, the processor obtains The first instruction for obtaining the Slot ID corresponding to the PCI-E bus interface on the backplane.
  • S202 The processor executes the first instruction to send the first slot view signal to the FPGA.
  • the processor executes the first instruction described above, generates a first slot view signal, and transmits the signal to the FPGA.
  • the FPGA After receiving the first slot view signal sent by the processor, the FPGA sends a mapping relationship between the pre-stored bus slot number and the backplane slot number to the processor in response to the first slot view signal.
  • the mapping relationship between the Slot ID and the backplane slot number (Bay ID) is pre-stored in the FPGA, and the mapping relationship is that the electronic device is programmed to the FPGA before leaving the factory, and is set by the manufacturer of the electronic device.
  • the FPGA firmware may be stored in the FPGA after the electronic device is shipped from the factory, and is not specifically limited in this embodiment.
  • the processor may be connected and communicated with the FPGA through the I2C bus; then, the S203 may be: the FPGA responds to the first slot view signal, and sends the mapping relationship to the processor through the I2C bus.
  • S204 The processor obtains a Slot ID corresponding to the slot of the backplane of the PCI-E bus interface according to the mapping relationship.
  • the S204 may include: acquiring, by the processor, a Bay ID of a slot of a backplane slot where the PCI-E bus interface is located; and acquiring, according to the mapping relationship, a slot corresponding to a Bay ID of a slot of the backplane of the PCI-E bus interface. ID.
  • the processor can obtain at least one Slot ID corresponding to the slot of the backplane provided with the PCI-E bus interface according to the foregoing mapping relationship sent by the FPGA, for example, all PCI-E bus interfaces are provided. Slot ID corresponding to the slot of the backplane, or the Slot ID corresponding to the slot of the backplane on which the PCI-E bus interface is configured. So, after Regardless of which NVMe storage device the user wants to manage, the corresponding NVMe storage device can be found through the Slot ID and managed.
  • the first instruction for acquiring the bus slot number corresponding to the PCI-E bus interface on the backplane is obtained, and then the first instruction is executed, and the first slot is sent to the FPGA.
  • FIG. 1B schematically shows a schematic structural diagram of an electronic device according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic flow chart showing a method of information processing according to another embodiment of the present disclosure.
  • the method includes:
  • the processor acquires the second instruction.
  • the second instruction is used to obtain a bus slot number corresponding to the SAS interface.
  • the user may input an acquisition command on the SAS management tool, and at this time, the processor obtains The second instruction for obtaining the Slot ID corresponding to the SAS interface on the backplane.
  • S302 The processor executes the second instruction to send a second slot view signal to the RAID controller.
  • the processor executes the second instruction described above, generates a second slot view signal, and transmits the signal to the RAID controller.
  • the RAID controller obtains a group ID corresponding to the backplane slot (Bay) of the SAS interface from the SEP of the backplane in response to the second slot view signal.
  • the RAID controller determines the corresponding Slot ID according to the group ID corresponding to the slot number of the backplane slot of the SAS interface, and sends the corresponding Slot ID to the processor.
  • a baseboard management controller (BMC) is activated at a stage when the electronic device is just powered on, and a Group ID and a Bay ID are set for the SEP through an I2C bus bundled in the backplane power line. And Slot ID.
  • SEP is the only source of information on the backplane slot information. Once it is set, it will always retain the set value. Once the upper device requests to read the related information, no matter what type of device, it can be obtained from SEP. A consistent and consistent response.
  • the foregoing S303 to S304 can be configured to respond to the second slot view signal of the RAID controller, and obtain the group ID corresponding to the slot of the backplane slot (Bay) of the SAS interface from the SEP. Then, the RAID controller determines the corresponding slot ID according to the group ID. For example, if a group includes four Slots, the RAID controller obtains the Group ID as Group0, and determines that the corresponding Slot ID is Slot0 ⁇ 3, that is, Slot0, Slot1, Slot2, and Slot3; for example, the RAID controller obtains the Group ID. For Group1, determine the corresponding Slot ID as Slot 4 ⁇ 7, namely Slot4, Slot5, Slot6, and Slot7. Of course, a group may also include five Slots, eight Slots, ten Slots, and the like. The corresponding relationship between the Group and the Slot is as described above, and so on, and the embodiment of the present disclosure is not specifically limited.
  • the Slot ID corresponding to the slot of the backplane of the SAS interface and the slot ID corresponding to the slot of the backplane of the PCI-E bus interface are sequentially numbered. For example, there are 6 interfaces on the backplane slot, and the corresponding Slot ID is 0 to 5, that is, Slot0, Slot1, Slot2, Slot3, Slot4, and Slot5. At this time, whether the interface is a PCI-E bus interface or a SAS interface, The processor is the same, that is, the difference in interface type is transparent to the processor.
  • the difference between the interfaces is masked and numbered uniformly, that is, the Slo corresponding to each interface is sequentially numbered.
  • the storage devices on the backplane are serially numbered, regardless of the storage device in the slot of the backplane.
  • the slot number can be represented by the same Slot number. , the difference in the interface on the transparent backplane.
  • FIG. 4 schematically shows a flow chart of a processor side information processing method according to an embodiment of the present disclosure.
  • the method includes:
  • the first instruction is used to obtain a bus slot number corresponding to the PCI-E bus interface on the backplane.
  • S402 Execute the first instruction to send the first slot view signal to the FPGA.
  • S403 Receive a mapping relationship between the Slot ID and the Bay ID stored in the FPGA in advance.
  • the mapping relationship is sent by the FPGA in response to the first slot view signal.
  • S404 Obtain a Slot ID corresponding to a slot of the backplane of the PCI-E bus interface according to the mapping relationship.
  • the electronic device further includes: a RAID array RAID controller, and a SAS interface is further disposed on the backplane
  • the method further includes: acquiring a second instruction, where the second instruction is used to acquire a SAS interface on the backplane Corresponding bus slot number; executing a second instruction to send a second slot view signal to the RAID array controller, and the second slot view signal is used to instruct the RAID controller to obtain a group corresponding to the slot of the backplane where the SAS interface is located.
  • the bus slot numbers corresponding to the slots on the backplane of the PCI-E bus interface are numbered sequentially.
  • S403 may include receiving a mapping relationship from an FPGA through a built-in integrated circuit I2C bus.
  • the S404 may include: obtaining a backplane slot number of a slot of the backplane where the PCI-E bus interface is located; and obtaining a backplane slot of the backplane slot where the PCI-E bus interface is located according to the mapping relationship. Number corresponding to the bus slot number.
  • the PCI-E bus interface described above is connected to the NVMe storage device. Based on the same disclosure concept, an embodiment of the present disclosure provides an electronic device consistent with the electronic device described in one or more of the above embodiments.
  • the electronic device includes a processor 11, an FPGA 12, a backplane 13, and at least one PCI-E bus interface 14 disposed on the backplane 13.
  • the processor is configured to acquire a first instruction, where the first instruction is used to obtain a bus slot number corresponding to the PCI-E bus interface on the backplane, and execute the first instruction to send the first slot to the FPGA.
  • the signal is also used to receive the mapping between the pre-stored bus slot number from the FPGA and the slot number of the backplane. According to the mapping relationship, obtain the bus slot number corresponding to the slot of the backplane of the PCI-E bus interface.
  • the FPGA is configured to receive the first slot view signal, and send the pre-stored mapping relationship to the processor in response to the first slot view signal of the processor.
  • the electronic device further includes: a RAID controller 16, and a SAS interface 15 disposed on the backplane 13.
  • the processor is further configured to acquire a second instruction, where the second instruction is used to obtain a bus slot number corresponding to the SAS interface, and execute a second instruction to send a second slot view signal to the RAID controller.
  • the bus slot number corresponding to the slot of the backplane slot of the SAS interface is the same as the slot number of the backplane slot where the PCI-E bus interface is located.
  • the bus slot number is sequentially numbered; the RAID controller is configured to receive the second slot view signal; in response to the second slot view signal, the group number corresponding to the slot of the backplane where the SAS interface is located is obtained from the backplane; The label determines the corresponding bus slot number; the group label determines the corresponding bus slot number to be sent to the processor.
  • the processor and the FPGA communicate through an I2C bus, and the processor is specifically configured to receive a mapping relationship from the FPGA through the I2C bus.
  • the processor is specifically configured to obtain the backplane slot number of the slot of the backplane where the PCI-E bus interface is located; and obtain the backplane slot of the backplane slot where the PCI-E bus interface is located according to the mapping relationship.
  • the bus slot number corresponding to the bit number.
  • the PCI-E bus interface is coupled to the NVMe storage device.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units; they may be located in one place or distributed on multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the above integration
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes The foregoing steps of the method embodiment; and the foregoing storage medium includes: a removable storage device, a read only memory (ROM), a magnetic disk, or an optical disk, and the like, which can store program codes.
  • ROM read only memory

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Abstract

一种信息处理的方法及一种电子设备，所述方法包括：获取第一指令（S401），所述第一指令用于获取背板上PCI-E总线接口对应的总线槽位编号；执行所述第一指令，以向现场可编程门阵列FPGA发送第一槽位查看信号（S402）；接收来自所述FPGA的预先存储的Slot ID与Bay ID之间的映射关系（S403），其中，所述映射关系是所述FPGA响应于所述第一槽位查看信号发送的；根据所述映射关系，获取所述PCI-E总线接口所在背板槽位对应的Slot ID（S404）。

Description

一种信息处理的方法及电子设备 技术领域
本公开涉及计算机领域，尤其涉及一种信息处理的方法及电子设备。
背景技术
非易失性存储器标准(NVMe，Non-Volatile Memory express)协议是一种新型的接口协议，能够允许主机端通过扩展的外设部件互连标准(PCI-E，Peripheral Component Interconnect Express)总线接口直接与NVMe存储设备通信，免去了更多的总线通信的成本，带宽和效率更高，是目前非常热门的存储协议技术。
目前，传统的序列式小型计算机系统接口(SAS，Serial Attached Small Computer System Interface)或者串行高级技术附件(SATA，Serial Advanced Technology Attachment)的管理方法是由SAS控制器执行的，而NVMe存储设备是无法由SAS控制器管理的。
所以，现有技术中并不存在一种管理NVMe存储设备的方案。
发明内容
有鉴于此，本公开实施例提供一种信息处理的方法及电子设备，以实现对NVMe存储设备的管理。
第一方面，本公开实施例提供了一种信息处理的方法，包括：获取第一指令，所述第一指令用于获取背板上PCI-E总线接口对应的总线槽位编号；执行所述第一指令，以向现场可编程门阵列(FPGA，Field Programmable Gate Array)发送第一槽位查看信号；接收来自所述FPGA的预先存储的总线槽位编号与背板槽位编号之间的映射关系，其中，所述映射关系是所述FPGA响应于所述第一槽位查看信号发送的；根据所述映射关系，获取所述PCI-E总线接口所在背板槽位对应的总线槽位编号。
可选地，所述背板上还设置有SAS接口，所述方法还包括：获取第二指令，所述第二指令用于获取所述背板上SAS接口对应的总线槽位编号；执行所述第二指令，以向磁盘阵列(RAID，Redundant Array of Independent Disk)控制器发送第二槽位查看信号，其中，所述第二槽位查看信号用于指示所述RAID控制器获取所述SAS接口所在背板槽位对应的组编号，根据所述组标号确定对应的总线槽位编号；接收来自所述RAID控制器的所述SAS接口所在背板槽位对应的总线槽位编号，其中，所述SAS接口所在背板槽位对应的总线槽位编号与所述PCI-E总线接口所在背板槽位对应的总线槽位编号是顺序编号的。
可选地，所述接收来自所述FPGA的预先存储的总线槽位编号与背板槽位编号之间的映射关系，包括：通过内置集成电路(I2C，Inter-Integrated Circuit)总线，接收来自所述FPGA的所述映射关系。
可选地，所述根据所述映射关系，获取所述PCI-E总线接口所在背板槽位对应的总线槽位编号，包括：获取与所述PCI-E总线接口所在背板槽位的背板槽位编号；根据所述映射关系，获取所述PCI-E总线接口所在背板槽位的背板槽位编号对应的总线槽位编号。
可选地，所述PCI-E总线接口连接NVMe存储设备。
第二方面，本公开实施例提供了一种电子设备，包括：处理器、FPGA、背板、设置于背板的至少一个PCI-E总线接口。处理器，用于获取第一指令，所述第一指令用于获取所述背板上所述PCI-E总线接口对应的总线槽位编号；执行所述第一指令，以向所述FPGA发送第一槽位查看信号；还用于接收来自所述FPGA的预先存储的总线槽位编号与背板槽位编号之间的映射关系；根据所述映射关系，获取所述PCI-E总线接口所在背板槽位对应的总线槽位编号。FPGA，用于接收所述第一槽位查看信号；响应于所述处理器发送的所述第一槽位查看信号，将预先存储的所述映射关系发送给所述处理器。
可选地，所述电子设备还包括：RAID控制器、设置于所述背板上的SAS接口。处理器，还用于获取第二指令，所述第二指令用于获取所述SAS接口对应的总线槽位编号；执行所述第二指令以向所述RAID控制器发送第二槽位查看信号；还用于接收来自所述RAID控制器的所述SAS接口所在背板槽位对应的总线槽位编号，其中，所述SAS接口所在背板槽位对应的总线槽位编号与所述PCI-E总线接口所在背板槽位对应的总线槽位编号是顺序编号的；所述RAID控制器，用于接收所述第二槽位查看信号；响应于所述第二槽位查看信号，从所述背板获取所述SAS接口所在背板槽位对应的组编号；根据所述组标号确定对应的总线槽位编号；将所述组标号确定对应的总线槽位编号发送给所述处理器。
可选地，所述处理器与所述FPGA通过I2C总线通信，所述处理器，还用于通过所述I2C总线，接收来自所述FPGA的所述映射关系。
可选地，所述处理器，还用于获取与所述PCI-E总线接口所在背板槽位的背板槽位编号；根据所述映射关系，获取所述PCI-E总线接口所在背板槽位的背板槽位编号对应的总线槽位编号。
可选地，所述PCI-E总线接口连接NVMe存储设备。
如上所述，本公开实施例提供了一种信息处理的方法及电子设备，首先，获取用于获取背板上PCI-E总线接口对应的总线槽位编号的第一指令，然后，执行该第一指令，向FPGA发送第一槽位查看信号；接收来自FPGA的预先存储的总线槽位编号与背板槽位编号之间的 映射关系，其中，上述映射关系是FPGA响应于第一槽位查看信号后发送的，接下来，根据上述映射关系，获取PCI-E总线接口所在背板槽位对应的总线槽位编号，如此，电子设备就能够通过FPGA获取背板上PCI-E总线接口对应的总线槽位编号，进而实现对NVMe存储设备的管理。
附图说明
图1A示意性示出了根据本公开实施例的电子设备的结构示意图；
图1B示意性示出了根据本公开另一实施例的电子设备的结构示意图；
图2示意性示出了根据本公开实施例的信息处理的方法流程示意图；
图3示意性示出了根据本公开另一实施例的信息处理的方法流程示意图；
图4示意性示出了根据本公开实施例的处理器侧信息处理方法的流程示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在，但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。
在此使用的所有术语(包括技术和科学术语)具有本领域技术人员通常所理解的含义，除非另外定义。应注意，这里使用的术语应解释为具有与本说明书的上下文相一致的含义，而不应以理想化或过于刻板的方式来解释。
在使用类似于“A、B和C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如，“具有A、B和C中至少一个的系统”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的系统等)。在使用类似于“A、B或C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如，“具有A、B或C中至少一个的系统”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的系统等)。本领域技术人员还应理解，实质上任意表示两个或更多可选项目的转折连词和/或短语，无论是在说明书、权利要求书还是附图中，都应被理解为给出了包括这些项目之一、这些项目任一方、或两个项目的可能性。例如，短语“A或B”应当被理解为包括“A”或“B”、或“A和B”的可 能性。
附图中示出了一些方框图和/或流程图。应理解，方框图和/或流程图中的一些方框或其组合可以由计算机程序指令来实现。这些计算机程序指令可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器，从而这些指令在由该处理器执行时可以创建用于实现这些方框图和/或流程图中所说明的功能/操作的装置。
因此，本公开的技术可以硬件和/或软件(包括固件、微代码等)的形式来实现。另外，本公开的技术可以采取存储有指令的计算机可读介质上的计算机程序产品的形式，该计算机程序产品可供指令执行系统使用或者结合指令执行系统使用。在本公开的上下文中，计算机可读介质可以是能够包含、存储、传送、传播或传输指令的任意介质。例如，计算机可读介质可以包括但不限于电、磁、光、电磁、红外或半导体系统、装置、器件或传播介质。计算机可读介质的具体示例包括：磁存储装置，如磁带或硬盘(HDD)；光存储装置，如光盘(CD-ROM)；存储器，如随机存取存储器(RAM)或闪存；和/或有线/无线通信链路。
在相关技术中，当背板同时接入SATA/SAS存储设备和NVMe存储设备时，往往会为NVMe存储设备保留一段固定的编号，比如，背板支持4块SATA/SAS存储设备和2块NVMe存储设备，前四个总线槽位编号(Slot ID)为0～3，后两个Slot ID为NVMe存储设备，而且，为了保证不与SATA/SAS存储设备冲突，预留的Slot ID会比较大，可以为64～65。那么，如果背板保留的NVMe存储设备的PCI-E总线接口位于整个背板的中间时，NVMe存储设备的Slot ID位于SATA/SAS存储设备的Slot ID中间，导致Slot ID不连续，此时，背板上设备的Slot ID为Slot0、Slot1、Slot64、Slot65、Slot2、Slot3。
由此可见，由于Slot ID不连续，就导致背板的配置不够灵活，不便于用户管理；另外，由于NVMe存储设备的PCI-E总线接口通常与SAS接口设置在统一背板槽位中，那么，当该背板槽位连接的是SATA/SAS存储设备时，该背板槽位对应的Slot ID就会前后会不一致，对用户使用造成困扰。
为了解决上述技术问题，本公开实施例提供一种信息处理的方法，该方法应用于电子设备中，如个人计算机(PC，Personal Computer)、平板电脑、多媒体设备等，只要是能够接入存储设备的电子设备均落入本公开的保护范围内。
在本公开实施例中，上述NVMe存储设备可以为NVMe协议的存储设备，如NVMe机械硬盘、NVMe固态硬盘等；上述SATA/SAS存储设备为SATA/SAS接口的存储设备，如SATA/SAS机械硬盘、SATA/SAS固态硬盘等。当然，还可以其它设备，本公开实施例不作具体限定。
为了更好地理解本公开实施例提供的信息处理方法，首先给出上述电子设备的结构示意 图。
图1A示意性示出了根据本公开实施例的电子设备的结构示意图。参见图1A所示，该电子设备10包括：处理器11、FPGA12、背板13、设置于背板13的至少一个PCI-E总线接口14。
根据本公开的实施例，上述处理器和FPGA设置于电子设备的主板上，上述背板设置有至少一个背板槽位(Bay)，在每个背板槽位上至少设置有一个PCI-E总线接口，PCI-E总线接口连接NVMe存储设备。
下面结合上述电子设备来对本公开实施例所述的信息处理的方法进行说明。
图2示意性示出了根据本公开实施例的信息处理的方法流程示意图。参见图2所示，该方法包括：
S201：处理器获取第一指令。
其中，第一指令用于获取背板上PCI-E总线接口对应的总线槽位编号。
根据本公开的实施例，在用户使用NVMe存储设备的管理工具的过程中，如果需要获取NVMe存储设备对应Slot ID，那么，用户可以在NVMe管理工具上输入获取命令，此时，处理器获得用于获取背板上PCI-E总线接口对应的Slot ID的第一指令。
S202：处理器执行第一指令，以向FPGA发送第一槽位查看信号。
根据本公开的实施例，处理器执行上述第一指令，生成第一槽位查看信号，并发送给FPGA。
S203：FPGA接收到处理器发送的第一槽位查看信号后，会响应第一槽位查看信号，将预先存储的总线槽位编号与背板槽位编号之间的映射关系发送给处理器。FPGA中预先存储有Slot ID与背板槽位编号(Bay ID)之间的映射关系，该映射关系是电子设备出厂前烧录至FPGA的，由电子设备的制造商设置。当然，也可以在电子设备出厂后，更新FPGA固件时，存储至FPGA中，本公开实施例不做具体限定。
根据本公开的实施例，处理器可以通过I2C总线与FPGA连接和通信；那么，上述S203可以为：FPGA响应第一槽位查看信号，将上述映射关系通过I2C总线发送给处理器。
S204：处理器根据映射关系，获取PCI-E总线接口所在背板槽位对应的Slot ID。
根据本公开的实施例，S204可以包括：处理器获取PCI-E总线接口所在背板槽位的Bay ID；根据上述映射关系，获取PCI-E总线接口所在背板槽位的Bay ID对应的Slot ID。
根据本公开的实施例，处理器根据FPGA发送的上述映射关系，就能够获得至少一个设置有PCI-E总线接口的背板槽位对应的Slot ID，比如，所有设置有PCI-E总线接口的背板槽位对应的Slot ID，或者，某一个设置有PCI-E总线接口的背板槽位对应的Slot ID。如此，后 续无论用户想要对哪个NVMe存储设备进行管理，均可以通过Slot ID找到对应的NVMe存储设备，进而对其进行管理。
由此可知，根据本公开的实施例，通过获取用于获取背板上PCI-E总线接口对应的总线槽位编号的第一指令，然后，执行该第一指令，向FPGA发送第一槽位查看信号；接收来自FPGA的预先存储的总线槽位编号与背板槽位编号之间的映射关系，其中，上述映射关系是FPGA响应第一槽位查看信号后发送的，接下来，根据上述映射关系，获取PCI-E总线接口所在背板槽位对应的总线槽位编号，如此，电子设备就能够通过FPGA获取背板上PCI-E总线接口对应的总线槽位编号，进而实现对NVMe存储设备的管理。
图1B示意性示出了根据本公开另一实施例的电子设备的结构示意图。
参见图1B所示，在背板槽位上除了设置有PCI-E总线接口14，同时还可以设置有SAS接口15，PCI-E总线接口14与SAS接口15可以设置在同一背板槽位上，也可以设置在不同背板槽位上。在进行总线槽位编号时，无论是何种接口，其所对应的Slot ID均顺序编号。
仍参见图1B所示，为了对SAS存储设备进行管理，电子设备还包括：RAID控制器16。
图3示意性示出了根据本公开另一实施例的信息处理的方法流程示意图。
参见图3所示，该方法包括：
S301：处理器获取第二指令。其中，第二指令用于获取SAS接口对应的总线槽位编号。
根据本公开的实施例，在用户使用SAS存储设备的管理工具的过程中，如果需要获取SAS存储设备对应Slot ID，那么，用户可以在SAS管理工具上输入获取命令，此时，处理器获得用于获取背板上SAS接口对应的Slot ID的第二指令。
S302：处理器执行第二指令，向RAID控制器发送第二槽位查看信号。
根据本公开的实施例，处理器执行上述第二指令，生成第二槽位查看信号，并发送给RAID控制器。
S303：RAID控制器响应于第二槽位查看信号，从背板的SEP获取SAS接口所在背板槽位(Bay)对应的组编号(Group ID)。
S304：RAID控制器根据SAS接口所在背板槽位对应的组编号即Group ID确定对应的Slot ID，并发送给处理器。
根据本公开的实施例，在电子设备刚刚加电的阶段，基板管理控制器(BMC，Baseboard Management Controller)启动，并通过捆绑在背板电源线中的I2C总线，为SEP设置Group ID、Bay ID和Slot ID。SEP是背板槽位信息的唯一提供源，一旦被设定好后，就会始终保留设定值，一旦有上层设备请求读取相关信息时，不论是什么类型的设备，都可以从SEP得到统一且一致的响应。
那么，上述S303至S304可以为RAID控制器响应第二槽位查看信号，从SEP获取SAS接口所在背板槽位(Bay)对应的Group ID，然后，RAID控制器根据Group ID确定对应的Slot ID，例如，一个Group包括四个Slot，那么，RAID控制器获得Group ID为Group0，确定对应的Slot ID就为Slot0～3，即Slot0、Slot1、Slot2、Slot3；再如，RAID控制器获得Group ID为Group1，确定对应的Slot ID就为Slot4～7，即Slot4、Slot5、Slot6、Slot7。当然，一个Group还可以包括五个Slot、8个Slot、10个Slot等，Group与Slot的对应关系如上所述，以此类推，本公开实施例不做具体限定。
需要说明的是，上述SAS接口所在背板槽位对应的Slot ID与PCI-E总线接口所在背板槽位对应的Slot ID是顺序编号的。例如，背板槽位上共6个接口，对应的Slot ID为0～5，即Slot0、Slot1、Slot2、Slot3、Slot4、Slot5，此时，无论接口是PCI-E总线接口还是SAS接口，对于处理器来说都是一样的，也就是说，对处理器来说接口类型的差异是透明的。
由此可知，在本公开实施例中，当背板混合接入NVMe存储设备和SAS存储设备时，屏蔽各类接口之间的差异，统一进行编号，即对各个接口对应的Slo顺序编号，如此，不论是NVMe存储设备还是SATA/SAS存储设备，所有背板上的存储设备连续编号，进而不论背板槽位接入何种存储设备，都能以不变的Slot编号代表该背板槽位，透明化背板上接口的差异。
基于前述实施例，下面对处理器侧的信息处理方法进行说明。
图4示意性示出了根据本公开实施例的处理器侧信息处理方法的流程示意图。
参见图4所示，该方法包括：
S401：获取第一指令。
其中，第一指令用于获取背板上PCI-E总线接口对应的总线槽位编号。
S402：执行第一指令，以向FPGA发送第一槽位查看信号。
S403：接收预先存储在FPGA中的Slot ID与Bay ID之间的映射关系。
其中，映射关系是FPGA响应于第一槽位查看信号发送的。
S404：根据映射关系，获取PCI-E总线接口所在背板槽位对应的Slot ID。
根据本公开的实施例，所述电子设备还包括：磁盘阵列RAID控制器，背板上还设置有SAS接口，上述方法还包括：获取第二指令，第二指令用于获取背板上SAS接口对应的总线槽位编号；执行第二指令，以向磁盘阵列RAID控制器发送第二槽位查看信号，第二槽位查看信号用于指示RAID控制器获取SAS接口所在背板槽位对应的组编号，并根据组标号确定对应的总线槽位编号；接收来自RAID控制器的SAS接口所在背板槽位对应的总线槽位编号，其中，SAS接口所在背板槽位对应的总线槽位编号与PCI-E总线接口所在背板槽位对应的总线槽位编号是顺序编号的。
根据本公开的实施例，S403可以包括：通过内置集成电路I2C总线，接收来自FPGA的映射关系。
根据本公开的实施例，S404可以包括：获取与PCI-E总线接口所在背板槽位的背板槽位编号；根据映射关系，获取PCI-E总线接口所在背板槽位的背板槽位编号对应的总线槽位编号。
根据本公开的实施例，上述PCI-E总线接口连接NVMe存储设备。基于同一公开构思，本公开实施例提供一种电子设备，与上述一个或者多个实施例中所述的电子设备一致。
参见图1A所示，该电子设备，包括：处理器11、FPGA12、背板13、设置于背板13的至少一个PCI-E总线接口14。
根据本公开的实施例，处理器，用于获取第一指令，第一指令用于获取背板上PCI-E总线接口对应的总线槽位编号；执行第一指令，向FPGA发送第一槽位查看信号；还用于接收来自FPGA的预先存储的总线槽位编号与背板槽位编号之间的映射关系；根据映射关系，获取PCI-E总线接口所在背板槽位对应的总线槽位编号；FPGA，用于接收第一槽位查看信号；响应处理器第一槽位查看信号，将预先存储的映射关系发送给处理器。
在公开其它实施例中，参见图1B所示，电子设备还包括：RAID控制器16、设置于背板13的SAS接口15。
根据本公开的实施例，处理器，还用于获取第二指令，第二指令用于获取SAS接口对应的总线槽位编号；执行第二指令，向RAID控制器发送第二槽位查看信号；还用于接收来自RAID控制器的SAS接口所在背板槽位对应的总线槽位编号，其中，SAS接口所在背板槽位对应的总线槽位编号与PCI-E总线接口所在背板槽位对应的总线槽位编号是顺序编号的；RAID控制器，用于接收第二槽位查看信号；响应第二槽位查看信号，从背板获取SAS接口所在背板槽位对应的组编号；根据组标号确定对应的总线槽位编号；将组标号确定对应的总线槽位编号发送给处理器。
根据本公开的实施例，处理器与FPGA通过I2C总线通信，处理器，具体用于通过I2C总线，接收来自FPGA的映射关系。
根据本公开的实施例，处理器，具体用于获取PCI-E总线接口所在背板槽位的背板槽位编号；根据映射关系，获取PCI-E总线接口所在背板槽位的背板槽位编号对应的总线槽位编号。
在公开其它实施例中，PCI-E总线接口连接NVMe存储设备。
这里需要指出的是：以上电子设备实施例项的描述，与上述方法描述是类似的，具有同方法实施例相同的有益效果，因此不做赘述。对于本公开电子设备实施例中未披露的技术细 节，本领域的技术人员请参照本公开方法实施例的描述而理解，为节约篇幅，这里不再赘述。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本公开各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(Read Only Memory，ROM)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本公开上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本公开实施例的技 术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本公开各个实施例所述方法的全部或部分。而前述的存储介质包括：移动存储设备、ROM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种信息处理的方法，包括：
    获取第一指令，所述第一指令用于获取背板上PCI-E总线接口对应的总线槽位编号；
    执行所述第一指令，以向现场可编程门阵列FPGA发送第一槽位查看信号；
    接收来自所述FPGA的预先存储的总线槽位编号与背板槽位编号之间的映射关系，其中，所述映射关系是所述FPGA响应于所述第一槽位查看信号发送的；
    根据所述映射关系，获取所述PCI-E总线接口所在背板槽位对应的总线槽位编号。
  2. 根据权利要求1所述的方法，其中，所述背板上还设置有序列式小型计算机系统接口SAS，所述方法还包括：
    获取第二指令，所述第二指令用于获取所述背板上SAS接口对应的总线槽位编号；
    执行所述第二指令，以向磁盘阵列RAID控制器发送第二槽位查看信号，其中，所述第二槽位查看信号用于指示所述RAID控制器获取所述SAS接口所在背板槽位对应的组编号，根据所述组标号确定对应的总线槽位编号；
    接收来自所述RAID控制器的所述SAS接口所在背板槽位对应的总线槽位编号，其中，所述SAS接口所在背板槽位对应的总线槽位编号与所述PCI-E总线接口所在背板槽位对应的总线槽位编号是顺序编号的。
  3. 根据权利要求1所述的方法，其中，所述接收来自所述FPGA的预先存储的总线槽位编号与背板槽位编号之间的映射关系，包括：
    通过内置集成电路I2C总线，接收来自所述FPGA的所述映射关系。
  4. 根据权利要求1所述的方法，其中，所述根据所述映射关系，获取所述PCI-E总线接口所在背板槽位对应的总线槽位编号，包括：
    获取所述PCI-E总线接口所在背板槽位的背板槽位编号；
    根据所述映射关系，获取与所述PCI-E总线接口所在背板槽位的背板槽位编号对应的总线槽位编号。
  5. 根据权利要求1至4任一项所述的方法，其中，所述PCI-E总线接口连接非易失性存储器标准NVMe存储设备。
  6. 一种电子设备，包括：处理器、现场可编程门阵列FPGA、背板、设置于背板的至少一个PCI-E总线接口，其中：
    处理器，用于获取第一指令，所述第一指令用于获取所述背板上所述PCI-E总线接口对应的总线槽位编号；执行所述第一指令，以向所述FPGA发送第一槽位查看信号；还用于接 收来自所述FPGA的预先存储的总线槽位编号与背板槽位编号之间的映射关系；根据所述映射关系，获取所述PCI-E总线接口所在背板槽位对应的总线槽位编号；
    FPGA，用于接收所述第一槽位查看信号；响应于所述处理器发送的所述第一槽位查看信号，将预先存储的所述映射关系发送给所述处理器。
  7. 根据权利要求6所述的电子设备，其中，所述电子设备还包括：磁盘阵列RAID控制器、设置于所述背板上的SAS，其中：
    所述处理器，还用于获取第二指令，所述第二指令用于获取所述SAS接口对应的总线槽位编号；执行所述第二指令，以向所述RAID控制器发送第二槽位查看信号；还用于接收来自所述RAID控制器的所述SAS接口所在背板槽位对应的总线槽位编号，其中，所述SAS接口所在背板槽位对应的总线槽位编号与所述PCI-E总线接口所在背板槽位对应的总线槽位编号是顺序编号的；
    所述RAID控制器，用于接收所述第二槽位查看信号；响应于所述第二槽位查看信号，从所述背板获取所述SAS接口所在背板槽位对应的组编号；根据所述组标号确定对应的总线槽位编号；将所述组标号确定对应的总线槽位编号发送给所述处理器。
  8. 根据权利要求6所述的电子设备，其中，所述处理器与所述FPGA通过内置集成电路I2C总线通信，所述处理器，还用于通过所述I2C总线，接收来自所述FPGA的所述映射关系。
  9. 根据权利要求6所述的电子设备，其中，所述处理器，还用于获取与所述PCI-E总线接口所在背板槽位的背板槽位编号；根据所述映射关系，获取所述PCI-E总线接口所在背板槽位的背板槽位编号对应的总线槽位编号。
  10. 根据权利要求6至9任一项所述的电子设备，其中，所述PCI-E总线接口连接非易失性存储器标准NVMe存储设备。
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