WO2018188135A1 - 一种像素补偿电路及显示装置 - Google Patents

一种像素补偿电路及显示装置 Download PDF

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Publication number
WO2018188135A1
WO2018188135A1 PCT/CN2017/082821 CN2017082821W WO2018188135A1 WO 2018188135 A1 WO2018188135 A1 WO 2018188135A1 CN 2017082821 W CN2017082821 W CN 2017082821W WO 2018188135 A1 WO2018188135 A1 WO 2018188135A1
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WIPO (PCT)
Prior art keywords
transistor
storage capacitor
module
light emitting
writing module
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PCT/CN2017/082821
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English (en)
French (fr)
Inventor
李骏
张娣
李光
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/568,800 priority Critical patent/US10147357B2/en
Publication of WO2018188135A1 publication Critical patent/WO2018188135A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel compensation circuit and a display device.
  • OLEDs Organic light-emitting diodes
  • OLEDs have a wide color gamut, high contrast ratio, energy saving, and foldable type, so they are highly competitive in existing displays.
  • Active matrix organic light emitting diode (AMOLED) technology is one of the key development directions of flexible display.
  • the traditional AMOLED adopts the 2T1C pixel driving method, which uses a switching transistor, a driving transistor and a storage capacitor to control the light emission of the diode.
  • the threshold voltage of the driving transistor is easily drifted, the diode driving current fluctuates, causing a malfunction of the display device and affecting image quality.
  • the conventional 6T1C pixel driving method usually solves the above-mentioned diode current variation caused by the threshold voltage shift.
  • the power supply of the pixel circuit generates a large voltage drop, which also causes the diode current. The change caused the display device to be defective and affected the image quality.
  • the present invention provides a pixel compensation circuit, including: a reset module, a data voltage writing module, a power voltage writing module, a reference voltage writing module, a switching module, a storage capacitor, and a light emitting device;
  • the reset module is connected to the first end of the storage capacitor and the second end of the storage capacitor for resetting the storage capacitor;
  • the data voltage writing module is connected to the first end of the storage capacitor for connecting a data voltage to the first end of the storage capacitor before the light emitting device emits light;
  • the power voltage writing module is connected to the second end of the storage capacitor, and is configured to connect a difference between the power voltage and the threshold voltage to the second end of the storage capacitor before the light emitting device emits light;
  • the reference voltage writing module is connected to the first end of the storage capacitor for connecting a reference voltage to the first end of the storage capacitor during illumination of the light emitting device;
  • the switch module is connected to the power voltage writing module, and is configured to turn on the power voltage writing module and the light emitting device during the light emitting process of the light emitting device;
  • An anode of the light emitting device is connected to the switch module, and a cathode of the light emitting device is connected to a common ground electrode;
  • the pixel compensation circuit further includes: a first control signal source;
  • the reset module includes a first transistor, a gate of the first transistor is connected to the first control signal source, and a source of the first transistor is connected to a first end of the storage capacitor, the first a drain of the transistor is coupled to the second end of the storage capacitor;
  • the pixel compensation circuit further includes a second control signal source, and the second control signal source is coupled to the power voltage writing module and the data voltage writing module.
  • the power voltage writing module includes: a second transistor and a driving transistor;
  • a gate of the driving transistor and a drain of the second transistor are connected to a second end of the storage capacitor, a source of the driving transistor is connected to the power supply voltage, a drain of the driving transistor, and a The source of the second transistor is connected to the switch module, and the gate of the second transistor is connected to the second control signal source.
  • the data voltage writing module includes a third transistor, a source of the third transistor is connected to the data voltage, and a drain of the third transistor and the storage capacitor The first end is connected, and the gate of the third transistor is connected to the second control signal source.
  • the pixel compensation circuit further includes a third control signal source, and the third control signal source is coupled to the reference voltage writing module and the switching module.
  • the reference voltage writing module includes a fourth transistor, a source of the fourth transistor is connected to the reference voltage, and a drain of the fourth transistor and the storage capacitor The first end is connected, and the gate of the fourth transistor is connected to the third control signal source.
  • the switch module includes a fifth transistor, a source of the fifth transistor is connected to the power voltage writing module, and a drain of the fifth transistor and the light emitting device An anode is connected, and a gate of the fifth transistor is connected to the third control signal source.
  • the present invention also provides a pixel compensation circuit, comprising: a reset module, a data voltage writing module, a power voltage writing module, a reference voltage writing module, a switching module, a storage capacitor, and a light emitting device;
  • the reset module is connected to the first end of the storage capacitor and the second end of the storage capacitor for resetting the storage capacitor;
  • the data voltage writing module is connected to the first end of the storage capacitor for connecting a data voltage to the first end of the storage capacitor before the light emitting device emits light;
  • the power voltage writing module is connected to the second end of the storage capacitor, and is configured to connect a difference between the power voltage and the threshold voltage to the second end of the storage capacitor before the light emitting device emits light;
  • the reference voltage writing module is connected to the first end of the storage capacitor for connecting a reference voltage to the first end of the storage capacitor during illumination of the light emitting device;
  • the switch module is connected to the power voltage writing module, and is configured to turn on the power voltage writing module and the light emitting device during the light emitting process of the light emitting device;
  • the anode of the light emitting device is connected to the switch module, and the cathode of the light emitting device is connected to a common ground electrode.
  • the pixel compensation circuit further includes: a first control signal source;
  • the reset module includes a first transistor, a gate of the first transistor is connected to the first control signal source, and a source of the first transistor is connected to a first end of the storage capacitor, the first A drain of the transistor is coupled to the second end of the storage capacitor.
  • the pixel compensation circuit further includes a second control signal source, and the second control signal source is coupled to the power voltage writing module and the data voltage writing module.
  • the power voltage writing module includes: a second transistor and a driving transistor;
  • a gate of the driving transistor and a drain of the second transistor are connected to a second end of the storage capacitor, a source of the driving transistor is connected to the power supply voltage, a drain of the driving transistor, and a The source of the second transistor is connected to the switch module, and the gate of the second transistor is connected to the second control signal source.
  • the data voltage writing module includes a third transistor, a source of the third transistor is connected to the data voltage, and a drain of the third transistor and the storage capacitor The first end is connected, and the gate of the third transistor is connected to the second control signal source.
  • the pixel compensation circuit further includes a third control signal source, and the third control signal source is coupled to the reference voltage writing module and the switching module.
  • the reference voltage writing module includes a fourth transistor, a source of the fourth transistor is connected to the reference voltage, and a drain of the fourth transistor and the storage capacitor The first end is connected, and the gate of the fourth transistor is connected to the third control signal source.
  • the switch module includes a fifth transistor, a source of the fifth transistor is connected to the power voltage writing module, and a drain of the fifth transistor and the light emitting device An anode is connected, and a gate of the fifth transistor is connected to the third control signal source.
  • a display device includes a pixel compensation circuit, and the pixel circuit includes: a reset module, a data voltage writing module, a power voltage writing module, a reference voltage writing module, and a switch module.
  • the reset module is connected to the first end of the storage capacitor and the second end of the storage capacitor for resetting the storage capacitor;
  • the data voltage writing module is connected to the first end of the storage capacitor for connecting a data voltage to the first end of the storage capacitor before the light emitting device emits light;
  • the power voltage writing module is connected to the second end of the storage capacitor, and is configured to connect a difference between the power voltage and the threshold voltage to the second end of the storage capacitor before the light emitting device emits light;
  • the reference voltage writing module is connected to the first end of the storage capacitor for connecting a reference voltage to the first end of the storage capacitor during illumination of the light emitting device;
  • the switch module is connected to the power voltage writing module, and is configured to turn on the power voltage writing module and the light emitting device during the light emitting process of the light emitting device;
  • the anode of the light emitting device is connected to the switch module, and the cathode of the light emitting device is connected to a common ground electrode.
  • the pixel compensation circuit further includes: a first control signal source;
  • the reset module includes a first transistor, a gate of the first transistor is connected to the first control signal source, and a source of the first transistor is connected to a first end of the storage capacitor, the first A drain of the transistor is coupled to the second end of the storage capacitor.
  • the pixel compensation circuit further includes a second control signal source, and the second control signal source is coupled to the power voltage writing module and the data voltage writing module.
  • the power voltage writing module includes: a second transistor and a driving transistor;
  • a gate of the driving transistor and a drain of the second transistor are connected to a second end of the storage capacitor, a source of the driving transistor is connected to the power supply voltage, a drain of the driving transistor, and a The source of the second transistor is connected to the switch module, and the gate of the second transistor is connected to the second control signal source.
  • the data voltage writing module includes a third transistor, a source of the third transistor is connected to the data voltage, and a drain of the third transistor and a portion of the storage capacitor Connected to one end, the gate of the third transistor is connected to the second control signal source.
  • the pixel compensation circuit further includes a third control signal source, the third control signal source being coupled to the reference voltage writing module and the switching module.
  • the pixel compensation circuit and the display device of the present invention connect the data voltage to the first end of the storage capacitor through the data voltage writing module and the power voltage writing module before the light emitting device emits light, and connect the difference between the power source and the threshold voltage.
  • the second end of the storage capacitor, and the reference voltage is connected to the second end of the storage capacitor during the illumination process of the light emitting device by the reference voltage writing module, so that the pixel circuit not only has the threshold voltage compensation function, but also has the pixel power supply
  • the voltage drop compensation function on the line further improves the display level of the display device.
  • FIG. 1 is a structural block diagram of a pixel compensation circuit according to a preferred embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a pixel compensation circuit according to a preferred embodiment of the present invention.
  • FIG. 3 is a timing diagram of a pixel compensation circuit provided by a preferred embodiment of the present invention.
  • FIG. 1 is a structural block diagram of a pixel compensation circuit according to a preferred embodiment of the present invention.
  • a pixel compensation circuit provided by a preferred embodiment of the present invention includes: a reset module 101 , a data voltage writing module 102 , a power voltage writing module 103 , a reference voltage writing module 104 , a switching module 105 , and a storage capacitor Cst and the light emitting device D1.
  • the reset module 101 is connected to the first end of the storage capacitor Cst and the second end of the storage capacitor Cst for resetting the storage capacitor Cst.
  • the data voltage writing module 102 is connected to the first end of the storage capacitor Cst for The data voltage is connected to the first end of the storage capacitor Cst before the light-emitting device D1 emits light; the power voltage writing module 103 is connected to the second end of the storage capacitor Cst for using the power supply voltage and the threshold before the light-emitting device D1 emits light.
  • the difference between the voltages is connected to the second end of the storage capacitor Cst; the reference voltage writing module 104 is connected to the first end of the storage capacitor Cst for connecting the reference voltage to the first of the storage capacitor Cst during the illumination process of the light emitting device D1
  • the switch module 105 is connected to the power supply voltage writing module 103 for turning on the power voltage writing module 103 and the light emitting device D1 during the light emitting process of the light emitting device D1; the anode of the light emitting device D1 is connected to the switch module 105, and the light emitting device D1
  • the cathode is connected to the common ground electrode VSS.
  • the pixel compensation circuit further includes: a first control signal source S1, a second control signal source S2, and a third control signal source S3.
  • the first control signal source S1 is connected to the reset module 101
  • the second control signal source S2 is connected to the power voltage writing module 103 and the data voltage writing module 102
  • the third control signal source S3 and the reference voltage writing module 104 are
  • the switch module 105 is connected.
  • FIG. 2 is a circuit diagram of a pixel compensation circuit according to a preferred embodiment of the present invention.
  • the reset module 101 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the first control signal source S1, and the source of the first transistor T1 is connected to the first end of the storage capacitor Cst.
  • the drain of the transistor T1 is connected to the second end of the storage capacitor Cst.
  • the power supply voltage writing module 103 includes: a second transistor T2 and a driving transistor T0; a gate of the driving transistor T0 and a drain of the second transistor T2 are connected to a second end of the storage capacitor Cst, and a source of the driving transistor T0 is connected to the power source
  • the voltage VDD, the drain of the driving transistor T0 and the source of the second transistor T2 are connected to the switch module 105, and the gate of the second transistor T2 is connected to the second control signal source S2.
  • the data voltage writing module 102 includes a third transistor T3.
  • the source of the third transistor T3 is connected to the data voltage Vdata, the drain of the third transistor T3 is connected to the first end of the storage capacitor Cst, and the gate of the third transistor T3 is connected.
  • the second control signal source S2 is connected.
  • the reference voltage writing module 104 includes a fourth transistor T4.
  • the source of the fourth transistor T4 is connected to the reference voltage Vref
  • the drain of the fourth transistor T4 is connected to the first end of the storage capacitor Cst
  • the gate of the fourth transistor T4 is connected.
  • the pole is connected to the third control signal source S3.
  • the switch module 105 includes a fifth transistor T5.
  • the source of the fifth transistor T5 is connected to the power supply voltage writing module 103, the drain of the fifth transistor T5 is connected to the anode of the light emitting device D1, and the gate of the fifth transistor T5 is connected to the third.
  • the control signal source S3 is connected.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the driving transistor T0 in the preferred embodiment are all P-type transistors.
  • the pixel compensation circuit since the pixel compensation circuit includes six transistors and one capacitor, it can also be called a novel 6T1C pixel compensation circuit according to a naming manner commonly used in the art.
  • FIG. 3 is a timing diagram of a pixel compensation circuit provided by a preferred embodiment of the present invention.
  • the operation timing diagram of the pixel compensation circuit generally has three stages of operation: a reset phase, a pre-lighting phase, and an illumination phase.
  • the pixel circuit resets the storage capacitor Cst before the operation. Specifically, the first control signal source S1 outputs a low level signal, and the second control signal source S2 and the third control signal source S3 output a high level signal. At this time, the first transistor T1 is turned on, and the storage capacitor Cst is turned One end is shorted to the second end of the storage capacitor Cst to reset the storage capacitor Cst.
  • the second control signal source S2 outputs a low level signal
  • the first control signal source S1 and the third control signal source S3 output a high level signal
  • the second transistor T2 and the third transistor T3 are turned on.
  • the data voltage Vdata is transmitted to the first end of the storage capacitor Cst via the third thin film transistor T3 such that the charging voltage level of the first end of the storage capacitor Cst is substantially equal to the data voltage Vdata.
  • the pixel compensation circuit is reset due to the reset phase t1, so that the driving transistor T0 is turned on at this time, and the turned-on driving transistor T0 and the second transistor T2 are along the source and the drain of the driving transistor T0, and the second The source and the drain of the transistor T2 and the second end of the storage capacitor Cst form a path of current. Since the source input power supply voltage VDD of the driving transistor T0 is determined, the power supply voltage VDD charges the second end of the storage capacitor Cst.
  • the charging continues until the finally reached critical state, which means that the charging voltage level of the second end of the storage capacitor Cst is substantially equal to the power supply voltage VDD minus the threshold voltage Vth of the driving transistor, that is, approximately equal to VDD-Vth, and this The voltage level at the second end of the storage capacitor Cst directly causes the driving transistor T0 to enter an off state.
  • the third control signal source S3 outputs a low level signal
  • the first control signal source S1 and the second control signal source S2 output a high level signal
  • the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the reference voltage Vref is transmitted to the first end of the storage capacitor Cst via the fourth transistor T4, such that the first end of the storage capacitor Cst undergoes an instantaneous jump from the first end of the storage capacitor Cst with the data voltage Vdata to the reference voltage Vref Changing, and charging to the reference voltage Vref, the coupling effect of the storage capacitor Cst causes the actual voltage level of the second end of the storage capacitor Cst to be substantially equal to VDD-Vth-Vdata+Vref.
  • the fifth transistor T5 is turned on at this time, and the current flowing through the driving transistor T0 satisfies the following functional relationship:
  • the current flowing through the light-emitting device is only related to the data voltage and the relatively stable reference voltage, and is independent of the threshold voltage of the driving transistor and the power supply voltage which is liable to generate a voltage drop.
  • the pixel compensation circuit not only has a threshold voltage compensation function, but also has a voltage drop compensation function on the pixel power line.
  • the pixel compensation circuit of the preferred embodiment connects the data voltage to the first end of the storage capacitor through the data voltage writing module and the power voltage writing module before the light emitting device emits light, and connects the difference between the power source and the threshold voltage to a second end of the storage capacitor, and a reference voltage is connected to the second end of the storage capacitor during the illumination process of the light emitting device by the reference voltage writing module, so that the pixel circuit not only has a threshold voltage compensation function, but also has a pixel power line
  • the pressure drop compensation function on the top improves the display level of the display device.
  • the invention also provides a display device.
  • the display device includes the pixel compensation circuit provided by the above-mentioned preferred embodiment.
  • the pixel compensation circuit provided in the above preferred embodiment, which is not described herein.
  • the pixel compensation circuit and the display device of the present invention connect the data voltage to the first end of the storage capacitor through the data voltage writing module and the power voltage writing module before the light emitting device emits light, and connect the difference between the power source and the threshold voltage.
  • the second end of the storage capacitor, and the reference voltage is connected to the second end of the storage capacitor during the illumination process of the light emitting device by the reference voltage writing module, so that the pixel circuit not only has the threshold voltage compensation function, but also has the pixel power supply
  • the voltage drop compensation function on the line further improves the display level of the display device.

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  • Computer Hardware Design (AREA)
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Abstract

一种像素补偿电路及显示装置，像素补偿电路包括：复位模块(101)、数据电压写入模块(102)、电源电压写入模块(103)、基准电压写入模块(104)、开关模块(105)、存储电容(Cst)以及发光器件(D1)。

Description

一种像素补偿电路及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种像素补偿电路及显示装置。
 背景技术
有机发光二极管（OLED）色域广、对比度高、节能、并具有可折叠型，因而在现有的显示器中具有强有力的竞争力。有源矩阵有机发光二极管（AMOLED）技术是柔性显示重点发展方向之一。传统的AMOLED采用2T1C的像素驱动方式，利用一个开关晶体管、一个驱动晶体管和一个存储电容来控制二极管的发光。然而，由于驱动晶体管的阈值电压容易漂移，导致二极管驱动电流变动，使得显示装置出现不良，影响画质。
现有的通常采用6T1C的像素驱动方式解决上述因阈值电压偏移导致的二极管电流变动，然而，在像素电源尺寸较长时，像素电路的电源会产生较大的压降，同样会导致二极管电流变动，使得显示装置出现不良，影响画质。
故，有必要提供一种像素补偿电路及显示装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种像素补偿电路及显示装置，其不仅具有阈值电压补偿功能，同时还具有像素电源线上的压降补偿功能。
 技术解决方案
本发明提供一种像素补偿电路，包括：复位模块、数据电压写入模块、电源电压写入模块、基准电压写入模块、开关模块、存储电容以及发光器件；其中，
所述复位模块与所述存储电容的第一端以及所述存储电容的第二端连接，用于对所述存储电容进行复位；
所述数据电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光前阶段将数据电压接至所述存储电容的第一端；
所述电源电压写入模块与所述存储电容的第二端连接，用于在所述发光器件发光前阶段将电源电压与阈值电压的差值接至所述存储电容的第二端；
所述基准电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光过程中将基准电压接至所述存储电容的第一端；
所述开关模块与所述电源电压写入模块连接，用于在所述发光器件发光过程中导通所述电源电压写入模块与所述发光器件；
所述发光器件的阳极与所述开关模块连接，所述发光器件的阴极与公共接地电极连接；
所述像素补偿电路还包括：第一控制信号源；
所述复位模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号源连接，所述第一晶体管的源极与所述存储电容的第一端连接，所述第一晶体管的漏极与所述存储电容的第二端连接；
所述像素补偿电路还包括第二控制信号源，所述第二控制信号源与所述电源电压写入模块以及所述数据电压写入模块连接。
在本发明的像素补偿电路中，所述电源电压写入模块包括：第二晶体管以及驱动晶体管；
所述驱动晶体管的栅极以及所述第二晶体管的漏极与所述存储电容的第二端连接，所述驱动晶体管的源极接入所述电源电压，所述驱动晶体管的漏极以及所述第二晶体管的源极与所述开关模块连接，所述第二晶体管的栅极与所述第二控制信号源连接。
在本发明的像素补偿电路中，所述数据电压写入模块包括第三晶体管，所述第三晶体管的源极接入所述数据电压，所述第三晶体管的漏极与所述存储电容的第一端连接，所述第三晶体管的栅极与所述第二控制信号源连接。
在本发明的像素补偿电路中，所述像素补偿电路还包括第三控制信号源，所述第三控制信号源与所述基准电压写入模块以及所述开关模块连接。
在本发明的像素补偿电路中，所述基准电压写入模块包括第四晶体管，所述第四晶体管的源极接入所述基准电压，所述第四晶体管的漏极与所述存储电容的第一端连接，所述第四晶体管的栅极与所述第三控制信号源连接。
在本发明的像素补偿电路中，所述开关模块包括第五晶体管，所述第五晶体管的源极与所述电源电压写入模块连接，所述第五晶体管的漏极与所述发光器件的阳极连接，所述第五晶体管的栅极与所述第三控制信号源连接。
本发明还提供一种像素补偿电路，包括：复位模块、数据电压写入模块、电源电压写入模块、基准电压写入模块、开关模块、存储电容以及发光器件；其中，
所述复位模块与所述存储电容的第一端以及所述存储电容的第二端连接，用于对所述存储电容进行复位；
所述数据电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光前阶段将数据电压接至所述存储电容的第一端；
所述电源电压写入模块与所述存储电容的第二端连接，用于在所述发光器件发光前阶段将电源电压与阈值电压的差值接至所述存储电容的第二端；
所述基准电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光过程中将基准电压接至所述存储电容的第一端；
所述开关模块与所述电源电压写入模块连接，用于在所述发光器件发光过程中导通所述电源电压写入模块与所述发光器件；
所述发光器件的阳极与所述开关模块连接，所述发光器件的阴极与公共接地电极连接。
在本发明的像素补偿电路中，所述像素补偿电路还包括：第一控制信号源；
所述复位模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号源连接，所述第一晶体管的源极与所述存储电容的第一端连接，所述第一晶体管的漏极与所述存储电容的第二端连接。
在本发明的像素补偿电路中，所述像素补偿电路还包括第二控制信号源，所述第二控制信号源与所述电源电压写入模块以及所述数据电压写入模块连接。
在本发明的像素补偿电路中，所述电源电压写入模块包括：第二晶体管以及驱动晶体管；
所述驱动晶体管的栅极以及所述第二晶体管的漏极与所述存储电容的第二端连接，所述驱动晶体管的源极接入所述电源电压，所述驱动晶体管的漏极以及所述第二晶体管的源极与所述开关模块连接，所述第二晶体管的栅极与所述第二控制信号源连接。
在本发明的像素补偿电路中，所述数据电压写入模块包括第三晶体管，所述第三晶体管的源极接入所述数据电压，所述第三晶体管的漏极与所述存储电容的第一端连接，所述第三晶体管的栅极与所述第二控制信号源连接。
在本发明的像素补偿电路中，所述像素补偿电路还包括第三控制信号源，所述第三控制信号源与所述基准电压写入模块以及所述开关模块连接。
在本发明的像素补偿电路中，所述基准电压写入模块包括第四晶体管，所述第四晶体管的源极接入所述基准电压，所述第四晶体管的漏极与所述存储电容的第一端连接，所述第四晶体管的栅极与所述第三控制信号源连接。
在本发明的像素补偿电路中，所述开关模块包括第五晶体管，所述第五晶体管的源极与所述电源电压写入模块连接，所述第五晶体管的漏极与所述发光器件的阳极连接，所述第五晶体管的栅极与所述第三控制信号源连接。
依据本发明的上述目的，还提供一种显示装置，其包括像素补偿电路，所述像素电路，包括：复位模块、数据电压写入模块、电源电压写入模块、基准电压写入模块、开关模块、存储电容以及发光器件；其中，
所述复位模块与所述存储电容的第一端以及所述存储电容的第二端连接，用于对所述存储电容进行复位；
所述数据电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光前阶段将数据电压接至所述存储电容的第一端；
所述电源电压写入模块与所述存储电容的第二端连接，用于在所述发光器件发光前阶段将电源电压与阈值电压的差值接至所述存储电容的第二端；
所述基准电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光过程中将基准电压接至所述存储电容的第一端；
所述开关模块与所述电源电压写入模块连接，用于在所述发光器件发光过程中导通所述电源电压写入模块与所述发光器件；
所述发光器件的阳极与所述开关模块连接，所述发光器件的阴极与公共接地电极连接。
在本发明的显示装置中，所述像素补偿电路还包括：第一控制信号源；
所述复位模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号源连接，所述第一晶体管的源极与所述存储电容的第一端连接，所述第一晶体管的漏极与所述存储电容的第二端连接。
在本发明的显示装置中，所述像素补偿电路还包括第二控制信号源，所述第二控制信号源与所述电源电压写入模块以及所述数据电压写入模块连接。
在本发明的显示装置中，所述电源电压写入模块包括：第二晶体管以及驱动晶体管；
所述驱动晶体管的栅极以及所述第二晶体管的漏极与所述存储电容的第二端连接，所述驱动晶体管的源极接入所述电源电压，所述驱动晶体管的漏极以及所述第二晶体管的源极与所述开关模块连接，所述第二晶体管的栅极与所述第二控制信号源连接。
在本发明的显示装置中，所述数据电压写入模块包括第三晶体管，所述第三晶体管的源极接入所述数据电压，所述第三晶体管的漏极与所述存储电容的第一端连接，所述第三晶体管的栅极与所述第二控制信号源连接。
在本发明的显示装置中，所述像素补偿电路还包括第三控制信号源，所述第三控制信号源与所述基准电压写入模块以及所述开关模块连接。
 有益效果
本发明的像素补偿电路及显示装置，通过数据电压写入模块以及电源电压写入模块在发光器件发光前阶段将数据电压接至存储电容的第一端，将电源电源与阈值电压的差值接至存储电容的第二端，以及通过基准电压写入模块在发光器件发光过程中将基准电压接至存储电容的第二端，从而使得该像素电路不仅具有阈值电压补偿功能，同时还具有像素电源线上的压降补偿功能，进而提高显示装置的显示水平。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为本发明优选实施例提供的像素补偿电路的结构框图；
图2为本发明优选实施例提供的像素补偿电路的电路图；
图3为为本发明优选实施例提供的像素补偿电路的时序图。
 本发明的最佳实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
参阅图1，图1为本发明优选实施例提供的像素补偿电路的结构框图。如图1所示，本发明优选实施例提供的像素补偿电路，包括：复位模块101、数据电压写入模块102、电源电压写入模块103、基准电压写入模块104、开关模块105、存储电容Cst以及发光器件D1。
其中，复位模块101与存储电容Cst的第一端以及存储电容Cst的第二端连接，用于对存储电容Cst进行复位；数据电压写入模块102与存储电容Cst的第一端连接，用于在发光器件D1发光前阶段将数据电压接至存储电容Cst的第一端；电源电压写入模块103与存储电容Cst的第二端连接，用于在发光器件D1发光前阶段将电源电压与阈值电压的差值接至存储电容Cst的第二端；基准电压写入模块104与存储电容Cst的第一端连接，用于在发光器件D1发光过程中将基准电压接至存储电容Cst的第一端；开关模块105与电源电压写入模块103连接，用于在发光器件D1发光过程中导通电源电压写入模块103与发光器件D1；发光器件D1的阳极与开关模块105连接，发光器件D1的阴极与公共接地电极VSS连接。
进一步的，该像素补偿电路还包括：第一控制信号源S1、第二控制信号源S2以及第三控制信号源S3。其中，第一控制信号源S1与复位模块101连接，第二控制信号源S2与电源电压写入模块103以及数据电压写入模块102连接，第三控制信号源S3与基准电压写入模块104以及开关模块105连接。
具体的，请参阅图2，图2为本发明优选实施例提供的像素补偿电路的电路图。如图2所示，复位模块101包括第一晶体管T1，第一晶体管T1的栅极与第一控制信号源S1连接，第一晶体管T1的源极与存储电容Cst的第一端连接，第一晶体管T1的漏极与存储电容Cst的第二端连接。
电源电压写入模块103包括：第二晶体管T2以及驱动晶体管T0；驱动晶体管T0的栅极以及第二晶体管T2的漏极与存储电容Cst的第二端连接，驱动晶体管T0的源极接入电源电压VDD，驱动晶体管T0的漏极以及第二晶体管T2的源极与开关模块105连接，第二晶体管T2的栅极与第二控制信号源S2连接。
数据电压写入模块102包括第三晶体管T3，第三晶体管T3的源极接入数据电压Vdata，第三晶体管T3的漏极与存储电容Cst的第一端连接，第三晶体管T3的栅极与第二控制信号源S2连接。
基准电压写入模块104包括第四晶体管T4，第四晶体管T4的源极接入所述基准电压Vref，第四晶体管T4的漏极与存储电容Cst的第一端连接，第四晶体管T4的栅极与第三控制信号源S3连接。
开关模块105包括第五晶体管T5，第五晶体管T5的源极与电源电压写入模块103连接，第五晶体管T5的漏极与发光器件D1的阳极连接，第五晶体管T5的栅极与第三控制信号源S3连接。
需要说明的是，本优选实施例中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及驱动晶体管T0均为P型晶体管。
从而，由于本像素补偿电路包含了6个晶体管和一个电容，所以也可以按本领域常用的命名方式而称为新型的6T1C像素补偿电路。
下面结合图3对图2所示的像素补偿电路驱动发光器件发光的过程进行详细描述。图3为为本发明优选实施例提供的像素补偿电路的时序图。如图3所示，该像素补偿电路的工作时序图，总体来说，该像素补偿电路的工作分为三个阶段：复位阶段、发光前阶段、和发光阶段。
在复位阶段t1，该像素电路在工作之前，先对存储电容Cst进行复位。具体地，第一控制信号源S1输出低电平信号，第二控制信号源S2以及第三控制信号源S3输出高电平信号，此时，第一晶体管T1导通，将存储电容Cst的第一端与存储电容Cst的第二端短接，从而对存储电容Cst进行复位。
在发光前阶段t2，第二控制信号源S2输出低电平信号，第一控制信号源S1以及第三控制信号源S3输出高电平信号，此时第二晶体管T2以及第三晶体管T3导通，数据电压Vdata经第三薄膜晶体管T3传至存储电容Cst的第一端，使得此时存储电容Cst的第一端的充电电压水准大致等于数据电压Vdata。同时，由于复位阶段t1对该像素补偿电路进行复位，使得此时驱动晶体管T0导通，而导通的驱动晶体管T0与第二晶体管T2会沿着驱动晶体管T0的源极与漏极、第二晶体管T2的源极与漏极、及存储电容Cst的第二端形成电流的通路，因为确定驱动晶体管T0的源极输入电源电压VDD，所述电源电压VDD会向存储电容Cst的第二端充电，充电持续到最终达成的临界状态，这种临界状态是指存储电容Cst的第二端的充电电压水准大致等于电源电压VDD减去驱动晶体管的阈值电压Vth，也即大致等于VDD-Vth，并且此时存储电容Cst第二端的电压水准会直接导致驱动晶体管T0进入截止状态。
在发光阶段t3，第三控制信号源S3输出低电平信号，第一控制信号源S1以及第二控制信号源S2输出高电平信号，此时第四晶体管T4以及第五晶体管T5导通，基准电压Vref经第四晶体管T4传至存储电容Cst的第一端，从而使得存储电容Cst的第一端经历从之前第二阶段存储电容Cst第一端具有数据电压Vdata到基准电压Vref的瞬时跳变，并且会充电到基准电压Vref，藉由存储电容Cst的耦合效应会导致存储电容Cst的第二端的实际电压水准大致等于VDD-Vth-Vdata+Vref。同时，第五晶体管T5此时导通，并且流经驱动晶体管T0的电流满足以下函数关系：
从该函数关系的计算结果来看，该流经发光器件的电流只与数据电压以及相对稳定的基准电压有关，而与驱动晶体管的阈值电压和容易产生压降的电源电压无关。该像素补偿电路不仅具有阈值电压补偿功能，同时还具有像素电源线上的压降补偿功能。
本优选实施例的像素补偿电路，通过数据电压写入模块以及电源电压写入模块在发光器件发光前阶段将数据电压接至存储电容的第一端，将电源电源与阈值电压的差值接至存储电容的第二端，以及通过基准电压写入模块在发光器件发光过程中将基准电压接至存储电容的第二端，从而使得该像素电路不仅具有阈值电压补偿功能，同时还具有像素电源线上的压降补偿功能，进而提高显示装置的显示水平。
本发明还提供一种显示装置。在本实施方式中，该显示装置包括上述优选实施例提供的像素补偿电路，具体可参照上述优选实施例提供的像素补偿电路的描述，在此不做赘述。
本发明的像素补偿电路及显示装置，通过数据电压写入模块以及电源电压写入模块在发光器件发光前阶段将数据电压接至存储电容的第一端，将电源电源与阈值电压的差值接至存储电容的第二端，以及通过基准电压写入模块在发光器件发光过程中将基准电压接至存储电容的第二端，从而使得该像素电路不仅具有阈值电压补偿功能，同时还具有像素电源线上的压降补偿功能，进而提高显示装置的显示水平。
综上，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素补偿电路，其包括：复位模块、数据电压写入模块、电源电压写入模块、基准电压写入模块、开关模块、存储电容以及发光器件；其中，
    所述复位模块与所述存储电容的第一端以及所述存储电容的第二端连接，用于对所述存储电容进行复位；
    所述数据电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光前阶段将数据电压接至所述存储电容的第一端；
    所述电源电压写入模块与所述存储电容的第二端连接，用于在所述发光器件发光前阶段将电源电压与阈值电压的差值接至所述存储电容的第二端；
    所述基准电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光过程中将基准电压接至所述存储电容的第一端；
    所述开关模块与所述电源电压写入模块连接，用于在所述发光器件发光过程中导通所述电源电压写入模块与所述发光器件；
    所述发光器件的阳极与所述开关模块连接，所述发光器件的阴极与公共接地电极连接；
    所述像素补偿电路还包括：第一控制信号源；
    所述复位模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号源连接，所述第一晶体管的源极与所述存储电容的第一端连接，所述第一晶体管的漏极与所述存储电容的第二端连接；
    所述像素补偿电路还包括第二控制信号源，所述第二控制信号源与所述电源电压写入模块以及所述数据电压写入模块连接。
  2. 根据权利要求1所述的像素补偿电路，其中所述电源电压写入模块包括：第二晶体管以及驱动晶体管；
    所述驱动晶体管的栅极以及所述第二晶体管的漏极与所述存储电容的第二端连接，所述驱动晶体管的源极接入所述电源电压，所述驱动晶体管的漏极以及所述第二晶体管的源极与所述开关模块连接，所述第二晶体管的栅极与所述第二控制信号源连接。
  3. 根据权利要求1所述的像素补偿电路，其中所述数据电压写入模块包括第三晶体管，所述第三晶体管的源极接入所述数据电压，所述第三晶体管的漏极与所述存储电容的第一端连接，所述第三晶体管的栅极与所述第二控制信号源连接。
  4. 根据权利要求1所述的像素补偿电路，其中所述像素补偿电路还包括第三控制信号源，所述第三控制信号源与所述基准电压写入模块以及所述开关模块连接。
  5. 根据权利要求4所述的像素补偿电路，其中所述基准电压写入模块包括第四晶体管，所述第四晶体管的源极接入所述基准电压，所述第四晶体管的漏极与所述存储电容的第一端连接，所述第四晶体管的栅极与所述第三控制信号源连接。
  6. 根据权利要求4所述的像素补偿电路，其中所述开关模块包括第五晶体管，所述第五晶体管的源极与所述电源电压写入模块连接，所述第五晶体管的漏极与所述发光器件的阳极连接，所述第五晶体管的栅极与所述第三控制信号源连接。
  7. 一种像素补偿电路，其包括：复位模块、数据电压写入模块、电源电压写入模块、基准电压写入模块、开关模块、存储电容以及发光器件；其中，
    所述复位模块与所述存储电容的第一端以及所述存储电容的第二端连接，用于对所述存储电容进行复位；
    所述数据电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光前阶段将数据电压接至所述存储电容的第一端；
    所述电源电压写入模块与所述存储电容的第二端连接，用于在所述发光器件发光前阶段将电源电压与阈值电压的差值接至所述存储电容的第二端；
    所述基准电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光过程中将基准电压接至所述存储电容的第一端；
    所述开关模块与所述电源电压写入模块连接，用于在所述发光器件发光过程中导通所述电源电压写入模块与所述发光器件；
    所述发光器件的阳极与所述开关模块连接，所述发光器件的阴极与公共接地电极连接。
  8. 根据权利要求7所述的像素补偿电路，其中所述像素补偿电路还包括：第一控制信号源；
    所述复位模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号源连接，所述第一晶体管的源极与所述存储电容的第一端连接，所述第一晶体管的漏极与所述存储电容的第二端连接。
  9. 根据权利要求7所述的像素补偿电路，其中所述像素补偿电路还包括第二控制信号源，所述第二控制信号源与所述电源电压写入模块以及所述数据电压写入模块连接。
  10. 根据权利要求9所述的像素补偿电路，其中所述电源电压写入模块包括：第二晶体管以及驱动晶体管；
    所述驱动晶体管的栅极以及所述第二晶体管的漏极与所述存储电容的第二端连接，所述驱动晶体管的源极接入所述电源电压，所述驱动晶体管的漏极以及所述第二晶体管的源极与所述开关模块连接，所述第二晶体管的栅极与所述第二控制信号源连接。
  11. 根据权利要求9所述的像素补偿电路，其中所述数据电压写入模块包括第三晶体管，所述第三晶体管的源极接入所述数据电压，所述第三晶体管的漏极与所述存储电容的第一端连接，所述第三晶体管的栅极与所述第二控制信号源连接。
  12. 根据权利要求1所述的像素补偿电路，其中所述像素补偿电路还包括第三控制信号源，所述第三控制信号源与所述基准电压写入模块以及所述开关模块连接。
  13. 根据权利要求12所述的像素补偿电路，其中所述基准电压写入模块包括第四晶体管，所述第四晶体管的源极接入所述基准电压，所述第四晶体管的漏极与所述存储电容的第一端连接，所述第四晶体管的栅极与所述第三控制信号源连接。
  14. 根据权利要求12所述的像素补偿电路，其中所述开关模块包括第五晶体管，所述第五晶体管的源极与所述电源电压写入模块连接，所述第五晶体管的漏极与所述发光器件的阳极连接，所述第五晶体管的栅极与所述第三控制信号源连接。
  15. 一种显示装置，其包括像素补偿电路，所述像素电路，包括：复位模块、数据电压写入模块、电源电压写入模块、基准电压写入模块、开关模块、存储电容以及发光器件；其中，
    所述复位模块与所述存储电容的第一端以及所述存储电容的第二端连接，用于对所述存储电容进行复位；
    所述数据电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光前阶段将数据电压接至所述存储电容的第一端；
    所述电源电压写入模块与所述存储电容的第二端连接，用于在所述发光器件发光前阶段将电源电压与阈值电压的差值接至所述存储电容的第二端；
    所述基准电压写入模块与所述存储电容的第一端连接，用于在所述发光器件发光过程中将基准电压接至所述存储电容的第一端；
    所述开关模块与所述电源电压写入模块连接，用于在所述发光器件发光过程中导通所述电源电压写入模块与所述发光器件；
    所述发光器件的阳极与所述开关模块连接，所述发光器件的阴极与公共接地电极连接。
  16. 根据权利要求15所述的显示装置，其中所述像素补偿电路还包括：第一控制信号源；
    所述复位模块包括第一晶体管，所述第一晶体管的栅极与所述第一控制信号源连接，所述第一晶体管的源极与所述存储电容的第一端连接，所述第一晶体管的漏极与所述存储电容的第二端连接。
  17. 根据权利要求15所述的显示装置，其中所述像素补偿电路还包括第二控制信号源，所述第二控制信号源与所述电源电压写入模块以及所述数据电压写入模块连接。
  18. 根据权利要求17所述的显示装置，其中所述电源电压写入模块包括：第二晶体管以及驱动晶体管；
    所述驱动晶体管的栅极以及所述第二晶体管的漏极与所述存储电容的第二端连接，所述驱动晶体管的源极接入所述电源电压，所述驱动晶体管的漏极以及所述第二晶体管的源极与所述开关模块连接，所述第二晶体管的栅极与所述第二控制信号源连接。
  19. 根据权利要求17所述的显示装置，其中所述数据电压写入模块包括第三晶体管，所述第三晶体管的源极接入所述数据电压，所述第三晶体管的漏极与所述存储电容的第一端连接，所述第三晶体管的栅极与所述第二控制信号源连接。
  20. 根据权利要求15所述的显示装置，其中所述像素补偿电路还包括第三控制信号源，所述第三控制信号源与所述基准电压写入模块以及所述开关模块连接。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107146580A (zh) * 2017-07-20 2017-09-08 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107680530A (zh) 2017-09-28 2018-02-09 深圳市华星光电半导体显示技术有限公司 像素补偿电路、扫描驱动电路及显示面板
US10497316B2 (en) 2017-11-17 2019-12-03 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Amoled pixel driving circuit and driving method thereof
CN107657921B (zh) * 2017-11-17 2019-09-24 深圳市华星光电半导体显示技术有限公司 Amoled像素驱动电路及其驱动方法
CN108922476B (zh) * 2018-06-21 2020-06-12 武汉华星光电半导体显示技术有限公司 一种oled像素驱动电路及oled显示器
CN109410844B (zh) * 2018-10-29 2023-12-29 武汉华星光电技术有限公司 像素驱动电路及显示装置
CN109872682A (zh) * 2019-03-28 2019-06-11 武汉华星光电半导体显示技术有限公司 像素补偿电路及显示装置
CN110738964A (zh) * 2019-10-29 2020-01-31 京东方科技集团股份有限公司 像素电路及显示装置
CN114333686A (zh) * 2020-09-25 2022-04-12 京东方科技集团股份有限公司 驱动电路和显示面板
CN112837656A (zh) * 2021-01-11 2021-05-25 武汉华星光电半导体显示技术有限公司 像素驱动电路、显示面板及其驱动方法
CN114822406B (zh) * 2022-05-20 2023-12-05 昆山国显光电有限公司 显示装置及其驱动方法
CN115331615B (zh) * 2022-08-29 2023-11-21 惠科股份有限公司 驱动电路及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101075410A (zh) * 2006-05-19 2007-11-21 统宝光电股份有限公司 影像显示系统和驱动显示组件的方法
US20070279337A1 (en) * 2006-06-01 2007-12-06 Lg Philips Lcd Co., Ltd. Organic light-emitting diode display device and driving method thereof
CN101471032A (zh) * 2007-12-27 2009-07-01 乐金显示有限公司 发光显示器及其驱动方法
US20100073266A1 (en) * 2008-09-19 2010-03-25 Samsung Electronics Co., Ltd. Display device and method of driving the same
CN103296055A (zh) * 2012-12-26 2013-09-11 上海天马微电子有限公司 有机发光显示器的像素电路及驱动方法、有机发光显示器
CN103943060A (zh) * 2013-06-28 2014-07-23 上海天马微电子有限公司 有机发光显示器及其像素电路、像素电路的驱动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101075410A (zh) * 2006-05-19 2007-11-21 统宝光电股份有限公司 影像显示系统和驱动显示组件的方法
US20070279337A1 (en) * 2006-06-01 2007-12-06 Lg Philips Lcd Co., Ltd. Organic light-emitting diode display device and driving method thereof
CN101471032A (zh) * 2007-12-27 2009-07-01 乐金显示有限公司 发光显示器及其驱动方法
US20100073266A1 (en) * 2008-09-19 2010-03-25 Samsung Electronics Co., Ltd. Display device and method of driving the same
CN103296055A (zh) * 2012-12-26 2013-09-11 上海天马微电子有限公司 有机发光显示器的像素电路及驱动方法、有机发光显示器
CN103943060A (zh) * 2013-06-28 2014-07-23 上海天马微电子有限公司 有机发光显示器及其像素电路、像素电路的驱动方法

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