WO2018188119A1 - 液晶显示装置及其goa电路 - Google Patents

液晶显示装置及其goa电路 Download PDF

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Publication number
WO2018188119A1
WO2018188119A1 PCT/CN2017/081976 CN2017081976W WO2018188119A1 WO 2018188119 A1 WO2018188119 A1 WO 2018188119A1 CN 2017081976 W CN2017081976 W CN 2017081976W WO 2018188119 A1 WO2018188119 A1 WO 2018188119A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
pull
module
drain
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PCT/CN2017/081976
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English (en)
French (fr)
Inventor
石龙强
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to EP17905458.0A priority Critical patent/EP3611721A4/en
Priority to JP2019547619A priority patent/JP2020509425A/ja
Priority to US15/545,652 priority patent/US10269318B2/en
Priority to KR1020197033216A priority patent/KR20190131593A/ko
Publication of WO2018188119A1 publication Critical patent/WO2018188119A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the technical field of liquid crystal display, and in particular to a liquid crystal display device and a GOA circuit thereof.
  • A-Si based GOA circuits are currently widely used in displays of various sizes. GOA Technology is beneficial for cost reduction and has a narrow bezel design.
  • FIG. 1 is a schematic structural view of a GOA circuit commonly used in the prior art, in which 17 TFTs (thin film transistors) are used in the first-level GOA circuit.
  • TFTs thin film transistors
  • FIG. 1 is a schematic structural view of a GOA circuit commonly used in the prior art, in which 17 TFTs (thin film transistors) are used in the first-level GOA circuit.
  • the increase in the number of TFTs increases the size of the bezel.
  • the structure of the GOA circuit in the prior art obviously cannot meet the design requirements of the narrow bezel display.
  • the embodiment of the invention provides a liquid crystal display device and a GOA circuit thereof to solve the technical problem that the display frame is not narrow enough due to the complicated structure of the GOA circuit in the prior art.
  • an embodiment of the present invention provides a GOA circuit, where the GOA circuit includes a plurality of cascaded GOA units, and the Nth level of the GOA unit includes a pull-up control module, a pull-up module, and a downlink.
  • the pull-up control module is respectively connected to the downlink module and the pull-down maintaining module, and one end of the bootstrap capacitor and the downlink module and the The pull-up module is connected, the pull-down module is respectively connected to the downlink module and the scan line of the current stage, and the pull-down maintenance module and the pull-down module are also respectively connected with the pull-down signal line, and the pull-up module and the clock signal respectively The line and the scan line connection of this level.
  • the embodiment of the present invention further provides a liquid crystal display device comprising the GOA circuit according to any of the above embodiments.
  • the liquid crystal display device and the GOA circuit provided by the invention greatly simplify the design structure of the circuit while ensuring the completion of the liquid crystal display driving requirement, and on the other hand, the structural cost of the circuit is saved, and on the other hand, The structural size of the GOA circuit is reduced, so that the liquid crystal display device can have a design space of a narrower frame structure.
  • FIG. 1 is a schematic structural diagram of a GOA circuit commonly used in the prior art.
  • FIG. 2 is a schematic diagram showing the circuit structure of an embodiment of an Nth-level GOA unit of the present invention
  • 3 is a waveform diagram of driving signals of the GOA circuit in the embodiment.
  • FIG. 4 is a schematic diagram showing the circuit structure of the first two stages of the GOA unit in the embodiment of FIG. 2;
  • FIG. 5 is a schematic diagram showing the circuit structure of the last two stages of the GOA unit in the GOA circuit of the present invention.
  • Fig. 6 is a schematic view showing the structure of an embodiment of a liquid crystal display device of the present invention.
  • the embodiment of the present invention first provides a GOA circuit, and the GOA circuit includes a plurality of cascaded GOA units.
  • the connection and control relationship of the plurality of cascaded GOA units are within the scope of those skilled in the art, and are not described herein again.
  • the structure of the Nth stage GOA unit will be described in detail below.
  • FIG. 2 is a schematic diagram of a circuit structure of an embodiment of an Nth-level GOA unit according to the present invention.
  • the N-th stage GOA unit includes a pull-up control module 100, a pull-up module 200, a downlink module 300, and a pull-down module 400.
  • the sustain module 500 and the bootstrap capacitor 600 are pulled down.
  • the pull-up control module 100 is connected to the downlink module 300 and the pull-down maintenance module 500, and one end of the bootstrap capacitor 600 is respectively connected to the downlink module 300 and the pull-up module 200, and the pull-down module 400 and the downlink module respectively.
  • 300 and the scan line 700 of the current stage are connected.
  • the pull-down maintaining module 500 and the pull-down module 400 are also respectively connected to the pull-down signal line 800.
  • the pull-up module 200 is respectively connected to the clock signal line 900 and the scan line 700 of the current stage.
  • the pull-up control module 100 includes a first thin film transistor T11, and the gate of the first thin film transistor T11 is configured to receive a trigger signal ST(N-2) of the N-2th GOA unit, and the source is used for connecting The scan line signal G(N-2) of the N-2 stage GOA unit is connected to the down module 300 and the pull-down maintaining module 500, respectively.
  • the downstream module 300 includes a second thin film transistor T22 having a gate connected to the drain of the first thin film transistor T11, a source connected to the clock signal line 900, and a drain for outputting the GOA unit of the present stage. Trigger signal ST(N).
  • the pull-up module 200 includes a third thin film transistor T21 having a gate connected to the drain of the first thin film transistor T11, a source connected to the clock signal line 900, and a drain and a scan line of the current stage. 700 connections.
  • One end of the bootstrap capacitor 600 is connected to the gates of the second thin film transistor T22 and the third thin film transistor T21, and the other end is connected to the scanning line 700 of the present stage.
  • the pull-down module 400 includes a fourth thin film transistor T41 and a fifth thin film transistor T31.
  • the gate of the fourth thin film transistor T41 is configured to receive the N+2th scan line signal G(N+2), the source and the first film.
  • the drain of the transistor T11 is connected, the drain is connected to the pull-down signal line 800;
  • the gate of the fifth thin film transistor T31 is for receiving the scan line signal G(N+2) of the N+2 stage, the source and the level of the source
  • the scan line 700 is connected, and the drain is connected to the pull-down signal line 800.
  • the pull-down maintaining module 500 includes a sixth thin film transistor T51, a seventh thin film transistor T53, an eighth thin film transistor T32, a ninth thin film transistor T42, a tenth thin film transistor T52, and an eleventh thin film transistor T54; the gate of the sixth thin film transistor T51 The pole is connected to the clock signal line 900, the source is connected to the source of the seventh thin film transistor T53, and the drain of the sixth thin film transistor T51 is connected to the gate of the seventh thin film transistor T53 and the source of the tenth thin film transistor T52, respectively.
  • the drain of the seventh thin film transistor T53 is respectively connected to the gate of the ninth thin film transistor T42 and the source of the eleventh thin film transistor T54, and the gate of the eighth thin film transistor T32 is connected to the clock signal line 900, and the source and the first
  • the drain of the thin film transistor T11 is connected, the drain of the eighth thin film transistor T32 is connected to the source of the scan line 700 of the current stage and the source of the ninth thin film transistor T42, and the drain of the ninth thin film transistor T42 is connected to the pull-down signal line 800.
  • the gate of the tenth thin film transistor T52 is connected to the drain of the first thin film transistor T11, and the drain of the tenth thin film transistor T52 is connected to the pull-down signal line 800, tenth The thin film transistor T54 is connected to the gate and the drain of the first thin film transistor T11, the drain of the eleventh TFT T54 of the pull-down signal line 800 is connected.
  • the source of the eighth thin film transistor T32 is connected to the drain of the first thin film transistor T11 through the first node Q(N); the drain of the seventh thin film transistor T53, the gate of the ninth thin film transistor T42, and the first The sources of the eleven thin film transistors T54 are connected to each other through the second node P(N).
  • FIG. 3 is a waveform diagram of driving signals of the GOA circuit in this embodiment.
  • the GOA circuit in this embodiment uses four clock signals, CK1, CK2, CK3, and CK4.
  • the time of the overlap between the clock signals is called H.
  • the clock signal has a pulse width of 2H and a duty cycle of 50%.
  • the high potential of the clock signal can be 28V (adjustable), and the low potential of the clock signal can be -8V (also adjustable).
  • STV is the trigger signal, which is a high-frequency AC power supply.
  • the pulse width is 2H, and the STV is turned on once per frame.
  • the high potential is 28V and the low potential is -8V.
  • the overlap between STV and CK1 is H; VSS DC DC power supply, -6V (adjustable).
  • Q(N), G(N), ST(N-2), ST(N), and P(N) are important nodes in the circuit.
  • FIG. 4 is a schematic diagram of the circuit structure of the first two stages of the GOA unit in the embodiment of FIG. 2
  • FIG. 5 is a schematic diagram of the circuit structure of the last two stages of the GOA unit in the GOA circuit of the present invention.
  • the T11 of the GOA unit pull-up control module uses STV to control gate and drain
  • the GOA unit pull-down unit in Figure 5 uses STV control.
  • G(N) is controlled by CK3
  • G(N-2) is controlled by CK1
  • G(N+2) is controlled by CK1.
  • G(N) When G(N) is operating: When CK3 goes high, G(N) outputs a high potential, and Q(N) generates a higher potential due to the capacitive coupling effect, and G(N-2) at this time, ST(N-2) is low and does not affect the high potential of Q; when G(N+2) is working: G(N+2) is high, at this time T31, T41 is open, Q(N), G(N) is pulled to a low potential.
  • CK3 will periodically be high, then P(N) will be high, T42 will be periodically turned on, G(N) will be very low, and T32 will be controlled by CK(N). It also opens periodically, so Q(N) is well maintained at a low potential.
  • This patent not only has fewer TFTs, but also facilitates the fabrication of narrow bezels. Moreover, because T32 and T42 are connected in series, the resistance becomes larger, which reduces the risk of Q(N) high potential being pulled to a low potential due to TFT leakage, ensuring Q. The normal waveform of (N) ensures that G(N) is normally turned on.
  • the GOA circuit provided by the invention greatly simplifies the design structure of the circuit while ensuring the completion of the liquid crystal display driving requirement, on the one hand, the structural cost of the circuit is saved, and on the other hand, the structural size of the GOA circuit can be reduced, and the liquid crystal display is enabled.
  • the device can have a design space with a narrower bezel structure.
  • FIG. 6 is a schematic diagram showing the structure of a liquid crystal display device according to an embodiment of the present invention.
  • the liquid crystal display device includes a liquid crystal panel 1 and a GOA circuit 2, wherein
  • the GOA circuit 2 can be a GOA circuit in any of the above embodiments.
  • the structural features of other parts of the liquid crystal display device those skilled in the art will not repeat them here.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Mathematical Physics (AREA)
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Abstract

一种液晶显示装置及其GOA电路，该GOA电路包括多个级联的GOA单元，第N级GOA单元包括上拉控制模块（100）、上拉模块（200）、下传模块（300）、下拉模块（400）、下拉维持模块（500）以及自举电容（600）。该GOA电路在保证完成液晶显示驱动要求的情况下，大大简化了电路的设计结构，一方面节省了电路的结构成本，另一方面可以减小GOA电路的结构尺寸，使液晶显示装置可以有更窄边框结构的设计空间。

Description

液晶显示装置及其GOA电路
【技术领域】
本发明涉及液晶显示的技术领域，具体是涉及一种液晶显示装置及其GOA电路。
【背景技术】
基于a-Si的GOA电路目前被广泛应用于大小尺寸的显示器。GOA 技术有利于成本的降低，并且还有窄边框的设计。
图1是现有技术中常用的一种GOA电路的结构示意图，其一级GOA电路中就采用了17颗TFT（薄膜晶体管）。然而，对于非晶硅GOA电路来说，TFT数量增加会增加边框的尺寸，在目前窄边框的发展趋势下，现有技术中GOA电路结构明显不能满足窄边框显示的设计要求。
【发明内容】
本发明实施例提供一种液晶显示装置及其GOA电路，以解决现有技术中由于GOA电路结构复杂而导致的显示边框不够窄的技术问题。
为解决上述问题，本发明实施例一方面提供了一种GOA电路，所述GOA电路包括多个级联的GOA单元，第N级所述GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块以及自举电容；所述上拉控制模块分别与所述下传模块以及所述下拉维持模块连接，所述自举电容的一端分别与所述下传模块以及所述上拉模块连接，所述下拉模块分别与所述下传模块以及本级的扫描线连接，所述下拉维持模块以及所述下拉模块还分别与下拉信号线连接，上拉模块分别与时钟信号线以及本级的扫描线连接。
为解决上述技术问题，本发明实施例还提供一种液晶显示装置，所述液晶显示装置包括上述实施例中任一项所述的GOA电路。
相对于现有技术，本发明提供的液晶显示装置及其GOA电路，在保证完成液晶显示驱动要求的情况下，大大简化了电路的设计结构，一方面节省了电路的结构成本，另一方面可以减小GOA电路的结构尺寸，使液晶显示装置可以有更窄边框结构的设计空间。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中常用的一种GOA电路的结构示意图
图2是本发明第N级GOA单元一实施例的电路结构示意图；
图3是本实施例中GOA电路的驱动信号波形图；
图4是图2实施例中GOA单元前两级的电路结构示意图；
图5是本发明GOA电路中最后两级GOA单元的电路结构示意图；
图6是本发明液晶显示装置一实施例的结构示意简图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例首先提供GOA电路，该GOA电路包括多个级联的GOA单元，关于多个级联的GOA单元的连接及控制关系在本领域技术人员的理解范围内，此处不再赘述，下面对第N级GOA单元的结构做详细介绍。
请参阅图2，图2是本发明第N级GOA单元一实施例的电路结构示意图，该第N级GOA单元包括上拉控制模块100、上拉模块200、下传模块300、下拉模块400、下拉维持模块500以及自举电容600。
具体而言，该上拉控制模块100分别与下传模块300以及下拉维持模块500连接，自举电容600的一端分别与下传模块300以及上拉模块200连接，下拉模块400分别与下传模块300以及本级的扫描线700连接，下拉维持模块500以及下拉模块400还分别与下拉信号线800连接，上拉模块200分别与时钟信号线900以及本级的扫描线700连接。
其中，该上拉控制模块100包括第一薄膜晶体管T11，该第一薄膜晶体管T11的栅极用于接收第N-2级GOA单元的触发信号ST（N-2），源极用于连接第N-2级GOA单元的的扫描线信号G（N-2），漏极用于分别与下传模块300以及下拉维持模块500连接。
该下传模块300则包括第二薄膜晶体管T22，第二薄膜晶体管T22的栅极与第一薄膜晶体管T11的漏极连接，源极与时钟信号线900连接，漏极用于输出本级GOA单元的触发信号ST（N）。
而该上拉模块200包括第三薄膜晶体管T21，该第三薄膜晶体管T21的栅极与第一薄膜晶体管T11的漏极连接，源极与时钟信号线900连接，漏极与本级的扫描线700连接。
自举电容600的一端分别与第二薄膜晶体管T22以及第三薄膜晶体管T21的栅极连接，另一端与本级的扫描线700连接。
下拉模块400包括第四薄膜晶体管T41以及第五薄膜晶体管T31，该第四薄膜晶体管T41的栅极用于接收第N+2级的扫描线信号G（N+2），源极与第一薄膜晶体管T11的漏极连接，漏极与下拉信号线800连接；该第五薄膜晶体管T31的栅极用于接收第N+2级的扫描线信号G（N+2），源极与本级的扫描线700连接，漏极与下拉信号线800连接。
下拉维持模块500包括第六薄膜晶体管T51、第七薄膜晶体管T53、第八薄膜晶体管T32、第九薄膜晶体管T42、第十薄膜晶体管T52以及第十一薄膜晶体管T54；该第六薄膜晶体管T51的栅极与时钟信号线900连接，源极与第七薄膜晶体管T53的源极连接，第六薄膜晶体管T51的漏极分别与第七薄膜晶体管T53的栅极以及第十薄膜晶体管T52的源极连接，第七薄膜晶体管T53的漏极分别与第九薄膜晶体管T42的栅极以及第十一薄膜晶体管T54的源极连接，第八薄膜晶体管T32的栅极与时钟信号线900连接，源极与第一薄膜晶体管T11的漏极连接，第八薄膜晶体管T32的漏极分别与本级的扫描线700以及第九薄膜晶体管T42的源极连接，第九薄膜晶体管T42的漏极连接下拉信号线800连接，第十薄膜晶体管T52的栅极与第一薄膜晶体管T11的漏极连接，第十薄膜晶体管T52的漏极与下拉信号线800连接，第十一薄膜晶体管T54的栅极与第一薄膜晶体管T11的漏极连接，第十一薄膜晶体管T54的漏极与下拉信号线800连接。
其中，该第八薄膜晶体管T32的源极通过第一节点Q（N）与第一薄膜晶体管T11的漏极连接；而第七薄膜晶体管T53的漏极、第九薄膜晶体管T42的栅极以及第十一薄膜晶体管T54的源极之间通过第二节点P（N）相互连接。
请参阅图3，图3是本实施例中GOA电路的驱动信号波形图。本实施例中的GOA电路采用4个时钟信号，CK1、CK2、CK3、以及CK4 高频交流电源。时钟信号之间的overlap的时间取名叫做H。时钟信号的脉宽2H，占空比50%。时钟信号的高电位可以为28V（可调），时钟信号的低电位可以为-8V（也可调）。STV是触发信号，为高频交流电源，脉宽为2H、STV每frame开启一次，高电位为28V，低电位为-8V； STV 跟CK1的 overlap为H； VSS DC直流电源,为-6V（可调）。Q（N）、G（N）、ST（N-2）、ST（N）以及P（N）是电路中重要节点。
下面用第N级的GOA电路作为例子，进行原理性的说明。进一步地，请参阅图4和图5，图4是图2实施例中GOA单元的前两级的电路结构示意图，而图5是本发明GOA电路中最后两级GOA单元的电路结构示意图。图4中GOA单元上拉控制模块的T11采用STV控制gate和drain，而图5中GOA单元下拉单元则采用STV控制。
根据图3中的波形可知，G（N）由CK3控制，那么G（N-2）由CK1控制，G（N+2）则由CK1控制。
G（N-2）工作时：当G（N-2）、ST（N-2）为高电位的时候，G（N-2）的高电位输入到Q（N），T21打开，此时CK（N）=CK3，为低电位，G（N）输出低电位。
G（N）工作时：当CK3变为高电位时，G（N）输出高电位，Q（N）由于电容耦合效应，会产生更高的电位，并且此时的G（N-2）、ST（N-2）为低电位，不会影响Q点高电位；当G（N+2）工作时：G（N+2）为高电位，此时T31，T41打开，Q（N）、G（N）被拉到低电位。
后续CK3会周期性的为高电位，那么P（N）为高电位，T42会周期性的打开，G（N）会被很好的低电位；同时，T32因受到CK（N）的控制，也会周期的打开，所以Q（N）被很好的维持了低电位。
本专利不但TFT少，有利于窄边框的制作，而且因为T32、T42采用串联的方式，电阻变大，降低了由于TFT漏电，Q（N）高电位被拉到低电位的风险，保证了Q（N）的正常波形，确保G（N）正常的打开。
本发明提供的GOA电路，在保证完成液晶显示驱动要求的情况下，大大简化了电路的设计结构，一方面节省了电路的结构成本，另一方面可以减小GOA电路的结构尺寸，使液晶显示装置可以有更窄边框结构的设计空间。
另外，本发明实施例还提供一种液晶显示装置，请参阅图6，图6是本发明液晶显示装置一实施例的结构示意简图，该液晶显示装置包括液晶面板1以及GOA电路2，其中该GOA电路2可以为上述任一实施例中的GOA电路。而关于液晶显示装置其他部分的结构特征，在本领域技术人员的理解范围内，此处不再赘述。
以上所述仅为本发明的部分实施例，并非因此限制本发明的保护范围，凡是利用本发明说明书及附图内容所作的等效装置或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种GOA电路，其特征在于，所述GOA电路包括多个级联的GOA单元，第N级所述GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块以及自举电容；所述上拉控制模块分别与所述下传模块以及所述下拉维持模块连接，所述自举电容的一端分别与所述下传模块以及所述上拉模块连接，所述下拉模块分别与所述下传模块以及本级的扫描线连接，所述下拉维持模块以及所述下拉模块还分别与下拉信号线连接，上拉模块分别与时钟信号线以及本级的扫描线连接；所述上拉控制模块包括第一薄膜晶体管T11，所述第一薄膜晶体管T11的栅极用于接收第N-2级GOA单元的触发信号，源极用于连接第N-2级GOA单元的的扫描线信号，漏极用于分别与所述下传模块以及所述下拉维持模块连接；所述下拉维持模块包括第六薄膜晶体管T51、第七薄膜晶体管T53、第八薄膜晶体管T32、第九薄膜晶体管T42、第十薄膜晶体管T52以及第十一薄膜晶体管T54；所述第六薄膜晶体管T51的栅极与所述时钟信号线连接，源极与所述第七薄膜晶体管T53的源极连接，所述第六薄膜晶体管T51的漏极分别与所述第七薄膜晶体管T53的栅极以及所述第十薄膜晶体管T52的源极连接，所述第七薄膜晶体管T53的漏极分别与所述第九薄膜晶体管T42的栅极以及所述第十一薄膜晶体管T54的源极连接，所述第八薄膜晶体管T32的栅极与所述时钟信号线连接，源极与所述第一薄膜晶体管T11的漏极连接，所述第八薄膜晶体管T32的漏极分别与本级的扫描线以及所述第九薄膜晶体管T42的源极连接，所述第九薄膜晶体管T42的漏极连接所述下拉信号线连接，所述第十薄膜晶体管T52的栅极与所述第一薄膜晶体管T11的漏极连接，所述第十薄膜晶体管T52的漏极与所述下拉信号线连接，所述第十一薄膜晶体管T54的栅极与所述第一薄膜晶体管T11的漏极连接，所述第十一薄膜晶体管T54的漏极与所述下拉信号线连接。
  2. 一种GOA电路，其特征在于，所述GOA电路包括多个级联的GOA单元，第N级所述GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块以及自举电容；所述上拉控制模块分别与所述下传模块以及所述下拉维持模块连接，所述自举电容的一端分别与所述下传模块以及所述上拉模块连接，所述下拉模块分别与所述下传模块以及本级的扫描线连接，所述下拉维持模块以及所述下拉模块还分别与下拉信号线连接，上拉模块分别与时钟信号线以及本级的扫描线连接。
  3. 根据权利要求2所述的GOA电路，其特征在于，所述上拉控制模块包括第一薄膜晶体管T11，所述第一薄膜晶体管T11的栅极用于接收第N-2级GOA单元的触发信号，源极用于连接第N-2级GOA单元的的扫描线信号，漏极用于分别与所述下传模块以及所述下拉维持模块连接。
  4. 根据权利要求3所述的GOA电路，其特征在于，所述下传模块包括第二薄膜晶体管T22，所述第二薄膜晶体管T22的栅极与所述第一薄膜晶体管T11的漏极连接，源极与所述时钟信号线连接，漏极用于输出本级GOA单元的触发信号。
  5. 根据权利要求4所述的GOA电路，其特征在于，所述上拉模块包括第三薄膜晶体管T21，所述第三薄膜晶体管T21的栅极与所述第一薄膜晶体管T11的漏极连接，源极与所述时钟信号线连接，漏极与本级的扫描线连接。
  6. 根据权利要求5所述的GOA电路，其特征在于，自举电容的一端分别与所述第二薄膜晶体管T22以及所述第三薄膜晶体管T21的栅极连接，另一端与本级的扫描线连接。
  7. 根据权利要求6所述的GOA电路，其特征在于，所述下拉模块包括第四薄膜晶体管T41以及第五薄膜晶体管T31，所述第四薄膜晶体管T41的栅极用于接收第N+2级的扫描线信号，源极与所述第一薄膜晶体管T11的漏极连接，漏极与所述下拉信号线连接；所述第五薄膜晶体管T31的栅极用于接收第N+2级的扫描线信号，源极与本级的扫描线连接，漏极与所述下拉信号线连接。
  8. 根据权利要求2所述的GOA电路，其特征在于，所述下拉维持模块包括第六薄膜晶体管T51、第七薄膜晶体管T53、第八薄膜晶体管T32、第九薄膜晶体管T42、第十薄膜晶体管T52以及第十一薄膜晶体管T54；所述第六薄膜晶体管T51的栅极与所述时钟信号线连接，源极与所述第七薄膜晶体管T53的源极连接，所述第六薄膜晶体管T51的漏极分别与所述第七薄膜晶体管T53的栅极以及所述第十薄膜晶体管T52的源极连接，所述第七薄膜晶体管T53的漏极分别与所述第九薄膜晶体管T42的栅极以及所述第十一薄膜晶体管T54的源极连接，所述第八薄膜晶体管T32的栅极与所述时钟信号线连接，源极与所述第一薄膜晶体管T11的漏极连接，所述第八薄膜晶体管T32的漏极分别与本级的扫描线以及所述第九薄膜晶体管T42的源极连接，所述第九薄膜晶体管T42的漏极连接所述下拉信号线连接，所述第十薄膜晶体管T52的栅极与所述第一薄膜晶体管T11的漏极连接，所述第十薄膜晶体管T52的漏极与所述下拉信号线连接，所述第十一薄膜晶体管T54的栅极与所述第一薄膜晶体管T11的漏极连接，所述第十一薄膜晶体管T54的漏极与所述下拉信号线连接。
  9. 根据权利要求8所述的GOA电路，其特征在于，所述第八薄膜晶体管T32的源极通过第一节点Q（N）与所述第一薄膜晶体管T11的漏极连接。
  10. 根据权利要求8所述的GOA电路，其特征在于，所述第七薄膜晶体管T53的漏极、所述第九薄膜晶体管T42的栅极以及所述第十一薄膜晶体管T54的源极之间通过第二节点P（N）相互连接。
  11. 一种液晶显示装置，其特征在于，所述液晶显示装置包括GOA电路，所述GOA电路包括多个级联的GOA单元，第N级所述GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块以及自举电容；所述上拉控制模块分别与所述下传模块以及所述下拉维持模块连接，所述自举电容的一端分别与所述下传模块以及所述上拉模块连接，所述下拉模块分别与所述下传模块以及本级的扫描线连接，所述下拉维持模块以及所述下拉模块还分别与下拉信号线连接，上拉模块分别与时钟信号线以及本级的扫描线连接。
  12. 根据权利要求11所述的液晶显示装置，其特征在于，所述上拉控制模块包括第一薄膜晶体管T11，所述第一薄膜晶体管T11的栅极用于接收第N-2级GOA单元的触发信号，源极用于连接第N-2级GOA单元的的扫描线信号，漏极用于分别与所述下传模块以及所述下拉维持模块连接。
  13. 根据权利要求12所述的液晶显示装置，其特征在于，所述下传模块包括第二薄膜晶体管T22，所述第二薄膜晶体管T22的栅极与所述第一薄膜晶体管T11的漏极连接，源极与所述时钟信号线连接，漏极用于输出本级GOA单元的触发信号。
  14. 根据权利要求13所述的液晶显示装置，其特征在于，所述上拉模块包括第三薄膜晶体管T21，所述第三薄膜晶体管T21的栅极与所述第一薄膜晶体管T11的漏极连接，源极与所述时钟信号线连接，漏极与本级的扫描线连接。
  15. 根据权利要求14所述的液晶显示装置，其特征在于，自举电容的一端分别与所述第二薄膜晶体管T22以及所述第三薄膜晶体管T21的栅极连接，另一端与本级的扫描线连接。
  16. 根据权利要求15所述的液晶显示装置，其特征在于，所述下拉模块包括第四薄膜晶体管T41以及第五薄膜晶体管T31，所述第四薄膜晶体管T41的栅极用于接收第N+2级的扫描线信号，源极与所述第一薄膜晶体管T11的漏极连接，漏极与所述下拉信号线连接；所述第五薄膜晶体管T31的栅极用于接收第N+2级的扫描线信号，源极与本级的扫描线连接，漏极与所述下拉信号线连接。
  17. 根据权利要求11所述的液晶显示装置，其特征在于，所述下拉维持模块包括第六薄膜晶体管T51、第七薄膜晶体管T53、第八薄膜晶体管T32、第九薄膜晶体管T42、第十薄膜晶体管T52以及第十一薄膜晶体管T54；所述第六薄膜晶体管T51的栅极与所述时钟信号线连接，源极与所述第七薄膜晶体管T53的源极连接，所述第六薄膜晶体管T51的漏极分别与所述第七薄膜晶体管T53的栅极以及所述第十薄膜晶体管T52的源极连接，所述第七薄膜晶体管T53的漏极分别与所述第九薄膜晶体管T42的栅极以及所述第十一薄膜晶体管T54的源极连接，所述第八薄膜晶体管T32的栅极与所述时钟信号线连接，源极与所述第一薄膜晶体管T11的漏极连接，所述第八薄膜晶体管T32的漏极分别与本级的扫描线以及所述第九薄膜晶体管T42的源极连接，所述第九薄膜晶体管T42的漏极连接所述下拉信号线连接，所述第十薄膜晶体管T52的栅极与所述第一薄膜晶体管T11的漏极连接，所述第十薄膜晶体管T52的漏极与所述下拉信号线连接，所述第十一薄膜晶体管T54的栅极与所述第一薄膜晶体管T11的漏极连接，所述第十一薄膜晶体管T54的漏极与所述下拉信号线连接。
  18. 根据权利要求17所述的液晶显示装置，其特征在于，所述第八薄膜晶体管T32的源极通过第一节点Q（N）与所述第一薄膜晶体管T11的漏极连接。
  19. 根据权利要求17所述的液晶显示装置，其特征在于，所述第七薄膜晶体管T53的漏极、所述第九薄膜晶体管T42的栅极以及所述第十一薄膜晶体管T54的源极之间通过第二节点P（N）相互连接。
PCT/CN2017/081976 2017-04-10 2017-04-26 液晶显示装置及其goa电路 WO2018188119A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115862511A (zh) * 2022-11-30 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108172181A (zh) * 2017-12-21 2018-06-15 深圳市华星光电技术有限公司 一种goa电路及液晶显示面板
CN109036307B (zh) * 2018-07-27 2019-06-21 深圳市华星光电技术有限公司 包括goa电路的液晶面板及其驱动方法
CN113168880A (zh) * 2018-12-28 2021-07-23 深圳市柔宇科技股份有限公司 Goa单元及其goa电路、显示装置
CN111161689B (zh) * 2020-02-12 2021-07-06 武汉华星光电技术有限公司 一种goa电路及其显示面板
CN113362752A (zh) * 2021-06-01 2021-09-07 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080101529A1 (en) * 2006-10-26 2008-05-01 Mitsubishi Electric Corporation Shift register and image display apparatus containing the same
CN104008739A (zh) * 2014-05-20 2014-08-27 深圳市华星光电技术有限公司 一种扫描驱动电路和一种液晶显示装置
CN104064158A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN104064160A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN106205528A (zh) * 2016-07-19 2016-12-07 深圳市华星光电技术有限公司 一种goa电路及液晶显示面板
CN106328084A (zh) * 2016-10-18 2017-01-11 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104167191B (zh) * 2014-07-04 2016-08-17 深圳市华星光电技术有限公司 用于平板显示的互补型goa电路
CN105632441B (zh) * 2016-02-26 2018-03-27 深圳市华星光电技术有限公司 栅极驱动电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080101529A1 (en) * 2006-10-26 2008-05-01 Mitsubishi Electric Corporation Shift register and image display apparatus containing the same
CN104008739A (zh) * 2014-05-20 2014-08-27 深圳市华星光电技术有限公司 一种扫描驱动电路和一种液晶显示装置
CN104064158A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN104064160A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN106205528A (zh) * 2016-07-19 2016-12-07 深圳市华星光电技术有限公司 一种goa电路及液晶显示面板
CN106328084A (zh) * 2016-10-18 2017-01-11 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3611721A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115862511A (zh) * 2022-11-30 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862511B (zh) * 2022-11-30 2024-04-12 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

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