WO2018184406A1 - 一种射频开关电路 - Google Patents

一种射频开关电路 Download PDF

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Publication number
WO2018184406A1
WO2018184406A1 PCT/CN2017/117627 CN2017117627W WO2018184406A1 WO 2018184406 A1 WO2018184406 A1 WO 2018184406A1 CN 2017117627 W CN2017117627 W CN 2017117627W WO 2018184406 A1 WO2018184406 A1 WO 2018184406A1
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parallel
series
radio frequency
branch
mos transistors
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PCT/CN2017/117627
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English (en)
French (fr)
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张志浩
陈哲
章国豪
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广东工业大学
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Publication of WO2018184406A1 publication Critical patent/WO2018184406A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to the field of radio frequency integrated circuits, and more particularly to a radio frequency switching circuit.
  • the current cellular communication working frequency band has been increased to 14 or 16.
  • RF radio frequency
  • the main antenna switch usually includes band channels such as GSM and 3G./4G. It has the largest size, the highest complexity, and the strongest power handling capability. It must have at least +36dBm GSM Tx power capacity. If circuit loss and antenna mismatch are considered.
  • the power handling capability should be +40dBm (10W).
  • each of the current RF switching circuits is generally composed of a series branch and a parallel branch, and each series branch and parallel branch are composed of one or more N-type MOS transistor stacks, each of which The gates of the transistors are each connected in series with a resistor Rg.
  • Rg resistor
  • the size of the tube of the series branch is usually larger, and the voltage swing of the transistor chain of the series branch is not balanced.
  • the size of the tube in the parallel branch is usually larger. Small, generally one-fifth to one-seventh the size of the tube in the series branch.
  • the top transistor will first reach the breakdown voltage, limiting the maximum input power that the RF switch can handle; on the other hand, MOS transistors with larger voltage swings will contribute to higher harmonics, thereby reducing RF The overall linearity of the switch.
  • the traditional solution is to increase the number of stacked transistors in series and parallel branches at the expense of greater insertion loss and larger chip area.
  • the object of the present invention is to provide a radio frequency switching circuit to improve the power handling capability and linearity of the switch, and prevent the MOS transistor at the top of the stacked transistor chain from being first broken down under a large voltage swing, thereby achieving higher reliability.
  • RF switch
  • the embodiment of the present invention provides the following technical solutions:
  • a radio frequency switching circuit comprising a plurality of radio frequency signal paths, each radio frequency signal path comprising a series branch and a parallel branch, each parallel branch comprising N stacked MOS transistors; wherein N is a positive integer greater than 1;
  • Each parallel branch also includes:
  • N gate parallel resistors respectively connected to the gates of the N MOS transistors
  • One end is connected to at least one gate in parallel with a resistance resistor connected to the parallel control signal; wherein M is a positive integer greater than 1 and less than N.
  • each parallel branch includes:
  • N gate parallel resistors respectively connected to the gates of the N MOS transistors
  • K is a positive integer greater than 1 and less than N;
  • a second bias resistor connected at one end to the rear N-K gate shunt resistors and the other end to a parallel control signal.
  • One end of the series branch in each RF signal path is connected to the antenna port, and the other end is connected to the RF signal port; one end of each parallel signal path in the RF signal path is connected to the RF signal port, and the other end is connected to the ground end. .
  • each RF signal path includes:
  • One end is connected to the gates of the N MOS transistors, and the other end is connected to the series control signals of the N series series resistors.
  • the MOS transistors in each of the parallel branches are N-type transistors.
  • MOS transistors in each series branch are N-type transistors.
  • the serial control signal of the target RF signal path is at a high level
  • the parallel control signal of the target RF signal path is at a low level
  • the series control signal is low and the parallel control signal is high.
  • a radio frequency switching circuit provided by an embodiment of the present invention includes multiple radio frequency signal paths, each radio frequency signal path includes a series branch and a parallel branch, and each parallel branch includes N stacked MOS transistors. Where N is a positive integer greater than 1; each parallel branch further includes: N gate parallel resistors respectively connected to the gates of the N MOS transistors; one end is connected to at least one gate parallel resistor, and the other end is connected in parallel The M bias resistors to which the control signals are connected; wherein M is a positive integer greater than one and less than N.
  • each of the parallel shunt resistors in the parallel branch is connected to the bias resistor and then connected to the control signal port, which can effectively improve the large voltage swing on each stacked MOS transistor.
  • the uneven distribution allows each tube to withstand a relatively uniform voltage swing, thereby preventing the tube at the top of the stacked transistor chain from being broken first, and preventing the deterioration of the switching harmonics caused by the large voltage swing on the tube, further improving Power handling capability and linearity of the RF switch.
  • FIG. 1 is a circuit diagram of a structure of a radio frequency switch in the prior art
  • FIG. 2 is a schematic diagram of a voltage swing simulation curve of each transistor of the RF switch structure in the prior art
  • FIG. 3 is a circuit diagram of an embodiment of a radio frequency switch according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a voltage swing simulation curve of each transistor of a radio frequency switch structure disclosed in an embodiment of the present invention
  • FIG. 5 is a schematic diagram showing a comparison curve of a maximum voltage amplitude of a transistor of the RF switch structure disclosed in the embodiment of the present invention
  • FIG. 6 is a schematic diagram showing a simulation comparison curve of an RF switch structure disclosed in an embodiment of the present invention and an insertion loss loss vs. input power of a radio frequency switch structure in the prior art;
  • FIG. 7 is a schematic diagram showing a simulation comparison curve between a radio frequency switch structure and a second harmonic vs input power of a radio frequency switch structure according to an embodiment of the present invention
  • FIG. 8 is a schematic diagram showing a simulation comparison curve between a radio frequency switch structure and a third harmonic vs input power of a radio frequency switch structure according to an embodiment of the present invention.
  • the embodiment of the invention discloses a radio frequency switching circuit to improve the power processing capability and linearity of the switch, and prevent the MOS transistor at the top of the stacked transistor chain from being first broken down under a large voltage swing, thereby achieving higher reliability.
  • RF switch
  • a radio frequency switching circuit includes a plurality of radio frequency signal paths, each of which includes a series branch and a parallel branch, each parallel branch including N stacked MOS transistors; wherein N is a positive integer greater than one; each parallel branch also includes:
  • N gate parallel resistors respectively connected to the gates of the N MOS transistors
  • One end is connected to at least one gate in parallel with a resistance resistor connected to the parallel control signal; wherein M is a positive integer greater than 1 and less than N.
  • One end of the series branch in each RF signal path is connected to the antenna port, and the other end is connected to the RF signal port; one end of each parallel signal path in the RF signal path is connected to the RF signal port, and the other end is connected to the ground end. .
  • each RF signal path includes:
  • One end is connected to the gates of the N MOS transistors, and the other end is connected to the series control signals of the N series series resistors.
  • FIG. 1 is a circuit diagram of a conventional RF switch structure provided by the embodiment
  • the RF signal path in the RF switch circuit is composed of a series branch and a parallel branch; for example, the series branch 1 One end is connected to the RF1 RF signal port, and the other end is connected to the antenna port ANT; the parallel branch 1 is connected to the RF1 RF signal port, and the other end is connected to the ground; the other RF path (RF2, RF3, ..., RFN) is connected with the RF1
  • the series branch and the parallel branch are routed by one or more N-type MOS transistor stacks, wherein the gates of each transistor are respectively connected in series with a resistor Rg.
  • the gates of the N N-type MOS transistors (M1, M2, ..., MN) stacked in the series branch 1 are respectively connected to one gate series resistor Rg, and the other ends of the gate series resistors Rg in all the series branches 1 are Connected to the control signal VGser1; the gates of the N N-type MOS transistors (M01, M02, ..., M0N) stacked in the parallel branch 1 are respectively connected to a gate series resistor Rg, and the gates of all the parallel branches 1 are connected in series
  • the other end of the resistor Rg is connected to the control signal VGsht1.
  • connection structure of the series branches (series branches 2, 3, ..., N) in the other RF paths (RF2, RF3, ..., RFN) is the same as the series branch 1 in the RF1 path, and other RF paths (RF2, RF3)
  • connection structure of the parallel branches (parallel branches 2, 3, ..., N) in ..., RFN) is the same as the parallel branch 1 in the RF1 path.
  • Control signal pairs (VGser1 and VGsht1, VGser2 and VGsht2, ..., VGserN and VGshtN) keep one of them high (usually 2.0 to 2.5V) and the other low (usually -2.0 to -2.5V).
  • the control signal VGser1 When the first RF signal path RF1 is turned on, the control signal VGser1 is at a high level, the series branch 1 under the RF1 path enters an ON state, the control signal VGsht1 is at a low level, and the parallel branch under the RF1 path 1 enters the OFF state; the control signals (VGser2, VGser3, ..., VGserN) of the series branches 2, 3, ..., N in the remaining paths (RF2, RF3, ..., RFN) are low.
  • the series branches 2, 3, ..., N enter the OFF state, and the control signals (VGsht2, VGsht3, ..., VGshtN) of the parallel branches 2, 3, ..., N are at a high level, and the parallel branch 2 3, ..., N enters the ON state.
  • each stacked transistor of the OFF branch can be equally divided into the same RF voltage swing.
  • the maximum input power that the RF switch can handle is:
  • the branch circuit is composed of N transistors, and the source-drain breakdown voltage of the single transistor is Vbdds, and the load impedance is Zo.
  • the total RF voltage swing will be unevenly distributed across the MOS transistors.
  • the effect of uneven distribution of voltage swing is also related to the size of the tube. The smaller the tube size, the more uneven the voltage swing is.
  • the size of the tube of the series branch is usually larger, and the voltage swing of the transistor chain of the series branch is not balanced.
  • the size of the tube in the parallel branch is usually larger. Small, generally one-fifth to one-seventh the size of the pipe in the series branch.
  • FIG. 2 is a voltage swing simulation curve of each transistor of a parallel branch stack in an OFF state when a single-pole double-throw (SPDT) switch of the prior art is used at an input power of 36 dBm.
  • SPDT single-pole double-throw
  • the parallel branch is divided into a plurality of sections, and the gates of the MOS transistors in each section are connected to a bias resistor through a gate parallel resistor, and the other end of the bias resistor is connected in parallel.
  • the signals are connected.
  • M bias resistors are included in the parallel branch, it is equivalent to dividing all the MOS transistors into M parts; thus, the bias resistors are connected to the parallel control signals, which can effectively improve the large
  • the uneven distribution of the voltage swing across the stacked MOS transistors allows each tube to withstand a relatively uniform voltage swing, thereby preventing the tube at the top of the stacked transistor chain from being broken down and reducing the voltage swing harmonics on the tube. , making the power handling capability of the switch closer to equation (1).
  • the solution is applicable to a single-pole multi-throw antenna switch chip with a symmetrical structure, and can be easily extended to the application of a band selection switch, a diversity antenna switch, an asymmetric switch structure, and a multi-tool multi-throw switch chip.
  • each parallel branch includes:
  • N gate parallel resistors respectively connected to the gates of the N MOS transistors
  • K is a positive integer greater than 1 and less than N;
  • a second bias resistor connected at one end to the rear N-K gate shunt resistors and the other end to a parallel control signal.
  • the MOS transistors in each parallel branch are N-type transistors; the MOS transistors in each series branch are N-type transistors; in each RF signal path, only parallel control signals and series control signals are maintained at the same time One of the signals is at a high level; when the target RF signal path is turned on, the series control signal of the target RF signal path is at a high level, and the parallel control signal of the target RF signal path is at a low level; In other RF signal paths other than the target RF signal path, the series control signal is low and the parallel control signal is high.
  • the parallel branch is equivalent
  • the N MOS transistors in the path are divided into two parts; one part is the front K (1 ⁇ K ⁇ N) stacked transistors, and the other part is the latter NK stacked transistors.
  • the MOS transistor in this scheme The stacked transistor technology is used. Therefore, in the present embodiment, the MOS transistor is described from front to back. From the front to the back, it can be understood that the end of the parallel branch connected to the RF signal port is the front, which can also be understood as: the parallel branch. The end connected to the ground is the front, which is not particularly limited as long as the N MOS transistors can be divided into two parts.
  • the RF switch provided by the present invention includes N radio frequency signal paths (RF1, RF2, RF3, ..., RFN), and each path is composed of a series branch and a parallel branch.
  • One end of the series branch circuit 1 is connected to the RF1 radio frequency signal port, and the other end is connected to the antenna port ANT; one end of the parallel branch circuit 1 is connected to the RF1 radio frequency signal port, and the other end is connected to the ground.
  • the other RF paths (RF2, RF3, ..., RFN) are connected the same as the RF1 path.
  • the series branch and the parallel branch are routed by one or more N-type MOS transistor stacks, wherein the gates of each transistor are each connected in series with a resistor Rg.
  • the gates of the N N-type MOS transistors (M1, M2, ..., MN) stacked in the series branch 1 are respectively connected to one gate series resistor Rg, and the other ends of all the gate series resistors Rg in the series branch 1 are Connected to the control signal VGser1; the gates of the N N-type MOS transistors (M01, M02, ..., M0N) stacked in the parallel branch 1 are respectively connected to a gate series resistor Rg, and then the front K of the parallel branch 1 ( The other end of the gate series resistor Rg to which 1 ⁇ K ⁇ N) stacked transistors (M01, M02, ..., M0K) are connected is connected to a bias resistor Rbias1, and the NK stacked transistors in the parallel branch 1 are followed by (M0(K+1), M0(K+2), ..., M0N) The other end of the connected gate series resistor Rg is connected to a bias resistor Rbias2, and the other ends of the bias resistors
  • the signal VGsht1 is connected.
  • the connection structure of the series branches (series branches 2, 3, ..., N) in the other RF paths (RF2, RF3, ..., RFN) is the same as the series branch 1 in the RF1 path, and other RF paths (RF2, RF3)
  • the connection structure of the parallel branches (parallel branches 2, 3, ..., N) in ..., RFN) is the same as the parallel branch 1 in the RF1 path.
  • VGser1 and VGsht1, VGser2 and VGsht2, ..., VGserN and VGshtN are a control signal pair, and one of them is kept at a high level (usually 2.0 to 2.5V) at the same time, and One is low (usually -2.0 to -2.5V).
  • the control signal VGser1 When the RF1 path is turned on, the control signal VGser1 is at a high level, the series branch 1 under the RF1 path enters an ON state, the control signal VGsht1 is at a low level, and the parallel branch 1 under the RF1 path is turned OFF (off) State; the control signals (VGser2, VGser3, ..., VGserN) of the series branches 2, 3, ..., N in the remaining other paths (RF2, RF3, ..., RFN) are low level, series branch 2 3, ..., N enters the OFF state, the control signals (VGsht2, VGsht3, ..., VGshtN) of the parallel branches 2, 3, ..., N are high, parallel branches 2, 3, ..., N Enter the state of ON.
  • FIG. 4 is a voltage swing simulation curve of each transistor of a parallel branch stack in an OFF state with an input power of 36 dBm using a single pole double throw (SPDT) switch embodiment of the present invention
  • FIG. 5 is a A single pole double throw (SPDT) switch embodiment of the prior art simulates a comparison curve of the maximum voltage amplitude experienced by each transistor of the parallel branch stack in the OFF state at an input power of 36 dBm.
  • Simulation and experimental results show that the existing typical switching circuit structure will make the RF voltage swing spread from top to bottom and unevenly distributed on each stacked MOS transistor, and the switching RF voltage swing of the present invention is relatively evenly distributed. On each of the stacked MOS transistors, the robustness of the switch is improved.
  • Figure 6 is a simulated comparison of the insertion loss vs input power of a single pole double throw (SPDT) switch embodiment of the present invention and prior art.
  • the results show that the 0.1 dB power compression point of the switching circuit using the present invention is higher than that of the prior art switch, and the present invention functions to provide switching power processing capability.
  • 7 and 8 are simulation comparison curves of the second harmonic vs input power and the third harmonic vs input power of a single pole double throw (SPDT) switch embodiment of the present invention and the prior art, respectively.
  • the results show that under large signal power conditions, the second and third harmonics of the switching circuit employing the present invention are significantly better than those of the prior art.
  • the simulation and experimental results show that the RF switch structure proposed by the present invention can effectively improve the uneven distribution of the voltage swing of the stacked tube chain, thereby improving the power handling capability and linearity of the switch.

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Abstract

一种射频开关电路，包括多个射频信号通路（RF1，RF2，……，RFN），每个射频信号通路（RF1，RF2，……，RFN）包括串联支路（1，2，……，N）和并联支路（1，2，……，N），每个并联支路（1，2，……，N）包括N个堆叠的MOS晶体管（M01，M02，……，M0N）；每个并联支路（1，2，……，N）还包括：分别与N个MOS晶体管（M01，M02，……，M0N）栅极相连的N个栅极并联电阻（Rg）；一端与至少一个栅极并联电阻（Rg）相连，另一端与并联控制信号（VGsht1，VGsht2，……，VGshtN）相连的M个偏置电阻（Rbias1，Rbias2）；可见，并联支路（1，2，……，N）中的每个栅极并联电阻（Rg）均与偏置电阻（Rbias1，Rbias2）相连后再一同连接到控制信号（VGsht1，VGsht2，……，VGshtN）端口，能够非常有效地改善大电压摆幅在各个堆叠的MOS晶体管（M01，M02，……，M0N）上的不均匀分布，让每个管子都承受比较均匀的电压摆幅，从而防止堆叠晶体管链顶端的管子率先被击穿，以及防止管子上大电压摆幅所导致的开关谐波的恶化，进一步提高了射频开关的功率处理能力和线性度。

Description

一种射频开关电路
本申请要求于2017年04月07日提交中国专利局、申请号为201710225103.1、发明名称为“一种射频开关电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及射频集成电路技术领域，更具体地说，涉及一种射频开关电路。
背景技术
随着移动终端版本的不断演进和WCDMA与3GPP LTE标准的采纳，目前蜂窝通信工作频段已经增加到14或16个，在移动小型设备中要支持如此多频段和工作模式，射频(RF)开关扮演了越来越重要的作用，特别是主天线开关。但主天线开关通常包含GSM和3G./4G等频段通路，尺寸最大，复杂性最高，功率处理能力也要求最强，其至少要具备+36dBm GSM Tx功率容量，如果考虑电路损耗和天线失配，功率处理能力应达到+40dBm(10W)。另外考虑到正交频分多址(OFDMA)等这些复杂的调制方案产生的波形幅度变化范围非常大，因此信号具有很高的峰均比(PAPR)，这要求处理它们的射频开关具有杰出的线性度，以便最大限度地降低射频信号路径中的失真。由于低功耗高集成高可靠性的优势，基于硅衬底的射频开关在高掷数开关应用中具有一定优势。考虑到由硅材料制作的晶体管的漏源击穿电压只有3.0～4.0V，当前主流的绝缘硅(SOI)CMOS射频开关通常采用堆叠晶体管(stacked-FETs)技术来提高开关的功率处理能力。
如图1所示，目前射频开关电路中的每一条通路通常由一个串联支路和一个并联支路组成，每个串联支路和并联支路由一个或多个N型MOS晶体管堆叠组成，其中每个晶体管的栅极都分别与一个电阻Rg串联。然而，由于MOS晶体管存在多处寄生电容效应以及栅电阻Rg并不能完全阻断射频信号，总的射频电压摆幅将会不均匀地分布在各个MOS晶体管上。 这种电压摆幅不均匀分布的效应还跟管子尺寸有关，管子尺寸越小，电压摆幅不均匀分布的现象就越严重。对于射频开关，为了获得较低的插入损耗，通常串联支路的管子尺寸较大，串联支路的晶体管链的电压摆幅不平衡分布现象并不严重；然而并联支路中管子的尺寸通常较小，一般为串联支路中管子尺寸的5分之一至七分之一，当并联支路处于OFF状态时，堆叠晶体管链的顶端管子承受最大的电压摆幅，底端管子承受最小的电压摆幅，分布在各个晶体管上的电压摆幅从堆叠晶体管链的顶端至底端依次减小。一方面，顶端晶体管将首先达到击穿电压，限制了射频开关能够处理的最大输入功率；另一方面，具有较大电压摆幅的MOS晶体管将贡献更大的高次谐波，从而降低了射频开关的总体线性度。传统的解决方法是增加串联和并联支路堆叠晶体管的数量，其代价是产生更大的插入损耗和占用更大的芯片面积。
因此，如何使射频电压摆幅尽量均匀地分布在各个MOS晶体管上，提高开关的功率处理能力和线性度，同时防止堆叠晶体管链顶端的MOS晶体管在大电压摆幅下首先被击穿，实现可靠性更高的射频开关，是本领域技术人员需要解决的问题。
发明内容
本发明的目的在于提供一种射频开关电路，以实现提高开关的功率处理能力和线性度，同时防止堆叠晶体管链顶端的MOS晶体管在大电压摆幅下首先被击穿，实现可靠性更高的射频开关。
为实现上述目的，本发明实施例提供了如下技术方案：
一种射频开关电路，包括多个射频信号通路，每个射频信号通路包括串联支路和并联支路，每个并联支路包括N个堆叠的MOS晶体管；其中，N为大于1的正整数；每个并联支路还包括：
分别与N个MOS晶体管栅极相连的N个栅极并联电阻；
一端与至少一个栅极并联电阻相连，另一端与并联控制信号相连的M个偏置电阻；其中，M为大于1且小于N的正整数。
其中，当M为2时，每个并联支路包括：
分别与N个MOS晶体管栅极相连的N个栅极并联电阻；
一端与前K个栅极并联电阻相连，另一端与并联控制信号相连的第一偏置电阻；其中，K为大于1且小于N的正整数；
一端与后N-K个栅极并联电阻相连，另一端与并联控制信号相连的第二偏置电阻。
其中，每个射频信号通路中的串联支路的一端与天线端口相连，另一端与射频信号端口相连；每个射频信号通路中的并联支路一端与射频信号端口相连，另一端与接地端相连。
其中，每个射频信号通路中的串联支路包括：
N个堆叠的MOS晶体管；
一端与N个MOS晶体管的栅极相连，另一端均与串联控制信号相连的N个栅极串联电阻。
其中，每个并联支路中的MOS晶体管为N型晶体管。
其中，每个串联支路中的MOS晶体管为N型晶体管。
其中，在每个射频信号通路中，在同一时刻仅保持并联控制信号和串联控制信号中的一者为高电平。
其中，当目标射频信号通路开启时，所述目标射频信号通路的串联控制信号为高电平，所述目标射频信号通路的并联控制信号为低电平；除所述目标射频信号通路之外的其他射频信号通路中，串联控制信号为低电平，并联控制信号为高电平。
通过以上方案可知，本发明实施例提供的一种射频开关电路，包括多个射频信号通路，每个射频信号通路包括串联支路和并联支路，每个并联支路包括N个堆叠的MOS晶体管；其中，N为大于1的正整数；每个并联支路还包括：分别与N个MOS晶体管栅极相连的N个栅极并联电阻；一端与至少一个栅极并联电阻相连，另一端与并联控制信号相连的M个偏置电阻；其中，M为大于1且小于N的正整数。可见，在本方案中，并联支路中的每个栅极并联电阻均与偏置电阻相连后再一同连接到控制信号端口，能够非常有效地改善大电压摆幅在各个堆叠的MOS晶体管上的不均匀分布，让每个管子都承受比较均匀的电压摆幅，从而防止堆叠晶体管 链顶端的管子率先被击穿，以及防止管子上大电压摆幅所导致的开关谐波的恶化，进一步提高了射频开关的功率处理能力和线性度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中射频开关结构电路图；
图2为现有技术中射频开关结构各晶体管承受的电压摆幅仿真曲线示意图；
图3为本发明实施例公开的射频开关实施例的电路图；
图4为本发明实施例公开的一射频开关结构各晶体管承受的电压摆幅仿真曲线示意图；
图5为本发明实施例公开的一射频开关结构与现有技术中射频开关结构各晶体管承受的最大电压幅度仿真对比曲线示意图；
图6为本发明实施例公开的一射频开关结构与现有技术中射频开关结构插入损耗vs输入功率的仿真对比曲线示意图；
图7为本发明实施例公开的一射频开关结构与现有技术中射频开关结构二次谐波vs输入功率的仿真对比曲线示意图；
图8为本发明实施例公开的一射频开关结构与现有技术中射频开关结构三次谐波vs输入功率的仿真对比曲线示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例公开了一种射频开关电路，以实现提高开关的功率处理能力和线性度，同时防止堆叠晶体管链顶端的MOS晶体管在大电压摆幅下首先被击穿，实现可靠性更高的射频开关。
本发明实施例提供的一种射频开关电路，包括多个射频信号通路，每个射频信号通路包括串联支路和并联支路，每个并联支路包括N个堆叠的MOS晶体管；其中，N为大于1的正整数；每个并联支路还包括：
分别与N个MOS晶体管栅极相连的N个栅极并联电阻；
一端与至少一个栅极并联电阻相连，另一端与并联控制信号相连的M个偏置电阻；其中，M为大于1且小于N的正整数。
其中，每个射频信号通路中的串联支路的一端与天线端口相连，另一端与射频信号端口相连；每个射频信号通路中的并联支路一端与射频信号端口相连，另一端与接地端相连。
其中，每个射频信号通路中的串联支路包括：
N个堆叠的MOS晶体管；
一端与N个MOS晶体管的栅极相连，另一端均与串联控制信号相连的N个栅极串联电阻。
具体的，参见图1，为本实施例提供的现有射频开关结构电路图，可以看出，射频开关电路中的射频信号通路由一个串联支路和一个并联支路组成；例如：串联支路1一端与RF1射频信号端口相连，另一端与天线端口ANT相连；并联支路1一端与RF1射频信号端口相连，另一端与地相连；其他射频通路(RF2,RF3,…,RFN)的连接与RF1通路相同。并且，根据不同应用不同功率容量的需求，串联支路和并联支路由一个或多个N型MOS晶体管堆叠组成，其中每个晶体管的栅极都分别与一个电阻Rg串联。
串联支路1中堆叠的N个N型MOS晶体管(M1，M2，…，MN)的栅极都分别与一个栅串联电阻Rg相连，所有串联支路1中的栅串联电阻 Rg的另外一端都与控制信号VGser1相连；并联支路1中堆叠的N个N型MOS晶体管(M01，M02，…，M0N)的栅极都分别与一个栅串联电阻Rg相连，所有并联支路1中的栅串联电阻Rg的另外一端都与控制信号VGsht1相连。其他射频通路(RF2，RF3，…，RFN)中的串联支路(串联支路2，3，…，N)的连接结构与RF1通路中的串联支路1相同，其他射频通路(RF2，RF3，…，RFN)中的并联支路(并联支路2，3，…，N)的连接结构与RF1通路中的并联支路1相同。
控制信号对(VGser1与VGsht1，VGser2与VGsht2，…，VGserN与VGshtN)在同一时刻保持其中之一为高电平(通常为2.0至2.5V)，另外一个为低电平(通常为-2.0至-2.5V)。当第一个射频信号通路RF1开启时，控制信号VGser1为高电平，RF1通路下的串联支路1进入ON(开)的状态，控制信号VGsht1为低电平，RF1通路下的并联支路1进入OFF(关)的状态；剩余其他通路(RF2，RF3，…，RFN)中的串联支路2、3、…、N的控制信号(VGser2，VGser3，…，VGserN)为低电平，串联支路2、3、…、N进入OFF(关)的状态，并联支路2、3、…、N的控制信号(VGsht2，VGsht3，…，VGshtN)为高电平，并联支路2、3、…、N进入ON(开)的状态。
在理想状态下，OFF支路每一个堆叠的晶体管能够平均分到相同的射频电压摆幅，这时射频开关能够处理的最大输入功率为：
Figure PCTCN2017117627-appb-000001
其中，设支路由N个晶体管堆叠组成，且单个晶体管的源漏击穿电压为Vbdds，负载阻抗为Zo。
然而，由于MOS晶体管存在多处寄生电容效应以及栅电阻Rg并不能完全阻断射频信号，总的射频电压摆幅将会不均匀地分布在各个MOS晶体管上。同时，这种电压摆幅不均匀分布的效应还跟管子尺寸有关，管子尺寸越小，电压摆幅不均匀分布的现象就越严重。对于射频开关，为了获得较低的插入损耗，通常串联支路的管子尺寸较大，串联支路的晶体管链的电压摆幅不平衡分布现象并不严重；然而并联支路中管子的尺寸通常较小，一般为串联支路中管子尺寸的5分之一至七分之一。
图2是采用现有技术中的一个单刀双掷(SPDT)开关在输入功率为36dBm时，处于OFF状态的并联支路堆叠的各个晶体管承受的电压摆幅仿真曲线。由图2可知，当并联支路处于OFF状态时，堆叠晶体管链的顶端管子承受最大的电压摆幅，底端管子承受最小的电压摆幅，分布在各个晶体管上的电压摆幅从堆叠晶体管链的顶端至底端依次减小。一方面，顶端晶体管将首先达到击穿电压，这时公式(1)将被替换成：
Figure PCTCN2017117627-appb-000002
明显P max2＜P max1，从而限制了射频开关能够处理的最大输入功率。另一方面，具有较大电压摆幅的MOS晶体管将贡献更大的高次谐波，从而降低了射频开关的总体线性度。传统的解决方法是再增加串联和并联支路堆叠晶体管的数量，其代价是产生更大的插入损耗和占用更大的芯片面积。
因此，在本实施例中，将并联支路分为多个部分，每个部分中的MOS晶体管的栅极均通过栅极并联电阻与一个偏置电阻相连，偏置电阻的另一端与并联控制信号相连，需要说明的是，若并联支路中包括M个偏置电阻，则相当于将所有MOS晶体管分为M个部分；这样通过偏置电阻再与并联控制信号相连，可有效地改善大电压摆幅在各个堆叠的MOS晶体管上的不均匀分布，让每个管子都承受比较均匀的电压摆幅，从而防止堆叠晶体管链顶端的管子被击穿以及降低管子上电压摆幅谐波的产生，使得开关的功率处理能力更接近于公式(1)。
需要说明的是，本方案适用于对称结构的单刀多掷天线开关芯片，也可以很容易扩展到频带选择开关、分集天线开关和非对称开关结构以及多刀多掷的开关芯片的应用中。
参见图3，在本实施例中，M为2，每个并联支路包括：
分别与N个MOS晶体管栅极相连的N个栅极并联电阻；
一端与前K个栅极并联电阻相连，另一端与并联控制信号相连的第一偏置电阻；其中，K为大于1且小于N的正整数；
一端与后N-K个栅极并联电阻相连，另一端与并联控制信号相连的第 二偏置电阻。
其中，每个并联支路中的MOS晶体管为N型晶体管；每个串联支路中的MOS晶体管为N型晶体管；在每个射频信号通路中，在同一时刻仅保持并联控制信号和串联控制信号中的一者为高电平；当目标射频信号通路开启时，所述目标射频信号通路的串联控制信号为高电平，所述目标射频信号通路的并联控制信号为低电平；除所述目标射频信号通路之外的其他射频信号通路中，串联控制信号为低电平，并联控制信号为高电平。
具体的，在本实施例中的M＝2，即偏置电阻的数量为两个，分别为第一偏执电阻和第二偏执电阻；由于本方案中有两个偏执电阻，相当于将并联支路中的N个MOS晶体管分为两部分；一部分是前K(1<K<N)个堆叠的晶体管，另一部分是后面N-K个堆叠的晶体管，需要说明的是，由于本方案中的MOS晶体管均采用堆叠晶体管技术，因此在本实施例中对MOS晶体管按照从前至后进行描述，从前至后可以理解为：并联支路与射频信号端口相连的一端为前，也可以理解为：并联支路与接地端相连的一端为前，在此并不具体限定，只要能将N个MOS晶体管分为两部分即可。
具体的，如图3所示，本发明提供的射频开关含有N个射频信号通路(RF1，RF2，RF3，…，RFN)，每一条通路由一个串联支路和一个并联支路组成。串联支路1一端与RF1射频信号端口相连，另一端与天线端口ANT相连；并联支路1一端与RF1射频信号端口相连，另一端与地相连。其他射频通路(RF2，RF3，…，RFN)的连接与RF1通路相同。根据不同应用不同功率容量的需求，串联支路和并联支路由一个或多个N型MOS晶体管堆叠组成，其中每个晶体管的栅极都分别与一个电阻Rg串联。
串联支路1中堆叠的N个N型MOS晶体管(M1，M2，…，MN)的栅极都分别与一个栅串联电阻Rg相连，串联支路1中的所有栅串联电阻Rg的另外一端都与控制信号VGser1相连；并联支路1中堆叠的N个N型MOS晶体管(M01，M02，…，M0N)的栅极都分别与一个栅串联电阻Rg相连，然后并联支路1中前K(1<K<N)个堆叠的晶体管(M01， M02，…，M0K)所连接的栅串联电阻Rg的另外一端都与一个偏置电阻Rbias1相连，而并联支路1中后面N-K个堆叠的晶体管(M0(K+1)，M0(K+2)，…，M0N)所连接的栅串联电阻Rg的另外一端都与一个偏置电阻Rbias2相连，偏置电阻Rbias1和Rbias2的另外一端都与控制信号VGsht1相连。其他射频通路(RF2，RF3，…，RFN)中的串联支路(串联支路2，3，…，N)的连接结构与RF1通路中的串联支路1相同，其他射频通路(RF2，RF3，…，RFN)中的并联支路(并联支路2，3，…，N)的连接结构与RF1通路中的并联支路1相同。
需要说明的是，本实施例中的VGser1与VGsht1，VGser2与VGsht2，…，VGserN与VGshtN为一个控制信号对，在同一时刻保持其中之一为高电平(通常为2.0至2.5V)，另外一个为低电平(通常为-2.0至-2.5V)。当RF1通路开启时，控制信号VGser1为高电平，RF1通路下的串联支路1进入ON(开)的状态，控制信号VGsht1为低电平，RF1通路下的并联支路1进入OFF(关)的状态；剩余其他通路(RF2，RF3，…，RFN)中的串联支路2、3、…、N的控制信号(VGser2，VGser3，…，VGserN)为低电平，串联支路2、3、…、N进入OFF(关)的状态，并联支路2、3、…、N的控制信号(VGsht2，VGsht3，…，VGshtN)为高电平，并联支路2、3、…、N进入ON(开)的状态。
需要说明的是，本方案所提及的所有控制信号对的值，所有电阻的元件值，以及所有N类MOS晶体管的尺寸值，需要根据射频开关的具体情况来设计，这对于本领域技术人员来讲是易于理解的。
图4是采用本发明的一个单刀双掷(SPDT)开关实施例在输入功率为36dBm时，处于OFF状态的并联支路堆叠的各个晶体管承受的电压摆幅仿真曲线；图5是采用本发明与现有技术的一个单刀双掷(SPDT)开关实施例在输入功率为36dBm时，处于OFF状态的并联支路堆叠的各个晶体管承受的最大电压幅度仿真对比曲线。仿真与实验结果表明，现有的典型开关电路结构会使射频电压摆幅自上而下、不均匀地分布在各个堆叠的MOS晶体管上，而采用本发明的开关射频电压摆幅相对均匀地分布在各个堆叠的MOS晶体管上，从而提高了开关的鲁棒性。
图6是采用本发明与现有技术的一个单刀双掷(SPDT)开关实施例插入损耗vs输入功率的仿真对比曲线。结果表明，采用本发明内容的开关电路的0.1dB功率压缩点要高于采用现有技术的开关，本发明起到了提供开关功率处理能力的作用。图7和图8分别是采用本发明与现有技术的一个单刀双掷(SPDT)开关实施例二次谐波vs输入功率和三次谐波vs输入功率的仿真对比曲线。结果表明，在大信号功率条件下，采用本发明内容的开关电路的二次和三次谐波明显好于采用现有技术的开关。仿真和实验结果表明，利用本发明所提出的射频开关结构能够有效改善堆叠管子链电压摆幅不均匀分配的问题，从而提高开关的功率处理能力和线性度。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (8)

  1. 一种射频开关电路，包括多个射频信号通路，每个射频信号通路包括串联支路和并联支路，每个并联支路包括N个堆叠的MOS晶体管；其中，N为大于1的正整数；其特征在于，每个并联支路还包括：
    分别与N个MOS晶体管栅极相连的N个栅极并联电阻；
    一端与至少一个栅极并联电阻相连，另一端与并联控制信号相连的M个偏置电阻；其中，M为大于1且小于N的正整数。
  2. 根据权利要求1所述的射频开关电路，其特征在于，当M为2时，每个并联支路包括：
    分别与N个MOS晶体管栅极相连的N个栅极并联电阻；
    一端与前K个栅极并联电阻相连，另一端与并联控制信号相连的第一偏置电阻；其中，K为大于1且小于N的正整数；
    一端与后N-K个栅极并联电阻相连，另一端与并联控制信号相连的第二偏置电阻。
  3. 根据权利要求2所述的射频开关电路，其特征在于，每个射频信号通路中的串联支路的一端与天线端口相连，另一端与射频信号端口相连；每个射频信号通路中的并联支路一端与射频信号端口相连，另一端与接地端相连。
  4. 根据权利要求3所述的射频开关电路，其特征在于，每个射频信号通路中的串联支路包括：
    N个堆叠的MOS晶体管；
    一端与N个MOS晶体管的栅极相连，另一端均与串联控制信号相连的N个栅极串联电阻。
  5. 根据权利要求4所述的射频开关电路，其特征在于，每个并联支路中的MOS晶体管为N型晶体管。
  6. 根据权利要求5所述的射频开关电路，其特征在于，每个串联支路中的MOS晶体管为N型晶体管。
  7. 根据权利要求6所述的射频开关电路，其特征在于，在每个射频信号通路中，在同一时刻仅保持并联控制信号和串联控制信号中的一者为 高电平。
  8. 根据权利要求7所述的射频开关电路，其特征在于，
    当目标射频信号通路开启时，所述目标射频信号通路的串联控制信号为高电平，所述目标射频信号通路的并联控制信号为低电平；除所述目标射频信号通路之外的其他射频信号通路中，串联控制信号为低电平，并联控制信号为高电平。
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CN108039585A (zh) * 2017-12-19 2018-05-15 无锡中普微电子有限公司 一种天线调谐电路
CN110611499B (zh) * 2018-06-15 2024-01-12 锐迪科微电子（上海）有限公司 一种基于D-pHEMT器件的射频开关的ESD保护电路
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CN113824466B (zh) * 2021-08-30 2022-11-18 电子科技大学 一种采用钳位电阻的超宽带射频收发开关
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