WO2018184293A1 - 阵列基板及该阵列基板的制作方法 - Google Patents

阵列基板及该阵列基板的制作方法 Download PDF

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Publication number
WO2018184293A1
WO2018184293A1 PCT/CN2017/088379 CN2017088379W WO2018184293A1 WO 2018184293 A1 WO2018184293 A1 WO 2018184293A1 CN 2017088379 W CN2017088379 W CN 2017088379W WO 2018184293 A1 WO2018184293 A1 WO 2018184293A1
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WIPO (PCT)
Prior art keywords
substrate
layer
pixel electrode
disposed
gate insulating
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PCT/CN2017/088379
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English (en)
French (fr)
Inventor
陈兴武
陈黎暄
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深圳市华星光电技术有限公司
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Priority to US15/547,580 priority Critical patent/US10416506B2/en
Publication of WO2018184293A1 publication Critical patent/WO2018184293A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate and a method for fabricating the array substrate.
  • liquid crystal display technology has become the most widely used display technology.
  • people are increasingly demanding display technologies, such as higher viewing angles, high penetration rates, and high reliability.
  • TN Transmission Nematic
  • VA Vertical Alignment
  • IPS In-plane switching
  • FFS Ringe Field Switching
  • the FFS mode has attracted attention due to its wide viewing angle, high transmittance, and hard-screen technology.
  • the FFS mode still has some shortcomings, the most important of which is the IS (image sticking) phenomenon, that is, the phenomenon that the previous picture is still visible when switching to the next picture after displaying the same picture for a long time.
  • Vcom common voltage
  • an object of the present invention to provide an array substrate capable of rapidly releasing aggregated ions and reducing parasitic capacitance, and a method of fabricating the same.
  • an array substrate comprising: a substrate; a thin film transistor disposed on the substrate; and a pixel electrode disposed on the substrate and in contact with a drain of the thin film transistor a common electrode disposed above the pixel electrode and electrically insulated from the pixel electrode, wherein the common electrode has a plurality of first via holes therein.
  • the array substrate further includes a passivation layer, and the passivation layer is disposed on the thin film transistor Above the pixel electrode, the passivation layer under the pixel electrode has a plurality of protrusions, and the pixel electrode has a plurality of second via holes therein, the protrusions passing through corresponding The second through hole.
  • the common electrode is disposed on the protrusion, and the first through hole corresponds to between two adjacent protrusions.
  • the thin film transistor includes: a gate disposed on the substrate; a gate insulating layer disposed on the substrate and the gate; and an active layer disposed on the gate insulating layer a first N-type conductive layer and a second N-type conductive layer, spaced apart from each other on the active layer; a source and a drain, respectively disposed on the first N-type conductive layer and the second N-type conductive layer Upper, the source and the drain are in contact with the active layer, and the source and the drain respectively extend onto the gate insulating layer; wherein the pixel electrode is located in the On the gate insulating layer on the substrate, a passivation layer on the substrate is between the pixel electrode and the gate insulating layer on the substrate.
  • the array substrate further includes a passivation layer disposed on the thin film transistor and the pixel electrode, and the passivation layer above the pixel electrode has a plurality of bumps
  • the common electrode is disposed above the protrusion, and the first through hole corresponds to between two adjacent protrusions.
  • the thin film transistor includes: a gate disposed on the substrate; a gate insulating layer disposed on the substrate and the gate; and an active layer disposed on the gate insulating layer a first N-type conductive layer and a second N-type conductive layer, spaced apart from each other on the active layer; a source and a drain, respectively disposed on the first N-type conductive layer and the second N-type conductive layer Upper, the source and the drain are in contact with the active layer, and the source and the drain respectively extend onto the gate insulating layer; wherein a pixel electrode on the substrate Located on the gate insulating layer on the substrate.
  • a method for fabricating an array substrate including: providing a substrate; forming a thin film transistor on the substrate; forming a first on the thin film transistor and the substrate a passivation layer; forming a via hole exposing a drain of the thin film transistor in the first passivation layer; forming a first passivation layer on the substrate to form a plurality of first via holes a pixel electrode, wherein the pixel electrode is in contact with a drain of the thin film transistor through the via hole; forming a second passivation layer on the first passivation layer and the pixel electrode, the second passivation a layer filling the first via hole; forming a common electrode having a plurality of second via holes on the second passivation layer on the pixel electrode, the first via hole and the second via hole being staggered And removing a second passivation layer over the thin film transistor and a second passivation layer exposed by the second via hole.
  • the method for forming a thin film transistor on the substrate comprises: forming a gate on the substrate; forming the gate insulating layer on the substrate and the gate; wherein a first passivation layer on the substrate is disposed on the gate insulating layer on the substrate; an active layer is formed on the gate insulating layer on the gate; and a mutual formation is formed on the active layer a first N-type conductive layer and a second N-type conductive layer; a source and a drain are formed on the first N-type conductive layer and the second N-type conductive layer, respectively, the source and the The drain is in contact with the active layer, and the source and the drain respectively extend onto the gate insulating layer.
  • a method for fabricating an array substrate includes: providing a substrate; forming a thin film transistor on the substrate; forming a pixel electrode on the substrate, the pixel electrode Forming a passivation layer on the thin film transistor and the pixel electrode; forming a common electrode having a plurality of via holes on the passivation layer on the pixel electrode; A portion of the passivation layer over the thin film transistor and a portion of the passivation layer exposed by the second via are etched away.
  • the method for forming a thin film transistor on the substrate comprises: forming a gate on the substrate; forming the gate insulating layer on the substrate and the gate; wherein a pixel electrode on the substrate is located on the gate insulating layer on the substrate; an active layer is formed on the gate insulating layer on the gate; and a space is formed on the active layer
  • An N-type conductive layer and a second N-type conductive layer forming a source and a drain on the first N-type conductive layer and the second N-type conductive layer, the source and the drain Contacting the active layer, and the source and the drain respectively extend onto the gate insulating layer.
  • the array substrate of the present invention and the method of fabricating the same can reduce the parasitic capacitance between the common electrode and the pixel electrode, and can accelerate the release of the aggregated ions.
  • the present invention effectively enhances the lateral electric field by forming a three-dimensional electrode structure, thereby reducing the driving voltage, improving the display transmittance, and reducing the energy consumption.
  • FIG. 1 is a schematic structural view of an array substrate according to a first embodiment of the present invention
  • FIGS. 2A to 2L are process diagrams of an array substrate according to a first embodiment of the present invention.
  • FIG. 3 is a schematic structural view of an array substrate according to a second embodiment of the present invention.
  • FIGS. 4A through 4J are process diagrams of an array substrate in accordance with a second embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an array substrate according to a first embodiment of the present invention.
  • an array substrate includes a substrate 110, a thin film transistor 120, a pixel electrode 130, and a common electrode 140.
  • the substrate 110 may be, for example, a transparent glass substrate and a resin substrate.
  • the thin film transistor 120 is formed over the substrate 110.
  • the pixel electrode 130 is formed over the substrate 110. Further, the pixel electrode 130 is formed on a region of the substrate 110 other than the region occupied by the thin film transistor 120, and the pixel electrode 130 is in contact with the drain of the thin film transistor 120.
  • the common electrode 140 is disposed above the pixel electrode 130, and the common electrode 140 and the pixel electrode 130 are electrically insulated from each other, and the common electrode 140 has a plurality of first through holes 141 therein.
  • the overlapping area between the common electrode 140 and the pixel electrode 130 is reduced, thereby reducing the parasitic capacitance between the common electrode 140 and the pixel electrode 130.
  • the pixel electrode 130 has a plurality of second through holes 131 therein, wherein the first pass The hole 141 and the second through hole 131 are alternately disposed, that is, between each of the first through holes 141 and the corresponding adjacent two second through holes 131. In this way, the overlapping area between the common electrode 140 and the pixel electrode 130 can be further reduced, thereby further reducing the parasitic capacitance between the common electrode 140 and the pixel electrode 130.
  • the array substrate according to the first embodiment of the present invention further includes: a passivation layer 150 disposed on the thin film transistor Above the pixel 120 and under the pixel electrode 130, and the passivation layer 150 under the pixel electrode 130 has a plurality of protrusions 150a, each of which passes through the corresponding second through hole 131, thereby making the protrusion 150a
  • the top surface is higher than the top surface of the pixel electrode 130, and the common electrode 140 is disposed on the bump 150a.
  • the thin film transistor 120 includes a gate electrode 121 disposed on the substrate 110, a gate insulating layer 122 disposed on the substrate 110 and the gate electrode 121, and an active layer 123 disposed on the gate electrode 121.
  • the first N-type conductive layer 124a and the second N-type conductive layer 124b are spaced apart from each other on the active layer 123; the source electrode 125a and the drain electrode 125b are respectively disposed on the first N-type conductive layer 124a and the second N
  • the source 125a and the drain 125b are both in contact with the active layer 123, and the source 125a and the drain 125b respectively extend onto the gate insulating layer 122; wherein the pixel electrode 130 is located on the substrate 110
  • the gate insulating layer 122 is on the passivation layer 150 between the pixel electrode 130 and the gate insulating layer 122 on the substrate 110. Further, the pixel electrode 130 is in contact with the drain electrode 125b through the via
  • the active layer 123 is made of amorphous silicon (a-Si), but the present invention is not limited thereto.
  • the first N-type conductive layer 124a and the second N-type conductive layer 124b are each made of N-type doped silicon (n+Si), but the invention is not limited thereto.
  • the passivation layer 150 is made of a material having a low dielectric constant, for example, the passivation layer 150 may be composed of an acrylic resin, an epoxy resin, a polyfunctional polymerizable monomer, a photoinitiator, a tackifier, and a polyvinyl alcohol.
  • the mixture is prepared by dissolving and dissolving in a solvent, and the solvent may be propylene glycol methyl ether acetate (PGMEA), ethoxy diethylene glycol (EDG) or the like.
  • PMEA propylene glycol methyl ether acetate
  • EDG ethoxy diethylene glycol
  • the passivation layer 150 by forming the passivation layer 150 using a material having a low dielectric constant, the parasitic capacitance between the common electrode 140 and the pixel electrode 130 can be further reduced, and the release of aggregated ions can be accelerated, thereby reducing ion accumulation. DC residual.
  • FIGS. 2A through 2L are process diagrams of an array substrate in accordance with a first embodiment of the present invention.
  • a substrate 110 is provided.
  • the substrate 110 can be, for example, a transparent glass substrate and a resin substrate.
  • Step 2 Referring to FIG. 2B, a gate electrode 121 is formed on the substrate 110.
  • the gate electrode 121 may be made of a conductive metal.
  • Step 3 Referring to FIG. 2C, a gate insulating layer 122 is formed on the substrate 110 and the gate electrode 121.
  • the gate insulating layer 122 may be made of an insulating material such as SiO X or SiN X .
  • Step 4 Referring to FIG. 2D, an active layer 123 is formed on the gate insulating layer 122, wherein the active layer 123 is opposite to the gate electrode 121.
  • the active layer 123 is made of amorphous silicon (a-Si), but the present invention is not limited thereto.
  • Step 5 Referring to FIG. 2E, a first N-type conductive layer 124a and a second N-type conductive layer 124b spaced apart from each other are formed on the active layer 123.
  • the first N-type conductive layer 124a and the second N-type conductive layer 124b are each made of N-type doped silicon (n+Si), but the invention is not limited thereto.
  • Step 6 Referring to FIG. 2F, a source electrode 125a and a drain electrode 125b are formed on the first N-type conductive layer 124a and the second N-type conductive layer 124b, respectively, and the source electrode 125a and the drain electrode 125b are in contact with the active layer 123. And the source electrode 125a and the drain electrode 125b extend to the gate insulating layer 122, respectively.
  • the fabrication of the thin film transistor 120 is completed by performing the steps 2 to 6.
  • Step 7 Referring to FIG. 2G, a first passivation layer 151 is formed on the thin film transistor 120 and the gate insulating layer 122 on the substrate 110.
  • the first passivation layer 151 may be made of a material having a low dielectric constant.
  • Step 8 Referring to FIG. 2H, a via hole 151a exposing the drain electrode 125b is formed in the first passivation layer 151.
  • Step 9 Referring to FIG. 2I, a pixel electrode 130 having a plurality of second via holes 131 is formed on the first passivation layer 151 on the substrate 110, wherein the pixel electrode 130 fills the via hole 151a to be in contact with the drain electrode 125b. .
  • Step 10 Referring to FIG. 2J, forming a second blunt on the first passivation layer 151 and the pixel electrode 130
  • the second passivation layer 152 fills the second via hole 131.
  • the first passivation layer 151 and the second passivation layer 152 will constitute the structure of the passivation layer 150 in FIG. 1, and please refer to the following description.
  • Step 11 Referring to FIG. 2K, a common electrode 140 having a plurality of second via holes 141, the first via holes 131 and the second via holes 141 are formed on the second passivation layer 152 on the pixel electrode 130. Interlaced settings.
  • Step 12 Referring to FIG. 2L, the second passivation layer 152 on the thin film transistor 120 and the second passivation layer 152 exposed by the second via hole 141 are etched away. Thus, the first passivation layer 151 and the remaining second passivation layer 152 form the structure of the passivation layer 150 shown in FIG. 1.
  • the pixel electrode 130 and the common electrode 140 are simultaneously exposed, and the accumulated ions are quickly released.
  • a stereoscopic electrode structure ie, the pixel electrode 130 and the common electrode 140 formed up and down
  • the lateral electric field is effectively enhanced, thereby reducing the driving voltage, increasing the display transmittance, and reducing the energy consumption.
  • FIG 3 is a schematic structural view of an array substrate according to a second embodiment of the present invention.
  • an array substrate includes a substrate 210, a thin film transistor 220, a pixel electrode 230, and a common electrode 240.
  • the substrate 210 may be, for example, a transparent glass substrate and a resin substrate.
  • the thin film transistor 220 is formed over the substrate 210.
  • the pixel electrode 230 is formed on the substrate 110. Further, the pixel electrode 230 is formed on a region of the substrate 210 other than the region occupied by the thin film transistor 220, and the pixel electrode 230 is in contact with the drain of the thin film transistor 220.
  • the common electrode 240 is disposed above the pixel electrode 230, and the common electrode 240 and the pixel electrode 230 are electrically insulated from each other, and the common electrode 240 has a plurality of third through holes 241 therein.
  • the overlapping area between the common electrode 240 and the pixel electrode 230 is reduced, thereby reducing the parasitic capacitance between the common electrode 240 and the pixel electrode 230.
  • the array substrate according to the second embodiment of the present invention further includes: a passivation layer 250 disposed on the thin film transistor 220 and the pixel electrode 230, and the passivation layer 250 on the pixel electrode 130 has a plurality of protrusions 251, the common electrode 240 is disposed on the protrusion 251, and the third through hole 241 is interlaced with the protrusion 251, that is, The third through hole 241 is opposite to the corresponding adjacent two protrusions 251.
  • the thin film transistor 220 includes a gate electrode 221 disposed on the substrate 210, a gate insulating layer 222 disposed on the substrate 210 and the gate electrode 221, and an active layer 223 disposed on the gate electrode 221.
  • the first N-type conductive layer 224a and the second N-type conductive layer 224b are spaced apart from each other on the active layer 223; the source 225a and the drain 225b are respectively disposed on the first N-type conductive layer 224a and the second N
  • the source 225a and the drain 225b are both in contact with the active layer 223, and the source 225a and the drain 225b respectively extend onto the gate insulating layer 222; wherein the pixel electrode 230 is located on the substrate 210 On the gate insulating layer 222.
  • the active layer 223 is made of amorphous silicon (a-Si), but the present invention is not limited thereto.
  • the first N-type conductive layer 224a and the second N-type conductive layer 224b are each made of N-type doped silicon (n+Si), but the invention is not limited thereto.
  • the passivation layer 250 is made of a material having a low dielectric constant, for example, the passivation layer 250 may be composed of an acrylic resin, an epoxy resin, a polyfunctional polymerizable monomer, a photoinitiator, a tackifier, and a polyvinyl alcohol.
  • the mixture is prepared by dissolving and dissolving in a solvent, and the solvent may be propylene glycol methyl ether acetate (PGMEA), ethoxy diethylene glycol (EDG) or the like.
  • PMEA propylene glycol methyl ether acetate
  • EDG ethoxy diethylene glycol
  • the passivation layer 250 using a material having a low dielectric constant, the parasitic capacitance between the common electrode 240 and the pixel electrode 230 can be further reduced, and the release of aggregated ions can be accelerated, thereby reducing ion accumulation. DC residual.
  • FIGS. 4A through 4J are process diagrams of an array substrate in accordance with a second embodiment of the present invention.
  • a substrate 210 is provided.
  • the substrate 210 can be, for example, a transparent glass substrate and a resin substrate.
  • Step 2 Referring to FIG. 4B, a gate electrode 221 is formed on the substrate 210.
  • the gate 221 can be electrically conductive Made of metal.
  • Step 3 Referring to FIG. 4C, a gate insulating layer 222 is formed on the substrate 210 and the gate electrode 221.
  • the gate insulating layer 222 may be made of an insulating material such as SiO X or SiN X .
  • Step 4 Referring to FIG. 4D, an active layer 223 is formed on the gate insulating layer 222, wherein the active layer 223 is opposite to the gate electrode 221.
  • the active layer 223 is made of amorphous silicon (a-Si), but the present invention is not limited thereto.
  • Step 5 Referring to FIG. 4E, a first N-type conductive layer 224a and a second N-type conductive layer 224b spaced apart from each other are formed on the active layer 223.
  • the first N-type conductive layer 224a and the second N-type conductive layer 224b are each made of N-type doped silicon (n+Si), but the invention is not limited thereto.
  • Step 6 Referring to FIG. 4F, a source 225a and a drain 225b are formed on the first N-type conductive layer 224a and the second N-type conductive layer 224b, respectively, and the source 225a and the drain 225b are both in contact with the active layer 223. And the source 225a and the drain 225b extend to the gate insulating layer 222, respectively.
  • the fabrication of the thin film transistor 220 is completed by performing the steps 2 to 6.
  • Step 7 Referring to FIG. 4G, a pixel electrode 230 is formed on the gate insulating layer 222 on the substrate 210.
  • Step 8 Referring to FIG. 4H, a passivation layer 250 is formed on the thin film transistor 220 and the pixel electrode 230.
  • the passivation layer 250 may be made of a material having a low dielectric constant.
  • Step 9 Referring to FIG. 4I, a common electrode 240 having a plurality of third via holes 241 is formed on the passivation layer 250 on the pixel electrode 230.
  • Step 10 Referring to FIG. 4J, a portion of the passivation layer 250 on the thin film transistor 220 and a portion of the passivation layer 250 exposed by the third via hole 241 are etched away.
  • the three-dimensional electrode structure ie, the pixel electrode 230 and the common electrode 240 formed above and below
  • the passivation layer 250 can be formed by etching the passivation layer 250, thereby effectively enhancing the lateral electric field. Therefore, the driving voltage can be lowered, the display transmittance can be improved, and the power consumption can be reduced.

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Abstract

一种阵列基板，包括：基板（110）；薄膜晶体管（120），设置于基板（110）之上；像素电极（130），设置于基板（110）之上且与薄膜晶体管（120）的漏极接触；公共电极（140），设置于像素电极（130）之上且与像素电极（130）电绝缘，公共电极（140）中具有多个第一通孔（141）。还提供一种阵列基板的制作方法。阵列基板及其制作方法，能够降低公共电极（140）和像素电极（130）之间的寄生电容，并且能够加速聚集离子的释放。通过形成立体电极结构，增强横向电场，从而可以降低驱动电压，提高显示穿透率，降低能耗。

Description

阵列基板及该阵列基板的制作方法 技术领域
本发明属于显示技术领域，具体地讲，涉及一种阵列基板及该阵列基板的制作方法。
背景技术
随着显示技术的快速发展，液晶显示技术已经成为了目前应用最广泛的显示技术。此外，人们对显示技术的要求越来越高，例如对大视角、高穿透率和高信赖性等提出了更高的要求。
目前，常用的液晶显示器有TN(TwistNematic，扭转向列型)模式、VA(VerticalAlignment，垂直对齐)模式，IPS(In-plane switching，平面方向转换)模式和FFS(Fringe Field Switching，边缘场开关)模式等。其中，FFS模式因具有广视角、高穿透率且为硬屏技术而备受关注。然而，FFS模式仍然有一些不足，其中最重要的是IS(image sticking，影像残留)现象，即长时间显示同一画面后切换到下一画面时依旧可见前一画面残影的现象。
IS现象产生的根源有很多，其中最主要的原因是由于长时间驱动导致的离子聚集无法及时释放和寄生电容过大而导致公共电压(Vcom)的对称性变差。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种能够使聚集的离子快速的释放且降低寄生电容的阵列基板及其制作方法。
根据本发明的一方面，提供了一种阵列基板，其包括：基板；薄膜晶体管，设置于所述基板之上；像素电极，设置于所述基板之上且与所述薄膜晶体管的漏极接触；公共电极，设置于所述像素电极之上且与所述像素电极电绝缘，所述公共电极中具有多个第一通孔。
可选地，所述阵列基板还包括钝化层，所述钝化层设置于所述薄膜晶体管 之上和所述像素电极之下，在所述像素电极之下的所述钝化层具有多个凸起，所述像素电极中具有多个第二通孔，所述凸起穿过对应的所述第二通孔。
可选地，所述公共电极设置于所述凸起之上，所述第一通孔对应于相邻的两个凸起之间。
可选地，所述薄膜晶体管包括：栅极，设置在所述基板上；栅极绝缘层，设置在所述基板和所述栅极上；有源层，设置在所述栅极绝缘层上；第一N型导电层和第二N型导电层，彼此间隔设置在所述有源层上；源极和漏极，分别设置在第一N型导电层和所述第二N型导电层上，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延伸至所述栅极绝缘层上；其中，所述像素电极位于在所述基板上的所述栅极绝缘层上，在所述基板上的钝化层位于所述像素电极和在所述基板上的所述栅极绝缘层之间。
可选地，所述阵列基板还包括钝化层，所述钝化层设置于所述薄膜晶体管和所述像素电极之上，在所述像素电极之上的所述钝化层具有多个凸起，所述公共电极设置于所述凸起之上，所述第一通孔对应于相邻的两个凸起之间。
可选地，所述薄膜晶体管包括：栅极，设置在所述基板上；栅极绝缘层，设置在所述基板和所述栅极上；有源层，设置在所述栅极绝缘层上；第一N型导电层和第二N型导电层，彼此间隔设置在所述有源层上；源极和漏极，分别设置在第一N型导电层和所述第二N型导电层上，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延伸至所述栅极绝缘层上；其中，在所述基板上的像素电极位于在所述基板上的所述栅极绝缘层上。
根据本发明的另一方面，还提供了一种阵列基板的制作方法，其包括：提供一基板；在所述基板上制作形成薄膜晶体管；在所述薄膜晶体管和所述基板上制作形成第一钝化层；在所述第一钝化层中制作形成将所述薄膜晶体管的漏极暴露的过孔；在所述基板上的第一钝化层上制作形成具有多个第一通孔的像素电极，所述像素电极通过所述过孔与所述薄膜晶体管的漏极接触；在所述第一钝化层和所述像素电极上制作形成第二钝化层，所述第二钝化层填充所述第一通孔；在所述像素电极上的第二钝化层上制作形成具有多个第二通孔的公共电极，所述第一通孔和所述第二通孔交错设置；将所述薄膜晶体管之上的第二钝化层和由所述第二通孔暴露出的第二钝化层刻蚀去除。
可选地，在所述基板上制作形成薄膜晶体管的方法包括：在所述基板上制作形成栅极；在所述基板和所述栅极上制作形成所述栅极绝缘层；其中，在所述基板上的第一钝化层位于在所述基板上的栅极绝缘层上；在所述栅极上的栅极绝缘层上制作形成有源层；在所述有源层上制作形成彼此间隔的第一N型导电层和第二N型导电层；在所述第一N型导电层和所述第二N型导电层上分别制作形成源极和漏极，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延伸至所述栅极绝缘层上。
根据本发明的又一方面，又提供了一种阵列基板的制作方法，其包括：提供一基板；在所述基板上制作形成薄膜晶体管；在所述基板上制作形成像素电极，所述像素电极与所述薄膜晶体管的漏极接触；在所述薄膜晶体管和所述像素电极上制作形成钝化层；在所述像素电极上的钝化层上制作形成具有多个通孔的公共电极；将所述薄膜晶体管之上的钝化层的部分和由所述第二通孔暴露出的钝化层的部分刻蚀去除。
可选地，在所述基板上制作形成薄膜晶体管的方法包括：在所述基板上制作形成栅极；在所述基板和所述栅极上制作形成所述栅极绝缘层；其中，在所述基板上的像素电极位于在所述基板上的栅极绝缘层上；在所述栅极上的栅极绝缘层上制作形成有源层；在所述有源层上制作形成彼此间隔的第一N型导电层和第二N型导电层；在所述第一N型导电层和所述第二N型导电层上分别制作形成源极和漏极，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延伸至所述栅极绝缘层上。
本发明的有益效果：本发明的阵列基板及其制作方法，能够降低公共电极和像素电极之间的寄生电容，并且能够加速聚集离子的释放。此外，本发明通过形成立体电极结构，有效增强横向电场，从而可以降低驱动电压，提高显示穿透率，降低能耗。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的第一实施例的阵列基板的结构示意图；
图2A至图2L是根据本发明的第一实施例的阵列基板的制程图；
图3是根据本发明的第二实施例的阵列基板的结构示意图；
图4A至图4J是根据本发明的第二实施例的阵列基板的制程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在附图中始终表示相同的元件。
也将理解的是，在一元件被称为设置于另一元件“之上”或“上”时，它可以直接设置于该另一元件上，或者也可以存在中间元件。
图1是根据本发明的第一实施例的阵列基板的结构示意图。
参照图1，根据本发明的第一实施例的阵列基板包括：基板110、薄膜晶体管120、像素电极130和公共电极140。
基板110可例如是透明的玻璃基板和树脂基板。薄膜晶体管120形成在基板110之上。像素电极130形成在基板110之上，进一步地，像素电极130形成在基板110上的除薄膜晶体管120所占区域之外的区域，并且像素电极130与薄膜晶体管120的漏极连接接触。公共电极140设置于像素电极130之上，并且公共电极140与像素电极130彼此电绝缘，公共电极140中具有多个第一通孔141。
这样，通过在公共电极140中形成第一通孔141，减小公共电极140与像素电极130之间的重叠面积，从而降低公共电极140与像素电极130之间的寄生电容。
此外，进一步地，像素电极130中具有多个第二通孔131，其中，第一通 孔141和第二通孔131交错设置，即每个第一通孔141相对于对应的相邻两个第二通孔131之间。这样，可以进一步减小公共电极140与像素电极130之间的重叠面积，进而进一步降低公共电极140与像素电极130之间的寄生电容。
在本实施例中，为了实现公共电极140和像素电极130的上述结构，进一步地，根据本发明的第一实施例的阵列基板还包括：钝化层150，该钝化层150设置于薄膜晶体管120之上和像素电极130之下，并且在像素电极130之下的钝化层150具有多个凸起150a，每个凸起150a穿过对应的第二通孔131，从而使凸起150a的顶表面高于像素电极130的顶表面，公共电极140设置于凸起150a上。
另外，薄膜晶体管120包括：栅极121，设置在基板110上；栅极绝缘层122，设置在基板110和栅极121上；有源层123，设置在栅极121上的栅极绝缘层122上；第一N型导电层124a和第二N型导电层124b，彼此间隔设置在有源层123上；源极125a和漏极125b，分别设置在第一N型导电层124a和第二N型导电层124b上，源极125a和漏极125b均与有源层123接触，并且源极125a和漏极125b分别延伸至栅极绝缘层122上；其中，像素电极130位于在基板110上的栅极绝缘层122上，并且钝化层150位于像素电极130和在基板110上的栅极绝缘层122之间。进一步地，像素电极130通过钝化层150中的过孔151a与漏极125b连接接触。
以上，描述了薄膜晶体管120的一种结构示例，但本发明并不限制于此。此外，有源层123由非晶硅(a-Si)制成，但本发明并不限制于此。第一N型导电层124a和第二N型导电层124b均由N型掺杂的硅(n+Si)制成，但本发明并不限制于此。
进一步地，钝化层150由低介电常数的材料制成，例如钝化层150可以由丙烯酸树脂、环氧树脂、多官能团可聚合单体、光引发剂、增粘剂和聚乙烯醇等混合溶解到溶剂中制成，所述溶剂可以为丙二醇甲醚醋酸酯(PGMEA)、乙氧基二乙二醇(EDG)等。这里，通过利用低介电常数的材料制成钝化层150，能够更进一步地降低公共电极140与像素电极130之间的寄生电容，并且可以加速聚集的离子的释放，从而降低离子聚集导致的直流残留。
图2A至图2L是根据本发明的第一实施例的阵列基板的制程图。
根据本发明的第一实施例的阵列基板的制作方法包括：
步骤一：参照图2A，提供一基板110。该基板110可例如是透明的玻璃基板和树脂基板。
步骤二：参照图2B，在基板110上制作形成栅极121。栅极121可由导电金属制成。
步骤三：参照图2C，在基板110和栅极121上制作形成栅极绝缘层122。栅极绝缘层122可由绝缘材料(诸如SiOX或SiNX)制成。
步骤四：参照图2D，在栅极绝缘层122上制作形成有源层123，其中，有源层123与栅极121相对。有源层123由非晶硅(a-Si)制成，但本发明并不限制于此。
步骤五：参照图2E，在有源层123上制作形成彼此间隔的第一N型导电层124a和第二N型导电层124b。第一N型导电层124a和第二N型导电层124b均由N型掺杂的硅(n+Si)制成，但本发明并不限制于此。
步骤六：参照图2F，在第一N型导电层124a和第二N型导电层124b上分别制作形成源极125a和漏极125b，源极125a和漏极125b均与有源层123接触，并且源极125a和漏极125b分别延伸至栅极绝缘层122上。
这里，通过进行步骤二至步骤六，完成薄膜晶体管120的制作。
步骤七：参照图2G，在薄膜晶体管120和基板110上的栅极绝缘层122上制作形成第一钝化层151。第一钝化层151可以由低介电常数的材料制成。
步骤八：参照图2H，在第一钝化层151中形成将漏极125b暴露出的过孔151a。
步骤九：参照图2I，在基板110上的第一钝化层151上制作形成具有多个第二通孔131的像素电极130，其中，像素电极130填充过孔151a，以与漏极125b接触。
步骤十：参照图2J，在第一钝化层151和像素电极130上制作形成第二钝 化层152，第二钝化层152填充第二通孔131。这里第一钝化层151和第二钝化层152将构成图1中钝化层150的结构，具体请继续参考下面的描述。
步骤十一：参照图2K，在像素电极130上的第二钝化层152上制作形成具有多个第二通孔141的公共电极140，所述第一通孔131和该第二通孔141交错设置。
步骤十二：参照图2L，将薄膜晶体管120上的第二钝化层152和由第二通孔141暴露出的第二钝化层152刻蚀去除。这样，第一钝化层151和剩余的第二钝化层152形成了图1所示的钝化层150的结构。
在根据本发明的第一实施例的阵列基板的制作过程中，通过对第二钝化层152刻蚀，使像素电极130和公共电极140同时裸露，利用聚集的离子快速释放。
此外，在根据本发明的第一实施例的阵列基板及其制作方法中，通过对第二钝化层152的刻蚀可以形成立体电极结构(即上下形成的像素电极130和公共电极140)，有效增强横向电场，从而可以降低驱动电压，提高显示穿透率，降低能耗。
图3是根据本发明的第二实施例的阵列基板的结构示意图。
参照图3，根据本发明的第二实施例的阵列基板包括：基板210、薄膜晶体管220、像素电极230和公共电极240。
基板210可例如是透明的玻璃基板和树脂基板。薄膜晶体管220形成在基板210之上。像素电极230形成在基板110之上，进一步地，像素电极230形成在基板210上的除薄膜晶体管220所占区域之外的区域，并且像素电极230与薄膜晶体管220的漏极连接接触。公共电极240设置于像素电极230之上，并且公共电极240与像素电极230彼此电绝缘，公共电极240中具有多个第三通孔241。
这样，通过在公共电极240中形成第三通孔241，减小公共电极240与像素电极230之间的重叠面积，从而降低公共电极240与像素电极230之间的寄生电容。
在本实施例中，为了实现公共电极240和像素电极230的上述结构，进一步地，根据本发明的第二实施例的阵列基板还包括：钝化层250，该钝化层250设置于薄膜晶体管220和像素电极230之上，并且在像素电极130上的钝化层250具有多个凸起251，公共电极240设置于凸起251上，并且第三通孔241与凸起251交错设置，即第三通孔241相对于对应的相邻两个凸起251之间。
另外，薄膜晶体管220包括：栅极221，设置在基板210上；栅极绝缘层222，设置在基板210和栅极221上；有源层223，设置在栅极221上的栅极绝缘层222上；第一N型导电层224a和第二N型导电层224b，彼此间隔设置在有源层223上；源极225a和漏极225b，分别设置在第一N型导电层224a和第二N型导电层224b上，源极225a和漏极225b均与有源层223接触，并且源极225a和漏极225b分别延伸至栅极绝缘层222上；其中，像素电极230位于在基板210上的栅极绝缘层222上。
以上，描述了薄膜晶体管220的一种结构示例，但本发明并不限制于此。此外，有源层223由非晶硅(a-Si)制成，但本发明并不限制于此。第一N型导电层224a和第二N型导电层224b均由N型掺杂的硅(n+Si)制成，但本发明并不限制于此。
进一步地，钝化层250由低介电常数的材料制成，例如钝化层250可以由丙烯酸树脂、环氧树脂、多官能团可聚合单体、光引发剂、增粘剂和聚乙烯醇等混合溶解到溶剂中制成，所述溶剂可以为丙二醇甲醚醋酸酯(PGMEA)、乙氧基二乙二醇(EDG)等。这里，通过利用低介电常数的材料制成钝化层250，能够更进一步地降低公共电极240与像素电极230之间的寄生电容，并且可以加速聚集的离子的释放，从而降低离子聚集导致的直流残留。
图4A至图4J是根据本发明的第二实施例的阵列基板的制程图。
根据本发明的第二实施例的阵列基板的制作方法包括：
步骤一：参照图4A，提供一基板210。该基板210可例如是透明的玻璃基板和树脂基板。
步骤二：参照图4B，在基板210上制作形成栅极221。栅极221可由导电 金属制成。
步骤三：参照图4C，在基板210和栅极221上制作形成栅极绝缘层222。栅极绝缘层222可由绝缘材料(诸如SiOX或SiNX)制成。
步骤四：参照图4D，在栅极绝缘层222上制作形成有源层223，其中，有源层223与栅极221相对。有源层223由非晶硅(a-Si)制成，但本发明并不限制于此。
步骤五：参照图4E，在有源层223上制作形成彼此间隔的第一N型导电层224a和第二N型导电层224b。第一N型导电层224a和第二N型导电层224b均由N型掺杂的硅(n+Si)制成，但本发明并不限制于此。
步骤六：参照图4F，在第一N型导电层224a和第二N型导电层224b上分别制作形成源极225a和漏极225b，源极225a和漏极225b均与有源层223接触，并且源极225a和漏极225b分别延伸至栅极绝缘层222上。
这里，通过进行步骤二至步骤六，完成薄膜晶体管220的制作。
步骤七：参照图4G，在基板210上的栅极绝缘层222上制作形成像素电极230。
步骤八：参照图4H，在薄膜晶体管220和像素电极230上制作形成钝化层250。钝化层250可以由低介电常数的材料制成。
步骤九：参照图4I，在像素电极230上的钝化层250上制作形成具有多个第三通孔241的公共电极240。
步骤十：参照图4J，将薄膜晶体管220上的钝化层250的部分以及由第三通孔241暴露出的钝化层250的部分刻蚀去除。
在根据本发明的第二实施例的阵列基板及其制作方法中，通过对钝化层250的刻蚀可以形成立体电极结构(即上下形成的像素电极230和公共电极240)，有效增强横向电场，从而可以降低驱动电压，提高显示穿透率，降低能耗。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (11)

  1. 一种阵列基板，其中，包括：
    基板；
    薄膜晶体管，设置于所述基板之上；
    像素电极，设置于所述基板之上且与所述薄膜晶体管的漏极接触；
    公共电极，设置于所述像素电极之上且与所述像素电极电绝缘，所述公共电极中具有多个第一通孔。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括钝化层，所述钝化层设置于所述薄膜晶体管之上和所述像素电极之下，在所述像素电极之下的所述钝化层具有多个凸起，所述像素电极中具有多个第二通孔，所述凸起穿过对应的所述第二通孔。
  3. 根据权利要求2所述的阵列基板，其中，所述公共电极设置于所述凸起之上，所述第一通孔对应于相邻的两个凸起之间。
  4. 根据权利要求2所述的阵列基板，其中，所述薄膜晶体管包括：
    栅极，设置在所述基板上；
    栅极绝缘层，设置在所述基板和所述栅极上；
    有源层，设置在所述栅极绝缘层上；
    第一N型导电层和第二N型导电层，彼此间隔设置在所述有源层上；
    源极和漏极，分别设置在第一N型导电层和所述第二N型导电层上，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延伸至所述栅极绝缘层上；
    其中，所述像素电极位于在所述基板上的所述栅极绝缘层上，在所述基板 上的钝化层位于所述像素电极和在所述基板上的所述栅极绝缘层之间。
  5. 根据权利要求3所述的阵列基板，其中，所述薄膜晶体管包括：
    栅极，设置在所述基板上；
    栅极绝缘层，设置在所述基板和所述栅极上；
    有源层，设置在所述栅极绝缘层上；
    第一N型导电层和第二N型导电层，彼此间隔设置在所述有源层上；
    源极和漏极，分别设置在第一N型导电层和所述第二N型导电层上，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延伸至所述栅极绝缘层上；
    其中，所述像素电极位于在所述基板上的所述栅极绝缘层上，在所述基板上的钝化层位于所述像素电极和在所述基板上的所述栅极绝缘层之间。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括钝化层，所述钝化层设置于所述薄膜晶体管和所述像素电极之上，在所述像素电极之上的所述钝化层具有多个凸起，所述公共电极设置于所述凸起之上，所述第一通孔对应于相邻的两个凸起之间。
  7. 根据权利要求6所述的阵列基板，其中，所述薄膜晶体管包括：
    栅极，设置在所述基板上；
    栅极绝缘层，设置在所述基板和所述栅极上；
    有源层，设置在所述栅极绝缘层上；
    第一N型导电层和第二N型导电层，彼此间隔设置在所述有源层上；
    源极和漏极，分别设置在第一N型导电层和所述第二N型导电层上，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延伸至所述栅极绝缘层上；
    其中，在所述基板上的像素电极位于在所述基板上的所述栅极绝缘层上。
  8. 一种阵列基板的制作方法，其中，包括：
    提供一基板；
    在所述基板上制作形成薄膜晶体管；
    在所述薄膜晶体管和所述基板上制作形成第一钝化层；
    在所述第一钝化层中制作形成将所述薄膜晶体管的漏极暴露的过孔；
    在所述基板上的第一钝化层上制作形成具有多个第一通孔的像素电极，所述像素电极通过所述过孔与所述薄膜晶体管的漏极接触；
    在所述第一钝化层和所述像素电极上制作形成第二钝化层，所述第二钝化层填充所述第一通孔；
    在所述像素电极上的第二钝化层上制作形成具有多个第二通孔的公共电极，所述第一通孔和所述第二通孔交错设置；
    将所述薄膜晶体管之上的第二钝化层和由所述第二通孔暴露出的第二钝化层刻蚀去除。
  9. 根据权利要求8所述的制作方法，其中，在所述基板上制作形成薄膜晶体管的方法包括：
    在所述基板上制作形成栅极；
    在所述基板和所述栅极上制作形成所述栅极绝缘层；其中，在所述基板上的第一钝化层位于在所述基板上的栅极绝缘层上；
    在所述栅极上的栅极绝缘层上制作形成有源层；
    在所述有源层上制作形成彼此间隔的第一N型导电层和第二N型导电层；
    在所述第一N型导电层和所述第二N型导电层上分别制作形成源极和漏极，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延 伸至所述栅极绝缘层上。
  10. 一种阵列基板的制作方法，其中，包括：
    提供一基板；
    在所述基板上制作形成薄膜晶体管；
    在所述基板上制作形成像素电极，所述像素电极与所述薄膜晶体管的漏极接触；
    在所述薄膜晶体管和所述像素电极上制作形成钝化层；
    在所述像素电极上的钝化层上制作形成具有多个通孔的公共电极；
    将所述薄膜晶体管之上的钝化层的部分和由所述第二通孔暴露出的钝化层的部分刻蚀去除。
  11. 根据权利要求10所述的制作方法，其中，在所述基板上制作形成薄膜晶体管的方法包括：
    在所述基板上制作形成栅极；
    在所述基板和所述栅极上制作形成所述栅极绝缘层；其中，在所述基板上的像素电极位于在所述基板上的栅极绝缘层上；
    在所述栅极上的栅极绝缘层上制作形成有源层；
    在所述有源层上制作形成彼此间隔的第一N型导电层和第二N型导电层；
    在所述第一N型导电层和所述第二N型导电层上分别制作形成源极和漏极，所述源极和所述漏极与所述有源层接触，并且所述源极和所述漏极分别延伸至所述栅极绝缘层上。
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