WO2018182327A1 - Prise de vérification de boîtier pour semi-conducteur et procédé de fabrication associé - Google Patents

Prise de vérification de boîtier pour semi-conducteur et procédé de fabrication associé Download PDF

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Publication number
WO2018182327A1
WO2018182327A1 PCT/KR2018/003703 KR2018003703W WO2018182327A1 WO 2018182327 A1 WO2018182327 A1 WO 2018182327A1 KR 2018003703 W KR2018003703 W KR 2018003703W WO 2018182327 A1 WO2018182327 A1 WO 2018182327A1
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WO
WIPO (PCT)
Prior art keywords
layer
test socket
support plate
semiconductor package
hole
Prior art date
Application number
PCT/KR2018/003703
Other languages
English (en)
Korean (ko)
Inventor
정상후
Original Assignee
정상후
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정상후 filed Critical 정상후
Publication of WO2018182327A1 publication Critical patent/WO2018182327A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks

Definitions

  • the present invention relates to a semiconductor package test socket and a method of manufacturing the same.
  • the semiconductor package test socket is a connection device for mounting a completed semiconductor package completed to the packaging process and connecting the test equipment.
  • the semiconductor package test socket transfers an electrical signal from the test equipment to the semiconductor package and transmits a return signal of the semiconductor package to the signal. It is a device for passing back to test equipment to test whether the semiconductor package performs normal operation.
  • a typical semiconductor package test socket consists of a conductor that carries an electrical signal and an insulator that blocks electrical interference.
  • a typical semiconductor package test socket consists of a conductor that carries an electrical signal and an insulator that blocks electrical interference.
  • Due to the miniaturization of the package there is a lot of difficulty in manufacturing a conductor track due to the fine pitch.
  • the present invention has been made in an effort to provide a semiconductor package test socket and a method of manufacturing the same, in which an insulator structure layer is formed through lamination to be manufactured to cope with a fine pitch, and a thickness of an insulator is formed to a desired thickness. will be.
  • the support plate is formed with a first through hole therein; A support part disposed inside the first through hole and having a plurality of second through holes formed of an insulating material; A metal part formed inside the plurality of second through holes; A protective layer disposed on the support; And it may include a heat-resistant layer disposed under the support.
  • the metal portion may be made of metal fine particles.
  • the height of the support portion may correspond to or higher than the height of the support plate.
  • At least one of the protective layer and the heat-resistant layer may be made of polyimide (PI).
  • the step of placing a first film layer on the lower portion of the support plate is formed with a first through-hole; Forming an insulator layer of an insulating material in the first through hole; Disposing a second film layer on the support plate and the insulator layer; Forming a plurality of second through holes in the insulator layer; And pasting metal particles in the second through hole.
  • the forming of the insulator layer may include an insulator layer corresponding to the shape of the first through hole.
  • the forming of the insulator layer may include forming an insulator layer by applying an insulating material corresponding to the shape of the first through hole.
  • the height of the insulator layer may correspond to the height of the support plate.
  • it may be made of gold.
  • the manufacturing method of an embodiment of the present invention may further include performing compression processing and curing after pasting the metal fine particles.
  • At least one of the first and second film layers may be made of polyimide (PI).
  • PI polyimide
  • the present invention has an effect of allowing the thickness of the support formed by the silicon layer in the semiconductor test socket to be formed to a desired thickness.
  • the present invention has an effect of preventing the pins from being misaligned and adversely affecting the test by forming through holes in the silicon layer and filling metal particles therein instead of inserting the previously formed fins.
  • FIG. 1 is a cross-sectional view of a semiconductor package test socket of an embodiment of the present invention.
  • FIG. 2 is a perspective view of a semiconductor package test socket of an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view illustrating a state in which a semiconductor package test socket of an embodiment of the present invention is used.
  • 4A to 4G are cross-sectional views illustrating a manufacturing process of a semiconductor package test socket according to an exemplary embodiment of the present invention.
  • FIG. 5 is an exemplary view for explaining that a plurality of support plates are formed in a plate shape.
  • 'first' and 'second' may be used to describe various components, but the components should not be limited by the above terms. The term may only be used to distinguish one component from another. For example, a 'first component' may be referred to as a 'second component' without departing from the scope of the present invention, and similarly, a 'second component' may also be referred to as a 'first component'. Can be. In addition, singular forms also include plural forms unless the context clearly indicates otherwise. Unless otherwise defined, terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those skilled in the art.
  • FIGS. 1 to 5 a semiconductor package test socket and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5.
  • FIG. 1 is a cross-sectional view of a semiconductor package test socket of an embodiment of the present invention
  • FIG. 2 is a perspective view of a semiconductor package test socket of an embodiment of the present invention
  • 3 is a cross-sectional view illustrating a state in which a semiconductor package test socket of an embodiment of the present invention is used. 3 is shown for simplicity for convenience of description.
  • the semiconductor package test socket 1 of an embodiment of the present invention may include a support plate 10 and a test socket 20.
  • the support plate 10 may support the test socket 20 such that the test socket 20 is movable in the vertical direction. Through holes 10a may be formed at each corner of the support plate 10.
  • the shape of the support plate 10 is hexagonal, and for example, the through holes 10a are formed at each corner and both sides, but the present invention is not limited thereto. It may vary depending on the type of (not shown).
  • the support plate 10 may be made of metal.
  • the test socket 20 includes a support 21 and a hole 21a in the support 21, and the hole 22a may be formed with a metal 24.
  • the support 21 is an insulator, for example, may be made of silicon. However, this is just an example, and may be made of an elastic plastic material. Accordingly, when the semiconductor device 3 presses the test socket 20 for energization between the bump 3a of the semiconductor device 3 and the terminal 5a of the test circuit board 5, the semiconductor device 3 may be resilient. Can be prevented from being damaged.
  • the height of the support 21 may be equal to or higher than the height of the support plate 10.
  • silicone was applied by magnetic force to limit the height of the support part 21.
  • silicone is disposed in the form of a film without applying silicone, for example, by the magnetic force, The support 21 can be formed regardless of the height.
  • the protective layer 22 may be disposed above the support 21, and the heat resistant layer 23 may be disposed below the support 21.
  • the protective layer 22 may protect the support 21 from the bumps 3a. When the bump 3a contacts the hole 21a of the support part 21 and is pressed from the upper part, damage to the support part 21 can be prevented.
  • the protective layer 22 may be formed in such a manner as to adhere to the support 21.
  • the heat resistant layer 23 may protect the support part 21 from heat generated from the lower circuit board 5.
  • the heat resistant layer 23 may also be formed in such a manner as to be bonded to the support 21.
  • the heat-resistant layer 23 is formed to be the same as the size of the support portion 21, but is not limited thereto. That is, the heat resistant layer 23 may be formed larger than the support part 21 to extend in front of the support plate 10 or to extend to a part of the support plate 10.
  • the protective layer 22 and the heat resistant layer 23 may be formed of, for example, polyimide (PI).
  • PI is characterized by high heat resistance, electrical insulation, flexibility, non-combustibility, and is suitable for the protective layer 22 and the heat resistant layer 23.
  • the present invention is not limited thereto, and various materials that perform the above functions may be used as the protective layer 22 and the heat resistant layer 23.
  • the protective layer 23 and the heat-resistant layer 23 may be made of the same material or may be made of a different material.
  • the height of the protective layer 23 and the heat-resistant layer 23 may be the same or different, it may be set according to the test environment.
  • the metal part 24 is formed in the through hole 21a of the support part 21, and may be formed by curing the metal powder.
  • the metal powder may be, for example, gold, but the present invention is not limited thereto, and various metals may be used.
  • the metal part 24 is formed in the through hole 21a of the support part 21, and the pattern in which the through hole 21a is formed may be changed according to the bump 3a of the semiconductor device 3.
  • 4A to 4I are cross-sectional views illustrating a manufacturing process of a semiconductor package test socket according to an exemplary embodiment of the present invention.
  • a support plate 10 may be prepared.
  • a plurality of support plates 10 may be prepared in a single plate shape.
  • 5 is an exemplary view for explaining, for example, that a plurality of support plates are formed in a plate shape.
  • the plurality of support plates 10 may be formed in a plate shape.
  • the through hole 10b for forming the support part 21 may be formed in the support plate 10.
  • the first film layer 23a for forming the heat resistant layer 23 may be disposed.
  • a first adhesive layer 23b may be formed between the first film layer 23a and the support plate 10 to allow the first film layer 23a to adhere to the support plate 10.
  • the heights of the first film layer 23a and the first adhesive layer 23b are shown to be substantially the same, but this is illustrated for the description of an embodiment of the present invention, and the height of the first adhesive layer 23b may be ignored.
  • an adhesive (not shown) is applied to a surface of the first film layer 23a facing the support plate 10, and the support plate 10 and the first film layer 23a may be adhered by the adhesive. There will be.
  • an adhesive (not shown) is applied to a surface of the first film layer 23a facing the support plate 10, and then the support plate 10 is melted by heat during squeezing and / or curing. ) And the silicon layer 21b.
  • the silicon layer 21b will be described by way of example, it will be apparent that the material of the support part 21 is not limited to silicon in one embodiment of the present invention.
  • the silicon layer 21b may be formed in the through hole 10b of the support plate 10.
  • the film-shaped silicon layer 21b formed to correspond to the shape of the through hole 10b may be disposed, or the silicon layer 21b may be formed by applying silicon to the through hole 10b. will be.
  • the fin was formed first and silicon was applied by applying a magnetic field to prevent the pin from twisting and maintaining straightness.
  • a magnetic field is applied when the silicon is applied. There is no need to do it.
  • the height of the support plate 10 and the height of the silicon layer 21b are independent of each other. That is, the height of the silicon layer 21b may be higher than that of the support plate 10.
  • the silicon layer 21b is formed by applying silicon to the through hole 10b of the support plate 10
  • the height of the silicon layer 21b may correspond to the height of the support plate 10.
  • the lower portion of the silicon layer 21b may be attached to the first film layer 23a by the first adhesive layer 23b.
  • the second film layer 22a for forming the protective layer 22 may be disposed on the support plate 10 and the silicon layer 21b.
  • a second adhesive layer 22b may be formed between the second film layer 22a and the support plate 10 to allow the second film layer 22a to adhere to the support plate 10 and the silicon layer 21b.
  • the heights of the second film layer 22a and the second adhesive layer 22b are shown to be substantially the same, but this is illustrated for the description of one embodiment of the present invention, and the height of the second adhesive layer 22b may be negligible. .
  • an adhesive (not shown) is applied to the surface of the second film layer 22a facing the support plate 10, and the support plate 10 and the second film layer 22a may be bonded by the adhesive. There will be.
  • an adhesive (not shown) is applied to a surface of the second film layer 22a facing the support plate 10, and then the support plate 10 is melted by heat during squeezing and / or curing. ) And the silicon layer 21b.
  • the through hole 21a and the support part 21 may be formed by drilling the silicon layer 21b. Perforation of the silicon layer 21b may be performed using a laser. When the silicon layer 21b is punctured using a laser, the fine through hole 21b may be formed, and the detailed description thereof will be omitted since it is widely known in relation to the laser drilling technique.
  • the metal fine particles 24a may be pasted in the through holes 21b.
  • the metal fine particles may be made of, for example, gold, but the present invention is not limited thereto.
  • the metal fine particles may be fine particles obtained by plating gold on nickel (Ni) powder, or may be fine particles obtained by performing carbon nanocoating thereon. There will be more varieties of particulates available.
  • the metal fine particles 24a may be formed as the metal part 24 by a squeezing and curing process. Accordingly, the test socket 1 according to the embodiment of the present invention as shown in FIG. 4G. This can be formed.
  • the first and second film layers 23a and 22a on the support plate 10 are shown to be removed, one or both of them may not be removed. Even in this case, it is apparent that the film layers 23a and 22a of the upper and lower portions of the through hole 10a of the support plate 10 may be removed.
  • the semiconductor package test socket 1 may form the thickness of the support portion 21 formed by the silicon layer 21b to a desired thickness, and does not insert a pre-formed pin.
  • a pre-formed pin By forming the through holes 21a in the layer 21b and filling the metal fine particles therein, it is possible to prevent the pins from slipping and adversely affecting the test.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

L'invention concerne une prise de vérification de boîtier pour semi-conducteur et un procédé de fabrication associé. La prise de vérification de la présente invention est fabriqué selon les étapes consistant : à disposer une première couche de film sur une partie inférieure d'une plaque de soutien ayant un premier trou traversant formé à l'intérieur de cette dernière ; à former une couche isolante d'un matériau isolant dans le premier trou traversant ; à disposer une seconde couche de film sur une partie supérieure de la plaque de soutien et de la couche isolante ; à former une pluralité de seconds trous traversants dans la couche isolante; et à coller les particules métalliques fines aux seconds trous traversants.
PCT/KR2018/003703 2017-03-31 2018-03-29 Prise de vérification de boîtier pour semi-conducteur et procédé de fabrication associé WO2018182327A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020170041335A KR101789694B1 (ko) 2017-03-31 2017-03-31 반도체 패키지 테스트 소켓 및 그 제작방법
KR10-2017-0041335 2017-03-31

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WO2018182327A1 true WO2018182327A1 (fr) 2018-10-04

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WO (1) WO2018182327A1 (fr)

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Publication number Priority date Publication date Assignee Title
KR20190086598A (ko) 2017-12-29 2019-07-23 엔트리움 주식회사 엘라스토머 소켓
KR102548091B1 (ko) 2021-04-16 2023-06-27 주식회사 대림 폴리이미드를 포함하는 반도체 소자 테스트 소켓용 성형체 및 이의 제조방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020079350A (ko) * 2001-04-12 2002-10-19 신종천 집적화된 실리콘 콘택터 및 그 제작장치와 제작방법
KR20040023776A (ko) * 2002-09-11 2004-03-18 다이니폰 인사츠 가부시키가이샤 전자 디바이스 검사용 콘택트시트 및 그 제조방법
KR20090111682A (ko) * 2008-04-22 2009-10-27 주식회사 엑스엘티 레이저 기법을 적용한 소자 테스트용 부품 및 그 제조방법
KR20100099598A (ko) * 2009-03-03 2010-09-13 광주과학기술원 실리콘 콘택터 및 그 표면 처리 방법
KR101110002B1 (ko) * 2011-06-22 2012-01-31 이정구 반도체 소자 테스트용 탄성 콘택터 및 그 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020079350A (ko) * 2001-04-12 2002-10-19 신종천 집적화된 실리콘 콘택터 및 그 제작장치와 제작방법
KR20040023776A (ko) * 2002-09-11 2004-03-18 다이니폰 인사츠 가부시키가이샤 전자 디바이스 검사용 콘택트시트 및 그 제조방법
KR20090111682A (ko) * 2008-04-22 2009-10-27 주식회사 엑스엘티 레이저 기법을 적용한 소자 테스트용 부품 및 그 제조방법
KR20100099598A (ko) * 2009-03-03 2010-09-13 광주과학기술원 실리콘 콘택터 및 그 표면 처리 방법
KR101110002B1 (ko) * 2011-06-22 2012-01-31 이정구 반도체 소자 테스트용 탄성 콘택터 및 그 제조방법

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