WO2018176799A1 - 阵列基板及其开路修理方法、显示装置 - Google Patents

阵列基板及其开路修理方法、显示装置 Download PDF

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WO2018176799A1
WO2018176799A1 PCT/CN2017/106122 CN2017106122W WO2018176799A1 WO 2018176799 A1 WO2018176799 A1 WO 2018176799A1 CN 2017106122 W CN2017106122 W CN 2017106122W WO 2018176799 A1 WO2018176799 A1 WO 2018176799A1
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Prior art keywords
line
array substrate
signal line
common electrode
repair
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PCT/CN2017/106122
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English (en)
French (fr)
Inventor
纪强强
刘国全
车璐
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/072,599 priority Critical patent/US10859883B2/en
Publication of WO2018176799A1 publication Critical patent/WO2018176799A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present disclosure relates to the field of circuit design, and more particularly to an array substrate, a display device including such an array substrate, and an open circuit repair method for such an array substrate.
  • a thin film transistor (TFT) liquid crystal display device is an LCD that uses TFT technology to enhance image quality (eg, addressing capability and contrast).
  • an open circuit also known as an open circuit or an open circuit
  • an open circuit is often present in its circuit, which in turn causes pixel failures associated with the open circuit in the display device, such as display devices. Bad points and so on.
  • an array substrate In order to at least partially solve or alleviate the above problems, an array substrate, a display device including such an array substrate, and an open circuit repair method for such an array substrate according to an embodiment of the present disclosure are provided.
  • an array substrate includes: a first signal line arranged along a first direction; a second signal line arranged along a second direction different from the first direction, the second signal line and the first signal line are overlapped to form An intersection region; and a repair portion disposed adjacent the intersection region, the repair portion being electrically connected to the common electrode line and electrically insulated from the first signal line.
  • the first signal line is a data line and the second signal line is a gate line.
  • the repair portion is formed by adding isolated gate lines when the gate lines are fabricated in the gate mask. In some embodiments, the repair portion is disposed in the gate layer. In some embodiments, the repair portion is disposed in a gate layer below the data line. In some embodiments, the repair portion and the common electrode line are made of the same material.
  • the repair portion is configured to occur in the intersection region when the first signal line When the circuit is open, electrically connected to a portion of the first signal line on the side of the open circuit, and through an electrical connection with the common electrode line and a portion of the first signal line on the other side of the open circuit Electrical connection.
  • the electrical connection is achieved by soldering.
  • a display device includes the array substrate according to the first aspect of the present disclosure.
  • a method of repairing an open circuit of a first signal line in an array substrate according to the first aspect of the present disclosure includes: electrically connecting a portion of the first signal line on the open side to the repair portion; electrically connecting a portion of the first signal line on the other side of the open circuit to the a common electrode line; and electrically insulating the common electrode line in the region including the intersection region from the surroundings
  • the electrical insulation is achieved by cutting a portion of the common electrode line in the region from other portions.
  • the sides of the region are square regions of 50 microns.
  • FIG. 1 is an equivalent circuit diagram showing a TFT LCD according to the related art.
  • FIG. 2 is a partial enlarged schematic view showing an example array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 3 is a partially enlarged schematic view showing an example array substrate after repair according to an embodiment of the present disclosure.
  • FIG. 4 is an X-ray cross-sectional view showing a portion of the repaired example array substrate corresponding to FIG. 3.
  • FIG. 5 is a partially enlarged schematic view showing an example array substrate in accordance with another embodiment of the present disclosure.
  • FIG. 6 is a partially enlarged schematic view showing an example array substrate after repair according to another embodiment of the present disclosure.
  • FIG. 7 is a flow chart showing an example open circuit repair method in accordance with another embodiment of the present disclosure.
  • the present disclosure will be described in detail by taking the scene of the present disclosure applied to a TFT LCD as an example.
  • the present disclosure is not limited thereto, and the present disclosure is also applicable to any other suitable circuit design including, but not limited to, any circuit in which an open circuit exists.
  • the technical solution according to an embodiment of the present disclosure is described in detail below by taking an open circuit as an example, it can be applied to other open conditions, for example, in the case of appropriate adjustments and changes as would occur to those skilled in the art, for example.
  • Scan (gate) line is open, etc.
  • FIG. 1 is an equivalent circuit diagram showing a TFT LCD according to the related art.
  • the equivalent circuit of the TFT LCD may include a plurality of pixel circuits arranged in an array.
  • Each of the pixel circuits may have a TFT corresponding thereto, a storage capacitor, and a liquid crystal (LC).
  • Each pixel circuit of the same row is under the control of the same scanning line (hereinafter sometimes referred to as a gate line), and each pixel circuit of the same column is under the control of the same data line (hereinafter sometimes referred to as a source line).
  • the scan lines and data lines are typically arranged in different directions, and more specifically, are generally arranged in generally mutually perpendicular directions.
  • each of the scanning lines in sequence (for example, the scanning direction is from top to bottom, that is, from the scanning line 1 to the scanning line m), so that the pixels corresponding to each scanning line are made. All TFTs in the row are turned on at the same time.
  • each pixel circuit in the same row can deflect or not deflect the liquid crystal according to the input in the corresponding data line, thereby making the backlight pass through or not through the liquid crystal layer, and finally make the corresponding on the display device.
  • the pixel emits light or does not emit light.
  • the gate of the TFT when a high level is applied to the gate of the TFT such that the TFT is turned on, if the input of the corresponding data line (source line) is at a high level at this time, the LC in the pixel circuit is deflected, and the backlight is turned off. Through Then, the corresponding pixels emit light, and at the same time, the corresponding storage capacitors are charged. After that, when the next row of pixels is scanned, the gate line of the pixel of the row is input with a low level, and at this time, each TFT in the row is in an off state.
  • the storage capacitor can still supply power to the LC even though the TFT is turned off and no new current enters. Let it continue to remain in a deflected state and cause the corresponding pixel to illuminate, waiting for the next scan. For a pixel that was not previously in a light-emitting state, it remains in a state in which it does not emit light.
  • a data line open circuit may occur, such as the data line open circuit 50 in FIG. 3 or the data line open circuit 50 in FIG.
  • an array substrate, a display device, and an open circuit repair method according to an embodiment of the present disclosure have been proposed. This will be described in detail below with reference to FIGS. 2 to 7.
  • FIG. 2 is a partially enlarged top plan view showing an example array substrate in accordance with an embodiment of the present disclosure.
  • Portions of the array substrate shown in FIG. 2 may include: a data line 10, a scan line 20, a common electrode line 30, a common electrode hole 35, and a TFT 40.
  • the common electrode hole 35 serves as a via hole for the common electrode conductor to pass through, since the insulating layer above it is etched away, so that the isolated pixel electrode can be placed on the via hole, thereby connecting the entire common electrode into a mesh shape. .
  • intersection portion 1 of the data line may be referred to as an intersection portion 1 of the data line, or may be referred to as a data line 10
  • the intersection area 1 is illustrated as a rectangle in the top view of FIG. 2, the present disclosure is not limited thereto. In fact, the intersection 1 can be any shape in a top view, such as a square, a triangle, a trapezoid, or any other regular or irregular polygon, etc., depending in part on the shape of the data line itself and partly on the size of the intersection 1 . Further, although the intersection area 1 is shown in FIG.
  • intersection 1 can have any shape and/or size without affecting the technical effects of the present disclosure as described below.
  • FIG. 3 is a partially enlarged schematic view showing an example array substrate after repair according to an embodiment of the present disclosure.
  • data line 10 is open (ie, data line crossing area DO) 50 within intersection area 1.
  • the data line 10 may have an open circuit 50 due to a production process or improper use.
  • the tungsten powder deposition 70 bypassing the DO 50 may be formed by depositing tungsten powder in a source drain layer (hereinafter sometimes simply referred to as an S-D layer or an SD layer).
  • a source drain layer hereinafter sometimes simply referred to as an S-D layer or an SD layer.
  • DCS data line-common electrode line short circuit
  • FIG. 4 is an X-ray cross-sectional view showing a portion of the repaired example array substrate corresponding to FIG. 3. As more clearly shown in the upper cross-sectional view of FIG. 4, it can be seen that after maintenance in the SD layer, the tungsten powder diffuses into the common electrode hole (Com hole), causing the data line and the common electrode line to be short-circuited (DCS). ) and caused the corresponding pixel to be bad.
  • Com hole common electrode hole
  • DCS short-circuited
  • it may be formed by using tungsten powder in the final layer (hereinafter sometimes referred to simply as a final layer, that is, a layer formed as a final process of the TFT array substrate process), as shown in FIG.
  • the tungsten powder deposit 70 at DO 50 is bypassed.
  • the adhesion of the tungsten powder is lowered, which may result in maintenance failure and cannot be debugged (for example, parameter adjustment).
  • the surrounding ITO needs to be stripped (otherwise the back end is poor pixel), and the ITO is damaged at this time, which may also cause the back pixel to be poor.
  • FIG. 5 illustrates a partial enlarged schematic view of an example array substrate in accordance with another embodiment of the present disclosure.
  • One of the main differences between the embodiment shown in Fig. 5 and the embodiment shown in Fig. 2 is the portion indicated by the dashed circle in Fig. 5.
  • the array substrate is provided with a repair portion 37 in addition to the respective elements shown in FIG.
  • repair portion 37 may be a conductor disposed adjacent an intersection of data line 10 (eg, similar to intersection 1 shown in Figures 2 and 3). More specifically, in some embodiments, the repair portion 37 can be a conductor disposed below the intersection of the data lines 10. However, embodiments of the present disclosure are not limited thereto. In fact, the repair portion 37 can be provided as long as it is near any position where an open circuit may occur.
  • the repair portion 37 may be electrically connected to the common electrode line 30 and electrically insulated from the data line 10. Although it appears that the data line 10 overlaps the repair portion 37 in the top view of Fig. 5, the two are actually in different layers and are not in direct contact.
  • the data line 10 may be in the source drain layer and electrically connected to the source of the TFT 40.
  • the repair portion 37 can be located in the gate layer to be electrically insulated from the data line 10.
  • the gate layer refers to a layer in which the gate and the gate line are located.
  • the repair portion 37 and the common electrode line 30 electrically connected thereto may be made of the same material.
  • the manufacturing order of the layers may be, for example, a first ITO layer, a gate layer, a source/drain layer, a PVX (layer, and a second ITO layer) according to a production process.
  • the first ITO layer can serve as a common electrode layer
  • the gate layer includes a gate electrode and a gate line electrically connected to the gate
  • the source/drain metal layer includes a source/drain electrode and a signal disposed in the same layer as the source and drain electrodes.
  • the line, the PVX layer can be used as the insulating layer or the passivation layer, and the second ITO layer can be used as the pixel electrode.
  • This embodiment only gives some exemplary structures, and the structure of the array substrate is not limited, and those skilled in the art can The structure of the array substrate and the corresponding production process are designed according to actual needs.
  • the maintenance portion 37 can be formed by adding an isolated gate line when the gate line is formed in the gate mask.
  • FIG. 6 is a partially enlarged schematic view showing an example array substrate after repair according to another embodiment of the present disclosure.
  • the repairing portion 37 in the array substrate is configured to be electrically connected to a portion of the first signal line on the open side when the first signal line is opened in the intersection region, and to pass through the common electrode line
  • the electrical connection is electrically connected to a portion of the first signal line on the other side of the open circuit.
  • the portion on the side of the open line 50 of the data line 10 can be electrically connected to the repair portion 37 (for example, the data line 10 in FIG. 6 is on the upper side of the open circuit 50).
  • a portion of the other side of the data line 10 open circuit 50 can be electrically connected to the common electrode line 30, and can be in the vicinity of the intersection area 1 (for example, a square area having a side length of 50 ⁇ m including the intersection area 1)
  • the common electrode line 30 is electrically insulated from the surroundings.
  • electrical connections e.g., solder joints or wire bonds 39
  • soldering may be achieved by soldering.
  • the effect of melting the metal by the laser thermal effect can be used to weld the data line 10 on both sides of the circuit to the repair portion 37 and the common electrode line 30, respectively.
  • electrical insulation e.g., cutting zone 38
  • the cutting may be performed near the pixel electrode position at the via position (for example, the common electrode hole 35), and the common electrode from the uppermost pixel electrode to the lower common electrode may be cut at the time of cutting, thereby isolating the common electrode metal at the via position.
  • FIG. 7 is a flow chart showing an example method 700 for repairing an open circuit of a first signal line (eg, a data line) in accordance with another embodiment of the present disclosure.
  • the method 700 is applicable to an array substrate as shown in FIG.
  • the method in FIG. 7 begins in step S710.
  • step S710 the portion of the first signal line on the open side may be electrically connected to the repair portion.
  • step S720 a portion of the first signal line on the other side of the open circuit may be electrically connected to the common electrode line.
  • the common electrode line in the region including the intersection region may be electrically insulated from the surroundings.
  • the sides of the region are square regions of 50 microns.
  • the first signal line can be a data line and the second signal line can be a gate line.
  • the repair portion may be formed by adding isolated gate lines when the gate lines are fabricated in the gate mask. By such a manufacturing method, the manufacturing of the repairing portion can be integrated with a conventional process to avoid or reduce the increase in cost due to the changing process.
  • the electrical connection may be achieved by soldering the repair portion to a portion on the open side of the first signal line and soldering the common electrode line to a portion on the other side of the first signal line open circuit.
  • the above electrical insulation may be achieved by cutting a portion of the common electrode line in the vicinity of the intersection (for example, a square region having a side length of 50 ⁇ m including the intersection) and other portions. In this way, each electrical connection and electrical insulation can be realized, and the short circuit or crack caused by using the tungsten powder to repair the open circuit can be avoided, the damage to each ITO layer is avoided, and the repair success rate is improved.
  • welding and cutting can be performed using the welding and cutting functions of conventional equipment, the cost is also reduced.
  • the repair portion 37 can be disposed in the gate layer. In some embodiments, the repair portion 37 can be disposed in a gate layer below the respective data line 10. By arranging the repair portion in the gate layer below the data line, the maintenance portion 37 can be formed by adding an isolated gate line when the gate line is formed in the gate mask, which is compatible with the conventional process flow and avoids changes. The cost of production can be increased.
  • the repair portion 37 and the common electrode line 30 may be made of the same material. By implementing the repair portion with the same material as the common electrode line, it is also possible to reduce the cost increase that may result from changing the production process.
  • functions described herein as being implemented by pure hardware, software, and/or firmware may also be implemented by dedicated hardware, a combination of general-purpose hardware and software, and the like.
  • functions described as being implemented by dedicated hardware eg, Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.
  • general purpose hardware eg, central processing unit (CPU), digital signal processing (DSP) is implemented in a way that is combined with software and vice versa.

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Abstract

一种阵列基板、显示装置和修理方法。该阵列基板包括：沿第一方向布置的第一信号线（10）；沿与第一方向不同的第二方向布置的第二信号线（20）；以及修理部(37)，布置在第一信号线（10）中的与第二信号线（20）交叠的交叉区（1）附近，修理部（37）与公共电极线（30）电连接，并与第一信号线（10）电绝缘。

Description

阵列基板及其开路修理方法、显示装置
相关申请的交叉引用
本申请要求于2017年4月1日提交的、申请号为201710216158.6的中国专利申请的优先权，其全部内容通过引用并入本申请中。
技术领域
本公开涉及电路设计领域，且更具体地涉及一种阵列基板、包括这种阵列基板在内的显示装置、以及针对这种阵列基板的开路修理方法。
背景技术
薄膜晶体管(TFT)液晶显示装置(LCD)是使用TFT技术来增强图像质量(例如，寻址能力和对比度)的一种LCD。
然而，在其生产、使用、维修过程中，经常会在其电路中出现开路(又称为断路或“open circuit”)的现象，进而导致显示装置中与该开路相关的像素故障，例如显示装置坏点等。
发明内容
为了至少部分解决或减轻上述问题，提供了根据本公开实施例的阵列基板、包括这种阵列基板在内的显示装置、以及针对这种阵列基板的开路修理方法。
根据本公开的第一方面，提出了一种阵列基板。该阵列基板包括：沿第一方向布置的第一信号线；沿与第一方向不同的第二方向布置的第二信号线，所述第二信号线与所述第一信号线通过交叠形成交叉区；以及修理部，布置在所述交叉区附近，所述修理部与公共电极线电连接，并与所述第一信号线电绝缘。
在一些实施例中，所述第一信号线是数据线且所述第二信号线是栅极线。在一些实施例中，所述修理部是通过在栅极掩膜板制作栅极线时增加孤立的栅极线来形成的。在一些实施例中，所述修理部布置于栅极层中。在一些实施例中，所述修理部布置于所述数据线下方的栅极层中。在一些实施例中，所述修理部与所述公共电极线是由相同材料制成的。
在一些实施例中，所述修理部被配置为，在所述第一信号线在交叉区中发生 开路时，与所述第一信号线的位于所述开路一侧的部分电连接，并通过与所述公共电极线的电连接与所述第一信号线的位于所述开路另一侧的部分电连接。
在一些实施例中，电连接是通过焊接实现的。
根据本公开的第二方面，提出了一种显示装置。该显示装置包括根据本公开第一方面所述的阵列基板在内。
根据本公开的第三方面，提出了一种修理根据本公开第一方面的阵列基板中的第一信号线的开路的方法。该方法包括：将所述第一信号线的位于所述开路一侧的部分电连接至所述修理部；将所述第一信号线的位于所述开路另一侧的部分电连接至所述公共电极线；以及将包含所述交叉区在内的区域中的公共电极线与周围电绝缘
在一些实施例中，所述电绝缘是通过将所述公共电极线在所述区域中的部分与其他部分切割开来实现的。
在一些实施例中，所述区域的边长是50微米的方形区域。
附图说明
通过下面结合附图说明本公开的优选实施例，将使本公开的上述及其它目的、特征和优点更加清楚，其中：
图1是示出了根据相关技术的TFT LCD的等效电路示意图。
图2是示出了根据本公开实施例的示例阵列基板的局部放大示意图。
图3是示出了根据本公开实施例的修理后的示例阵列基板的局部放大示意图。
图4是示出了与图3相对应的修理后的示例阵列基板局部的X射线截面图。
图5是示出了根据本公开另一实施例的示例阵列基板的局部放大示意图。
图6是示出了根据本公开另一实施例的修理后的示例阵列基板的局部放大示意图。
图7是示出了根据本公开另一实施例的示例开路修理方法的流程图。
具体实施方式
下面参照附图对本公开的优选实施例进行详细说明，在描述过程中省略了对于本公开来说是不必要的细节和功能，以防止对本公开的理解造成混淆。在本说 明书中，下述用于描述本公开原理的各种实施例只是说明，不应该以任何方式解释为限制公开的范围。参照附图的下述描述用于帮助全面理解由权利要求及其等同物限定的本公开的示例性实施例。下述描述包括多种具体细节来帮助理解，但这些细节应认为仅仅是示例性的。因此，本领域普通技术人员应认识到，在不脱离本公开的范围和精神的情况下，可以对本文中描述的实施例进行多种改变和修改。此外，为了清楚和简洁起见，省略了公知功能和结构的描述。此外，贯穿附图，相同的附图标记用于相同或相似的功能和操作。此外，在附图中，各部分并不一定按比例来绘制。换言之，附图中的各部分的相对大小、长度等并不一定与实际比例相对应。
以下，以本公开应用于TFT LCD的场景为例，对本公开进行了详细描述。但本公开并不局限于此，本公开也可以应用于任何其它适用的电路设计，包括(但不限于)存在开路的任何电路。此外，尽管以下以数据线开路为例详细描述了根据本公开实施例的技术方案，然而其在经过本领域技术人员所能想到的适当调整和变化的情况下也可以应用于其他开路情况，例如扫描(栅极)线开路等。
在本公开中，术语“包括”和“含有”及其派生词意为包括而非限制；术语“或”是包含性的，意为和/或。
首先将参照图1来大致介绍TFT LCD的构造以及原理。图1是示出了根据相关技术的TFT LCD的等效电路示意图。
如图1所示，TFT LCD的等效电路可包括阵列排布的多个像素电路。每个像素电路可以具有与其相对应的TFT、存储电容以及液晶(LC)。同一行的各个像素电路在同一条扫描线(以下有时也称为栅极线)的控制下，而同一列的各个像素电路在同一条数据线(以下有时也称为源极线)的控制下。扫描线和数据线通常是沿不同方向布置的，更具体地，通常是沿大体相互垂直的方向布置的。
在TFT LCD工作时，通常依次向各条扫描线顺序输入高电平(例如，扫描方向为从上到下，即从扫描线1至扫描线m)，从而使得与每条扫描线对应的像素行中的所有TFT同时导通。在TFT导通时，同一行中的各个像素电路可以根据各自对应数据线中的输入来使得液晶发生偏转或不偏转，进而使得背光透过或不透过液晶层，最终使得显示装置上的对应像素发光或不发光。
更具体地，当在对TFT的栅极施加高电平使得TFT导通时，如果此时相应数据线(源极线)的输入为高电平，则使得像素电路中的LC发生偏转，背光透 过，从而相应像素发光，同时还对相应存储电容进行充电。之后，当扫描到下一行像素时，本行像素的栅极线输入低电平，此时本行中的各TFT为截止状态。在该情况下，如果某一像素之前是发光状态，即其LC发生了偏转且存储电容中为充电状态，则尽管此时TFT截止且没有新的电流进入，但是存储电容依然可以为LC供电，使得其继续保持偏转状态并使得对应像素发光，等待下一次扫描。而对于之前不是发光状态的像素，则保持其不发光的状态。
如前所述，在生产、使用或维修这种TFT LCD的阵列基板时，可能会发生数据线开路的情况，例如图3中的数据线开路50或图6中的数据线开路50。为了至少部分解决或减轻该问题，提出了根据本公开实施例的阵列基板、显示装置和开路修理方法。以下将结合图2～图7对其进行详细描述。
首先，将结合图2～3来详细描述根据本公开实施例的示例阵列基板的布置。图2是示出了根据本公开实施例的示例阵列基板的局部放大俯视示意图。图2所示的阵列基板的局部可以包括：数据线10、扫描线20、公共电极线30、公共电极孔35、以及TFT 40。公共电极孔35作为过孔，其供公共电极导体通过，由于其上方的绝缘层均被刻蚀掉，因此可以通过孤立的像素电极搭在该过孔上，从而将整个公共电极连接成网状。
此外，如图2所示，数据线10在俯视图中与扫描线20相交的部分以及其延伸方向上两侧的扩展部分可被称为数据线的交叉区1，或者将其称为数据线10的与扫描线20交叠的部分。尽管在图2的俯视图中将交叉区1示出为矩形，然而本公开不限于此。事实上交叉区1在俯视图中可以是任何形状，例如正方形、三角形、梯形、或任何其他规则或不规则的多边形等等，这部分取决于数据线本身的形状且部分取决于交叉区1的大小。此外，尽管在图2中将交叉区1示出为具有扫描线宽度的3倍的长度，即从扫描线向上延伸1倍扫描线宽度，且从扫描线向下延伸1倍扫描线宽度，然而本公开不限于此。事实上，交叉区的长度可以具有任何其他尺寸。本领域技术人员应当理解：在不影响如下文所描述的本公开的技术效果的情况下，交叉区1可以具有任何形状和/或大小。
图3是示出了根据本公开实施例的修理后的示例阵列基板的局部放大示意图。与图2所示实施例不同的是，在图3的实施例中，数据线10在交叉区1内发生开路(即，数据线交叉区DO)50。例如，数据线10可能由于生产工艺或使用不当等情况而出现开路50。
为了使得数据线10依然能够正常工作，在一些实施例中，可以通过在源漏层(以下有时简称为S-D层或SD层)中沉积钨粉形成绕开DO 50的钨粉沉积70。此外，为了避免形成的钨粉沉积70与周围的其他导体(例如，扫描线20、公共电极线30)短接，需要对钨粉沉积70周围的ITO区域80进行移除，使得钨粉沉积70与周围的其他导电层电绝缘。在这种情况下，可以使得数据线10依然能够正常工作。
然而，在SD层中维修DO时，钨粉可能扩散进入公共电极孔35，导致例如“数据线-公共电极线短路”(以下有时也称为DCS)高发。如果维修后存在这种DCS，则在使用X射线来检查SD层修理效果时维修人员看到的可能是X薄暗线，从而极易漏检并将不良留到用户端，存在品质风险。
图4是示出了与图3相对应的修理后的示例阵列基板局部的X射线截面图。如在图4的上部截面图中更明确地示出的，可以看到在SD层中维修之后，钨粉扩散到公共电极孔(Com孔)中，使得数据线和公共电极线发生短路(DCS)，并造成对应像素不良。
此外，在另一些实施例中，还可以如图3所示通过使用钨粉在最终层(以下有时简称为final层，即作为TFT阵列基板工艺制程的最后一道工序所形成的层。)中形成绕开DO 50处的钨粉沉积70。此外，为了避免形成的钨粉沉积70与周围的其他导体(例如，扫描线20、公共电极线30)短接，需要对钨粉沉积70周围的ITO区域80进行移除，使得钨粉沉积70与周围的其他导电层电绝缘。在这种情况下，同样可以使得数据线10依然能够正常工作。
尽管在最终层中维修可以避免前述DCS问题，但是在Final层中维修时，同样存在其他问题。例如，如果钨粉沉积能量大，则容易造成跨栅极或公共电极时将PVX(钝化层)击穿造成裂缝，而钨粉沉积本身同样也可能存在裂缝现象(例如，如在图4的下部截面图中更明确地示出的)。在该情况下，导致生产、维修流程的下游(即，流程中更接近用户的一侧)中的产品的DO/DCS较高，同样容易漏检从而将不良留到用户端，存在品质风险。而如果钨粉沉积能量低，则钨粉粘附性降低，可能导致维修失败，不能通过调试(例如参数调试)。此外，钨粉沉积后需将周围的ITO剥除(否则后端均为像素不良)，此时ITO受损，同样可能造成后端像素不良较高。
因此，在图2和图3所示的实施例中，尽管可以通过在例如SD层或final层中实现对数据线开路的修复，但维修后可能依然存在数据线不良问题，进而导致对应像素为坏点。
为了至少进一步部分解决或减轻这些问题，以下将结合图5和图6来详细描述根据本公开另一实施例的阵列基板布置。
图5示出了根据本公开另一实施例的示例阵列基板的局部放大示意图。图5所示实施例与图2所示实施例的主要区别之一在于图5中的虚线圈所指示的部分。如图5所示，阵列基板除了包括图2所示的各个元件之外，还设置有修理部37。
在一些实施例中，修理部37可以是布置在数据线10的交叉区(例如，类似于图2和3所示的交叉区1)附近的导体。更具体地，在一些实施例中，修理部37可以是布置在数据线10的交叉区下方的导体。然而，本公开实施例不限于此。事实上，只要是任何可能出现开路的位置附近，都可以设置修理部37。
此外，修理部37可以与公共电极线30电连接，并与数据线10电绝缘。尽管在图5的俯视图中看起来数据线10与修理部37有重叠部分，但实际上这二者分处于不同的层中，并不直接接触。例如，数据线10可以在源漏层中，并与TFT40的源极电连接。相对地，修理部37可以位于栅极层中，从而与数据线10电绝缘。在本实施例中，栅极层指的是栅极、栅极线所处的层。
此外，修理部37和与其电连接的公共电极线30可以由相同材料制成。更具体地，在一些实施例中，在生产阵列基板时，根据生产工艺，各层的制造顺序可以是例如第一ITO层、栅极层、源漏层、PVX(层、以及第二ITO层。示例性的，第一ITO层可以作为公共电极层，栅极层包括栅极以及与栅极电连接的栅极线，源漏金属层包括源漏电极以及与源漏电极同层设置的信号线，PVX层可以作为绝缘层或钝化层，第二ITO层可以作为像素电极。本实施例只是给出了一些示例性的结构，对阵列基板的结构并不构成限定，本领域技术人员可以根据实际需要设计阵列基板的结构以及相应生产工艺。此时，为了制造修理部37，可以通过在栅极掩膜板制作栅极线时增加孤立的栅极线来形成维修部37。
图6是示出了根据本公开另一实施例的修理后的示例阵列基板的局部放大示意图。所述阵列基板中的修理部37被配置为，在第一信号线在交叉区中发生开路时，与第一信号线的位于所述开路一侧的部分电连接，并通过与公共电极线 的电连接与第一信号线的位于开路另一侧的部分电连接。
如图6所示，当数据线10在交叉区内发生开路50时，可将数据线10开路50一侧的部分电连接至修理部37(例如，图6中数据线10在开路50上侧的部分)，并可将数据线10开路50另一侧的部分电连接至公共电极线30，同时可将交叉区1附近(例如，包含交叉区1在内的边长50微米的方形区域中)的公共电极线30与周围电绝缘。在图6所示实施例中，电连接(例如，焊点或引线焊接39)可以是通过焊接实现的。例如，可以通过激光热效应将金属融化的效果，将数据线10断路两侧分别与修理部37和公共电极线30焊接。此外，在图6所示实施例中，电绝缘(例如，切割区38)可以是通过切割实现的。例如，可以在过孔位置(例如，公共电极孔35)靠近像素电极位置进行切割，切割时从最上面的像素电极到下面的公共电极均被切开，从而将过孔位置的公共电极金属孤立。
这样，通过利用已有的公共电极线以及简单的焊接与切割，而不是使用钨粉沉积，同样可以实现对数据线开路的修复，同时对ITO几乎无损伤。根据该实施例的方案无其它工艺风险，对产品良率无影响，且维修成功率高、维修后亮点不良发生率降低明显。
此外，尽管在图2～6的实施例中以“数据线”作为第一信号线的具体示例来详细说明了根据本公开的一些实施例的方案，然而本公开不限于此。事实上，可以将上述实施例中的“数据线”和“栅极线”互换，从而可以实现对“栅极线”开路的修复。
接下来，将结合图7来详细描述示例开路修理方法。
图7是示出了根据本公开另一实施例的用于修理第一信号线(例如，数据线)开路的示例方法700的流程图。所述方法700适用于如图5所示的阵列基板。图7中的方法开始于步骤S710。
在步骤S710中，可以将第一信号线的位于开路一侧的部分电连接至修理部。
在步骤S720中，可以将第一信号线的位于开路另一侧的部分电连接至公共电极线。
在步骤S730中，可以将包含交叉区在内的区域中的公共电极线与周围电绝缘。在一个实施例中，所述区域的边长是50微米的方形区域。
在一些实施例中，第一信号线可以是数据线且第二信号线可以是栅极线。在一些实施例中，修理部可以是通过在栅极掩膜板制作栅极线时增加孤立的栅极线来形成的。通过这样的制作方式，可以将修理部的制造与常规工艺融合，以避免或减少由于变更工艺所造成的成本增加。
在一些实施例中，上述电连接可以是通过将所述修理部与第一信号线开路一侧的部分焊接以及将所述公共电极线与第一信号线开路另一侧的部分焊接来实现的，以及上述电绝缘可以是通过将所述公共电极线在所述交叉区附近(例如，包含交叉区在内的边长50微米的方形区域中)的部分与其他部分切割开来实现的。以这种方式来实现各个电连接和电绝缘，可以避免使用钨粉修理开路时所造成的短路或开裂，避免了对各ITO层的损伤，提高维修成功率。另外，由于焊接和切割可以使用常规设备的焊接和切割功能，从而也降低了成本。
在一些实施例中，修理部37可以布置于栅极层中。在一些实施例中，修理部37可以布置于相应数据线10下方的栅极层中。通过将修理部布置在数据线下方的栅极层中，可以通过在栅极掩膜板制作栅极线时增加孤立的栅极线来形成维修部37，与常规工艺流程兼容，也避免了变更生产工艺所可能导致的成本增加。
在一些实施例中，修理部37与公共电极线30可以是由相同材料制成的。通过用与公共电极线相同的材料来实现修理部，也能降低变更生产工艺所可能导致的成本增加。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开的范围不局限于上述特定实施例，而应由所附权利要求所限定。
此外，在本文中被描述为通过纯硬件、纯软件和/或固件来实现的功能，也可以通过专用硬件、通用硬件与软件的结合等方式来实现。例如，被描述为通过专用硬件(例如，现场可编程门阵列(FPGA)、专用集成电路(ASIC)等)来实现的功能，可以由通用硬件(例如，中央处理单元(CPU)、数字信号处理器(DSP))与软件的结合的方式来实现，反之亦然。

Claims (12)

  1. 一种阵列基板，包括：
    沿第一方向布置的第一信号线；
    沿与第一方向不同的第二方向布置的第二信号线，所述第二信号线与所述第一信号线通过交叠形成交叉区；以及
    修理部，布置在所述交叉区附近，所述修理部与公共电极线电连接，并与所述第一信号线电绝缘。
  2. 根据权利要求1所述的阵列基板，其中，所述第一信号线是数据线且所述第二信号线是栅极线。
  3. 根据权利要求2所述的阵列基板，其中，所述修理部是通过在栅极掩膜板制作栅极线时增加孤立的栅极线来形成的。
  4. 根据权利要求2所述的阵列基板，其中，所述修理部布置于栅极层中。
  5. 根据权利要求4所述的阵列基板，其中，所述修理部布置于所述数据线下方的栅极层中。
  6. 根据权利要求1所述的阵列基板，其中，所述修理部与所述公共电极线是由相同材料制成的。
  7. 根据权利要求1所述的阵列基板，其中，
    所述修理部被配置为，在所述第一信号线在交叉区中发生开路时，与所述第一信号线的位于所述开路一侧的部分电连接，并通过与所述公共电极线的电连接与所述第一信号线的位于所述开路另一侧的部分电连接。
  8. 根据权利要求7所述的阵列基板，其中，所述电连接是通过焊接实现的。
  9. 一种显示装置，包括权利要求1～8中任一项所述的阵列基板。
  10. 一种修理根据权利要求1-8所述的阵列基板中的第一信号线的开路的方法，包括：
    将所述第一信号线的位于所述开路一侧的部分电连接至所述修理部；
    将所述第一信号线的位于所述开路另一侧的部分电连接至所述公共电极线；以及
    将包含所述交叉区在内的区域中的公共电极线与周围电绝缘。
  11. 根据权利要求10所述的方法，其中，所述电绝缘是通过将所述公共电 极线在所述区域中的部分与其他部分切割开来实现的。
  12. 根据权利要求10所述的方法，其中，所述区域的边长是50微米的方形区域。
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