WO2018176739A1 - 具有输入信号预比较与电荷重分配的流水线模数转换器 - Google Patents

具有输入信号预比较与电荷重分配的流水线模数转换器 Download PDF

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WO2018176739A1
WO2018176739A1 PCT/CN2017/101184 CN2017101184W WO2018176739A1 WO 2018176739 A1 WO2018176739 A1 WO 2018176739A1 CN 2017101184 W CN2017101184 W CN 2017101184W WO 2018176739 A1 WO2018176739 A1 WO 2018176739A1
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analog
sub
input signal
digital converter
switch
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PCT/CN2017/101184
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English (en)
French (fr)
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黄正波
李婷
张勇
李儒章
陈光炳
倪亚波
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中国电子科技集团公司第二十四研究所
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Priority to US16/497,806 priority Critical patent/US10979066B1/en
Publication of WO2018176739A1 publication Critical patent/WO2018176739A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
    • H03M1/168—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters and delivering the same number of bits

Definitions

  • the present invention relates to the field of integrated circuits, and more particularly to the technical field of high precision ultra high speed low power analog-to-digital converter design, and more particularly to a pipelined analog-to-digital converter with input signal pre-comparison and charge redistribution.
  • analog-to-digital converters In signal processing systems such as communication systems and radar systems, analog-to-digital converters have become an indispensable component. Commonly used analog-to-digital converters have medium- and low-precision ultra-high-speed flash and Folding-Interpolating structures; high-precision low- and medium-speed ⁇ - ⁇ and successive approximation (SAR) structures.
  • SAR successive approximation
  • the above-mentioned analog-to-digital converter structure mainly focuses on medium and low precision ultra high speed requirements and high precision medium and low speed requirements, and is difficult to be compatible with high speed and high precision application environments.
  • the pipelined analog-to-digital converter adopts a pipelined operation mode to quantize the single sample and hold result of the input signal step by step, and obtains the complete quantization result after the complete pipeline level quantization, thereby improving the conversion speed of the pipelined analog-to-digital converter;
  • the presence of the amplifier reduces the requirements of the comparator in the downstream pipeline and improves the conversion accuracy that the pipeline analog-to-digital converter can achieve, so that the pipelined analog-to-digital converter can achieve not only high-speed, ultra-high-speed converter speeds of 100 megahertz or even GHz. And can achieve 16-bit conversion accuracy requirements.
  • the traditional pipelined analog-to-digital converter has the following three limitations: the coarse quantization accuracy of each pipeline is limited by the gain bandwidth of the residual amplifier and the number of comparators in the sub-analog converter (Sub ADC), which can only be increased by increasing the number of pipeline stages.
  • Sub ADC sub-analog converter
  • input signal sample-and-hold capacitors are time-multiplexed into sub-amplifiers (MDAC) neutron digital-to-analog converters (Sub DAC) capacitors, resulting in various stages of analog-to-digital converter sample-and-hold process and margin signal amplification
  • MDAC sub-amplifiers
  • Sub DAC neutron digital-to-analog converters
  • the clock phase of the setup process is mutually exclusive, that is, when the sample is held in phase, the residual amplifier circuit stops working; when the margin is amplified, the sample and hold network stops working, which seriously limits the conversion efficiency of the pipeline analog-to-digital converter; the traditional pipelined analog-to-digital converter
  • the feedback factor of the negative feedback amplifying circuit of each level is limited by the coarse quantization precision of each stage pipeline, which severely limits the design flexibility of the amplifier.
  • the popular methods for improving pipeline conversion accuracy and speed mainly include successive approximation pipelined analog-to-digital converter structure and multi-channel time-interleaved analog-to
  • the present invention provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, comprising:
  • each stage of the pipeline structure unit is used to quantize the input signal
  • a first flash analog-to-digital converter for quantizing a margin signal output by the final pipeline structure unit, and outputting a corresponding quantized value
  • Adjusting an output unit configured to combine respective quantized values according to a connection order of the multi-stage pipeline structure unit and the flash analog-to-digital conversion unit, and output a complete quantization result
  • each stage of the pipeline structure unit includes at least a sub-analog converter for sampling and holding an input signal, and the pre-comparison sub-unit for performing an input signal with a corresponding reference voltage. Comparing, outputting the highest-order quantized value of the current stage and controlling the switching state of the reference level selection switch in the sub-analog converter according to the highest-order quantized value, the sub-analog-to-digital converter is further configured to use the highest-order quantized value and the reference The level of the switching state coarsely quantizes the sampled input signal to output a corresponding quantized value.
  • the pre-comparison sub-unit includes a comparator, a pre-compare switch, a reference voltage, and a reference level selector, and the forward input terminal of the comparator is connected to the input signal through a pre-comparison switch.
  • the negative input terminal of the comparator is connected to the reference voltage, and the output of the comparator is respectively connected to the reference level selector and the sub-analog converter, and latches and outputs the highest-order quantized value under the control of the clock signal ⁇ sp
  • the reference level selector controls the switching state of the reference level selection switch in the sub-analog converter according to the highest bit quantization value.
  • the sub-analog converter includes a plurality of one-bit quantization modules and an encoding module, and the output ends of the plurality of quantization modules are sequentially connected to an input end of the encoding module, according to the pre- Comparing the highest bit quantized value of the subunit, the coded mode outputs a corresponding quantized value.
  • each of the quantization modules includes a first sampling switch, a second fast analog-to-digital converter, a first reference level generator, and first and second reference level selection switches.
  • One end of the first sampling switch is connected to the input signal, and the other end is connected to the input end of the second flash analog-to-digital converter, and one ends of the first and second reference level selection switches are respectively connected to the second flash mode.
  • the other input end of the digital converter, the other ends of the first and second reference level selection switches are respectively connected to the output end of the first reference level generator to output a corresponding reference level, under the control of the clock signal ⁇ c
  • the output of the second flash analog-to-digital converter outputs a corresponding quantized value.
  • each stage of the pipeline structure unit further includes a acquisition and digital model subunit, a residual signal negative feedback amplification subunit, and the acquisition and digital mode subunit is used for sampling and maintaining an input signal, and For outputting a matched level value according to a quantized value of the sub-analog converter of the stage, the residual signal negative feedback amplifying sub-unit is configured to compare the level value The charge should be redistributed to the output margin signal.
  • the acquisition and digital mode subunit includes a second sampling switch, a second sampling capacitor, a second lower plate sampling switch and a second reference level generator, and the second sampling switch One end is connected to the input signal, and the other end is connected to the second sampling capacitor.
  • the output of the second reference level generator is connected between the lower board and the second sampling switch of the second sampling capacitor, and the second reference level occurs.
  • the controller generates a reference voltage according to the current quantized value of the sub-analog converter under the control of the clock signal ⁇ qs , and the upper board of the second sampling capacitor is connected with the grounded second lower-stage sampling switch.
  • the margin signal negative feedback amplification subunit includes a residual amplifier input signal switch, a residual signal amplification switch, a first reset switch, a residual amplifier input signal holding capacitor, a negative feedback capacitor, a second reset switch and a residual amplifier, wherein one end of the margin signal generating switch is connected to the output end of the acquisition and digital mode subunit, and the other end thereof is respectively connected to the negative input terminal of the residual amplifier, the first reset switch, and the margin a signal amplification switch, a residual amplifier input signal holding one end of the capacitor, the residual amplifier input signal holding capacitor, and the other end of the first reset switch are grounded; the positive input terminal of the residual amplifier is grounded, the margin The output end of the amplifier outputs a residual signal, and the output end of the residual amplifier is fed back to the other end of the residual signal amplifying switch through a negative feedback capacitor, and one end of the second reset switch is connected to the remaining signal of the output, and the other end thereof Ground.
  • the sample-and-hold process of the sub-analog converter, the acquisition and the digital-module sub-unit in each stage of the pipeline structure unit is synchronized with the remaining signal amplification process of the negative feedback amplification sub-unit of the residual signal And run independently.
  • the sub-analog converter and the sampling network in the acquisition and digital mode sub-units are scaled, and the sampling network has the same time constant.
  • the number of bits of the quantization precision of the first flash analog-to-digital converter is the same as the number of bits of the quantization precision of each of the pipeline structure units.
  • the pipelined analog-to-digital converter of the present invention having input signal pre-comparison and charge redistribution has the following
  • the residual amplifier input signal holding capacitor C c lower plate is always connected to the reference ground, and has the same effect as the ground parasitic capacitance of the residual amplifier input node, therefore, the charge redistribution technique adopted by the present invention It is also possible to use the parasitic capacitance of the input amplifier of the residual amplifier as a system signal processing effective capacitor to eliminate the influence of the parasitic capacitance of the portion;
  • FIG. 1 is a block diagram showing the structure of a pipelined analog-to-digital converter with input signal pre-comparison and charge redistribution according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing the structure of each stage pipeline structure unit in the pipelined analog-to-digital converter of FIG. 1 according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram of a pipelined analog-to-digital converter with 12-bit conversion accuracy of input signal pre-comparison and charge redistribution according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram showing the pipelined coarse quantized reference voltages of the pipelined analog-to-digital converters implementing the 12-bit conversion precision in FIG. 3;
  • FIG. 5 is a timing diagram of a pipelined analog-to-digital converter that implements 12-bit conversion accuracy using a pipelined analog-to-digital converter with input signal pre-comparison and charge redistribution in accordance with an embodiment of the present invention.
  • the present invention provides a structural block diagram of a pipelined analog-to-digital converter with input signal pre-comparison and charge redistribution, which is provided by an embodiment of the present invention, including:
  • a first flash analog-to-digital converter 2 configured to quantize a residual signal output by the final pipeline structure unit, and output a corresponding quantized value
  • the output unit 3 is configured to combine the respective quantized values according to the connection order of the multi-stage pipeline structure unit and the flash analog-to-digital conversion unit, and output the complete quantization result;
  • the multi-stage pipeline structure unit 1 is included in the present application, and the pipeline structure unit 1 in FIG. 1 is only a representative of a plurality, and each stage pipeline structure unit 1 includes at least a sub-analog converter 12 and a pre-comp. sub-unit 11,
  • the sub-analog converter 12 is configured to sample and hold an input signal
  • the pre-comparison sub-unit 11 is configured to compare the input signal with a corresponding reference voltage, output a highest-order quantized value of the current level, and according to the highest-order quantized value.
  • the sub-analog converter 12 is further configured to perform coarse-scale output corresponding to the sampled input signal according to the highest bit quantization value and the switching state of the reference level Quantitative value.
  • the reference voltage connected by the pre-comparison sub-unit 11 is determined according to the number of bits of conversion precision of each stage of the pipeline structure unit (ie, the sub-analog-to-digital converter 12), wherein the reference voltage is preferably The intermediate values of the reference voltages, such as: V ref0 , V ref1 ... V refn-1 , when the accuracy of the sub-analog converter 12 is N bits, it corresponds to 2 N reference voltages, that is, the intermediate value is 2 N- 1 corresponding reference voltage.
  • the invention is applied to the field of integrated circuits, in particular to the field of high-precision high-speed low-power analog-digital converter design, adopting a pipeline structure as a whole, adopting a pre-comparison technique for input signals, and obtaining the highest position of each pipeline structure unit by using a pre-comparison unit.
  • the coarse quantization reduces the number of comparators of the sub-analog converters in each pipeline structure unit, so that the number thereof is reduced by half, which greatly saves power consumption and reduces cost.
  • the number of bits of the quantization precision of the first flash analog-to-digital converter 2 and the number of bits of the quantization precision of each of the pipeline structure units 1 may be different, and the first flash analog-to-digital converter 2 In analog-to-digital conversion, it does not output the corresponding margin signal, and only needs to coarsely quantize the signal connected to its input.
  • the pre-comparison sub-unit 11 includes a comparator, a pre-compare switch, a reference voltage, and a reference level selector, and the forward input terminal of the comparator is connected to the input signal through a pre-comparison switch.
  • the negative input terminal of the comparator is connected to the reference voltage, and the output of the comparator is respectively connected to the reference level selector and the sub-analog converter, and latches and outputs the highest-order quantized value under the control of the clock signal ⁇ sp
  • the reference level selector controls the switching state of the reference level selection switch in the sub-analog converter according to the highest bit quantization value.
  • the reference level selector outputs a level switch control signal to control a switching state thereof according to a specific value of the highest bit quantization value
  • the sub-analog converter has a plurality of One or two reference level selection switches, when the highest bit quantization value is high level, the first level switch is in the closed state, the second level switch is in the off state; the highest level quantization value is the low level, the first level The switch is in an off state, and the second level switch is in a closed state; that is, controlling a switching state of an internal reference level selection switch in the sub-analog converter, and in addition, the reference voltage in the pre-comparison sub-unit 11 is generally first The intermediate value of the reference level generator output.
  • the sub-analog-to-digital converter 12 includes a plurality of one-bit quantization modules and coding modules, and the outputs of the plurality of quantization modules are sequentially connected to the input ends of the coding modules, and the highest of the pre-comparison sub-units Under the bit quantized value input, the output of the encoding module is connected to the input of the adjustment output unit for outputting the multi-bit coarse quantized value of each stage of the pipeline structure unit.
  • the conversion precision of the sub-analog-to-digital converter 12 is n bits, and corresponding to 2 n-1 -1 quantization modules, n is a natural number greater than or equal to 1, and each quantization module follows the slave. High to low or low to high connected to the input end of the coding module, the coarse bit quantization is performed according to the connection order; in addition, the acquisition and hold circuit is integrated in each quantization module, which will not be repeated here.
  • each of the quantization modules includes a first sampling network, a second flash analog-to-digital converter, a first reference level generator, and first and second reference level selection switches, the first sampling network One end is connected to the input signal, and the other end is connected to the input end of the second flash analog-to-digital converter, and one ends of the first and second reference level selection switches are respectively connected to the second flash analog-to-digital converter and the first Between the sampling networks, the other ends of the first and second reference level selection switches are respectively connected to the output end of the first reference level generator to output a corresponding reference level, and the second flash analog-to-digital converter is another The input terminal is grounded, and the output of the second flash analog-to-digital converter outputs corresponding quantization under the control of the clock signal ⁇ c .
  • the first sampling switch, the first sampling capacitor, and the first lower-level sampling switch constitute a first sampling network
  • the combination of the first sampling network and the comparator (equivalent to) the second flash mode a digital converter one end of the first sampling switch is connected to the input signal, and the other end is connected to the upper board of the first sampling capacitor, and the lower board of the first sampling capacitor is respectively connected to the forward input end of the comparator, the first lower One end of the stage sampling switch, and the other end of the first lower stage sampling switch is grounded, the negative input end of the comparator is grounded, and one ends of the first and second reference level selection switches are respectively connected to the first sampling
  • the other end of the switch is connected to the output of the reference level generator to output a corresponding reference level, and the sampled value of the first sampling network and the reference level of the first reference level generator are output.
  • the difference between the difference is compared with the negative input of the comparator, and the output of the comparator outputs a corresponding quantized value under the
  • the first sampling switch, the first sampling capacitor and the first lower-level sampling switch constitute an acquisition and holding circuit, that is, a first sampling network, the first sampling network and the acquisition and digital sub-unit
  • the mid-sampling network is scaled, and the two sampling networks have the same time constant, which prevents distortion of the sampling network due to mismatch of time constants.
  • Each bit quantization module corresponds to a connected reference level generator according to its arrangement positional relationship in the sub-analog converter, and the output end of the first reference level generator outputs an appropriate reference level V ref0 , V ref1 ...
  • N is the number of conversion precision bits of the sub-analog converter
  • N is at least one bit, that is, in the initial order of the reference level V ref1 , Arranging one by one, from high to low or from low to high, wherein the first and second reference level selection switches respectively connect two reference voltages with a difference of 2 N-1 , according to the output of the pre-comparison subunit
  • the highest bit quantization value is high level or low level control.
  • One of the first and second reference level selection switches is in the off state and the other is in the closed state (not repeated here), and the closed reference level and the second selection are selected.
  • the input end of the flash analog-to-digital converter is connected, the clock signal ⁇ c is connected to the control input end of the second flash analog-to-digital converter Flash ADC, and one end of the first sampling switch S sc is connected to the input signal, and the other One end is connected to an input end of a second flash analog-to-digital converter Flash ADC, and the flash analog-to-digital converter Flash ADC output quantized value is connected to the input end of the encoding module, and the input end of the encoding module is further The output of the comparator in the comparison subunit is connected, and the output of the coding module is connected to the input of the output alignment unit.
  • each stage of the pipeline structure unit further includes a mining and digital module sub-unit 13 (production and digital-to-analog converter), a residual signal negative feedback amplification sub-unit 14, and the acquisition and digital-module sub-unit 13 is used for
  • the sample-and-hold input signal is further configured to output a matched level value according to the quantized value of the sub-analog converter of the stage
  • the residual signal negative feedback amplifying sub-unit 14 is configured to perform the charge corresponding to the level value Redistribute the output margin signal.
  • the acquisition and digital mode sub-unit 13, the residual signal negative feedback amplification sub-unit 14 utilizes charge redistribution.
  • the technology uses two sets of sampling capacitors to simultaneously perform input signal sampling and residual signal generation and amplification processes, so that the respective capacitors of the signal sampling and the residual signal amplification process are independent of each other at the same time, realizing signal sampling and maintaining and remaining signal amplification.
  • the purpose of the pipeline is to greatly improve the conversion rate of the pipeline analog-to-digital converter.
  • the acquisition and digital mode sub-unit 13 includes a second sampling switch, a second sampling capacitor, a second lower-level sampling switch, and a second reference level generator, and one end of the second sampling switch is connected to the input signal. The other end is connected to the second sampling capacitor, and the output of the second reference level generator is connected between the lower plate of the second sampling capacitor and the second sampling switch, and the second reference level generator is at the clock signal ⁇
  • a reference voltage is generated according to the current quantized value of the sub-analog converter, and the upper board of the second sampling capacitor is connected with a grounded second lower-stage sampling switch.
  • the margin signal negative feedback amplifying subunit 14 includes a residual amplifier input signal switch, a residual signal amplifying switch, a first reset switch, a residual amplifier input signal holding capacitor, a negative feedback capacitor, a second reset switch, and a residual amplifier, one end of the margin signal generating switch is connected to the output end of the acquisition and digital mode subunit, and the other end is connected to the negative input end of the residual amplifier, the first reset switch, the residual signal amplifying switch, and the remaining
  • the amplifier input signal holds one end of the capacitor, the residual amplifier input signal holding capacitor, and the other end of the first reset switch are grounded; the forward input terminal of the margin amplifier is grounded, and the output of the margin amplifier is output The remaining signal, the output of the residual amplifier is fed back to the other end of the second reset switch through a negative feedback capacitor, one end of the second reset switch is connected to the remaining signal of the output, and the other end is grounded.
  • the residual amplifier input signal is grounded through the residual amplifier input signal holding capacitor C c lower-level board, and has the same effect as the ground-parasitic capacitance of the input node of the residual amplifier, and the charge redistribution technology can also
  • the parasitic capacitance of the residual amplifier input node is used as an effective capacitor for system signal processing to eliminate the influence of this part of parasitic capacitance.
  • the acquisition and digital mode sub-unit outputs an appropriate reference level according to the coarse quantization result, and the corresponding charge is distributed to the remaining charge by the charge redistribution principle.
  • the residual amplifier input signal holding capacitor C c is separated, so that the acquisition and digital mode sub-unit and the residual signal negative feedback amplification sub-unit are independent of each other, that is, the sample-and-hold capacitor and the residual amplification circuit are independent, and the sampling and holding and the margin amplification are realized.
  • the process is synchronized to increase the conversion rate of the analog to digital converter.
  • the size of the negative feedback factor can be changed by selecting the appropriate level of the second sampling capacitor C s of the pipeline and the capacitance of the residual amplifier input signal holding capacitor C c to facilitate flexible design of the residual amplifier.
  • FIG. 3 a circuit diagram of a pipelined analog-to-digital converter with 12-bit conversion precision of input signal pre-comparison and charge redistribution according to an embodiment of the present invention is described in detail as follows:
  • the analog-to-digital converter comprises a 3-stage 3-bit coarse quantization precision pipeline structure unit Stage1, Stage2 and Stage3, a 3-level 3-bit coarse quantization precision flash analog-to-digital converter 3-bit Flash ADC and an output alignment unit (OutPut Aligning)
  • the pipeline structure includes a recovery and digital-to-analog converter SH&DAC, a pre-comparison circuit Pre-Comp, a sub-analog converter Sub ADC, a second lower-plate sampling switch S sp , and a residual amplifier input signal.
  • the switch S qs the residual amplifier input signal holding capacitor C c , the residual amplifier reset switch S rs1 , the residual amplifier reset switch S rs2 , the residual signal amplification switch S a , the negative feedback capacitor C f and the residual amplifier AMP;
  • the acquisition and digital-to-analog converter SH&DAC includes a second sampling switch S s , a second sampling capacitor C s and a second reference level generator DAC Reference Generator;
  • the input signal pre-comparing circuit Pre-Comp includes a connection input signal comparison of the pre-switch S pc, comparator COMPp, the reference voltage V ref4 and the sub-ADC reference level selector sub ADC reference selector;
  • sub ADC the analog to digital converter comprises a first sub-sampling Off S sc, a first sampling capacitor C sc, the first lower plate sampling switch S spc, Sub ADC reference level V ref1, V ref2, V ref3 , V ref4, And V ref7 by the reference level generator, Sub ADC
  • the SH&DAC is composed of a second sampling switch S s , a second sampling capacitor C s and a second lower plate sampling switch S sp .
  • the sampling network and the Sub ADC are composed of a first sampling switch S sc , a first sampling capacitor C sc and a The sampling network consisting of the lower plate sampling switch S spc must be scaled to ensure that the two sampling networks have the same time constant.
  • FIG. 4 a schematic diagram of a pipelined coarse-quantized reference voltage of a pipelined analog-to-digital converter with 12-bit conversion precision based on a pipeline analog-to-digital converter technology based on input signal pre-comparison and charge redistribution is used in the embodiment of the present invention. It is used to describe the reference voltage amplitude relationship in the input signal comparison circuit Pre-Comp and the sub-analog converter Sub ADC, where V dd represents the power supply and the inverted triangle symbol represents the reference ground.
  • the first stage as shown As shown, when the clock signals ⁇ s and ⁇ sp are at a high level, the analog-to-digital converter first stage pipeline Stage1 is as shown in FIG. 3, the first sampling switch S sc , the second sampling switch S s , the first The lower plate sampling switch S spc , the second lower plate sampling switch S sp , and the pre-comparison switch S pc of the input signal are all in an on state, the acquisition and digital-to-analog converter (SH & DAC) and the sub- The analog-to-digital converter (Sub ADC) enters the sampling phase, and the pre-comparison circuit (Pre-Comp) enters the pre-comparison phase.
  • SH & DAC acquisition and digital-to-analog converter
  • Pre-Comp pre-comparison circuit
  • the second stage as shown Shown, when the falling edge of the clock signal ⁇ sp, the first sampling switch S sc, second sampling switch S s is turned on continues, the first sampling switch S SPC lower plate, the lower plate of the second sampling switch S sp is in an off state, the second sampling capacitor C s of the acquisition and digital-to-analog converter (SH & DAC) and the first sampling capacitor C sc of the sub-analog converter (Sub ADC) maintain the input at the moment
  • the sub-analog converter reference level selector (Sub ADC Reference Selector) in the pre-compare circuit (Pre-Comp) refers to the reference power of the sub-analog converter (Sub ADC) according to the latch result of the comparator COMPp.
  • the level selection switch S c is turned on, the sub-analog converter (Sub ADC) is turned off with reference to the level selection switch S c ', and the Sub ADC selects the reference levels V ref1 , V ref2 as shown in FIG. 4 .
  • V ref3 for the present two-stage pipeline coarse quantization; if the input signal V in (0) lower than the reference level V ref4, the comparator output is low COMPp, the sub-ADC (sub ADC) reference
  • the level selection switch S c is turned off, the sub-analog converter (Sub ADC) is turned on by the level selection switch S c ', and the sub-analog converter (Sub ADC) is selected as shown in FIG. level And V ref7 performs the two-level coarse quantization after the pipeline of this stage.
  • the third stage as shown As shown, when the clock signals ⁇ c and ⁇ a are high, the residual amplifier reset switch S rs1 , the residual amplifier reset switch S rs2 , and the residual signal amplification switch S a are turned on, and the residual amplifier AMP enters the reset phase.
  • the fourth stage as shown As shown, when the clock signal ⁇ qs is high, the residual amplifier input signal switch S qs is turned on, and the second reference level generator (DAC Reference Generator) in the acquisition and digital-to-analog converter (SH & DAC) Generate an appropriate DAC reference level V DAC according to the 3-bit full coarse quantization result B 2 B 1 B 0 of the stage pipeline, so that the second sampling capacitor C s and the residual amplifier in the acquisition and digital-to-analog converter (SH&DAC) The upper plate connected to the input signal holding capacitor C c generates a residual amplifier input signal V A .
  • DAC Reference Generator DAC Reference Generator
  • the sample and hold and digital to analog converter (SH & DAC) a second sampling capacitor C s and the amplifier input signal to maintain the overall balance the charge on the plates of the capacitor C c connected in the residue amplifier
  • the fifth stage as shown As shown, when the clock signals ⁇ a , ⁇ s and ⁇ sp are at a high level and the remaining clock signals are at a low level, the remaining amplifier input signal switch S qs is turned off, and the remaining signal amplifying switch S a is turned on,
  • the desired input signal amplification factor and residual signal output amplitude range can be obtained by designing the appropriate negative feedback capacitance Cf capacitance value and the DAC reference level V DAC .
  • the negative feedback capacitance value C f (C c C s ) / (8 ⁇ (C c + C s )) is designed, and the DAC reference power level
  • ⁇ represents a multiplication sign
  • V ref represents an analog-to-digital converter output amplitude
  • the variable i outputs a result B 2 B 1 B 0 from ( ⁇ 1, ⁇ 3, according to the stage of the pipeline coarse quantization precision. Choose within ⁇ 7).
  • the acquisition and digital-to-analog converter (SH&DAC) and the sub-analog-to-digital converter (Sub ADC) of the first-stage pipeline enter the sampling process of the first stage again, and the sampling input signal V in(1) is tracked .
  • the pre-compare circuit (Pre-Comp) again enters the input signal pre-comparison process of the first stage described above.
  • the second stage pipeline stage 2 's acquisition and digital-to-analog converter (SH&DAC) and sub-analog-to-digital converter (Sub ADC) enter the sampling process of the first stage in the above, and track the margin of the first stage pipeline Stage1
  • the output signal V R1 is amplified, and the pre-comparison circuit (Pre-Comp) enters the input signal pre-comparison process of the first stage in the above.
  • Pre-Comp pre-comparison circuit
  • the sixth stage as shown As shown, when the falling edge of the clock signal ⁇ sp comes, the first stage pipeline Stage1 enters the second stage of the above, and the coarsening process of the output signal V in(1) is performed.
  • the second stage pipeline Stage2 sampling and pre-comparison process ends, entering the second stage of the above, and further quantizing the input signal V in(0) due to the coarse-quantized residual signal V R1 of the first stage Stage1.
  • each pipeline structure unit is the same as the first stage to the fifth stage of the first pipeline stage Stage1.
  • the last stage of the 3-bit Flash ADC does not generate a margin output signal, only need
  • the remaining amount of the output signal V R3 of the third stage pipeline stage 3 may be coarsely quantized.
  • the output aligning unit OutPut Aligning Aligns and outputs the coarse quantized results of the pipelines to obtain a complete signal quantized output result.
  • a 12-bit conversion precision pipelined analog-to-digital converter realized by a pipeline analog-to-digital converter technology with input signal pre-comparison and charge redistribution is adopted, and the precision of each stage pipeline coarse quantization is 3 bits.
  • the embodiment explains that a pipeline analog-to-digital converter with multi-bit conversion accuracy and input signal pre-comparison and charge redistribution can be performed as needed, and the multi-bit conversion precision pipeline analog-to-digital converter is split into the above embodiment.
  • the multi-stage flow structure unit and the output alignment unit can be realized, and will not be described herein.
  • the present invention combines the highest bit coarse quantization process of each pipeline of the pipeline analog-to-digital converter with the sample-and-hold process, and increases the number of comparators in the sub-analog converter.
  • the quantization accuracy is 1 bit, which can reduce the number of pipelined analog-to-digital converter stages and reduce the overall power consumption under the same conversion accuracy.

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Abstract

一种具有输入信号预比较与电荷重分配的流水线模数转换器，包括：一或多级流水线结构单元（1），其中，每级流水线结构单元（1）用于对输入信号进行量化；第一快闪模数转换器（2），用于对末级流水线结构单元输出的余量信号进行量化，输出对应的量化值；调整输出单元（3），用于按照连接顺序组合各个量化值，输出完整的量化结果。输入信号采用预比较和电荷重分配技术，使用流水线结构进行整体设计，利用输入信号预比较技术进行各级流水线最高位粗量化，降低各级流水线子模数转换器的比较器个数，实现低功耗设计；利用电荷重分配技术，将采样电容与负反馈放大电路中的各个电容分离，实现信号采样保持与余量信号放大建立同时进行，提高了转换速率。

Description

具有输入信号预比较与电荷重分配的流水线模数转换器 技术领域
本发明涉及集成电路领域，特别涉及高精度超高速低功耗模数转换器设计技术领域，更具体地来说涉及一种具有输入信号预比较与电荷重分配的流水线模数转换器。
背景技术
在通信系统、雷达系统等信号处理系统中，模数转换器已经成为不可缺少的组成部分。常用的模数转换器结构有中低精度超高速的快闪(Flash)和折叠内插(Folding-Interpolating)结构；高精度中低速的∑-Δ和逐次逼近型(SAR)结构。上述模数转换器结构主要专注于中低精度超高速要求和高精度中低速要求，很难兼容高速高精度的应用环境。流水线模数转换器采用流水线工作模式，将输入信号的单次采样保持结果进行逐级量化，经过完整流水线级量化后得到完整的量化结果，提高流水线模数转换器的转换速度；由于级间余量放大器的存在，降低后级流水线对比较器的要求，提高流水线模数转换器能够达到的转换精度，使得流水线模数转换器不仅能够实现百兆赫兹甚至吉赫兹的高速、超高速转换器速率，而且能够达到16位的转换精度要求。
传统流水线模数转换器主要有以下三方面限制：各级流水线粗量化精度受到余量放大器增益带宽和子模数转换器(Sub ADC)中比较器个数的限制，只能通过增加流水线级数来实现高精度转换要求；输入信号采样保持电容分时复用为余量放大电路(MDAC)中子数模转换器(Sub DAC)电容，造成各级模数转换器采样保持过程与余量信号放大建立过程的时钟相位互斥，即：采样保持相位时，余量放大电路停止工作；余量放大相位时，采样保持网络停止工作，严重限制流水线模数转换器转换效率；传统流水线模数转换器各级负反馈放大电路反馈因子受限于各级流水线粗量化精度，严重限制了放大器的设计灵活性。目前比较流行的提高流水线转换精度和速度的方法主要有逐次逼近型流水线模数转换器结构和多路时间交织模数转换器结构。
逐次逼近型流水线模数转换器结构由于子模数转换器采用逐次逼近型模数转换器作为流水线模数转换器的子模数转换器，其串行转换过程严重限制了该结构的转换速率的提高；多路时间交织模数转换器结构虽然能够非常高效的提高转换速率，但是其时钟抖动和通道间失配问题严重限制着其应用，而且其功耗随着通道数的增加而增加，非常不利于低功耗设计。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种具有输入信号预比较与电荷 重分配的流水线模数转换器，用于解决现有技术中流水线模数转换器功耗高的问题。
为实现上述目的及其他相关目的，本发明提供一种具有输入信号预比较与电荷重分配的流水线模数转换器，包括：
一或多级流水线结构单元，其中，每级流水线结构单元用于对输入信号进行量化；
第一快闪模数转换器，用于对末级流水线结构单元输出的余量信号进行量化，输出对应的量化值；
调整输出单元，用于根据多级流水线结构单元与快闪模数转单元的连接顺序组合各个量化值，输出完整的量化结果；
其中，每级流水线结构单元至少包括子模数转换器和预比较子单元，所述子模数转换器用于采样保持输入信号，所述预比较子单元用于将输入信号与相应的参考电压进行比较，输出本级的最高位量化值并根据该最高位量化值控制子模数转换器中参考电平选择开关的开关状态，所述子模数转换器还用于根据最高位量化值以及参考电平的开关状态将采样的输入信号进行粗量化输出对应的量化值。
于本发明的一实施例中，所述预比较子单元包括比较器、预比较开关、参考电压和参考电平选择器，所述比较器的正向输入端通过预比较开关连接输入信号，所述比较器的负向输入端连接参考电压，所述比较器的输出端分别连接参考电平选择器、子模数转换器，且在时钟信号Φsp的控制下锁存并输出最高位量化值，所述参考电平选择器根据最高位量化值控制子模数转换器内参考电平选择开关的开关状态。
于本发明的一实施例中，所述子模数转换器包括多个一位的量化模块与编码模块，多个所述量化模块的输出端依次连接到编码模块的输入端，根据所述预比较子单元的最高位量化值所述编码模输出对应的量化值。
于本发明的一实施例中，每一位所述量化模块均包含第一采样开关、第二快闪模数转换器、第一参考电平发生器和第一、二参考电平选择开关，所述第一采样开关的一端连接输入信号，其另一端连接第二快闪模数转换器的输入端，所述第一、二参考电平选择开关的一端分别连接所述第二快闪模数转换器的另一输入端，所述第一、二参考电平选择开关的另一端分别连接第一参考电平发生器的输出端输出对应的参考电平，在时钟信号Φc的控制下第二快闪模数转换器的输出端输出对应的量化值。
于本发明的一实施例中，所述每级流水线结构单元还包括采保和数模子单元、余量信号负反馈放大子单元，所述采保和数模子单元用于采样保持输入信号，还用于根据子模数转换器本级的量化值输出匹配的电平值，所述余量信号负反馈放大子单元用于将所述电平值所对 应的电荷进行重分配输出余量信号。
于本发明的一实施例中，所述采保和数模子单元包括第二采样开关、第二采样电容、第二下级板采样开关与第二参考电平发生器，所述第二采样开关的一端连接输入信号，其另一端连接第二采样电容，所述第二采样电容的下级板与第二采样开关之间连接第二参考电平发生器的输出端，所述第二参考电平发生器在时钟信号Φqs的控制下根据子模数转换器当前的量化值生成参考电压，所述第二采样电容的上级板连接有接地的第二下级板采样开关。
于本发明的一实施例中，所述余量信号负反馈放大子单元包括余量放大器输入信号开关、余量信号放大开关、第一复位开关、余量放大器输入信号保持电容、负反馈电容、第二复位开关和余量放大器，所述余量信号产生开关的一端连接采保和数模子单元的输出端，其另一端分别连接余量放大器的负向输入端、第一复位开关、余量信号放大开关、余量放大器输入信号保持电容的一端，所述余量放大器输入信号保持电容、第一复位开关的另一端均接地；所述余量放大器的正向输入端接地，所述余量放大器的输出端输出余量信号，所述余量放大器的输出端通过负反馈电容反馈至余量信号放大开关的另一端，所述第二复位开关的一端连接输出的余量信号，其另一端接地。
于本发明的一实施例中，所述每级流水线结构单元内的子模数转换器、采保和数模子单元的采样保持过程与余量信号负反馈放大子单元的余量信号放大过程同步且独立运行。
于本发明的一实施例中，所述每级流水线结构单元中第二采样电容Cs、余量放大器输入信号保持电容Cc与负反馈电容Cf的关系为：Cf＝(Cs·Cc)/(Acloseloop·(Cs+Cc)，其中，Acloseloop表示余量放大电路闭环放大倍数，余量信号负反馈放大电路的反馈因子为(Cf(Cs+Cc))/(CsCc)，选择第二采样电容Cs和余量放大器输入信号保持电容Cc的尺寸用于控制负反馈因子大小。
于本发明的一实施例中，所述子模数转换器和采保和数模子单元中采样网络按比例缩放，且该采样网络具有相同的时间常数。
于本发明的一实施例中，所述第一快闪模数转换器的量化精度的位数与各级流水线结构单元的量化精度的位数相同。
如上所述，本发明的具有输入信号预比较与电荷重分配的流水线模数转换器，具有以下
有益效果：
第一，将所述流水线模数转换器的各级流水线的最高位粗量化过程与采样保持过程相结合，在子模数转换器中比较器的个数相同的情况下，增加量化精度1位，在相同转换精度下，能够减少流水线模数转换器级数，降低整体功耗；
第二，根据各级流水线模数转换器粗量化结果，建立合适的参考电平，利用电容重分配 原理将余量放大器输入信号保持于余量放大器输入信号保持电容Cc上，余量放大器输入信号建立完成后，断开第二采样电容Cs与余量放大器输入信号保持电容Cc的连接关系，此时，第二采样电容Cs与余量放大器输入信号保持电容Cc分离，从而使得采样保持电路与余量放大电路独立，实现采样保持与余量放大过程同步进行，提高模数转换器转换速率；
第三，所述余量放大器输入信号保持电容Cc下极板始终与参考地连接，与余量放大器输入节点的对地寄生电容作用效果相同，因此，本技术发明所采用的电荷重分配技术还能够将余量放大器输入节点寄生电容作为系统信号处理有效电容使用，消除该部分寄生电容影响；
第四，所述各级流水线第二采样电容Cs、余量放大器输入信号保持电容Cc与余量放大电路负反馈电容Cf的关系为：Cf＝(Cs·Cc)/(Acloseloop·(Cs+Cc))，其中Acloseloop表示余量放大电路闭环放大倍数；余量信号负反馈放大电路的反馈因子为：(Cf(Cs+Cc))/(CsCc)，选择合适的各级流水线采样电容Cs与余量放大器输入信号保持电容Cc的电容尺寸能够改变负反馈因子，便于余量放大器灵活设计。
附图说明
图1显示为本发明实施例提供的一种具有输入信号预比较与电荷重分配的流水线模数转换器结构框图；
图2显示为本发明实施例提供的图1中流水线模数转换器中每级流水线结构单元的结构框图；
图3显示为本发明实施例提供的具有输入信号预比较与电荷重分配的12位转换精度的流水线模数转换器电路图；
图4显示为图3中实现12位转换精度的流水线模数转换器各级流水线粗量化参考电压示意图；
图5显示为本发明实施例利用具有输入信号预比较与电荷重分配的流水线模数转换器实现12位转换精度的流水线模数转换器的时序图。
元件标号说明：
1   流水线结构单元
2   第一快闪模数转换器
3   调整输出单元
11  预比较子单元
12  子模数转换器
13  采保和数模子单元
14  余量信号负反馈放大子单元
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参阅图1，本发明提供一种显示为本发明实施例提供的一种具有输入信号预比较与电荷重分配的流水线模数转换器结构框图，包括：
一或多级流水线结构单元1，其中，每级流水线结构单元1用于对输入信号进行量化；
第一快闪模数转换器2，用于对末级流水线结构单元输出的余量信号进行量化，输出对应的量化值；
调整输出单元3，用于根据多级流水线结构单元与快闪模数转单元的连接顺序组合各个量化值，输出完整的量化结果；
其中，本申请中包含多级流水线结构单元1，图1中的流水结构单元1只是多个中的代表，且每级流水线结构单元1至少包括子模数转换器12和预比较子单元11，所述子模数转换器12用于采样保持输入信号，所述预比较子单元11用于将输入信号与相应的参考电压进行比较，输出本级的最高位量化值并根据该最高位量化值控制子模数转换器中参考电平选择开关的开关状态，所述子模数转换器12还用于根据最高位量化值以及参考电平的开关状态将采样的输入信号进行粗量化输出对应的量化值。
在本发明实施例中，所述预比较子单元11连接的参考电压是根据每级流水线结构单位(即，子模数转换器12)转换精度的位数确定，其中，该参考电压优选为多个参考电压的中间值，如：Vref0、Vref1…Vrefn-1，当子模数转换器12的精度为N位时，其对应有2N个参考电压，即中间值为2N-1所对应的参考电压。本发明应用于集成电路领域，特别是高精度高速低 功耗模数转换器设计领域，整体采用流水线结构，针对输入信号采用预比较技术，通过利用预比较单元获取各级流水线结构单元的最高位粗量化，降低各级流水线结构单元中子模数转换器的比较器的数目，使得其数目减少一半，大大地节约了功耗，降低了成本。
在上述实施例中，所述第一快闪模数转换器2的量化精度的位数与各级流水线结构单元1的量化精度的位数可以不相同，且第一快闪模数转换器2在模数转换时，其不会输出相应的余量信号，只需对连接在其输入端的信号进行粗量化即可。
具体地，所述预比较子单元11(预比较电路)包括比较器、预比较开关、参考电压和参考电平选择器，所述比较器的正向输入端通过预比较开关连接输入信号，所述比较器的负向输入端连接参考电压，所述比较器的输出端分别连接参考电平选择器、子模数转换器，且在时钟信号Φsp的控制下锁存并输出最高位量化值，所述参考电平选择器根据最高位量化值控制子模数转换器内参考电平选择开关的开关状态。
在本实施例中，所述参考电平选择器根据最高位量化值的具体值，输出电平开关控制信号，控制它们的开关状态，其中，所述子模数转换器内设有多个第一、二参考电平选择开关，最高位量化值为高电平时，第一电平开关处于闭合状态，第二电平开关处于断开状态；最高位量化值为低电平时，第一电平开关处于断开状态，第二电平开关处闭合状态；即控制子模数转换器中内参考电平选择开关的开关状态，另外，所述预比较子单元11中的参考电压一般为第一参考电平发生器输出的中间值。
具体地，所述子模数转换器12包括多个一位的量化模块与编码模块，多个所述量化模块的输出端依次连接到编码模块的输入端，在所述预比较子单元的最高位量化值输入下，所述编码模块的输出端连接到调整输出单元的输入端，用于输出每级流水线结构单元的多位粗量化值。
在本实施例中，所述子模数转换器12的转换精度为n位，则其对应有2n-1-1个量化模块，n为大于等于1的自然数，同时，各个量化模块按照从高至低或从低至高连接于编码模块的输入端，按照连接顺序进行粗位量化；另外，每一位量化模块内还集成了采集与保持电路，在此不一一赘述。
具体地，每一位所述量化模块均包含第一采样网络、第二快闪模数转换器、第一参考电平发生器和第一、二参考电平选择开关，所述第一采样网络的一端连接输入信号，其另一端连接第二快闪模数转换器的输入端，所述第一、二参考电平选择开关的一端分别连接所述第二快闪模数转换器与第一采样网络之间，所述第一、二参考电平选择开关的另一端分别连接第一参考电平发生器的输出端输出对应的参考电平，所述第二快闪模数转换器另一输入端接 地，在时钟信号Φc的控制下第二快闪模数转换器的输出端输出对应的量化。
其中，本实施例中，第一采样开关、第一采样电容、第一下级板采样开关组成第一采样网络，通过将第一采样网络与比较器的组合(相当于)第二快闪模数转换器，所述第一采样开关的一端连接输入信号，其另一端连接第一采样电容的上级板，所述第一采样电容的下级板分别连接比较器的正向输入端、第一下级板采样开关的一端，且第一下级板采样开关的另一端接地，所述比较器的负向输入端接地，所述第一、二参考电平选择开关的一端分别连接于第一采样开关、第一采样电容之间，其另一端分别连接参考电平发生器的输出端输出对应的参考电平，将第一采样网络的采样值与第一参考电平发生器输出的参考电平之间差值与比较器的负向输入端进行比较，在时钟信号Φc的控制下比较器的输出端输出对应的量化值。
在本实施例中，所述第一采样开关、第一采样电容和第一下级板采样开关构成了采集与保持电路，即第一采样网络，该第一采样网络与采保和数模子单元中采样网络按比例缩放，且两种采样网络具有相同的时间常数，可防止采样网络因时间常数的失配带来的失真。每一位量化模块按照其在子模数转换器中的排列位置关系均对应有连接参考电平发生器，第一参考电平发生器的输出端输出合适的参考电平Vref0、Vref1…Vrefn-1，其中，n＝2N，根据每个量化模块的排列关系，每个量化模块中第一、二参考电平选择开关的一端分别连接两个序号相差2N-1的参考电压，其中，N为子模数转换器的转换精度位数，N至少为一位，即按参考电平的初始顺序Vref1、
Figure PCTCN2017101184-appb-000001
进行逐一排列，从高至低或从低至高的顺序依次进行排列，其中，第一、二参考电平选择开关分别连接两个序号相差2N-1的参考电压，根据预比较子单元输出的最高位量化值为高电平或低电平控制第一、二参考电平选择开关中一个处于断开另一个处于闭合状态(在此不一一赘述)，选择闭合的参考电平与第二快闪模数转换器的输入端连接，所述时钟信号Φc与第二快闪模数转换器Flash ADC的控制输入端连接，所述第一采样开关Ssc一端与输入信号连接，其另一端与第二快闪模数转换器Flash ADC的输入端连接，所述快闪模数转换器Flash ADC输出量化值与所述编码模块输入端连接，所述编码模块输入端还与所述预比较子单元中的所述比较器的输出端连接，所述编码模块输出端与所述输出对准单元输入端连接。
具体地，所述每级流水线结构单元还包括采保和数模子单元13(采保和数模转换器)、余量信号负反馈放大子单元14，所述采保和数模子单元13用于采样保持输入信号，还用于根据子模数转换器本级的量化值输出匹配的电平值，所述余量信号负反馈放大子单元14用于将所述电平值所对应的电荷进行重分配输出余量信号。
在本实施例中，采保和数模子单元13、余量信号负反馈放大子单元14利用电荷重分配 技术，采用两组采样电容同时分别进行输入信号采样和余量信号产生和放大过程，使得信号采样与余量信号放大建立过程的各个电容同一时刻相互独立，实现信号采样保持与余量信号放大建立同时进行的目的，极大的提高流水线模数转换器转换速率。
具体地，所述采保和数模子单元13包括第二采样开关、第二采样电容、第二下级板采样开关与第二参考电平发生器，所述第二采样开关的一端连接输入信号，其另一端连接第二采样电容，所述第二采样电容的下级板与第二采样开关之间连接第二参考电平发生器的输出端，所述第二参考电平发生器在时钟信号Φqs的控制下根据子模数转换器当前的量化值生成参考电压，所述第二采样电容的上级板连接有接地的第二下级板采样开关。
具体地，所述余量信号负反馈放大子单元14包括余量放大器输入信号开关、余量信号放大开关、第一复位开关、余量放大器输入信号保持电容、负反馈电容、第二复位开关和余量放大器，所述余量信号产生开关的一端连接采保和数模子单元的输出端，其另一端分别连接余量放大器的负向输入端、第一复位开关、余量信号放大开关、余量放大器输入信号保持电容的一端，所述余量放大器输入信号保持电容、第一复位开关的另一端均接地；所述余量放大器的正向输入端接地，所述余量放大器的输出端输出余量信号，所述余量放大器的输出端通过负反馈电容反馈至第二复位开关的另一端，所述第二复位开关的一端连接输出的余量信号，其另一端接地。
在本实施例中，所述余量放大器输入信号经过余量放大器输入信号保持电容Cc下级板接地，与余量放大器输入节点的对地寄生电容作用效果相同，同时，电荷重分配技术还能够将余量放大器输入节点寄生电容作为系统信号处理的有效电容使用，消除该部分寄生电容的影响。另外，当每级流水结构单元中子模数转换器输出粗量化结果，采保和数模子单元根据该粗量化结果输出合适的参考电平，利用电荷重分配原理将其对应的电荷分配到余量放大器输入信号保持电容Cc，余量放大器输入信号建立完成后，断开第二采样电容Cs和余量放大器输入信号保持电容Cc的连接关系，此时，第二采样电容Cs和余量放大器输入信号保持电容Cc分离，从而使得采保和数模子单元、余量信号负反馈放大子单元相互独立，即，采样保持电容与余量放大电路独立，实现采样保持与余量放大过程同步进行，从而提高了模数转换器的转换速率。
于本发明的一实施例中，所述每级流水线结构单元中第二采样电容Cs、余量放大器输入信号保持电容Cc与负反馈电容Cf的关系为：Cf＝(Cs·Cc)/(Acloseloop·(Cs+Cc))，其中，Acloseloop表示余量放大电路闭环放大倍数，余量信号负反馈放大电路的反馈因子为(Cf(Cs+Cc))/(CsCc)，选择第二采样电容Cs和余量放大器输入信号保持电容Cc的尺寸用于控制 负反馈因子大小。
在本实施例中，通过选择合适的各级流水线第二采样电容Cs和余量放大器输入信号保持电容Cc的电容尺寸能够改变负反馈因子的大小，便于灵活设计余量放大器。
如图3所示，为本发明实施例提供的具有输入信号预比较与电荷重分配的12位转换精度的流水线模数转换器电路图，详述如下：
所述模数转换器包括3级3位粗量化精度的流水线结构单元Stage1、Stage2和Stage3、1级3位粗量化精度的快闪模数转换器3bit Flash ADC和一个输出对准单元(OutPut Aligning)；其中，所述各级流水线结构包括采保和数模转换器SH&DAC、预比较电路Pre-Comp、子模数转换器Sub ADC、第二下极板采样开关Ssp，余量放大器输入信号开关Sqs、余量放大器输入信号保持电容Cc、余量放大器复位开关Srs1、余量放大器复位开关Srs2、余量信号放大开关Sa、负反馈电容Cf和余量放大器AMP等；所述采保和数模转换器SH&DAC包括第二采样开关Ss、第二采样电容Cs和第二参考电平发生器DAC Reference Generator；所述输入信号预比较电路Pre-Comp包括连接输入信号的预比较开关Spc、比较器COMPp、参考电压Vref4和子模数转换器参考电平选择器Sub ADC Reference Selector；所述子模数转换器Sub ADC包括第一采样开关Ssc、第一采样电容Csc、第一下极板采样开关Sspc、Sub ADC参考电平Vref1、Vref2、Vref3、Vref4、
Figure PCTCN2017101184-appb-000002
和Vref7由参考电平发生器提供，Sub ADC参考电平选择开关Sc和Sc’、3个比较器COMP和1个编码模块Coding Block，其中，每个比较器与子模数转换器Sub ADC中对应的采样网络组成相当于第二快闪模数转换器。所述SH&DAC由第二采样开关Ss、第二采样电容Cs和第二下极板采样开关Ssp组成的采样网络与Sub ADC由第一采样开关Ssc、第一采样电容Csc和第一下极板采样开关Sspc组成的采样网络必须按比例缩放，保证所述两个采样网络具有相同的时间常数。
如图4所示，为本发明实施例利用一种基于输入信号预比较和电荷重分配的流水线模数转换器技术实现12位转换精度的流水线模数转换器各级流水线粗量化参考电压示意图，用于说明输入信号比较电路Pre-Comp和子模数转换器Sub ADC中参考电压幅值关系，所述图中Vdd表示电源，倒三角符号表示参考地。
如图
Figure PCTCN2017101184-appb-000003
所示为本发明实施例利用一种基于输入信号预比较和电荷重分配的流水线模数转换器技术实现12位转换精度的流水线模数转换器的时序图，用于说明本发明所述模数转换器实施例各模块单元时序关系。
结合如图3、图4和图
Figure PCTCN2017101184-appb-000004
说明本发明实施例提供的一款利用一种基于输入信号预比较和电荷重分配的流水线模数转换器技术实现12位转换精度的流水线模数转换器的工作原理如 下：
首先，介绍所述第一级流水线Stage1工作过程如下：
第一阶段：如图
Figure PCTCN2017101184-appb-000005
所示，时钟信号Φs和Φsp为高电平时，所述模数转换器第一级流水线Stage1如图3所示，所述第一采样开关Ssc、第二采样开关Ss、第一下极板采样开关Sspc、第二下极板采样开关Ssp、所述输入信号的预比较开关Spc均处于导通状态，所述采保和数模转换器(SH&DAC)和所述子模数转换器(Sub ADC)进入采样阶段、所述预比较电路(Pre-Comp)进入预比较阶段。
第二阶段：如图
Figure PCTCN2017101184-appb-000006
所示，时钟信号Φsp下降沿到来时，所述第一采样开关Ssc、第二采样开关Ss继续导通，所述第一下极板采样开关Sspc、第二下极板采样开关Ssp均处于断开状态，所述采保和数模转换器(SH&DAC)的第二采样电容Cs和所述子模数转换器(Sub ADC)的第一采样电容Csc保持此刻的输入信号幅值，所述第二采样电容Cs和第一采样电容Csc的上极板保持的电荷量分别为：Qs＝(-Vin(0))·Cs和Qsc＝-Vin(0)·Csc，所述预比较电路(Pre-Comp)中预比较开关Spc断开，其对应的比较器COPMp锁存并输出输入信号Vin(0)与参考电平Vref4的比较结果。所述预比较电路(Pre-Comp)中的子模数转换器参考电平选择器(Sub ADC Reference Selector)根据比较器COMPp锁存结果对所述子模数转换器(Sub ADC)的参考电平选择开关Sc和Sc’进行控制，如果输入信号Vin(0)比参考电平Vref4高，则比较器COMPp输出为高电平，所述子模数转换器(Sub ADC)参考电平选择开关Sc导通，所述子模数转换器(Sub ADC)参考电平选择开关Sc’断开，所述Sub ADC选择如图4所示参考电平Vref1、Vref2和Vref3进行本级流水线后两位粗量化；如果输入信号Vin(0)比参考电平Vref4低，则比较器COMPp输出为低电平，所述子模数转换器(Sub ADC)参考电平选择开关Sc断开，所述子模数转换器(Sub ADC)参考电平选择开关Sc’导通，所述子模数转换器(Sub ADC)选择如图4所示参考电平
Figure PCTCN2017101184-appb-000007
和Vref7进行本级流水线后两位粗量化。
第三阶段：如图
Figure PCTCN2017101184-appb-000008
所示，时钟信号Φc和Φa高电平时，所述余量放大器复位开关Srs1、余量放大器复位开关Srs2和余量信号放大开关Sa导通，余量放大器AMP进入复位相。所述子模数转换器(Sub ADC)的比较器COMP锁存并输出输入信号Vin(0)在本级流水线后两位粗量化结果，输入信号Vin(0)如果输入信号Vin(0)小于等于Vref3或者Vref7(即它们之间的差值与比较器的另一输入端比较)，则所述子模数转换器(Sub ADC)的3个比较器COMP输出b2b1b0＝000；如果输入信号Vin(0)大于Vref3或者Vref7，并且小于等于Vref2或者
Figure PCTCN2017101184-appb-000009
(即它们之间的差值与比较器的另一输入端比较)，则所述子模数转换器(Sub ADC)的3个比较器COMP输出b2b1b0＝001；如果输入信号Vin(0)大于Vref2或者
Figure PCTCN2017101184-appb-000010
并且小于等于Vref1或者
Figure PCTCN2017101184-appb-000011
(即它们之间的差值与比较器的另一输 入端比较)，则所述子模数转换器(Sub ADC)的3个比较器COMP输出b2b1b0＝011；如果输入信号Vin(0)大于Vref1或者
Figure PCTCN2017101184-appb-000012
(即它们之间的差值与比较器的另一输入端比较)，则所述子模数转换器(Sub ADC)的3个比较器COMP输出b2b1b0＝111。所述子模数转换器(Sub ADC)的编码单元(Coding Block)根据所述预比较电路(Pre-Comp)的比较结果B2和Sub ADC粗量化结果b2b1b，编码输出本级流水线完整的3位粗量化结果B2B1B0，当B2＝0，b2b1b0＝000时，B2B1B0＝000；当B2＝0，b2b1b0＝001时，B2B1B0＝001；当B2＝0，b2b1b0＝011时，B2B1B0＝010；当B2＝0，b2b1b0＝111时，B2B1B0＝011；当B2＝1，b2b1b0＝000时，B2B1B0＝100；当B2＝1，b2b1b0＝001时，B2B1B0＝101；当B2＝1，b2b1b0＝011时，B2B1B0＝110；当B2＝1，b2b1b0＝111时，B2B1B0＝111。
第四阶段：如图
Figure PCTCN2017101184-appb-000013
所示，时钟信号Φqs为高电平时，所述余量放大器输入信号开关Sqs导通，所述采保和数模转换器(SH&DAC)中第二参考电平发生器(DAC Reference Generator)根据本级流水线3位完整粗量化结果B2B1B0生成适当的DAC参考电平VDAC，从而在采保和数模转换器(SH&DAC)第二采样电容Cs与所述余量放大器输入信号保持电容Cc连接的上极板产生余量放大器输入信号VA。根据电荷守恒原理，所述采保和数模转换器(SH&DAC)的第二采样电容Cs与所述余量放大器输入信号保持电容Cc连接的上极板总电荷量在所述余量放大器输入信号开关Sqs导通前后相同，即：Qs＝(-Vin(0))·Cs＝(VA-VDAC)·Cs+VA·Cc，从而得到余量放大器输入信号电平为VA＝(Cs/(Cs+Cc))·(-Vin(0)+VDAC)。
第五阶段，如图
Figure PCTCN2017101184-appb-000014
所示，时钟信号Φa、Φs和Φsp为高电平且其余时钟信号为低电平时，余量放大器输入信号开关Sqs断开，所述余量信号放大开关Sa导通，所述第一级流水线Stage1的所述余量信号放大电路进入余量信号放大阶段，根据所述余余量放大器输入信号保持电容Cc上极板电荷守恒和负反馈运算放大器原理，输出信号VR1＝(-CcCs)/(Cf·(Cc+Cs))·(-Vin(0)+VDAC)。通过设计合适的所述负反馈电容Cf电容值和所述DAC参考电平VDAC就能得到需要的输入信号放大倍数和余量信号输出幅值范围。例如，为满足本优选实施例3位粗量化精度要求，设计所述负反馈电容容值Cf＝(CcCs)/(8·(Cc+Cs))，所述DAC参考电平
Figure PCTCN2017101184-appb-000015
其中，本申请中·表示乘号，Vref表示模数转换器输出幅值，变量i根据本级流水线粗量化精度输出结果B2B1B0从(±1，±3，
Figure PCTCN2017101184-appb-000016
±7)内进行选择。当所述本级流水线粗量化精度输出结果B2B1B0＝000时，i＝7；B2B1B0＝001时，
Figure PCTCN2017101184-appb-000017
B2B1B0＝010时，i＝3；B2B1B0＝011时，i＝1；B2B1B0＝100时，i＝(-1)；B2B1B0＝101时，i＝(-3)；B2B1B0＝110时，
Figure PCTCN2017101184-appb-000018
B2B1B0＝111时，i＝(-7)。并且此时所述第一级流水线的所述采保和数模转换器(SH&DAC)和子模数转换器(Sub ADC)再次进入上述第一阶段的采样过程，跟踪采样输入信号Vin(1)，所述预比较电路(Pre-Comp)再次进入上述第一阶段的输入信号预比较过程。所述第二级流水线Stage2的采保 和数模转换器(SH&DAC)和子模数转换器(Sub ADC)进入与上述中的第一阶段的采样过程，跟踪所述第一级流水线Stage1的余量放大输出信号VR1，所述预比较电路(Pre-Comp)进入上述中的第一阶段的输入信号预比较过程。
第六阶段，如图
Figure PCTCN2017101184-appb-000019
所示，时钟信号Φsp下降沿到来时，所述第一级流水线Stage1进入上述中的第二阶段，进行输出信号Vin(1)的粗量化过程。所述第二级流水线Stage2采样和预比较过程结束，进入上述中的第二阶段，针对输入信号Vin(0)因第一级Stage1粗量化后的余量信号VR1进行进一步量化。
后续过程以此类推，各级流水线结构单元的具体工作过程与第一节流水线Stage1的第一阶段到第五阶段工作过程相同，最后一级所述3bit Flash ADC不产生余量输出信号，只需要对所述第三级流水线Stage3的余量放大输出信号VR3进行粗量化即可。随着所述输入信号Vin(0)流过所述所有流水线级数和最后的所述3bit Flash ADC，完成对输入信号Vin(0)的所有输出编码量化，最终通过输出对准单元(OutPut Aligning)对所述各级流水线粗量化结果进行对准输出，得到完整的信号量化输出结果。
在本发明实施例中，采用一种具有输入信号预比较和电荷重分配的流水线模数转换器技术实现的12位转换精度流水线模数转换器，并且每级流水线粗量化精度为3位的优选实施例进行解释说明，可根据需要进行多位转换精度且具有输入信号预比较和电荷重分配的流水线模数转换器，将该多位转换精度流水线模数转换器的按上述实施例拆分成多级流水结构单元与输出对准单元即可实现，在此不一一赘述。
综上所述，本发明将所述流水线模数转换器的各级流水线的最高位粗量化过程与采样保持过程相结合，在子模数转换器中比较器的个数相同的情况下，增加量化精度1位，在相同转换精度下能够减少流水线模数转换器级数，降低整体功耗。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种具有输入信号预比较与电荷重分配的流水线模数转换器，其特征在于，包括：
    一或多级流水线结构单元，其中，每级流水线结构单元用于对输入信号进行量化；
    第一快闪模数转换器，用于对末级流水线结构单元输出的余量信号进行量化，输出对应的量化值；
    调整输出单元，用于根据多级流水线结构单元与快闪模数转单元的连接顺序来组合各个所述量化值，以输出完整的量化结果；
    其中，每级流水线结构单元至少包括子模数转换器和预比较子单元，所述子模数转换器用于采样保持输入信号，所述预比较子单元用于将输入信号与相应的参考电压进行比较，输出本级的最高位量化值并根据该最高位量化值控制子模数转换器中参考电平选择开关的开关状态，所述子模数转换器还用于根据最高位量化值以及参考电平的开关状态将采样的输入信号进行粗量化输出对应的量化值。
  2. 根据权利要求1所述的流水线模数转换器，其特征在于，所述预比较子单元包括比较器、预比较开关、参考电压和参考电平选择器，所述比较器的正向输入端通过预比较开关连接输入信号，所述比较器的负向输入端连接参考电压，所述比较器的输出端分别连接参考电平选择器、子模数转换器，且在时钟信号Φsp的控制下锁存并输出最高位量化值，所述参考电平选择器根据最高位量化值控制子模数转换器内参考电平选择开关的开关状态。
  3. 根据权利要求1所述的流水线模数转换器，其特征在于，所述子模数转换器包括多个一位的量化模块与编码模块，多个所述量化模块的输出端依次连接到编码模块的输入端，所述编码模块的输入端还连接所述预比较子单元的输出端，所述编码模块根据所述预比较子单元的最高位量化值与量化模块的输出值得到对应的量化值。
  4. 根据权利要求3所述的流水线模数转换器，其特征在于，每一位所述量化模块均包含第一采样网络、第二快闪模数转换器、第一参考电平发生器和第一、二参考电平选择开关，所述第一采样网络的一端连接输入信号，其另一端连接第二快闪模数转换器的输入端，所述第一、二参考电平选择开关的一端分别连接所述第二快闪模数转换器与第一采样网络之间，所述第一、二参考电平选择开关的另一端分别连接第一参考电平发生器的输出端输出对应的参考电平，所述第二快闪模数转换器另一输入端接地，在时钟信号Φc 的控制下第二快闪模数转换器的输出端输出对应的量化值。
  5. 根据权利要求1所述的流水线模数转换器，其特征在于，所述每级流水线结构单元还包括采保和数模子单元、余量信号负反馈放大子单元，所述采保和数模子单元用于采样保持输入信号，还用于根据子模数转换器本级的量化值输出匹配的电平值，所述余量信号负反馈放大子单元用于将所述电平值所对应的电荷进行重分配输出余量信号。
  6. 根据权利要求5所述的流水线模数转换器，其特征在于，所述采保和数模子单元包括第二采样开关、第二采样电容、第二下级板采样开关与第二参考电平发生器，所述第二采样开关的一端连接输入信号，其另一端连接第二采样电容，所述第二采样电容的下级板与第二采样开关之间连接第二参考电平发生器的输出端，所述第二参考电平发生器在时钟信号Φqs的控制下根据子模数转换器当前的量化值生成参考电压，所述第二采样电容的上级板连接有接地的第二下级板采样开关。
  7. 根据权利要求6所述的流水线模数转换器，其特征在于，所述余量信号负反馈放大子单元包括余量放大器输入信号开关、余量信号放大开关、第一复位开关、第二复位开关、余量放大器输入信号保持电容、负反馈电容和余量放大器，所述余量信号产生开关的一端连接采保和数模子单元的输出端，其另一端分别连接余量放大器的负向输入端、第一复位开关、余量信号放大开关、余量放大器输入信号保持电容的一端，所述余量放大器输入信号保持电容、第一复位开关的另一端均接地；所述余量放大器的正向输入端接地，所述余量放大器的输出端输出余量信号，所述余量放大器的输出端通过负反馈电容反馈至余量信号放大开关的另一端，所述第二复位开关的一端连接输出的余量信号，其另一端接地。
  8. 根据权利要求7所述的流水线模数转换器，其特征在于，所述每级流水线结构单元内的子模数转换器、采保和数模子单元的采样保持过程与余量信号负反馈放大子单元的余量信号放大过程同步且独立运行。
  9. 根据权利要求7所述的流水线模数转换器，其特征在于，所述采保和数模子单元中第二采样电容Cs、余量放大电路中余量放大器输入信号保持电容Cc与负反馈电容Cf的关系为：Cf＝(Cs·Cc)/(Acloseloop·(Cs+Cc))，其中，Acloseloop表示余量放大电路闭环放大倍数，余量信号负反馈放大电路的反馈因子为(Cf(Cs+Cc))/(CsCc)，选择第二采样电容Cs和余量放大 器输入信号保持电容Cc的尺寸用于控制负反馈因子大小。
  10. 根据权利要求5所述的流水线模数转换器，其特征在于，所述子模数转换器与采保数模子单元中采样网络按比例缩放，且该采样网络具有相同的时间常数。
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