WO2018161941A1 - Procédé et dispositif de mise en correspondance de débit de code polaire - Google Patents

Procédé et dispositif de mise en correspondance de débit de code polaire Download PDF

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Publication number
WO2018161941A1
WO2018161941A1 PCT/CN2018/078445 CN2018078445W WO2018161941A1 WO 2018161941 A1 WO2018161941 A1 WO 2018161941A1 CN 2018078445 W CN2018078445 W CN 2018078445W WO 2018161941 A1 WO2018161941 A1 WO 2018161941A1
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Prior art keywords
sequence
bit sequence
coded bit
reading
starting
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PCT/CN2018/078445
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English (en)
Chinese (zh)
Inventor
陈莹
张华滋
罗禾佳
张公正
李榕
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华为技术有限公司
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Publication of WO2018161941A1 publication Critical patent/WO2018161941A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/24—Radio transmission systems, i.e. using radiation field for communication between two or more posts
    • H04B7/26—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a rate matching method and apparatus for a Polar code.
  • Polar code is an encoding method that can achieve Shannon capacity and has low coding and decoding complexity.
  • Polar code is a linear block code whose generating matrix is F N and its encoding process is among them Is a binary line vector of length N (ie code length); F N is an N ⁇ N matrix, and Here Defined as the Kronecker product of log 2 N matrices F 2 .
  • the addition and multiplication operations mentioned above are addition and multiplication operations on a binary Galois field.
  • the Polar code is characterized by an integer length of 2, and the actual code length can be based on the Modulation and Coding Scheme (MCS) table. Achieve flexible configuration. Therefore, the flexibility of the code length needs to be realized by rate matching technology.
  • MCS Modulation and Coding Scheme
  • the present application provides a rate matching method and apparatus for a Polar code to improve the performance of Polar code rate matching.
  • the present application provides a rate matching method for a Polar code, including:
  • the second coded bit sequence and the third coded bit sequence are read in a predetermined order to obtain a rate matched output sequence.
  • the present application performs bit reverse order interleaving on the mother code codeword, and stores the coded bit sequence after the bit reverse order interleaving in the circular buffer, and then reads the circular buffer in a predetermined order based on the storage mode of the circular buffer to obtain rate matching.
  • the output sequence afterwards effectively improves the performance of rate matching.
  • the bits in the first coded bit sequence whose position index is odd are sequentially composed of the second coded bit sequence are stored in the circular buffer, and the bits whose position index is even are sequentially composed of the third coded bit sequence are stored in the loop.
  • the remaining space of the cache including:
  • the second coded bit sequence and the third coded bit sequence are sequentially stored in the circular buffer in a first direction and a second direction from a first position in the circular buffer, wherein the first The last bit of the second coded bit sequence is adjacent to the last bit of the third coded bit sequence at a second position, the first direction and the second direction being opposite directions.
  • the reading the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence including:
  • rate matching adopts a punching manner, starting from the first position, skipping along the first direction Bit bit sequence, skipping in the second direction a bit bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, and when P is an even number, alternately reading the second bit Encoding the bit sequence and the third coded bit sequence to obtain a rate matched output sequence, where P is the number of bits that need to be punctured;
  • the rate matching adopts a shortened manner, starting from the second position, skipping in the second direction Bit bit sequence, skipping in the first direction a bit bit sequence, when S is an odd number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate matched output sequence, and when S is an even number, alternately reading the third bit Encoding the bit sequence and the second coded bit sequence to obtain a rate matched output sequence, where S is the number of bits that need to be shortened;
  • rate matching adopts a repeating manner, starting from the first position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the second position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching is in a repeated manner, starting from the first position, sequentially reading the second coded bit sequence and the third coded bit sequence in the first direction and the second direction to obtain a first output. a sequence of reading the third coded bit sequence and the second coded bit sequence in a second direction from the first position to obtain a second output sequence; or, starting from the second position, along the Reading the third coded bit sequence and the second coded bit sequence in one direction to obtain the second output sequence; and obtaining a rate matched output sequence according to the first output sequence and the second output sequence .
  • the reading the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence including:
  • the rate matching adopts the method of puncturing, the third coded bit sequence and the second coded bit sequence are alternately read in the first direction and the second direction in sequence from the second position, and the rate matching is obtained.
  • the output sequence is obtained.
  • the second coded bit sequence and the third coded bit sequence are alternately read in the first direction and the second direction in sequence from the first position, and the rate matched is obtained. Output sequence.
  • rate matching adopts a repeating manner, starting from the first position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the second position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching is repeated, starting from the first position, sequentially reading the second coding bit sequence and the third coding bit sequence in the first direction and the second direction to obtain the first Outputting a sequence from the first position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a second output sequence; or, starting from the second position, along Reading the third encoded bit sequence and the second encoded bit sequence in a first direction to obtain the second output sequence; and obtaining a rate matched output according to the first output sequence and the second output sequence sequence.
  • the bits in the first coded bit sequence whose position index is odd are sequentially composed of the second coded bit sequence are stored in the circular buffer, and the bits whose position index is even are sequentially composed of the third coded bit sequence are stored in the loop.
  • the remaining space of the cache including:
  • the reading the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence including:
  • the rate matching adopts a punching manner, starting from the third position, skipping along the first direction a sequence of bit bits, starting from the fourth position, skipping along the first direction a bit bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, and when P is an even number, alternately reading the second bit Encoding the bit sequence and the third coded bit sequence to obtain a rate matched output sequence, where P is the number of bits that need to be punctured;
  • the rate matching adopts a shortened manner, starting from the third position, skipping along the second direction Bit bit sequence starting from the fourth position and skipping in the second direction a bit bit sequence, when S is an odd number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate matched output sequence, and when S is an even number, alternately reading the third bit Encoding the bit sequence and the second coded bit sequence to obtain a rate matched output sequence, where S is the number of bits that need to be shortened;
  • rate matching adopts a repeating manner, starting from the third position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the fourth position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching adopts a repeating manner, starting from the third position, in the first direction, starting from the fourth position, alternately reading the second coded bit sequence and along the first direction
  • the third coded bit sequence is obtained to obtain a third output sequence; starting from the third position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a fourth output sequence; Or, starting from the fourth position, reading the third coded bit sequence and the second coded bit sequence in a first direction to obtain the fourth output sequence; according to the third output sequence and the The fourth output sequence results in a rate matched output sequence.
  • the reading the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence including:
  • the rate matching adopts the method of punching, the third coded bit sequence and the second code are alternately read in the second direction starting from the third position and starting from the fourth position. a bit sequence to obtain a rate matched output sequence;
  • the second coded bit sequence and the third coded bit are alternately read in the first direction starting from the third position and starting from the fourth position in the first direction. Sequence, obtaining a rate matched output sequence;
  • rate matching adopts a repeating manner, starting from the third position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the fourth position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching adopts a repeating manner, starting from the third position, in the first direction, starting from the fourth position, alternately reading the second coded bit sequence and along the first direction
  • the third coded bit sequence is obtained to obtain a third output sequence; starting from the third position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a fourth output sequence; Or, starting from the fourth position, reading the third coded bit sequence and the second coded bit sequence in a first direction to obtain the fourth output sequence; according to the third output sequence and the The fourth output sequence results in a rate matched output sequence.
  • the bits in the first coded bit sequence whose position index is odd are sequentially composed of the second coded bit sequence are stored in the circular buffer, and the bits whose position index is even are sequentially composed of the third coded bit sequence are stored in the loop.
  • the remaining space of the cache including:
  • the second coded bit sequence and the third coded bit sequence are stored in the circular buffer from the fifth position in a first direction, wherein the first bit of the second coded bit sequence The last bit of the third encoded bit sequence is adjacent to the fifth position.
  • the reading the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence including:
  • the rate matching adopts the method of puncturing, skipping the P-bit bit sequence in the first direction from the fifth position, and alternately reading the third coded bit sequence and the second when P is an odd number Encoding the bit sequence to obtain a rate-matched output sequence, and when P is an even number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate-matched output sequence; wherein, P is required The number of bits punched;
  • the rate matching adopts a shortening manner, starting from the fifth position, the S-bit bit sequence is skipped in the second direction, and when S is an odd number, the third coded bit sequence and the second encoding are alternately read. a bit sequence, the rate-matched output sequence is obtained, and when S is an even number, the second coded bit sequence and the third coded bit sequence are alternately read to obtain a rate-matched output sequence; the first direction and The second direction is the opposite direction; wherein S is the number of bits that need to be shortened;
  • rate matching is repeated, starting from the fifth position, sequentially reading the second coded bit sequence and the third coded bit sequence in the first direction to obtain a fifth output sequence; Starting at five positions, reading the third coded bit sequence in the first direction or the second direction, and then reading the second code sequence to obtain a sixth output sequence; according to the fifth output sequence and the The sixth output sequence yields a rate matched output sequence.
  • the reading the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence including:
  • the third coded bit sequence and the second coded bit sequence are alternately read in the second direction from the fifth position to obtain a rate matched output sequence.
  • the rate matching adopts a shortening manner, starting from the fifth position, the second coded bit sequence and the third coded bit sequence are alternately read in the first direction to obtain a rate matched output sequence;
  • rate matching is repeated, starting from the fifth position, sequentially reading the second coded bit sequence and the third coded bit sequence in the first direction to obtain a fifth output sequence; Starting at five positions, reading the third coded bit sequence in the first direction or the second direction, and then reading the second code sequence to obtain a sixth output sequence; according to the fifth output sequence and the The sixth output sequence yields a rate matched output sequence.
  • the present application provides a rate matching device for a Polar code, the device comprising:
  • a Polar coding unit for encoding an information bit sequence using an encoding matrix of a Polar code to obtain a mother codeword
  • An interleaving unit configured to perform bit reverse order interleaving on the mother codeword to obtain a first encoded bit sequence
  • a storage unit configured to store, in the first coded bit sequence, a bit with an odd position index into a second coded bit sequence, and store the second coded bit sequence in a circular buffer, where the bit with an even position index is sequentially formed into a third coded bit sequence, and the third coded bit sequence is stored in the In the remaining space of the loop cache;
  • a reading unit configured to read the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence.
  • the storage unit is configured to: store the second coded bit sequence and the third coded bit sequence sequentially from the first position in the circular buffer according to the first direction and the second direction, respectively.
  • a last bit of the second coded bit sequence is adjacent to a last bit of the third coded bit sequence at a second position, the first direction and the second direction being opposite The direction.
  • the reading unit is specifically configured to:
  • rate matching adopts a punching manner, starting from the first position, skipping along the first direction Bit bit sequence, skipping in the second direction a bit bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, and when P is an even number, alternately reading the second bit Encoding the bit sequence and the third coded bit sequence to obtain a rate matched output sequence, where P is the number of bits that need to be punctured;
  • the rate matching adopts a shortened manner, starting from the second position, skipping in the second direction Bit bit sequence, skipping in the first direction a bit bit sequence, when S is an odd number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate matched output sequence, and when S is an even number, alternately reading the third bit Encoding the bit sequence and the second coded bit sequence to obtain a rate matched output sequence, where S is the number of bits that need to be shortened;
  • rate matching adopts a repeating manner, starting from the first position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the second position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching is repeated, starting from the first position, sequentially reading the second coding bit sequence and the third coding bit sequence in the first direction and the second direction to obtain the first Outputting a sequence from the first position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a second output sequence; or, starting from the second position, along Reading the third encoded bit sequence and the second encoded bit sequence in a first direction to obtain the second output sequence; and obtaining a rate matched output according to the first output sequence and the second output sequence sequence.
  • the reading unit is specifically configured to:
  • the third coded bit sequence and the second coded bit sequence are alternately read in the first direction and the second direction in sequence from the second position, and the rate matching is obtained.
  • the second coded bit sequence and the third coded bit sequence are alternately read in the first direction and the second direction in sequence from the first position, and the rate matched is obtained.
  • rate matching adopts a repeating manner, starting from the first position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the second position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching is repeated, starting from the first position, sequentially reading the second coding bit sequence and the third coding bit sequence in the first direction and the second direction to obtain the first Outputting a sequence from the first position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a second output sequence; or, starting from the second position, along Reading the third encoded bit sequence and the second encoded bit sequence in a first direction to obtain the second output sequence; and obtaining a rate matched output according to the first output sequence and the second output sequence sequence.
  • the storage unit is specifically configured to:
  • the reading unit is specifically configured to:
  • the rate matching adopts a punching manner, starting from the third position, skipping along the first direction a sequence of bit bits, starting from the fourth position, skipping along the first direction a bit bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, and when P is an even number, alternately reading the second bit Encoding the bit sequence and the third coded bit sequence to obtain a rate matched output sequence, where P is the number of bits that need to be punctured;
  • the rate matching adopts a shortened manner, starting from the third position, skipping along the second direction Bit bit sequence starting from the fourth position and skipping in the second direction a bit bit sequence, when S is an odd number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate matched output sequence, and when S is an even number, alternately reading the third bit Encoding the bit sequence and the second coded bit sequence to obtain a rate matched output sequence, where S is the number of bits that need to be shortened;
  • rate matching adopts a repeating manner, starting from the third position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the fourth position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching adopts a repeating manner, starting from the third position, in the first direction, starting from the fourth position, alternately reading the second coded bit sequence and along the first direction
  • the third coded bit sequence is obtained to obtain a third output sequence; starting from the third position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a fourth output sequence; Or, starting from the fourth position, reading the third coded bit sequence and the second coded bit sequence in a first direction to obtain the fourth output sequence; according to the third output sequence and the The fourth output sequence results in a rate matched output sequence.
  • the reading unit is specifically configured to:
  • the rate matching adopts the method of punching, the third coded bit sequence and the second code are alternately read in the second direction starting from the third position and starting from the fourth position. a bit sequence to obtain a rate matched output sequence;
  • the second coded bit sequence and the third coded bit are alternately read in the first direction starting from the third position and starting from the fourth position in the first direction. Sequence, obtaining a rate matched output sequence;
  • rate matching adopts a repeating manner, starting from the third position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the fourth position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching adopts a repeating manner, starting from the third position, in the first direction, starting from the fourth position, alternately reading the second coded bit sequence and along the first direction
  • the third coded bit sequence is obtained to obtain a third output sequence; starting from the third position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a fourth output sequence; Or, starting from the fourth position, reading the third coded bit sequence and the second coded bit sequence in a first direction to obtain the fourth output sequence; according to the third output sequence and the The fourth output sequence results in a rate matched output sequence.
  • the storage unit is specifically configured to:
  • the second coded bit sequence and the third coded bit sequence are stored in the circular buffer from the fifth position in a first direction, wherein the first bit of the second coded bit sequence The last bit of the third encoded bit sequence is adjacent to the fifth position.
  • the reading unit is specifically configured to:
  • the rate matching adopts the method of puncturing, skipping the P-bit bit sequence in the first direction from the fifth position, and alternately reading the third coded bit sequence and the second when P is an odd number Encoding the bit sequence to obtain a rate-matched output sequence, and when P is an even number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate-matched output sequence; wherein, P is required The number of bits punched;
  • the rate matching adopts a shortening manner, starting from the fifth position, the S-bit bit sequence is skipped in the second direction, and when S is an odd number, the third coded bit sequence and the second encoding are alternately read. a bit sequence, the rate-matched output sequence is obtained, and when S is an even number, the second coded bit sequence and the third coded bit sequence are alternately read to obtain a rate-matched output sequence; the first direction and The second direction is the opposite direction, where S is the number of bits that need to be shortened;
  • rate matching is repeated, starting from the fifth position, sequentially reading the second coded bit sequence and the third coded bit sequence in the first direction to obtain a fifth output sequence; Starting at five positions, reading the third coded bit sequence in the first direction or the second direction, and then reading the second code sequence to obtain a sixth output sequence; according to the fifth output sequence and the The sixth output sequence yields a rate matched output sequence.
  • the reading unit is specifically configured to:
  • the third coded bit sequence and the second coded bit sequence are alternately read in the second direction from the fifth position to obtain a rate matched output sequence.
  • the rate matching adopts a shortening manner, starting from the fifth position, the second coded bit sequence and the third coded bit sequence are alternately read in the first direction to obtain a rate matched output sequence;
  • rate matching is repeated, starting from the fifth position, sequentially reading the second coded bit sequence and the third coded bit sequence in the first direction to obtain a fifth output sequence; Starting at five positions, reading the third coded bit sequence in the first direction or the second direction, and then reading the second code sequence to obtain a sixth output sequence; according to the fifth output sequence and the The sixth output sequence yields a rate matched output sequence.
  • the present application provides a rate matching device for a Polar code, the device comprising:
  • a processor configured to execute the program stored by the memory, when the program is executed, the processor is configured to encode an information bit sequence by using an encoding matrix of a Polar code to obtain a mother codeword;
  • the mother code code word is subjected to bit reverse order interleaving to obtain a first coded bit sequence; the bits of the first coded bit sequence whose position index is odd are sequentially composed of the second coded bit sequence and stored in a circular buffer, and the position index is an even bit.
  • Forming a third coded bit sequence in turn is stored in the remaining space of the circular buffer; reading the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence.
  • the present application provides a rate matching device for a Polar code, the device comprising:
  • At least one input for inputting a sequence of information bits
  • a signal processor configured to encode an information bit sequence by using an encoding matrix of a Polar code to obtain a mother codeword; perform bit reverse order interleaving on the mother codeword to obtain a first encoded bit sequence; and the first encoding
  • the bits in the bit sequence whose position index is odd are sequentially composed of the second coded bit sequence and stored in the circular buffer, and the bits whose position index is even are sequentially composed of the third coded bit sequence stored in the remaining space of the circular buffer; in a predetermined order Reading the second coded bit sequence and the third coded bit sequence to obtain a rate matched output sequence;
  • At least one output for outputting an output sequence obtained by the signal processor.
  • Yet another aspect of the present application provides a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform the various aspects or various possible implementations described above The encoding method or decoding method described.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when executed on a computer, cause the computer to perform the encoding method or the decoding method described in the above aspects or various possible implementations.
  • Yet another aspect of the present application provides a computer program that, when executed on a computer, causes the computer to perform the encoding method or the decoding method described in the above aspects or various possible implementations.
  • the coding sequence of the Polar code is used to encode the information bit sequence to obtain the mother codeword; the bit code is interleaved with the mother codeword to obtain the first coded bit sequence; and the first coded bit sequence is obtained.
  • the bits whose odd position is indexed are sequentially composed of the second coded bit sequence and stored in the circular buffer, and the bits whose position index is even are sequentially composed of the third coded bit sequence are stored in the remaining space of the circular buffer; read in a predetermined order.
  • the second coded bit sequence and the third coded bit sequence are subjected to a rate matched output sequence.
  • the coded bit sequence of the mother code code word is interleaved in the reverse order, and the coded bit sequence after the bit reverse order interleaving is stored in the circular buffer, and then the circular buffer is read in a predetermined order based on the storage mode of the circular buffer, and the rate matching is obtained.
  • the output sequence effectively improves the performance of rate matching.
  • FIG. 1 is a schematic diagram of a system architecture applicable to the present application
  • FIG. 2 is a schematic diagram showing the location of channel coding in a communication link
  • FIG. 3 is a schematic diagram of a channel coding and rate matching process in the prior art
  • FIG. 4 is a schematic flowchart of a method for matching a rate of a Polar code according to Embodiment 1 of the present application;
  • FIG. 5 is a block diagram of the Polar code encoding in the present application.
  • FIG. 6 is a schematic diagram of interleaving a mother code code word
  • FIG. 7A is a schematic diagram of a circular buffer in Embodiment 2 of the present application.
  • FIG. 7B is a schematic diagram of a circular buffer in Embodiment 3 of the present application.
  • FIG. 7C is a schematic diagram of a circular buffer in Embodiment 4 of the present application.
  • FIG. 7D is a schematic diagram of another circular buffer in the fourth embodiment of the present application.
  • FIG. 8 is a schematic diagram of a solution rate matching process in the present application.
  • Figure 9 is a comparison diagram of effects using the prior art scheme and the scheme of the present invention.
  • FIG. 10 is a schematic structural diagram of a rate matching apparatus for a Polar code according to Embodiment 6 of the present application.
  • FIG. 11 is a schematic structural diagram of a rate matching apparatus for a Polar code according to Embodiment 7 of the present application.
  • FIG. 12 is a schematic structural diagram of a rate matching apparatus for a Polar code according to Embodiment 8 of the present application.
  • FIG. 1 is a schematic diagram of a system architecture applicable to the present application.
  • the system architecture includes a network device 101, one or more terminals, such as the first terminal 1021, the second terminal 1022, and the third terminal 1023 shown in FIG. 1.
  • the network device 101 can perform data transmission with the first terminal 1021, the second terminal 1022, and the third terminal 1023 via the network.
  • the network device may be a base station (BS).
  • a base station device also referred to as a base station, is a device deployed in a wireless access network to provide wireless communication functionality.
  • a device providing a base station function in a 2G network includes a base transceiver station (BTS) and a base station controller (BSC), and the device providing the base station function in the 3G network includes a Node B (NodeB) and the wireless device.
  • BTS base transceiver station
  • BSC base station controller
  • NodeB Node B
  • a radio network controller which provides a base station function in a 4G network, includes an evolved NodeB (eNB), and a device that provides a base station function in a 5G network, including a new radio node B (New Radio NodeB) , gNB), Centralized Unit (CU), Distributed Unit (Distributed Unit) and a new wireless controller.
  • eNB evolved NodeB
  • gNB new radio node B
  • CU Centralized Unit
  • Distributed Unit Distributed Unit
  • AP Access Point
  • the terminal can be a device that provides voice and/or data connectivity to the user, including wired terminals and wireless terminals.
  • the wireless terminal can be a handheld device with wireless connectivity, or other processing device connected to a wireless modem, and a mobile terminal that communicates with one or more core networks via a wireless access network.
  • the wireless terminal can be a mobile phone, a computer, a tablet, a personal digital assistant (PDA), a mobile internet device (MID), a wearable device, and an e-book reader. Wait.
  • the wireless terminal can also be a portable, pocket, handheld, computer built-in or in-vehicle mobile device.
  • the wireless terminal can be part of a mobile station, an access point, or a user equipment (UE).
  • UE user equipment
  • the communication system applicable to the above system architecture includes but is not limited to: Code Division Multiple Access (CDMA) IS-95, Code Division Multiple Access (CDMA) 2000, Time Division Synchronous Code Division Multiple Access (Time) Division-Synchronous Code Division Multiple Access (TD-SCDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Duplexing-Long Term Evolution (TDD LTE), Frequency Division Dual Frequency Division Duplexing-Long Term Evolution (FDD LTE), Long Term Evolution-Advanced (LTE-advanced), and various wireless communication systems (for example, 5G systems) that are evolving in the future.
  • CDMA Code Division Multiple Access
  • CDMA Code Division Multiple Access
  • TD-SCDMA Time Division Synchronous Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • TDD LTE Time Division Duplexing-Long Term Evolution
  • FDD LTE Frequency Division Dual Frequency Division Duplexing-Long Term Evolution
  • LTE-advanced Long
  • 5G system also known as the New Radio system
  • 5G system also known as the New Radio system
  • a new communication scenario is defined in the 5G system: Ultra-Reliable and Low-Latency Communication (URLLC), enhancement.
  • eMBB Mobile broadband
  • mMTC Massive Machine Type Communication
  • URLLC Ultra-Reliable and Low-Latency Communication
  • eMBB Mobile broadband
  • mMTC Massive Machine Type Communication
  • channel coding is an important research object to meet the needs of 5G communication.
  • Figure 2 shows a schematic diagram of the location of channel coding in a communication link.
  • the communication system 200 includes a source device 201 and a receiver device 202.
  • the sender device may be the network device 101 shown in FIG. 1.
  • the receiver device 202 may be in the first terminal 1021, the second terminal 1022, and the third terminal 1023 shown in FIG. Any terminal; or the receiving device may be the network device 101 shown in FIG. 1, and correspondingly, the transmitting device 201 may be the first terminal 1021, the second terminal 1022, and the third shown in FIG. Any of the terminals 1023.
  • the process of data transmission through the communication link is: the source device 201 sequentially performs source coding, channel coding, rate matching, and digital modulation on the symbol sequence output by the source, and then sends the channel sequence to the receiving device 202 through the channel, and the receiving device 202 After receiving the data, digital demodulation, de-rate matching, channel decoding, and source decoding are sequentially performed, thereby recovering the original symbol sequence.
  • the present application focuses on the operations performed by the transmitting device 201, and the receiving device 202 can refer to the transmitting device 201. .
  • one implementation in the prior art is: dividing the mother codeword of the Polar code into four segments, respectively B0 ( x 0 , ..., x N/4-1 ), B1 (x N/4 , ..., x N/2-1 ), B2 (x N/2 , ..., x 3N/4-1 ), B3 (x 3N/4 , ..., x N-1 ), where N is the mother code length.
  • the circular buffer is designed such that the relative positions of B0 and B3 remain unchanged, and B1 and B2 are placed crosswise.
  • the bits in the circular buffer are read from the back to the front (B3, B1B2 alternates, B0) until the target code length, and puncture-based rate matching can be realized; read from the heading (B0, B1B2 alternate, B3 Until the target code length, rate matching based on shortening can be realized; cyclic reading (B3, B1B2 alternating, B0) is performed from the back to the front until the target code length, and rate matching based on repetition can be realized.
  • rate matching based on shortening is implemented by reading from the back to the end, if the number of bits to be punched is large, the B3 may be all punctured, and the receiving device cannot be accurately decoded. Rate matching performance is poor.
  • the present application provides a rate matching method for the Polar code, so that the performance of the rate matching can be effectively improved on the basis of combining three rate matching methods (puncturing, shortening, and repeating).
  • FIG. 4 is a schematic flowchart of a method for matching a rate of a Polar code according to Embodiment 1 of the present application, where the flow can be performed by the transmitting device 201 shown in FIG. 2. As shown in FIG. 4, the method includes:
  • Step 401 Encode the information bit sequence by using an encoding matrix of a Polar code to obtain a mother codeword
  • Step 402 Perform bit reverse order interleaving on the mother code codeword to obtain a first coded bit sequence.
  • Step 403 Store bits in the first coded bit sequence with an odd position index into a second code bit sequence and store them in a circular buffer.
  • the bits with an even position index are sequentially formed into a third code bit sequence and stored in the circular buffer. In the remaining space; wherein the position index of the bit in the first coded bit sequence starts with 1;
  • Step 404 Read the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence.
  • FIG. 5 is a block diagram of the Polar code encoding in the present application. The above steps 401 to 404 are specifically described below with reference to FIG. 5.
  • the process can be implemented by the Polar code construction module in FIG. 5; according to the target code length, the coding matrix of the Polar code is selected for encoding to obtain the mother codeword, and the process can be implemented by the coding module in FIG. 5.
  • step 402 the binary representation of the sequence number corresponding to the bit of the mother code codeword (starting from 0) is respectively reverse-ordered to obtain the sequence number after the reverse-order interleaving, and the sequence obtained after the interleaving is the first coded bit sequence, and the process may be performed.
  • Figure 6 is a schematic diagram of interleaving a mother codeword.
  • the length of the mother code code word is 16, and the number corresponding to each bit in the mother code code word is 0, 1, 2, ..., 15, and the binary representations are 0000, 0001, 0010, 0011, 0100, 0101, respectively.
  • 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, the bit numbers of each binary representation are respectively reversed in order to obtain 0000, 1000, 0100, 1100, 0010, 1010, 0110, 1110, 0001.
  • the corresponding numbers after the bit reverse order are 0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, respectively. 7, 15, 15, the mother codewords are sorted in the order of the bit reverse order to obtain the first coded bit sequence.
  • the second coded bit sequence and the third coded bit sequence are stored in a circular buffer.
  • the bit with the odd position index in the first coded bit sequence sequentially constitutes the second coded bit sequence
  • the second The serial numbers corresponding to the coded bit sequences are 0, 4, 2, 6, 1, 5, 3, and 7, respectively.
  • the bits whose position index is even in the first coded bit sequence sequentially constitute a second coded bit sequence
  • the numbers corresponding to the third coded bit sequence are 8, 12, 10, 14, 9, 13, 11, and 15, respectively.
  • step 404 the rate matched output sequence is read in the agreed order, and the process can be implemented by the rate matching module in FIG.
  • the bit with the position index of the first coded bit sequence is sequentially composed of the second coded bit sequence, and the bit with the position index of the even number is sequentially composed.
  • a third coded bit sequence (corresponding to a second interleaving of the first coded bit sequence).
  • the second coded bit sequence and the third coded bit sequence are sequentially stored in the circular buffer in a first direction and a second direction from a first position in the circular buffer, wherein the first The last bit of the second coded bit sequence is adjacent to the last bit of the third coded bit sequence at a second position, the first direction and the second direction being opposite directions.
  • first direction may be a counterclockwise direction, and correspondingly, the second direction is a clockwise direction; or the first direction may also be a clockwise direction, and correspondingly, the second direction is a counterclockwise direction.
  • first direction is a counterclockwise direction, and the second direction is a clockwise direction as an example.
  • the first location may be any location in the circular cache, which is not limited.
  • FIG. 6 is a schematic diagram of a circular cache in the second embodiment of the present application. For convenience of explanation, only the sequence numbers corresponding to the second coded bit sequence and the third coded bit sequence are shown in the cyclic buffer shown in FIG. 7A, and the second coded bit sequence and the third coded bit sequence are not specifically shown. Bit.
  • the rate matching may be performed by puncturing, shortening, or repeating.
  • Two scenarios (Scenario 1 and Scene 2) are provided in the present application, and the following two types of holes are punched, shortened, or repeated.
  • the reading mode of equal rate matching is explained. Among them, FIG. 7A only shows the reading manner of rate matching such as punching, shortening or repetition of the scene 1.
  • rate matching adopts the method of punching, starting from the first position, skipping in the counterclockwise direction Bit bit sequence, skipping in a clockwise direction a bit bit sequence, in order to ensure sequential reading of the bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, when P is an even number And reading the second coded bit sequence and the third coded bit sequence alternately to obtain a rate matched output sequence, where P is the number of bits that need to be punctured. among them, Round up the symbol.
  • bit bit sequence skipping counterclockwise a bit bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, and when P is an even number, alternately reading the second bit
  • the coded bit sequence and the third coded bit sequence are obtained to obtain a rate matched output sequence. among them, Round the symbol down.
  • S 3, Starting from P2 in Fig. 7A, the 2-bit bit sequence is skipped in the counterclockwise direction, and the 1-bit bit sequence is skipped in the clockwise direction. Since S is an odd number, when alternately read, the second coded bit sequence is read first, and then After reading the third coded bit sequence, the sequence number corresponding to the rate matched output sequence is [3 13 5 9 1 14 6 10 2 12 4 8 0].
  • the sequence of the even index (the third coded bit sequence) can be preferentially repeated, and the sequence of the odd index (the second coded bit sequence) is not repeated.
  • the sequence of the even index (the third coded bit sequence) can be preferentially repeated, and the sequence of the odd index (the second coded bit sequence) is not repeated.
  • the target code length is 20, a total of 20 bits need to be read cyclically.
  • the read bits include the complete 16 bits.
  • the output sequence is number 8, 12, 10, 14, 9, 13, 11, 15, 7, 3, 5, 1, 6, 2, 4, 0, 8, 12, The bits corresponding to 10 and 14, wherein the bits with the sequence numbers 8, 12, 10, and 14 are repeated bits.
  • the target code length is 26
  • 26 bits are cyclically read in the clockwise direction, and the read bits include the complete 16 bits.
  • the output sequence is number 8, 12, 10, 14, 9, 13, 11, 15, 7, 3, 5, 1, 6, 2, 4, 0, 8, 12
  • the third coded bit sequence and the second coded bit sequence are cyclically read in the first direction until the number of bits read reaches the target.
  • the code length is obtained, and the output sequence after the rate matching is obtained. For example, if the target code length is 20, a total of 20 bits need to be read cyclically. Starting from position P2 of FIG. 7A, cyclically reading 20 bits in the counterclockwise direction, then the read bits include the complete 16 bits. Bits and 4 bits that need to be repeated, the output sequence is number 15, 11, 13, 9, 14, 10, 12, 8, 0, 4, 2, 6, 1, 5, 3, 7, 15, 11, The bits corresponding to 13, 9 are the bits with the sequence numbers 15, 11, 13, and 9 being repeated bits.
  • the target code length is 26, a total of 26 bits need to be read cyclically.
  • 26 bits are cyclically read in the counterclockwise direction, and the read bits include the complete 16 bits.
  • Bits and 10 bits that need to be repeated, the output sequence is number 15, 11, 13, 9, 14, 10, 12, 8, 7, 0, 4, 2, 6, 1, 5, 3, 7, 15, The bits corresponding to 11, 13, 9, 14, 10, 12, 8, 7, 0, wherein the bits numbered 15, 11, 13, 9, 14, 10, 12, 8, 7, 0 are repeated bits.
  • the loop buffer can be read in other ways to obtain a rate matched output sequence. For example, starting from the first position, sequentially reading the second coded bit sequence and the third coded bit sequence in the counterclockwise direction and the clockwise direction to obtain a first output sequence; Starting at a position, reading the third coded bit sequence and the second coded bit sequence in a clockwise direction to obtain a second output sequence of length Q, where Q is the number of bits that need to be repeated; according to the first output The sequence and the second output sequence result in a rate matched output sequence.
  • the second coded bit sequence and the third coded bit sequence are alternately read in the counterclockwise direction and the clockwise direction, starting from the first position.
  • the sequence number corresponding to an output sequence [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15]
  • the length of the first output sequence is smaller than the target code length, so it is necessary to repeatedly read the 4-bit bit sequence, again from the first
  • the 4-bit bit sequence is read in a clockwise direction to obtain a second output sequence, and the second output sequence corresponds to the sequence number [8 12 10 14], and the sequence number corresponding to the rate-matched output sequence is [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15 8 12 10 14].
  • the second output sequence may also be obtained by reading the third coded bit sequence and the second coded bit sequence in a counterclockwise direction starting from the second position.
  • the sequence number corresponding to the output matching sequence is [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15 15 11 13 9], where [ 15 11 13 9] is the sequence number corresponding to the second output sequence.
  • the second output sequence is obtained by reading only the third coded bit sequence, and the second coded bit sequence has not yet been read.
  • the second coded bit sequence and the third coded bit sequence are alternately read in the counterclockwise direction and the clockwise direction, starting from the first position.
  • the first output sequence corresponds to the sequence number [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15]
  • the length of the first output sequence is smaller than the target code length, so it is necessary to repeatedly read the 10-bit bit sequence, again from the first
  • a 10-bit bit sequence, that is, a second output sequence, and a sequence number corresponding to the second output sequence [8 12 10 14 9 13 11 15 7 3] are read in a clockwise direction, thereby obtaining a rate-matched output sequence corresponding
  • the serial number is [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15 8 12 10 14 9 13 11 15 7 3].
  • the second encoding may be alternately read in the counterclockwise direction and the clockwise direction from the first position as described above.
  • a bit sequence and the third coded bit sequence to obtain a first output sequence or alternatively, starting from the second position (P2), sequentially reading the second coded bit in a counterclockwise direction and a clockwise direction
  • the sequence and the third coded bit sequence obtain a sequence number corresponding to the first output sequence [15 7 11 3 13 5 9 1 14 6 10 2 12 4 8 0], or alternatively, other read modes may be used as long as the guarantee Read the bits in the circular buffer completely in a reasonable order.
  • the target code length is 13, starting from the P2 position in Fig. 7A, when reading alternately, reading the third coded bit sequence first, and then reading the second code sequence, then obtaining
  • the sequence number corresponding to the rate matched output sequence is [15 7 11 3 13 5 9 1 14 6 10 2 12];
  • the target code length is 12, starting from the P2 position in FIG. 7A, when reading alternately, the third coded bit sequence is read first, and then the second coded sequence is read, and the rate matching is obtained.
  • the sequence number corresponding to the output sequence is [15 7 11 3 13 5 9 1 14 6 10 2].
  • rate matching adopts a shortening manner, starting from the first position, sequentially reading the second coded bit sequence and the third coded bit sequence in a counterclockwise direction and a clockwise direction to obtain a rate The matched output sequence.
  • the target code length is 13, starting from the P1 position in FIG. 7A, and when reading alternately, reading the second coded bit sequence first, and then reading the third coded bit sequence,
  • the sequence number corresponding to the output matching sequence obtained is [0 8 4 12 2 10 6 14 11 9 5 13 3];
  • the target code length is 12, starting from the P1 position in FIG. 7A, when reading alternately, reading the second coded bit sequence first, and then reading the third code sequence, the rate matching is obtained.
  • the sequence number corresponding to the output sequence is [0 8 4 12 2 10 6 14 11 9 5 13].
  • the sequence of the even index (the third coded bit sequence) may be preferentially repeated, and the sequence of the odd index (the second coded bit sequence) may be repeated.
  • the third coded bit sequence and the second coded bit sequence may be cyclically read in the second direction from the first position until the number of bits read reaches a target code length to obtain a rate matched output. a sequence; or, starting from the second position, cyclically reading the third coded bit sequence and the second coded bit sequence in the first direction until the number of bits read reaches a target code length, and after the rate matching is obtained
  • the output sequence is the same as the repetition in scenario 1, and is not described here.
  • the loop buffer can be read in other ways to obtain a rate matched output sequence. For example, starting from the first position, sequentially reading the second coded bit sequence and the third coded bit sequence in the counterclockwise direction and the clockwise direction to obtain a first output sequence; Starting at a position, reading the third coded bit sequence and the second coded bit sequence in a clockwise direction to obtain a second output sequence; or, reading from the second position, in a counterclockwise direction a third coded bit sequence and the second coded bit sequence are obtained to obtain the second output sequence; and the rate matched output sequence is obtained according to the first output sequence and the second output sequence.
  • the specific implementation is the same as the repetition in scenario 1, and is not described here.
  • the rate matching module may be set to the reading mode in the scene 1, or may also be set to the reading mode in the scene 2.
  • the second coded bit sequence and the third coded bit sequence are counterclockwise from the third position in the circular buffer. Or sequentially clockwise stored in the circular buffer, wherein a last bit of the second encoded bit sequence is adjacent to a first bit of the third encoded bit sequence at a fourth location.
  • FIG. 6 is a schematic diagram of a circular buffer in the third embodiment of the present application.
  • the rate matching may be performed by means of puncturing, shortening, or repeating.
  • Two scenarios (Scenario 3 and Scene 4) are provided in the present application, and the following two methods respectively punch, shorten, or repeat The reading mode of equal rate matching is explained. Among them, FIG. 7B only shows the reading manner of rate matching such as punching, shortening or repetition of the scene 3.
  • rate matching adopts the method of punching, skipping from the third position in the counterclockwise direction a sequence of bit bits, skipping from the fourth position in the counterclockwise direction a bit bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, and when P is an even number, alternately reading the second bit
  • the coded bit sequence and the third coded bit sequence are obtained as a rate matched output sequence, where P is the number of bits that need to be punctured.
  • the 2-bit bit sequence is skipped in the counterclockwise direction, starting from P3 in Fig. 7B, skipping the 1-bit bit sequence in the counterclockwise direction, since P is an odd number, when reading alternately, read first Taking the third coded bit sequence and then reading the second coded bit sequence, the sequence number corresponding to the rate matched output sequence is [12 2 10 6 14 11 9 5 13 3 11 7 15];
  • the sequence of the even index (the third coded bit sequence) may be preferentially repeated, and the sequence of the odd index (the second coded bit sequence) may be repeated. For example, starting from the third position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of read bits reaches a target code length, resulting in rate matching. After the output sequence. For example, if the target code length is 20, a total of 20 bits need to be read cyclically. Starting from position P3 of FIG. 7B, cyclically reading 20 bits in a clockwise direction, then the read bits include the complete 16 bits.
  • the output sequence is number 15, 11, 13, 9, 14, 10, 12, 8, 7, 3, 5, 1, 6, 2, 4, 0, 15, 11,
  • the bits corresponding to 13, 9 are the bits with the sequence numbers 15, 11, 13, and 9 being repeated bits.
  • the target code length is 26
  • 26 bits are cyclically read in a clockwise direction, and the read bits include the complete 16 bits.
  • the output sequence is number 15, 11, 13, 9, 14, 10, 12, 8, 7, 3, 5, 1, 6, 2, 4, 0, 15, 11
  • the bits corresponding to 13, 9, 14, 10, 12, 8, 7, 3, wherein the bits numbered 15, 11, 13, 9, 14, 10, 12, 8, 7, 3 are repeated bits.
  • the rate matching adopts a repeating manner, starting from the fourth position, cyclically reading the third coded bit sequence and the second coded bit sequence in the first direction until the number of bits read reaches the target code Long, get the output sequence after rate matching.
  • the target code length is 20, a total of 20 bits need to be read cyclically.
  • the read bits include the complete 16 bits. Bits and 4 bits that need to be repeated, the output sequence is number 8, 12, 10, 14, 9, 13, 11, 15, 0, 4, 2, 6, 1, 5, 3, 7, 8, 12, The bits corresponding to 10 and 14, wherein the bits with the sequence numbers 8, 12, 10, and 14 are repeated bits.
  • the target code length is 26, a total of 26 bits need to be read cyclically.
  • 26 bits are cyclically read in the counterclockwise direction, and the read bits include the complete 16 bits.
  • Bits and 10 bits that need to be repeated the output sequence is number 8, 12, 10, 14, 9, 13, 11, 15, 0, 4, 2, 6, 1, 5, 3, 7, 8, 12, The bits corresponding to 10, 14, 9, 13, 11, 15, 0, 4, wherein the bits numbered 8, 12, 10, 14, 9, 13, 11, 15, 0, 4 are repeated bits.
  • the cyclic buffer may be read by other methods to obtain a rate-matched output sequence, for example, starting from the third position, in a counterclockwise direction, starting from the fourth position, along the Reading the second coded bit sequence and the third coded bit sequence alternately in a counterclockwise direction to obtain a third output sequence; reading the third coded bit in a clockwise direction from the third position a sequence and the second coded bit sequence to obtain a fourth output sequence; and according to the third output sequence and the fourth output sequence, a rate matched output sequence is obtained.
  • the second coded bit sequence and the sequence are alternately read in the counterclockwise direction starting from P3 in FIG. 7B and in the counterclockwise direction from P4 in FIG. 7B.
  • the third coded bit sequence is obtained to obtain a third output sequence, and the third output sequence corresponds to a sequence number [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15], and the length of the first output sequence is smaller than the target code length. Therefore, it is necessary to repeatedly read the 4-bit bit sequence, and start from P3 in FIG.
  • the sequence number corresponding to the rate-matched output sequence is [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15 15 11 13 9].
  • the fourth output sequence may also be obtained by reading the third coded bit sequence and the second coded bit sequence in a counterclockwise direction starting from the fourth position.
  • the sequence number corresponding to the output matching sequence is [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15 8 12 10 14], where [ 8 12 10 14] is the sequence number corresponding to the fourth output sequence.
  • the third output sequence there are various ways of obtaining the third output sequence.
  • the second coded bit sequence and the third coded bit sequence are alternately read to obtain a third output sequence, or alternatively, starting from the third position and starting from the fourth position in the clockwise direction
  • sequentially reading the third coded bit sequence and the second coded bit sequence in a clockwise direction to obtain a sequence number corresponding to the third output sequence [15 7 11 3 13 5 9 1 14 6 10 2 12 4 8 0 ]
  • other reading methods can be used as long as the bits in the circular buffer are completely read in a reasonable order.
  • the second coded bit sequence and the number are alternately read in a counterclockwise direction from the third position in a counterclockwise direction from the third position.
  • the three coded bit sequences are obtained as a rate matched output sequence.
  • the loop buffer can be read in other ways to obtain a rate matched output sequence. For example, starting from the third position, in the counterclockwise direction, starting from the fourth position, alternately reading the second coded bit sequence and the third coded bit sequence in the counterclockwise direction Obtaining a third output sequence; reading the third coded bit sequence and the second coded bit sequence in a clockwise direction from the third position to obtain a fourth output sequence; or, from the fourth Starting at a position, reading the third coded bit sequence and the second coded bit sequence in a counterclockwise direction to obtain the fourth output sequence; obtaining a rate according to the third output sequence and the fourth output sequence The matched output sequence.
  • the specific implementation is the same as the repetition in scenario 3, and details are not described herein again.
  • the rate matching module may be set to the reading mode in the scene 3, or may be set to the reading mode in the scene 4.
  • the second coded bit sequence and the third coded bit sequence are started from the fifth position, and are mutually counterclockwise or clockwise.
  • An interval is stored in the circular buffer, wherein a first bit of the second coded bit sequence is adjacent to a last bit of the third coded bit sequence at a fifth position.
  • the first code sequence after bit interleaving is stored in the loop buffer in a natural order of position index in a counterclockwise direction or a clockwise direction.
  • FIG. 6 is a schematic diagram of a circular buffer in the fourth embodiment of the present application.
  • the second coded bit sequence and the third coded bit sequence in FIG. 6 may be stored in the circular buffer from the fifth position (P5) in the circular buffer and spaced apart from each other in the counterclockwise direction.
  • FIG. 7D is a schematic diagram of another circular buffer in the fourth embodiment of the present application.
  • the first coded bit sequence may be directly stored in the counterclockwise direction or the clockwise direction from the fifth position.
  • the results can be seen in Figures 7C and 7D. In this case, there is no need to perform secondary interleaving on the first coded bit sequence, which reduces the complexity of the interleaving process.
  • the rate matching may be performed by using a puncturing, shortening, or repeating manner.
  • two scenarios are provided (Scenario 5 and Scenario 6), and the following two scenarios are respectively performed.
  • the reading mode of rate matching such as punching, shortening or repeating is explained.
  • FIG. 7C only shows the reading manner of rate matching such as punching, shortening or repetition of the scene 5.
  • the rate matching adopts the method of puncturing, the P-bit bit sequence is skipped in the counterclockwise direction from the fifth position, and the third coded bit sequence and the sequence are alternately read when P is an odd number.
  • the second coded bit sequence is obtained to obtain a rate-matched output sequence.
  • P is the number of bits that need to be punctured.
  • 7C corresponds to the first coded bit sequence being sequentially stored in the loop buffer in the order of position index in the order of position index. Therefore, if the rate matching adopts the punching method, skip P in the counterclockwise direction and need to punch The number of bits, which cyclically reads the remaining bits in the first coded bit.
  • the sequence number corresponding to the rate-matched output sequence is [12 2 10 6 14 11 9 5 13 3 11 7 15].
  • the rate-matched output sequence is [3 13 5 9 1 14 6 10 2 12 4 8 0].
  • the rate-matched output sequence is [13 5 9 1 14 6 10 2 12 4 8 0] .
  • the second coded bit sequence and the third coded bit sequence are sequentially read in a counterclockwise direction to obtain a sequence number corresponding to the fifth output sequence.
  • the length of the fifth output sequence is smaller than the target code length, so it is necessary to repeatedly read the 4-bit bit sequence, starting again from the P5 position, counterclockwise Direction, first reading the third coded bit sequence, and then reading the second code sequence, and obtaining a sequence number corresponding to the sixth output sequence is [8 12 10 14], thereby obtaining [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15 8 12 10 14].
  • the sixth output sequence may also start from the fifth position, read the third coded bit sequence first in the clockwise direction, and then read the second code sequence.
  • the output sequence after the rate matching is obtained is [0 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15 15 11 13 9], where [15 11 13 9] is the sixth output sequence.
  • the sixth output sequence is obtained by reading only the third coded bit sequence, and the second coded bit sequence has not yet been read.
  • the second coded bit sequence and the third coded bit sequence are sequentially read in the counterclockwise direction from P5 in FIG. 7C, and the sequence number corresponding to the fifth output sequence is [0]. 8 4 12 2 10 6 14 11 9 5 13 3 11 7 15], the length of the fifth output sequence is smaller than the target code length, so it is necessary to repeatedly read the 10-bit bit sequence, starting again from the P5 position, in the counterclockwise direction, first Reading the third coded bit sequence, and then reading the second code sequence, and obtaining a sequence number corresponding to the sixth output sequence is [8 12 10 14 9 13 11 15 0 4], thereby obtaining [0 8 4 12 2 10 614 11 9 5 13 3 11 7 15 8 12 10 14 9 13 11 15 0 4].
  • the second coded bit sequence and the foregoing may be sequentially read in the counterclockwise direction from the fifth position as described above.
  • the third coded bit sequence and the second coded bit sequence are alternately read in a clockwise direction from the fifth position to obtain a rate matched Output sequence.
  • the sequence number of the output sequence after rate matching is [15 7 11 3 13 5 9 1 14 6 10 2 12] .
  • the second coded bit sequence and the third coded bit sequence are alternately read in a counterclockwise direction from the fifth position to obtain a rate matched output. sequence.
  • the sequence number of the output sequence after rate matching is [0 8 4 12 2 10 6 14 11 9 5 13 3] .
  • the rate matching module may be set to the reading mode in the scene 5, or may be set to the reading mode in the scene 6.
  • the rate matching can be performed in the manner of punching, shortening, or repeating.
  • the two scenarios are provided in the present application (Scenario 7 and Scene 8).
  • the reading mode of rate matching such as punching, shortening or repeating is explained.
  • FIG. 7D only shows the reading manner of rate matching such as punching, shortening or repetition of the scene 7.
  • the rate matching adopts the method of puncturing, starting from the fifth position, skipping the P-bit bit sequence in the clockwise direction to start reading until the number of read bits reaches the target code length, and the rate matching is obtained.
  • the output sequence; where P is the number of bits that need to be punctured. 7D corresponds to the first coded bit sequence being sequentially stored in the circular buffer in the order of position index in the order of position index. Therefore, if the rate matching adopts the punching method, skip P pieces that need to be punched in a clockwise direction. The number of bits, which cyclically reads the remaining bits of the first coded bit.
  • the sequence number corresponding to the rate-matched output sequence is [12 2 10 6 14 11 9 5 13 3 11 7 15].
  • the rate-matched output sequence is [3 13 5 9 1 14 6 10 2 12 4 8 0].
  • the rate-matched output sequence is [13 5 9 1 14 6 10 2 12 4 8 0] .
  • the third coded bit sequence and the second coded bit sequence are sequentially read in a counterclockwise direction to obtain a sequence number corresponding to the fifth output sequence.
  • the length of the fifth output sequence is smaller than the target code length, so it is necessary to repeatedly read the 4-bit bit sequence, starting again from the P5 position, counterclockwise Direction, first reading the third coded bit sequence, and then reading the second code sequence, and obtaining a sequence number corresponding to the sixth output sequence is [15 11 13 9], thereby obtaining [15 7 11 3 13 5 9 1 14 6 10 2 12 4 8 0 15 11 13 9].
  • the sixth output sequence is obtained by reading only the third coded bit sequence, and the second coded bit sequence has not yet been read.
  • the second coded bit sequence and the third coded bit sequence are sequentially read in the counterclockwise direction from P5 in FIG. 7D, and the sequence number corresponding to the fifth output sequence is [15]. 7 11 3 13 5 9 1 14 6 10 2 12 4 8 0], the length of the fifth output sequence is smaller than the target code length, so it is necessary to repeatedly read the 10-bit bit sequence, starting again from the P5 position, in the counterclockwise direction, first Reading the third coded bit sequence, and then reading the second code sequence, and obtaining a sequence number corresponding to the sixth output sequence is [15 11 13 9 14 10 12 8 7 7], thereby obtaining [15 7 11 3 13 5 9 1 14 6 10 2 12 4 8 0 15 11 13 9 14 10 12 8 0 7].
  • rate matching adopts the method of puncturing, starting from the fifth position, reading is started in the counterclockwise direction until the number of bits read reaches the target code length, and a rate-matched output sequence is obtained.
  • the sequence number of the output sequence after rate matching is [15 7 11 3 13 5 9 1 14 6 10 2 12 ].
  • the sequence number of the output sequence after rate matching is [0 8 4 12 2 10 6 14 11 9 5 13 3] .
  • the rate matching module may be set to the reading mode in the scene 7, or may be set to the reading mode in the scene 8.
  • the rate matching process is introduced based on the sending end device, and after the sending end device obtains the output sequence of the rate matching, the digital device performs digital modulation and sends the data to the receiving end device; the receiving end device receives the received data.
  • Digital demodulation is performed and de-rate matching is performed.
  • the receiving end device may know the rate matching method adopted by the sending end device in advance, and perform de-rate matching by using a de-rate matching method corresponding to the rate matching method.
  • the de-rate matching process of the receiving device is specifically described below.
  • FIG 8 is a schematic diagram of the solution rate matching process. As shown in Figure 8, the specific process is:
  • the receiving device digitally demodulates the received data to obtain a bit sequence
  • the receiving end device determines the sequence number of the punctured bit according to the sequence number of the bit in the bit sequence, and inserts 0 in the first four bits of the bit sequence according to the sequence number of the punctured bit to obtain a de-rate matched output sequence. .
  • the receiving end device performs bit reverse-order interleaving on the output sequence of the de-rate matching to obtain a de-interleaved sequence.
  • the receiving end device decodes the deinterleaved sequence.
  • a set of simulation results comparison chart is a comparison chart of the simulation results using the solution of the prior art scheme and the scheme of the present invention.
  • the present application also provides an apparatus, and the specific content of the apparatus can be implemented by referring to the above method.
  • FIG. 10 is a schematic structural diagram of a rate matching apparatus for a Polar code according to Embodiment 6 of the present application. As shown in FIG. 10, the apparatus includes:
  • the Polar coding unit 1001 is configured to encode the information bit sequence by using an encoding matrix of the Polar code to obtain a mother codeword.
  • the interleaving unit 1002 is configured to perform bit reverse order interleaving on the mother code codeword to obtain a first coded bit sequence.
  • the storage unit 1003 is configured to store, in the first coded bit sequence, a bit with an odd position index into a second code bit sequence, and store the second code bit sequence in a circular buffer, and the bit with an even position index is sequentially formed into a third coded bit sequence. In the remaining space of the circular cache;
  • the reading unit 1004 is configured to read the second coded bit sequence and the third coded bit sequence in a predetermined order to obtain a rate matched output sequence.
  • the storage unit 1003 is specifically configured to: sequence the second coded bit sequence and the third coded bit sequence from a first position in the circular buffer according to a first direction and a second direction, respectively Stored in the circular buffer, wherein a last bit of the second coded bit sequence is adjacent to a last bit of the third coded bit sequence at a second location, the first direction and the second direction being Opposite Direction.
  • the reading unit 1004 is specifically configured to:
  • rate matching adopts a punching manner, starting from the first position, skipping along the first direction Bit bit sequence, skipping in the second direction a bit bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, and when P is an even number, alternately reading the second bit Encoding the bit sequence and the third coded bit sequence to obtain a rate matched output sequence, where P is the number of bits that need to be punctured;
  • the rate matching adopts a shortened manner, starting from the second position, skipping in the second direction Bit bit sequence, skipping in the first direction a bit bit sequence, when S is an odd number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate matched output sequence, and when S is an even number, alternately reading the third bit Encoding the bit sequence and the second coded bit sequence to obtain a rate matched output sequence, where S is the number of bits that need to be shortened;
  • rate matching adopts a repeating manner, starting from the first position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the second position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching is repeated, starting from the first position, sequentially reading the second coding bit sequence and the third coding bit sequence in the first direction and the second direction to obtain the first Outputting a sequence from the first position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a second output sequence; or, starting from the second position, along Reading the third encoded bit sequence and the second encoded bit sequence in a first direction to obtain the second output sequence; and obtaining a rate matched output according to the first output sequence and the second output sequence sequence.
  • the reading unit 1004 is specifically configured to:
  • the third coded bit sequence and the second coded bit sequence are alternately read in the first direction and the second direction in sequence from the second position, and the rate matching is obtained.
  • the second coded bit sequence and the third coded bit sequence are alternately read in the first direction and the second direction in sequence from the first position, and the rate matched is obtained.
  • rate matching adopts a repeating manner, starting from the first position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the second position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching is repeated, starting from the first position, sequentially reading the second coding bit sequence and the third coding bit sequence in the first direction and the second direction to obtain the first Outputting a sequence from the first position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a second output sequence; or, starting from the second position, along Reading the third encoded bit sequence and the second encoded bit sequence in a first direction to obtain the second output sequence; and obtaining a rate matched output according to the first output sequence and the second output sequence sequence.
  • the storage unit 1003 is specifically configured to:
  • the reading unit 1004 is specifically configured to:
  • the rate matching adopts a punching manner, starting from the third position, skipping along the first direction a sequence of bit bits, starting from the fourth position, skipping along the first direction a bit bit sequence, when P is an odd number, alternately reading the third coded bit sequence and the second coded bit sequence to obtain a rate matched output sequence, and when P is an even number, alternately reading the second bit Encoding the bit sequence and the third coded bit sequence to obtain a rate matched output sequence, where P is the number of bits that need to be punctured;
  • the rate matching adopts a shortened manner, starting from the third position, skipping along the second direction Bit bit sequence starting from the fourth position and skipping in the second direction a bit bit sequence, when S is an odd number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate matched output sequence, and when S is an even number, alternately reading the third bit Encoding the bit sequence and the second coded bit sequence to obtain a rate matched output sequence, where S is the number of bits that need to be shortened;
  • rate matching adopts a repeating manner, starting from the third position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the fourth position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching adopts a repeating manner, starting from the third position, in the first direction, starting from the fourth position, alternately reading the second coded bit sequence and along the first direction
  • the third coded bit sequence is obtained to obtain a third output sequence; starting from the third position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a fourth output sequence; Or, starting from the fourth position, reading the third coded bit sequence and the second coded bit sequence in a first direction to obtain the fourth output sequence; according to the third output sequence and the The fourth output sequence results in a rate matched output sequence.
  • the reading unit 1004 is specifically configured to:
  • the rate matching adopts the method of punching, the third coded bit sequence and the second code are alternately read in the second direction starting from the third position and starting from the fourth position. a bit sequence to obtain a rate matched output sequence;
  • the second coded bit sequence and the third coded bit are alternately read in the first direction starting from the third position and starting from the fourth position in the first direction. Sequence, obtaining a rate matched output sequence;
  • rate matching adopts a repeating manner, starting from the third position, cyclically reading the third coded bit sequence and the second coded bit sequence in the second direction until the number of bits read reaches the target code Long, obtaining a rate-matched output sequence; or if the rate matching is repeated, starting from the fourth position, cyclically reading the third coded bit sequence and the second coded bit along the first direction Sequence until the number of bits read reaches the target code length, resulting in a rate matched output sequence; or
  • the rate matching adopts a repeating manner, starting from the third position, in the first direction, starting from the fourth position, alternately reading the second coded bit sequence and along the first direction
  • the third coded bit sequence is obtained to obtain a third output sequence; starting from the third position, reading the third coded bit sequence and the second coded bit sequence in a second direction to obtain a fourth output sequence; Or, starting from the fourth position, reading the third coded bit sequence and the second coded bit sequence in a first direction to obtain the fourth output sequence; according to the third output sequence and the The fourth output sequence results in a rate matched output sequence.
  • the storage unit 1003 is specifically configured to:
  • the second coded bit sequence and the third coded bit sequence are stored in the circular buffer from the fifth position in a first direction, wherein the first bit of the second coded bit sequence The last bit of the third encoded bit sequence is adjacent to the fifth position.
  • the reading unit 1004 is specifically configured to:
  • the rate matching adopts the method of puncturing, skipping the P-bit bit sequence in the first direction from the fifth position, and alternately reading the third coded bit sequence and the second when P is an odd number Encoding the bit sequence to obtain a rate-matched output sequence, and when P is an even number, alternately reading the second coded bit sequence and the third coded bit sequence to obtain a rate-matched output sequence; wherein, P is required The number of bits punched;
  • the rate matching adopts a shortening manner, starting from the fifth position, the S-bit bit sequence is skipped in the second direction, and when S is an odd number, the third coded bit sequence and the second encoding are alternately read. a bit sequence, the rate-matched output sequence is obtained, and when S is an even number, the second coded bit sequence and the third coded bit sequence are alternately read to obtain a rate-matched output sequence; the first direction and The second direction is the opposite direction, where S is the number of bits that need to be shortened;
  • rate matching is repeated, starting from the fifth position, sequentially reading the second coded bit sequence and the third coded bit sequence in the first direction to obtain a fifth output sequence; Starting at five positions, reading the third coded bit sequence in the first direction or the second direction, and then reading the second code sequence to obtain a sixth output sequence; according to the fifth output sequence and the The sixth output sequence yields a rate matched output sequence.
  • the reading unit 1004 is specifically configured to:
  • the third coded bit sequence and the second coded bit sequence are alternately read in the second direction from the fifth position to obtain a rate matched output sequence.
  • the rate matching adopts a shortening manner, starting from the fifth position, the second coded bit sequence and the third coded bit sequence are alternately read in the first direction to obtain a rate matched output sequence;
  • rate matching is repeated, starting from the fifth position, sequentially reading the second coded bit sequence and the third coded bit sequence in the first direction to obtain a fifth output sequence; Starting at five positions, reading the third coded bit sequence in the first direction or the second direction, and then reading the second code sequence to obtain a sixth output sequence; according to the fifth output sequence and the The sixth output sequence yields a rate matched output sequence.
  • FIG. 11 is a schematic structural diagram of a rate matching apparatus for a Polar code according to Embodiment 7 of the present application.
  • the device 1100 includes: a memory 1101 and a processor 1102;
  • the memory 1101 is configured to store a program; specifically, the program may include program code, and the program code includes computer operation instructions.
  • the memory 1101 may be a random access memory (RAM) or a non-volatile memory, such as at least one disk storage. Only one memory is shown in the figure, of course, the memory can also be set to a plurality as needed. Memory 1101 can also be a memory in processor 1102.
  • the memory 1101 stores the following elements, executable modules or data structures, or a subset thereof, or an extended set thereof:
  • Operation instructions include various operation instructions for implementing various operations.
  • Operating system Includes a variety of system programs for implementing various basic services and handling hardware-based tasks.
  • the processor 1102 may also be referred to as a central processing unit (English: Central Processing Unit, CPU).
  • the method disclosed in the foregoing embodiment of the present application may be applied to the processor 1102 or implemented by the processor 1102.
  • the processor 1102 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method may be completed by an integrated logic circuit of hardware in the processor 1102 or an instruction in a form of software.
  • the processor 1102 described above may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or discrete hardware. Component.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 1101, the processor 1102 reads the information in the memory 1101, and executes the program stored in the memory in conjunction with its hardware.
  • the processor is configured to:
  • the coded bit sequence and the third coded bit sequence are obtained to obtain a rate matched output sequence.
  • FIG. 12 is a schematic structural diagram of a rate matching apparatus for a Polar code according to Embodiment 8 of the present application. As shown in FIG. 12, the apparatus 1200 includes:
  • the signal processor 1202 is configured to encode the information bit sequence by using an encoding matrix of the Polar code to obtain a mother codeword; perform bit reverse order interleaving on the mother codeword to obtain a first encoded bit sequence; The bits of the coded bit sequence whose position index is odd are sequentially composed of the second coded bit sequence and stored in the circular buffer, and the bits whose position index is even are sequentially composed of the third coded bit sequence are stored in the remaining space of the circular buffer; Reading the second coded bit sequence and the third coded bit sequence sequentially to obtain a rate matched output sequence;
  • At least one output 1203 is configured to output an output sequence obtained by the signal processor.
  • the coding sequence of the Polar code is used to encode the information bit sequence to obtain the mother codeword; and the mother codeword is subjected to bit reverse order interleaving to obtain the first coded bit sequence;
  • the bits of the first coded bit sequence whose position index is odd are sequentially composed of the second coded bit sequence and stored in the circular buffer, and the bits whose position index is even are sequentially composed of the third coded bit sequence are stored in the remaining space of the circular buffer;
  • the second coded bit sequence and the third coded bit sequence are read in a predetermined order to obtain a rate matched output sequence.
  • the coded bit sequence of the mother code code word is interleaved in the reverse order, and the coded bit sequence after the bit reverse order interleaving is stored in the circular buffer, and then the circular buffer is read in a predetermined order based on the storage mode of the circular buffer, and the rate matching is obtained.
  • the output sequence effectively improves the performance of rate matching.
  • the application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

La présente invention concerne un procédé et un dispositif de mise en correspondance de débit de code polaire. Le procédé comprend : le codage d'une séquence de bits d'informations à l'aide d'une matrice de codage d'un code polaire pour obtenir un mot de code mère; la réalisation d'un entrelacement inverse de bits sur le mot de code mère pour obtenir une première séquence de bits codés ; des bits de la première séquence de bits codés dont les positions sont indexées de manière impaire constituant une deuxième séquence de bits codés à leur tour et étant stockés dans un tampon circulaire, et des bits dont les positions sont indexées de manière paire constituant une troisième séquence de bits codés à leur tour et étant stockés dans l'espace restant du tampon circulaire ; et la lecture de la deuxième séquence de bits codés et de la troisième séquence de bits codés dans un ordre prédéterminé pour obtenir une séquence de sortie adaptée au débit. Les performances de mise en correspondance de débit de code polaire peuvent être efficacement améliorées.
PCT/CN2018/078445 2017-03-10 2018-03-08 Procédé et dispositif de mise en correspondance de débit de code polaire WO2018161941A1 (fr)

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