WO2019037782A1 - Procédé de décodage et décodeur pour codes polaires - Google Patents

Procédé de décodage et décodeur pour codes polaires Download PDF

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Publication number
WO2019037782A1
WO2019037782A1 PCT/CN2018/102297 CN2018102297W WO2019037782A1 WO 2019037782 A1 WO2019037782 A1 WO 2019037782A1 CN 2018102297 W CN2018102297 W CN 2018102297W WO 2019037782 A1 WO2019037782 A1 WO 2019037782A1
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decoding
scl
result
data
circuit
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PCT/CN2018/102297
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English (en)
Chinese (zh)
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郭晗
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • the present application relates to the field of communications and, more particularly, to a decoding method and decoder for a polarization code in the field of communications.
  • the Polar code is the first code that theoretically proves that Shannon capacity can be obtained and has low decoding complexity.
  • the Polar code is a linear block code, and its decoding can be serially cancelled (SC).
  • SC serially cancelled
  • a decoding method or a serial cancellation list (SCL) decoding method performs decoding.
  • SC decoding and SCL decoding each have their own strengths. From the perspective of decoding performance, SC decoding can achieve good performance when the code length is long, but when the code length is short or medium length, the SC decoding performance of the Polar code is poor. For SCL decoding, the performance of SCL decoding is improved relative to the performance of SC decoding. However, from the processing delay of decoding, the complexity of SCL decoding is higher than that of SC decoding. The time is large, and the SC decoding complexity is low, the decoding accuracy is low, but the decoding delay is small.
  • the present application provides a decoding method and decoder for a polarization code.
  • the data to be decoded is subjected to SCL decoding and SC decoding, respectively.
  • the SC decoding result is output as the final decoding result of the data, and stops.
  • SCL decoding of the data is performed.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • a method for decoding a polarization code comprising: acquiring data to be decoded; respectively starting a serial cancellation list SCL decoding and serial cancellation SC decoding on the data; The decoding result of the SC decoding; if it is determined that the decoding result of the SC decoding is correct, the SCL decoding is stopped; and the decoding result of the SC decoding is output.
  • the method for decoding a polarization code performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • the method further includes: performing the SCL decoding; and outputting the decoding result of the SCL decoding. .
  • the separately performing serial cancellation list SCL decoding and serial cancellation SC decoding on the data includes: performing the SCL decoding on the data in parallel and the SC Decoding.
  • the method further includes: performing a cyclic redundancy CRC check on the decoding result of the SC decoding; and determining, in the case that the CRC check passes, determining the SC decoding The decoding result is correct, or if the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
  • the search width of the SCL decoding is 8 decoding paths.
  • the decoding delay is lower and the decoding accuracy is relatively better.
  • a decoder for performing the decoding method of the polarization code in the first aspect and various implementations described above.
  • the decoder includes an acquisition circuit, an SCL decoding circuit, an SC decoding circuit, and an output circuit.
  • the acquisition circuit is configured to acquire data to be decoded;
  • the SCL decoding circuit is configured to perform serial cancellation list SCL decoding on the data;
  • the SC decoding circuit is configured to perform serial cancellation SC translation on the data.
  • the SC decoding circuit is further configured to obtain a decoding result of the SC decoding; and when determining that the decoding result of the SC decoding is correct, the SCL decoding circuit is further configured to stop the SCL decoding;
  • an output circuit configured to output a decoding result of the SC decoding.
  • a decoder comprising a processor, a transceiver and a memory for supporting the decoder to perform a corresponding function in the above decoding method.
  • the memory stores instructions for performing specific signal transceiving under the driving of a processor for invoking the instruction to implement the decoding method of the polarization code in the first aspect and various implementations thereof.
  • a fourth aspect provides a decoder, including a processing module, a storage module, and a transceiver module, for supporting the decoder to perform the functions in the foregoing first aspect or any possible implementation manner of the first aspect, the function may be
  • the hardware implementation may also be implemented by hardware, and the hardware or software includes one or more modules corresponding to the above functions.
  • a readable medium for storing instructions comprising instructions for performing the decoding method of the first aspect or any of the possible implementations of the first aspect.
  • 1 is a schematic diagram of an SC decoding path.
  • FIG. 2 is a schematic diagram of an SCL decoding path.
  • FIG. 3 is a schematic flow chart of a typical SCL decoding processing manner.
  • FIG. 4 is a schematic diagram of a communication system of a decoding method and a decoder applicable to the polarization code of the present application.
  • FIG. 5 is a schematic flowchart of a method for decoding a polarization code according to an embodiment of the present invention.
  • FIG. 6 is a schematic flow chart of a method for decoding a polarization code according to another embodiment of the present invention.
  • Figure 7 is a schematic block diagram of a decoder in accordance with one embodiment of the present invention.
  • Figure 8 is a schematic block diagram of a decoder in accordance with another embodiment of the present invention.
  • Figure 9 is a schematic block diagram of a decoder in accordance with another embodiment of the present invention.
  • a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer.
  • an application running on a computing device and a computing device can be a component.
  • One or more components can reside within a process and/or execution thread, and the components can be located on one computer and/or distributed between two or more computers.
  • these components can execute from various computer readable media having various data structures stored thereon.
  • a component may, for example, be based on signals having one or more data packets (eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems) Communicate through local and/or remote processes.
  • data packets eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems
  • LTE long term evolution
  • FDD frequency division duplex
  • LTE/LTE LTE/LTE.
  • -A time division duplex (TDD) system LTE/LTE-A frequency division duplex (FDD) system
  • UMTS universal mobile telecommunication system
  • WiMAX worldwide interoperability for microwave access
  • PLMN public land mobile network
  • D2D device to device
  • M2M machine to machine
  • Wi-Fi wireless local area network
  • WLAN Wireless local area networks
  • the terminal device may also be referred to as a user equipment (UE), a mobile station (MS), a mobile terminal, etc., and the terminal device may be connected by using a wireless device.
  • a radio access network (RAN) communicates with one or more core network devices, for example, the terminal device may include various handheld devices with wireless communication capabilities, in-vehicle devices, wearable devices, computing devices, or connected to a wireless modem. Other processing equipment. It may also include a subscriber unit, a cellular phone, a smart phone, a wireless data card, a personal digital assistant (PDA) computer, a tablet computer, a wireless modem, and a handheld device.
  • PDA personal digital assistant
  • MTC machine type communication
  • STA station in wireless local area networks
  • WLAN wireless local area networks
  • It can be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a wireless local loop (WLL) station, and a next-generation communication system, for example, a terminal device in a 5G network or a future evolution.
  • SIP Session Initiation Protocol
  • WLL wireless local loop
  • next-generation communication system for example, a terminal device in a 5G network or a future evolution.
  • PLMN public land mobile network
  • the base station may also be referred to as a network side device or an access network device
  • the network side device may be a device for communicating with the terminal device
  • the network device may be an evolved base station (evolutional Node B, eNB) in the LTE system.
  • eNodeB evolved base station
  • gNB evolved base station
  • gNB access point in NR
  • base transceiver station transceiver node
  • in-vehicle device wearable device
  • network device in future 5G network or network side device in future evolved PLMN system
  • the network side device may be an access point (AP) in the WLAN, or may be a global system for mobile communication (GSM) or code dvision multiple access (CDMA).
  • GSM global system for mobile communication
  • CDMA code dvision multiple access
  • BTS Base Transceiver Station
  • eNB evolved NodeB
  • eNodeB evolved NodeB
  • LTE Long Term Evolution
  • the network device may also be a Node B of a 3rd Generation (3G) system.
  • the network device may also be a relay station or an access point, or an in-vehicle device, a wearable device, and a future 5G network.
  • the embodiments of the present invention are not limited herein. For convenience of description, in all embodiments of the present invention, the above devices for providing wireless communication functions to the MS are collectively referred to as network devices.
  • Polar code is a high-performance channel coding scheme proposed in recent years. It has the characteristics of high performance, low complexity and flexible rate matching. It has become the coding method of control information in 5G systems.
  • the decoding method of the Polar code is SCL decoding and SC decoding.
  • a Polar code having a code length of N may correspond to a binary decoding code tree composed of N layer edges. SC coding can be described as a decoding path search process on the code tree.
  • FIG. 1 is a schematic diagram of an SC decoding path.
  • SC decoding starts from the root node of the code tree and gradually expands on the decoding code tree, and each layer selects a relative probability from two candidate paths. The one with a large value, that is, the search width is 1. And the path expansion of the next layer is performed on the basis of the selected decoding path.
  • a decoding result is finally obtained through the decoding path, and the decoding result is verified to determine whether the decoding result is correct.
  • FIG. 2 is a schematic diagram of an SCL decoding path.
  • SCL decoding allows multiple candidate decoding paths to be reserved.
  • the SCL decoding starts from the root node of the code tree and is gradually expanded on the code tree.
  • Each layer selects L strips from 2L candidate decoding paths, that is, the search width is L.
  • the path expansion of the next layer is performed on the basis of the selected L decoding paths.
  • the four black solid lines in Figure 2 indicate the selected four SCL decoding paths.
  • one path with the largest reliability metric is selected from the four SCL decoding paths, and the corresponding bit estimation sequence is the decoding result.
  • FIG. 3 is a schematic flow chart of a typical SCL decoding processing manner, and FIG. 3 shows the whole process of processing a hard bit. All hard bit processing starts from the first stage to the last stage. End the loop process until all hard bit processing is complete. The stage is equivalent to the layer of the decoding code tree in FIG. 1 or FIG. 2.
  • L ie, the search width is L
  • the maximum log likelihood ratio (LLR) of the decoding path is obtained as a branch metric and a path metric for each decoding path, wherein the branch metric is used to calculate the cumulative metric.
  • the decoding result of the most accurate decoding path is selected by the hard bit stream check routing of the L decoding paths, as the final Output the result.
  • the flow of a typical SCL decoding processing method mainly includes the following steps:
  • m is a positive integer greater than 1, and select the LLR and the metric cumulative value of each stage cache of stage(1) to stage(m).
  • Each decoding path is synchronized from stage(1) to stage(m) to obtain LLR by stage.
  • the path formed from the root node of the code tree to any node in the decoding process corresponds to a path metric.
  • the information bit (bit) is extended to the path.
  • each layer selects L strips with larger path metric values in the current layer.
  • the path with the smallest absolute value of the metric in the path through the cyclic redundancy check is selected as the decoding result.
  • the present application provides a method for decoding a polarization code, so that the polarization code is decoded.
  • the decoding delay is reduced while maintaining good decoding performance. Considering the accuracy of the decoding result, the delay in the decoding process is considered, and the effect of reducing the decoding delay and ensuring the accuracy of the decoding result is achieved.
  • the communication system 100 includes a network device 102 that can include multiple antennas, such as antennas 104, 106, 108, 110, 112, and 114. Additionally, network device 102 may additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which may include multiple components related to signal transmission and reception (eg, processor, modulator, multiplexer) , encoder, demultiplexer or antenna, etc.).
  • a network device 102 can include multiple antennas, such as antennas 104, 106, 108, 110, 112, and 114.
  • network device 102 may additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which may include multiple components related to signal transmission and reception (eg, processor, modulator, multiplexer) , encoder, demultiplexer or antenna, etc.).
  • Network device 102 can communicate with a plurality of terminal devices, such as terminal device 116 and terminal device 122. However, it will be appreciated that network device 102 can communicate with any number of terminal devices similar to terminal device 116 or 122.
  • Terminal devices 116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other for communicating over wireless communication system 100. Suitable for equipment.
  • terminal device 116 is in communication with antennas 112 and 114, wherein antennas 112 and 114 transmit information to terminal device 116 over forward link 118 and receive information from terminal device 116 over reverse link 120.
  • terminal device 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to terminal device 122 over forward link 124 and receive information from terminal device 122 over reverse link 126.
  • the forward link 118 can utilize a different frequency band than that used by the reverse link 120, and the forward link 124 can utilize a different frequency band than that used by the reverse link 126.
  • the forward link 118 and the reverse link 120 can use a common frequency band
  • the forward link 124 and the reverse link 126 can use a common frequency band
  • Each antenna (or set of antennas consisting of multiple antennas) and/or regions designed for communication is referred to as a sector of network device 102.
  • the antenna group can be designed to communicate with terminal devices in sectors of the network device 102 coverage area.
  • the transmit antenna of network device 102 may utilize beamforming to improve the signal to noise ratio of forward links 118 and 124.
  • the network device 102 uses beamforming to transmit signals to the randomly dispersed terminal devices 116 and 122 in the relevant coverage area, the network device 102 uses a single antenna to transmit signals to all of its terminal devices. Mobile devices are subject to less interference.
  • network device 102, terminal device 116, or terminal device 122 may be a wireless communication transmitting device and/or a wireless communication receiving device.
  • the wireless communication transmitting device can encode the data for transmission.
  • the wireless communication transmitting device may acquire (eg, generate, receive from other communication devices, or store in memory, etc.) a certain number of data bits to be transmitted over the channel to the wireless communication receiving device.
  • Such data bits may be included in a transport block (or multiple transport blocks) of data that may be segmented to produce multiple code blocks.
  • the communication system 100 can be a PLMN network or a D2D network or an M2M network or other network.
  • FIG. 4 is only a simplified schematic diagram of an example, and the network may also include other network devices, which are not drawn in FIG. 4 .
  • FIG. 5 is a schematic flowchart of a method for decoding a polarization code 200 according to an embodiment of the present invention.
  • the method 200 can be applied to FIG.
  • the embodiment of the present invention is not limited thereto.
  • the decoding method 200 includes:
  • the data to be decoded when decoding the data to be decoded, the data to be decoded is first acquired, and then the data to be decoded is respectively subjected to serial offset list SCL decoding and serial offset SC translation.
  • the code that is, the data to be decoded is decoded in parallel by using two decoding methods. Due to the low complexity of the SC decoding process, there is only one candidate decoding path in the decoding process, which is relatively short in time. Therefore, the decoding result of the SC decoding (SC decoding result) is first obtained. When the SC decoding result is obtained, the SCL decoding of the data is in progress, that is, the SCL decoding has not ended yet, and the SCL decoding result has not been obtained yet.
  • the SC decoding result is not necessarily accurate, and it is necessary to determine whether to stop the SCL decoding of the data according to the SC decoding result. That is, in the case that it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and the decoding result of the SC decoding is output, that is, the decoding result of the SC decoding is used as the final decoding. result.
  • the method for decoding a polarization code performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • the method 200 further includes:
  • the decoding result is assumed SC obtained at time T 1, at this time, the decoded data SCL ongoing process, i.e., SCL translation The code has not finished yet, and the SCL decoding result has not been obtained yet. Therefore, in the case that it is determined that the decoding result of the SC decoding is incorrect, it is necessary to continue SCL decoding the data, and it is assumed that the SCL decoding result of the data is obtained at time T 2 , wherein the T 2 time is later than T At 1 o'clock, the decoding result of the SCL decoding is output, that is, the SCL decoding result is output as the final decoding result of the data.
  • the data start serial cancellation list SCL decoding and serial cancellation SC decoding respectively are performed, including:
  • serial offset list SCL decoding and the serial cancellation SC decoding are performed in parallel on the data.
  • SCL decoding and SC decoding may be performed on the data in parallel, that is, the time for performing SCL decoding and SC decoding on the data at least partially overlaps. Since the time taken for SC decoding is short, when the time for performing SCL decoding and SC decoding on the data at least partially overlaps, the length of time for obtaining the decoding result can be further shortened as a whole.
  • SCL decoding and SC decoding may be started on the data at the same time, so that the decoding delay may be further reduced.
  • the SC decoding result when performing SCL decoding and SC decoding on the data in parallel, the SC decoding result may be obtained earlier than the SCL decoding result.
  • the embodiments of the present invention are not limited herein.
  • the method for decoding a polarization code provided by the present application performs SCL decoding and SC decoding in parallel on the data to be decoded, and performs verification on the decoding result of the SC decoding first, and determines that the SC decoding result is correct. At the time, the SC decoding result is output as the final result of the decoding.
  • the decoding delay can be further reduced to improve the decoding efficiency.
  • the decoding method 200 further includes:
  • the SC decoding result is subjected to CRC check. That is, the CRC auxiliary code is used as an inner code, and is input into the data information to perform polarization code encoding as a part of the information symbol.
  • the SC decoding algorithm first generates an alternative decoding codeword, that is, the decoding result of the SC decoding, and then performs CRC decoding on the decoding result of the SC decoding, and decodes the CRC. The result is compared with the actually received CRC auxiliary code. If the two are the same, that is, the CRC check passes, it is determined that the decoding result of the SC decoding is correct. If the two are not the same, that is, the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
  • the decoding result of the SC decoding may be verified by other methods, for example, by using parity check (parity check,
  • parity check The embodiment of the present invention is not limited herein.
  • the search width of the SCL decoding is 8 decoding paths.
  • the search width in the SCL decoding process is 8, that is, there are 8 decoding paths simultaneously. The code delay is low and the decoding accuracy is relatively good.
  • the value of the search width in the SCL decoding process may be other values, for example, 2, or 4, or 16, or the like.
  • the embodiment of the present invention is not limited herein as long as the positive integer of the value of the decoding width is 2.
  • FIG. 6 is a schematic flow chart of a method for decoding a polarization code according to an embodiment of the present invention.
  • the flow of the typical SCL decoding processing mode is shown, and the lower half of the dotted line frame is the flow of the typical SC decoding processing mode.
  • the essence of SC decoding is SCL decoding of a single decoding path, and the two parts are executed in parallel. Since the number of decoding paths (path) of SC decoding is small, only two-choice path selection is needed, so the calculation is simple. Compared with the SCL decoding processing delay, the SC decoding result will be obtained earlier.
  • the SCL decoding is terminated by the decoding end decision, and the output is the SC decoding result.
  • the SCL needs to be executed, and finally the result of the SCL decoding is output.
  • the SCL decoding process is similar to the steps described in FIG. 3, and is not described here for brevity.
  • m is a positive integer greater than 1, and select the LLR and the metric cumulative value of each stage cache of stage(1) to stage(m).
  • Each decoding path is synchronized from stage(1) to stage(m) to obtain LLR by stage.
  • the method for decoding a polarization code utilizes the features of simple SC decoding, small delay, and high accuracy of SCL decoding, and performs SC decoding and SCL decoding in parallel through data to be decoded.
  • the SC decoding result obtained first is correct
  • the SC decoding result is taken as the final decoding result.
  • the decoding speed is improved, the decoding delay is reduced, the accuracy of the decoding result is ensured, and the decoding efficiency is improved.
  • the decoding method of the polarization code provided by the embodiment of the present invention is described in detail above with reference to FIG. 1 to FIG. 6.
  • the decoder provided by the embodiment of the present invention will be described in detail below with reference to FIG. 7 to FIG.
  • FIG. 7 shows a schematic block diagram of a decoder 300 according to an embodiment of the present invention.
  • the decoder 300 includes an acquisition circuit 310, an SCL decoding circuit 320, an SC decoding circuit 330, and an output circuit. 340.
  • the obtaining circuit 310 is configured to acquire data to be decoded.
  • the SCL decoding circuit 320 is configured to perform serial cancellation list SCL decoding on the data.
  • the SC decoding circuit 330 is configured to perform serial cancellation SC decoding on the data.
  • the SC decoding circuit 330 is also used to obtain the SC decoding result.
  • the SCL decoding circuit 320 is further configured to stop the SCL decoding.
  • the output circuit 340 is configured to output the decoded result of the SC decoding.
  • the decoder provided by the present application performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded, respectively. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • the SCL decoding circuit 320 is further configured to continue the SCL decoding.
  • the output circuit 340 is further configured to: output the decoded result of the SCL decoding.
  • the SCL decoding circuit 320 and the SC decoding circuit 330 decode the data in parallel.
  • the decoder 300 further includes a check circuit 350, configured to perform a cyclic redundancy CRC check on the decoded result of the SC decoding; In the case of passing, it is determined that the decoding result of the SC decoding is correct, or if the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
  • a check circuit 350 configured to perform a cyclic redundancy CRC check on the decoded result of the SC decoding; In the case of passing, it is determined that the decoding result of the SC decoding is correct, or if the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
  • the SCL decoding circuit 320 has a search width of eight decoding paths.
  • each circuit included in the decoder 300 may be composed of logic devices for supporting each circuit to perform the above various functions.
  • FIG. 8 is a schematic block diagram of a decoder 400 in accordance with an embodiment of the present invention.
  • the decoder 400 includes a processor 410, a memory 420, and a transceiver 430.
  • the processor 410, the memory 420, and the transceiver 430 communicate with each other through an internal connection path to transfer control and/or data signals. .
  • This memory 410 is used to store program code.
  • the transceiver 430 is configured to perform specific signal transceiving under the driving of the processor 410 to implement the decoding method in the above embodiments.
  • the processor 420 is configured to invoke the program code to implement the decoding method in the above embodiments of the present invention.
  • the decoder provided by the present application performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded, respectively. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • the various components in decoder 400 communicate with one another via a communication connection, i.e., processor 410, memory 420, and transceiver 430, through internal connection paths, to communicate control and/or data signals.
  • a communication connection i.e., processor 410, memory 420, and transceiver 430
  • the foregoing method embodiments of the present application may be applied to a processor, or the processor may implement the steps of the foregoing method embodiments.
  • the processor may be an integrated circuit chip with signal processing capabilities.
  • each step of the foregoing method embodiments may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software. To avoid repetition, it will not be described in detail here.
  • the above processor may be a central processing unit (CPU), a network processor (NP) or a combination of a CPU and an NP, a digital signal processor (DSP), an application specific integrated circuit (application). Specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component.
  • CPU central processing unit
  • NP network processor
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in connection with the present application may be directly embodied by the execution of the hardware decoding processor or by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method.
  • the memory 420 can include read only memory and random access memory and provides instructions and data to the processor 410. A portion of the memory 420 may also include a non-volatile random access memory. For example, the memory 420 can also store information of the device type.
  • a person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.
  • the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (ROMM), an erasable programmable read only memory (erasable PROM, EPROM), or an electrical Erase programmable EPROM (EEPROM) or flash memory.
  • ROM read-only memory
  • PROM programmable read only memory
  • EEPROM electrical Erase programmable EPROM
  • the processor 410 may be implemented by a processing module
  • the memory 420 may be implemented by a storage module
  • the transceiver 430 may be implemented by a transceiver module.
  • the decoder 500 may include a processing module 510.
  • the decoder 400 shown in FIG. 8 or the decoder 500 shown in FIG. 9 can implement the steps shown in FIG. 5 and FIG. 6 described above. To avoid repetition, details are not described herein again.
  • the embodiment of the present invention further provides a readable medium for storing program code, the program code comprising instructions for executing the decoding method of the polarization code of the embodiment of the present invention in FIG. 5 and FIG.
  • the readable medium may be a ROM or a RAM, which is not limited in the embodiment of the present invention.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

Cette invention concerne un procédé de décodage et un décodeur pour un code polaire. Le procédé de décodage consiste à : acquérir des données à décoder ; commencer respectivement à exécuter un décodage par annulations successives en liste (SCL) et un décodage par annulations successives (SC) sur les données ; obtenir un résultat de décodage du décodage SC ; lorsqu'il est déterminé que le résultat de décodage du décodage SC est correct, arrêter le décodage SCL ; et délivrer en sortie le résultat de décodage du décodage SC. Le procédé de décodage pour un code polaire selon l'invention peut respectivement effectuer un décodage SCL et un décodage SC sur des données à décoder, et lorsqu'il est déterminé qu'un résultat de décodage du décodage SC est correct, le résultat de décodage SC est délivré en sortie en tant que résultat de décodage final des données et le décodage SCL sur les données est arrêté. L'invention permet de réduire un retard de décodage et d'améliorer le rendement de décodage en partant du principe que la performance de décodage précise du décodage d'un code polaire est assurée.
PCT/CN2018/102297 2017-08-25 2018-08-24 Procédé de décodage et décodeur pour codes polaires WO2019037782A1 (fr)

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