WO2018157462A1 - 一种数字化预失真线性化器 - Google Patents

一种数字化预失真线性化器 Download PDF

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Publication number
WO2018157462A1
WO2018157462A1 PCT/CN2017/081889 CN2017081889W WO2018157462A1 WO 2018157462 A1 WO2018157462 A1 WO 2018157462A1 CN 2017081889 W CN2017081889 W CN 2017081889W WO 2018157462 A1 WO2018157462 A1 WO 2018157462A1
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Prior art keywords
attenuator
diode
digitized
predistortion linearizer
attenuation
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PCT/CN2017/081889
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English (en)
French (fr)
Inventor
贾鹏程
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广州程星通信科技有限公司
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Publication of WO2018157462A1 publication Critical patent/WO2018157462A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H03F1/3276—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using the nonlinearity inherent to components, e.g. a diode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to signal predistortion techniques, and more particularly to a digital predistortion linearizer.
  • the so-called pre-distortion is to pre-distort the signal entering the power amplifier to compensate the nonlinear distortion of the power amplifier.
  • phase distortion occurs, that is, a certain phase shift occurs when the signal passes through the power amplifier, and the magnitude of the phase shift varies with the input power. Therefore, the predistorter not only compensates for the output amplitude of the amplifier, but also compensates for its phase.
  • the predistorter parameters are adjusted so that the nonlinear characteristics of the predistorter and the nonlinear characteristics of the power amplifier are opposite, so that the cascade of the two nonlinear systems is represented as a linear system, and the specific principle diagram is shown in FIG. 1 .
  • a digital pre-distortion linearizer comprising:
  • a signal processing circuit for including a parallel diode and a series diode
  • control module for controlling an input power of the parallel diode and/or the series diode
  • the parallel diode is connected to a series diode, and the control module is connected to a parallel diode and/or a series diode.
  • control module includes an attenuator and a processor for controlling an attenuation of the attenuator by controlling, thereby controlling an input power of the parallel diode and/or the series diode, the processor being coupled to the attenuator, the attenuation
  • the device is connected to a parallel diode and/or a series diode.
  • the processor is further configured to control the current flowing through the parallel diode and/or the series diode.
  • bias circuit is included that is coupled to the parallel diode and/or series diode.
  • the attenuator includes a first attenuator
  • the processor is specifically configured to control the input power of the parallel diode by controlling the attenuation gain of the first attenuator.
  • the attenuator includes a second attenuator
  • the processor is specifically configured to control the input power of the series diode by controlling the attenuation gain of the second attenuator.
  • a third attenuator is further included, the third attenuator being disposed at a signal output end of the signal processing circuit.
  • control adjusts an attenuation gain of the attenuator, which is specifically:
  • the attenuation value of the corresponding attenuator is optimized, and the interpolation method is used to fit the attenuation value of the corresponding attenuator;
  • the obtained attenuation gain optimum value of the attenuator is written into the attenuator.
  • the two dimensions of the pre-stored two-dimensional table are temperature and output power, respectively, and the table content in the pre-stored two-dimensional table is an attenuation gain optimal value of the attenuator corresponding to the temperature and the output power.
  • the attenuation gain optimal value of the attenuator includes the following steps:
  • the attenuation gain of the attenuator is scanned, and the third-order intermodulation component of the signal output by the digitized predistortion linearizer is performed. Detection, when the third-order intermodulation component result is the minimum value, the attenuation gain of the currently scanned attenuator is the attenuation gain optimum value of the attenuator.
  • the invention has the beneficial effects that the digital predistortion linearizer of the present invention controls the input power of the parallel diode and/or the series diode through the control module, so that the power of the parallel diode and the series diode for predistortion is maintained in their respective places.
  • the series predistortion of the series diodes produces a large nonlinear slope, so that the two are effectively combined and connected.
  • the ability to generate nonlinear components of arbitrary curvature ensures that it can be cancelled with nonlinear distortion of different power amplifiers. It can be seen that the digital pre-distortion linearizer of the present invention not only has high compatibility and adjustable flexibility, but also has an ideal pre-distortion effect, which can ensure nonlinear distortion cancellation with different power amplifiers.
  • 1 is a schematic diagram showing the principle of a cascade of two nonlinear systems as a linear system
  • FIG. 2 is a schematic structural view of a digital predistortion linearizer of the present invention
  • FIG. 3 is a schematic structural view of a first embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 4 is a schematic structural view of a second embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 5 is a schematic structural view of a third embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 6 is a schematic structural view of a fourth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 7 is a schematic structural view of a fifth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 8 is a schematic structural view of a sixth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 9 is a schematic structural view of a seventh embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 10 is a schematic structural view of an eighth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 11 is a schematic structural view of a ninth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 12 is a schematic structural view of a tenth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 13 is a schematic structural view of an eleventh embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 14 is a schematic structural view of a twelfth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 15 is a schematic structural view of a thirteenth embodiment of a digital predistortion linearizer according to the present invention.
  • 16 is a schematic structural view of a fourteenth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 17 is a schematic structural view of a fifteenth embodiment of a digital predistortion linearizer according to the present invention.
  • FIG. 18 is a schematic structural view of a sixteenth embodiment of a digital predistortion linearizer according to the present invention.
  • 19 is a schematic diagram of a method for finding an optimum value of attenuation gain of three attenuators
  • 20 is a schematic diagram of phase distortion of a power amplifier
  • 21 is a schematic diagram of phase distortion generated by a parallel diode
  • Figure 22 is a schematic diagram of phase distortion generated by a series diode
  • Figure 23 is a schematic illustration of the overall phase distortion produced by a digital predistortion linearizer of the present invention.
  • ATT1 first attenuator; ATT2, second attenuator; ATT3, third attenuator; D1, parallel diode; D2, series diode; R1, first resistance; R2, second resistance; L1, first inductance; L2 Second inductance; L3, third inductance; C1, first capacitance; C2, second capacitance; C3, third capacitance; C4, fourth capacitance.
  • the present invention provides a digital predistortion linearizer, as shown in FIG. 2, which includes:
  • a signal processing circuit for including a parallel diode and a series diode; wherein the parallel diode refers to a diode connected in a circuit in a parallel connection, the series diode refers to a diode connected in series in a series connection;
  • control module for controlling an input power of the parallel diode and/or the series diode
  • the parallel diode is connected to a series diode, and the control module is connected to a parallel diode and/or a series diode.
  • the radio frequency signal is processed by a signal processing circuit and output.
  • connection relationship between the parallel diode and the series diode it can be a parallel connection relationship.
  • the accessed RF signal passes through the parallel diode to output the first RF signal, and the accessed RF signal is output through the series diode.
  • the second RF signal is then superimposed and outputted by the first RF signal and the second RF signal; or it may be a series connection relationship, as shown in FIG. 4, the accessed RF signal is sequentially output through the parallel diode and the series diode, or As shown in FIG. 5, the accessed RF signal is sequentially output through a series diode and a parallel diode.
  • control module includes an attenuator and a processor for controlling an attenuation gain of the attenuator by controlling, thereby controlling an input power of the parallel diode and/or the series diode, the processor and the processor An attenuator is connected, the attenuator being connected to a parallel diode and/or a series diode.
  • the attenuator includes a first attenuator, and the processor is specifically configured to control and adjust an input gain of the parallel diode by controlling an attenuation gain of the first attenuator.
  • the first attenuator is disposed at a front end of the parallel diode;
  • connection relationship between the parallel diode and the series diode is a parallel connection relationship, as shown in FIG. 3, the accessed RF signal sequentially passes through the first attenuator and the parallel diode to output the first RF signal;
  • the accessed RF signal is sequentially output through the first attenuator, the parallel diode, and the series diode, or as shown in FIG.
  • the accessed RF signal is sequentially output through a series diode, a first attenuator, and a parallel diode.
  • the attenuator includes a second attenuator, and the processor is specifically configured to control the input power of the series diode by controlling the attenuation gain of the second attenuator.
  • the second attenuator is disposed at a front end of the series diode;
  • connection relationship between the parallel diode and the series diode is a parallel connection relationship, as shown in FIG. 3, the accessed RF signal sequentially passes through the second attenuator and the series diode to output the second RF signal;
  • connection relationship between the parallel diode and the series diode is a series connection relationship, as shown in FIG. 4, the accessed RF signal is sequentially output through the parallel diode, the second attenuator, and the series diode, or, as shown in FIG.
  • the accessed RF signal is sequentially output through the second attenuator, the series diode, and the parallel diode.
  • the corresponding settings may be made according to actual conditions, for example, only the first attenuator or the second attenuator, or the first attenuator and the second attenuator are provided. Set at the same time.
  • the first attenuator and the second attenuator are simultaneously disposed.
  • the third attenuator is further disposed at a signal output end of the signal processing circuit, that is, the radio frequency signal output by the signal processing circuit is processed by the third attenuator, and then output. That is, the third attenuator is connected to the parallel diode and/or the series diode, as shown in particular in FIGS. 3 to 5.
  • the third attenuator is connected to the processor, and the processor is further configured to control the attenuation gain of the third attenuator to generate the parallel diode and the series diode.
  • the combination of the nonlinear signals that is, the nonlinear signals output by the signal processing circuit, adjusts the curvature, which further improves the compatibility and flexibility of the operation.
  • the processor is further configured to control the current flowing through the parallel diode and/or the series diode.
  • a bias circuit is further included, which is connected to the parallel diode and/or the series diode.
  • the bias circuit is primarily used to provide a bias voltage for the parallel diode and/or the series diode, in combination with a parallel diode and/or a series diode to form a loop, thereby allowing the parallel diode and/or series diode to function properly.
  • the processor is further configured to control the current flowing through the parallel diode and/or the series diode by controlling the bias circuit, the processor being coupled to the bias circuit.
  • control adjusts an attenuation gain of the attenuator, which is specifically:
  • the attenuation value of the corresponding attenuator is optimized, and the interpolation method is used to fit the attenuation value of the corresponding attenuator;
  • the obtained attenuation gain optimum value of the attenuator is written into the attenuator.
  • the two dimensions of the pre-stored two-dimensional table are temperature and output power, respectively, and the table content in the pre-stored two-dimensional table is the attenuation of the attenuator corresponding to the temperature and the output power.
  • the optimum value of the gain is the maximum value of the gain.
  • the attenuation gain optimal value of the attenuator includes the following steps:
  • the attenuation gain of the attenuator is scanned, and the third-order intermodulation component of the signal output by the digitized predistortion linearizer is performed. Detection, when the third-order intermodulation component result is the minimum value, the attenuation gain of the currently scanned attenuator is the attenuation gain optimum value of the attenuator.
  • a digitized predistortion linearizer specifically includes a first attenuator ATT1, a parallel diode D1, a second attenuator ATT2, a series diode D2, and a processor for controlling the attenuation gains of the adjustment ATT1 and ATT2 ( Not shown in FIG. 6), the accessed radio frequency signals are sequentially outputted after ATT1, D1, ATT2, and D2;
  • the anode of D1 is connected between the output end of ATT1 and the input end of ATT2, the negative pole of D1 is grounded; the anode of D2 is connected with the output end of ATT2, and the cathode of D2 is used as the output end of radio frequency signal.
  • a third attenuator ATT3 is further included, and the third attenuator ATT3 is disposed at a signal output end of the signal processing circuit, that is, as shown in FIG. 6, the negative pole of D2 is connected to the input end of the ATT3. .
  • the ATT3 is connected to the processor.
  • a bias circuit is further included, which is connected to D1 and D2, respectively.
  • the processor is further configured to control the current flowing through D1 and D2 by controlling the bias circuit.
  • a digital predistortion linearizer specifically includes a first attenuator ATT1, a parallel diode D1, a second attenuator ATT2, a series diode D2, and a processor for controlling the attenuation gains of the adjustments ATT1 and ATT2 ( Not shown in FIG. 7), the accessed radio frequency signals are sequentially outputted after ATT1, D1, ATT2, and D2;
  • the anode of D1 is connected between the output terminal of ATT1 and the input terminal of ATT2, the cathode of D1 is grounded, the cathode of D2 is connected with the output end of ATT2, and the anode of D2 is used as the output terminal of the radio frequency signal.
  • a third attenuator ATT3 is further included, and the third attenuator ATT3 is disposed at a signal output end of the signal processing circuit, that is, as shown in FIG. 7, the anode of the D2 is connected to the input end of the ATT3. .
  • the ATT3 is connected to the processor.
  • a bias circuit is further included, which is connected to D1 and D2, respectively.
  • the processor is further configured to control the current flowing through D1 and D2 by controlling the bias circuit.
  • a digitized predistortion linearizer specifically includes a first attenuator ATT1, a parallel diode D1, a second attenuator ATT2, a series diode D2, and a processor for controlling the attenuation gains of the adjustment ATT1 and ATT2 ( Not shown in FIG. 8), the accessed radio frequency signals are sequentially outputted after ATT1, D1, ATT2, and D2;
  • the negative electrode of D1 is connected between the output end of ATT1 and the input end of ATT2, the positive pole of D1 is grounded; the positive pole of D2 is connected with the output end of ATT2, and the negative pole of D2 is used as the output end of radio frequency signal.
  • a third attenuator ATT3 is further included, and the third attenuator ATT3 is disposed at a signal output end of the signal processing circuit, that is, as shown in FIG. 8, the negative pole of D2 is connected to the input end of ATT3. .
  • the ATT3 is connected to the processor.
  • a bias circuit is further included, which is connected to D1 and D2, respectively.
  • the processor is further configured to control the current flowing through D1 and D2 by controlling the bias circuit.
  • a digital predistortion linearizer specifically includes a first attenuator ATT1, a parallel diode D1, a second attenuator ATT2, a series diode D2, and a processor for controlling the attenuation gain of the adjustment ATT1 and ATT2 ( Not shown in FIG. 9), the accessed radio frequency signals are sequentially outputted after ATT1, D1, ATT2, and D2;
  • the negative pole of D1 is connected between the output end of ATT1 and the input end of ATT2, the positive pole of D1 is grounded; the negative pole of D2 is connected with the output end of ATT2, and the positive pole of D2 is used as the output end of radio frequency signal.
  • a third attenuator ATT3 is further included, and the third attenuator ATT3 is disposed at a signal output end of the signal processing circuit, that is, as shown in FIG. 9, the anode of the D2 is connected to the input end of the ATT3. .
  • the ATT3 is connected to the processor.
  • a bias circuit is further included, which is connected to D1 and D2, respectively.
  • the processor is further configured to control the current flowing through D1 and D2 by controlling the bias circuit.
  • connection relationship between D1 and D2 is a series relationship, and D1 is disposed at the front end of D2; for one end of D1 connected between the output end of ATT1 and the output end of ATT2, It is the positive or negative pole of D1, and the other end of D1 is correspondingly grounded; for the end of D2 connected to the output end of ATT2, it can also be the positive or negative pole of D2, and the other end of D2 acts as the RF signal output end.
  • the bias circuit connected to D1 and D2 according to the polarity of the bias voltage provided by itself, it can be connected to the positive or negative pole of D1 (D2), which can be connected according to actual conditions. .
  • a digital predistortion linearizer specifically includes a second attenuator ATT2, a series diode D2, a first attenuator ATT1, a parallel diode D1, and a processor for controlling the attenuation gains of the adjustment ATT1 and ATT2 ( Not shown in FIG. 10), the accessed radio frequency signals are sequentially outputted after ATT2, D2, ATT1, and D1;
  • the anode of D2 is connected to the output end of ATT2, the cathode of D2 is connected to the input end of ATT1, the anode of D1 is connected to the output end of ATT1, the cathode of D1 is grounded, and the anode of D1 is output as a radio frequency signal. end.
  • a third attenuator ATT3 is further provided, and the third attenuator ATT3 is disposed at a signal output end of the signal processing circuit, that is, as shown in FIG. 10, the anode of the D1 is connected to the input end of the ATT3. .
  • the ATT3 is connected to the processor.
  • a bias circuit is further included, which is connected to D1 and D2, respectively.
  • the processor is further configured to control the current flowing through D1 and D2 by controlling the bias circuit.
  • a digital predistortion linearizer specifically includes a second attenuator ATT2, a series diode D2, a first attenuator ATT1, a parallel diode D1, and a processor for controlling the attenuation gain of the adjustment ATT1 and ATT2 ( Not shown in FIG. 11), the accessed radio frequency signals are sequentially output after ATT2, D2, ATT1, and D1;
  • the anode of D2 is connected to the output end of ATT2, the cathode of D2 is connected to the input end of ATT1, the cathode of D1 is connected to the output end of ATT1, the anode of D1 is grounded, and the cathode of D1 is output as a radio frequency signal. end.
  • a third attenuator ATT3 is further provided, and the third attenuator ATT3 is disposed at a signal output end of the signal processing circuit, that is, as shown in FIG. 11, the negative pole of D1 is connected to the input end of ATT3. .
  • the ATT3 is connected to the processor.
  • a bias circuit is further included, which is connected to D1 and D2, respectively.
  • the processor is further configured to control the current flowing through D1 and D2 by controlling the bias circuit.
  • a digital pre-distortion linearizer specifically includes a second attenuator ATT2, a series diode D2, a first attenuator ATT1, a parallel diode D1, and a processor for controlling the attenuation gain of the adjustment ATT1 and ATT2 ( Not shown in FIG. 12), the accessed radio frequency signals are sequentially outputted after ATT2, D2, ATT1, and D1;
  • the negative pole of D2 is connected to the output end of ATT2
  • the positive pole of D2 is connected to the input end of ATT1
  • the positive pole of D1 is connected to the output end of ATT1
  • the negative pole of D1 is grounded
  • the positive pole of D1 is output as radio frequency signal. end.
  • a third attenuator ATT3 is further provided, and the third attenuator ATT3 is disposed at a signal output end of the signal processing circuit, that is, as shown in FIG. 12, the anode of the D1 is connected to the input end of the ATT3. .
  • the ATT3 is connected to the processor.
  • a bias circuit is further included, which is connected to D1 and D2, respectively.
  • the processor is further configured to control the current flowing through D1 and D2 by controlling the bias circuit.
  • a digital pre-distortion linearizer specifically includes a second attenuator ATT2, a series diode D2, a first attenuator ATT1, a parallel diode D1, and a processor for controlling the attenuation gains of the adjustment ATT1 and ATT2 ( Not shown in FIG. 13), the accessed radio frequency signals are sequentially outputted after ATT2, D2, ATT1, and D1;
  • the negative pole of D2 is connected to the output end of ATT2, the positive pole of D2 is connected to the input end of ATT1, the negative pole of D1 is connected to the output end of ATT1, the positive pole of D1 is grounded, and the negative pole of D1 is output as radio frequency signal. end.
  • a third attenuator ATT3 is further included, and the third attenuator ATT3 is disposed at a signal output end of the signal processing circuit, that is, as shown in FIG. 13, the negative pole of D1 is connected to the input end of ATT3. .
  • the ATT3 is connected to the processor.
  • a bias circuit is further included, which is connected to D1 and D2, respectively.
  • the processor is further configured to control the current flowing through D1 and D2 by controlling the bias circuit.
  • connection relationship between D1 and D2 is a series relationship, and D2 is disposed at the front end of D1; for one end of D2 connected to the output end of ATT2, it may be the positive or negative pole of D2.
  • the other end of D2 is correspondingly connected to the input end of ATT1; for one end of D1 connected to the output end of ATT1, it may be the positive or negative pole of D1, and the other end of D1 is grounded.
  • the bias circuit connected to D1 and D2 according to the polarity of the bias voltage provided by itself, it can be connected to the positive or negative pole of D1 (D2), which can be connected according to actual conditions. .
  • connection relationship between D1 and D2 in the above solution is a series connection relationship
  • connection relationship between D1 and D2 is a parallel connection relationship
  • the connection relationship between D1 and D2 is different, and the other contents are basically the same as those of the above embodiment. Therefore, based on the contents of the above embodiment, a specific embodiment of a scheme in which the connection relationship between D1 and D2 is a parallel connection relationship can be obtained.
  • connection relationship between D1 and D2 is a series connection relationship
  • D1 is disposed at the front end of D2
  • the bias circuit includes a first bias circuit for providing a bias voltage for D1, and for A second bias circuit that provides a bias voltage for D2.
  • a digitized predistortion linearizer specifically includes a first attenuator ATT1, a first bias circuit, a parallel diode D1, a second attenuator ATT2, a second bias circuit, a series diode D2, and a third An attenuator ATT3 and a processor for controlling an attenuation gain of the first attenuator ATT1, the second attenuator ATT2, and the third attenuator ATT3, the processor and the first attenuator ATT1, the second attenuator ATT2, and The third attenuator ATT3 is connected;
  • the first bias circuit is connected to D1
  • the second bias circuit is connected to D2
  • the first attenuator ATT1 sequentially passes through the parallel diode D1, the second attenuator ATT2, and the series diode D2 and the third attenuator ATT3. connection.
  • the output end of ATT1 is respectively connected to one end of D1 and the input end of ATT2, the other end of D1 is grounded, the output end of the ATT2 is connected to one end of D2, and the other end of D2 is connected with ATT3.
  • the input is connected.
  • the working principle is as follows: after the RF signal is input to the first attenuator ATT1, the RF output is processed through D1, ATT2, D2 and ATT3 in sequence; wherein the processor adjusts the ATT1 through control
  • the attenuation gain of ATT2, thereby adjusting the input power of the signal keeps the power entering the parallel predistortion diode D1 and the series predistortion diode D2 at their respective required levels, and the nonlinearity caused by the parallel predistortion formed by D1
  • the slope of the series is small, and the series predistortion formed by D2 produces a large nonlinear slope.
  • the two are effectively combined, and the input power of the signal is adjusted by adjusting ATT1 and ATT2, so that nonlinearity of arbitrary curvature can be generated.
  • the component is guaranteed to be canceled by different power amplifiers, and the processor can also control the ATT3 attenuation gain, thereby combining the nonlinear signals generated by D1 and D2, that is, the nonlinear signals output by the signal processing circuit. Rate adjustment. Therefore, the digital pre-distortion linearizer of the present invention has high compatibility and adjustable flexibility, and has an ideal pre-distortion effect, and has the advantages of being easy to implement, small in size, low in cost, and the like.
  • the first bias circuit includes a first voltage control circuit and a first resistor R1, and an output end of the first voltage control circuit is connected to one end of R1.
  • the other end of R1 is connected to D1.
  • the processor is connected to the first voltage control circuit, and the processor is further configured to control the voltage outputted by the first voltage control circuit to cooperate with R1 to control the current flowing through D1.
  • the circuit structure of the first bias circuit and the second bias circuit may be the same or different, and may be set according to actual needs.
  • the first bias circuit and the second bias circuit have the same circuit structure, that is, the second bias circuit includes a second voltage control circuit and a second resistor R2.
  • the output of the second voltage control circuit is connected to one end of R2, and the other end of R2 is connected to D2.
  • the processor is connected to a second voltage control circuit, and the processor is further configured to control the voltage outputted by the second voltage control circuit to cooperate with R2 to control the current flowing through D2.
  • first resistor R1 and the second resistor R2 may be replaced by the first inductor L1 and the second inductor L2, respectively.
  • first resistor R1 and the first inductor L1 may be connected in series. The latter is connected between the output of the first voltage control circuit and D1, and the second resistor R2 and the second inductor L2 are connected in series and connected between the output of the second voltage control circuit and D2. This allows the processor to regulate the voltage across the D1 and D2 by controlling the voltage output from the voltage control circuit to match the resistor and / inductor.
  • bias circuit in this embodiment can be applied to other embodiments.
  • the isolation capacitance and the inductance are correspondingly increased in the circuit.
  • it can be applied to other embodiments.
  • a digital predistortion linearizer includes a first attenuator ATT1, a first capacitor C1, a parallel diode D1, a second capacitor C2, a second attenuator ATT2, a third capacitor C3, and a series diode D2.
  • the output end of the ATT1 is connected to one end of C1, and the other end of C1 is respectively connected to one end of D1 and one end of C2, the other end of D1 is grounded, the other end of C2 is connected with the input end of ATT2, and the output end of ATT2 is connected with C3.
  • One end is connected, the other end of C3 is connected to one end of D2, and the other end of D2 is respectively connected with one end of L3 and one end of C4, the other end of L3 is grounded, and the other end of C4 is connected with the input end of ATT3;
  • the first voltage control circuit is connected to one end of R1, the other end of R1 is connected to one end of L1, the other end of L1 is connected to D1, the second voltage control circuit is connected to one end of R2, and the other end of R2 is connected with L1. One end is connected, and the other end of L1 is connected to D2.
  • the voltage value output by the first voltage control circuit is V1
  • the voltage value output by the second voltage control circuit is V2
  • the attenuation gain of the ATT1 is att1
  • the attenuation gain of ATT2 is att2
  • the attenuation gain of ATT3 For att3.
  • the processor can adjust the nonlinear slope of the signals generated by D1 and D2 by controlling the attenuation gains of ATT1, ATT2, and ATT3, and the processor can also adjust the output voltages of the first voltage control circuit and the second voltage control circuit by controlling V1 and V2, thereby matching the first resistor R1, the first inductor L1 and the second resistor R2, and the second inductor L2 to regulate the current flowing through D1 and D2.
  • the processor can generate any form of phase distortion and amplitude distortion according to the nonlinear characteristics of each power amplifier, realize the cancellation of the nonlinear component of the power amplifier, and also add the flow of D1 and D2.
  • the current control adjustment means that the adjustment flexibility is higher and the precision is higher, so that the nonlinear component of the output signal and the nonlinear component of the power amplifier have a higher matching degree, so that the power amplifier achieves the best linearization effect.
  • the phase predistortion is realized by the digital predistortion linearizer of the present invention, which is specifically shown in FIGS. 20 to 23. As shown in Figure 20, it is the phase distortion produced by the power amplifier, which is positive. As shown in FIG. 21 and FIG. 22, the phase distortion generated by the parallel predistortion diode D1 and the phase distortion generated by the series predistortion diode D2 are respectively shown by the parallel predistortion diode D1. The amplitude of the phase distortion is small, and the amplitude of the phase distortion generated by the series predistortion diode D2 is large.
  • phase distortion is completely cancelled, and the digital predistortion linearizer of the present invention adjusts the attenuation gain of the attenuator by the processor, and adjusts the controls V1, V2, and effectively combines D1 and D2, so the present invention
  • the phase distortion output by the digital predistortion linearizer as shown in Figure 23, fully produces a phase distortion curve that matches the power amplifier.
  • the processor of the embodiment is provided with a control algorithm, by which an optimal digital working state can be automatically generated, and the digital control of the linearizer is realized.
  • the means for controlling the attenuation gain of the attenuator is specifically:
  • the attenuation value of the corresponding attenuator is optimized, and the interpolation method is used to fit the attenuation value of the corresponding attenuator;
  • the obtained attenuation gain optimum value of the attenuator is written into the attenuator.
  • the means for adjusting the attenuation gain of the attenuator for the control is specifically:
  • ATT1's attenuation gain optimal value ATT2's attenuation gain optimal value and/or ATT3's attenuation gain optimal value. Otherwise, the interpolation method is used to fit the corresponding ATT1 attenuation gain optimal value, ATT2 The optimum value of the attenuation gain and/or the attenuation value of the ATT3;
  • the obtained ATT1 attenuation gain optimum value, the ATT2 attenuation gain optimum value, and/or the ATT3 attenuation gain optimum value are written into ATT1, ATT2, and/or ATT3, respectively.
  • the two dimensions are temperature and output power
  • the table contents in the table are the attenuation gain optimal value of ATT1 corresponding to temperature and output power, the attenuation gain optimal value of ATT2, and / or ATT3's attenuation gain optimum.
  • the obtaining steps include:
  • the digital pre-distortion linearizer is placed in the thermostat for changing different temperatures; and a vector signal source is connected to the input end of the linearizer for generating a double that can evaluate the intermodulation output.
  • the sound signal is connected to the spectrum analyzer at the output end of the linearizer, and the size of the third-order intermodulation component, that is, the third-order intermodulation component result can be directly read out; and the external computer is used to respectively separate the processor, the temperature box, and the vector.
  • the signal source is connected to the spectrum analyzer;
  • the temperature is divided into T1 to TN, a total of N temperature value points, and then according to the range of output power, the output power is divided into P1 to PM, a total of M output power value points;
  • the variables are only att1, att2, and/or att3.
  • the variables can be regarded as a cube composed of many points. Each node in the cube corresponds to a specific att1, att2, and/or att3. value;
  • the external computer controls the processor, uses a preferred algorithm, such as the Quasi-Newton algorithm, to scan att1, att2, and/or att3, and simultaneously detects the third-order intermodulation component result of the spectrum analyzer output, that is, the digital predistortion linearizer
  • the output signal is detected by the third-order intermodulation component.
  • the current search scans att1, att2, and/or att3 is the optimal value, then for each The temperature value point and the output power value point all correspond to the optimum values of att1, att2, and/or att3, as shown in FIG.
  • a two-dimensional table is established, and the two dimensions respectively correspond to the temperature and the output power, and the values in the table are the optimal values of att1, att2 and/or att3 corresponding to the temperature and the output power.
  • the digitized predistortion linearizer in this embodiment further includes a temperature sensor and an output power detecting circuit, and an input end of the output power detecting circuit and an output end of the signal processing circuit, Or the output of the third attenuator is connected, and the output of the output power detecting circuit and the output of the temperature sensor are both connected to the input end of the processor.
  • the temperature detected by the temperature sensor and the output power detected by the output power detection circuit are sent to the processor.
  • the attenuator may be a digital attenuator or an attenuator.

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Abstract

一种数字化预失真线性化器，包括用于包含有并联二极管和串联二极管信号的处理电路，以及用于控制调节并联二极管和/或串联二极管的输入功率的处理器，所述并联二极管和串联二极管连接，所述控制模块与并联二极管和/或串联二极管连接。该数字化预失真线性化器不仅兼容性和可调灵活性高，而且预失真效果理想，可保证与不同的功率放大器的非线性失真对消，可广泛应用于预失真线性化领域中。

Description

一种数字化预失真线性化器
技术领域
本发明涉及信号预失真技术，尤其涉及一种数字化预失真线性化器。
背景技术
所谓预失真，就是预先对进入功放的信号进行失真处理，用来补偿功放的非线性失真。对于功率放大器，其除了幅度失真还会产生相位失真，即信号通过功率放大器时会产生一定的相移，相移的大小随输入功率的大小而变化。因此，预失真器不仅要对功放的输出幅度进行补偿，还要对其相位进行补偿。通常在理想条件下，调节预失真器参数使得预失真器非线性特性和功放非线性特性相反，从而使得两非线性系统的级联表现为线性系统，其具体原理示意图如图1所示。然而，由于功放的非线性特性往往各不相同，导致线性化器所需产生的幅度失真和相位失真也各不相同，而普通的模拟预失真则是完全依赖产生非线性分量的二极管的特性来实现的，也就是说，普通的模拟预失真难以根据不同功率放大器的非线性特性而进行针对性的调整，从而适应不同的功率放大器，兼容性和可调灵活性差。
发明内容
为了解决上述技术问题，本发明的目的是提供一种数字化预失真线性化器。
本发明所采用的技术方案是：一种数字化预失真线性化器，包括：
信号处理电路，用于包含有并联二极管和串联二极管；
控制模块，用于控制调节并联二极管和/或串联二极管的输入功率；
所述并联二极管和串联二极管连接，所述控制模块与并联二极管和/或串联二极管连接。
进一步，所述控制模块包括衰减器和用于通过控制调节衰减器的衰减增益，从而控制调节并联二极管和/或串联二极管的输入功率的处理器，所述处理器与衰减器连接，所述衰减器与并联二极管和/或串联二极管连接。
进一步，所述处理器还用于控制调节流经并联二极管和/或串联二极管的电流。
进一步，还包括偏置电路，所述偏置电路与并联二极管和/或串联二极管连接。
进一步，所述衰减器包括第一衰减器，所述处理器具体用于通过控制调节第一衰减器的衰减增益，从而控制调节并联二极管的输入功率。
进一步，所述衰减器包括第二衰减器，所述处理器具体用于通过控制调节第二衰减器的衰减增益，从而控制调节串联二极管的输入功率。
进一步，还包括第三衰减器，所述第三衰减器设置在信号处理电路的信号输出端。
进一步，所述控制调节衰减器的衰减增益，其具体为：
根据检测到的温度和输出功率，判断预存的二维表格中是否存有相对应的温度和输出功率，若有，则根据检测到的温度和输出功率，从预存的二维表格中查找出相对应的衰减器的衰减增益最优值，反之，则利用插值方法从而拟合出相对应的衰减器的衰减增益最优值；
将得到的衰减器的衰减增益最优值写入衰减器中。
进一步，所述预存的二维表格的两个维度分别为温度和输出功率，所述预存的二维表格中的表格内容为温度和输出功率相对应的衰减器的衰减增益最优值。
进一步，所述衰减器的衰减增益最优值，其获取步骤包括有：
当环境温度达到目标温度且数字化预失真线性化器的输出功率达到目标输出功率时，对衰减器的衰减增益进行扫描，并且对数字化预失真线性化器所输出的信号进行三阶交调分量的检测，当三阶交调分量结果为最小值时，当前扫描到的衰减器的衰减增益则为衰减器的衰减增益最优值。
本发明的有益效果是：本发明的数字化预失真线性化器通过控制模块来控制调节并联二极管和/或串联二极管的输入功率，使得用于预失真的并联二极管和串联二极管的功率保持在各自所需的水平上，而且由于并联二极管的并联预失真所产生的非线性的斜率较小，串联二极管的串联预失真所产生的非线性的斜率较大，因此将两者有效地结合连接在一起，能够生成任意曲率的非线性分量，保证可以与不同的功率放大器的非线性失真对消。由此可见，本发明的数字化预失真线性化器不仅兼容性和可调灵活性高，而且预失真效果理想，可保证与不同的功率放大器的非线性失真对消。
附图说明
图1是两非线性系统的级联表现为线性系统的原理示意图；
图2是本发明一种数字化预失真线性化器的结构示意图；
图3是本发明一种数字化预失真线性化器的第一具体实施例结构示意图；
图4是本发明一种数字化预失真线性化器的第二具体实施例结构示意图；
图5是本发明一种数字化预失真线性化器的第三具体实施例结构示意图；
图6是本发明一种数字化预失真线性化器的第四具体实施例结构示意图；
图7是本发明一种数字化预失真线性化器的第五具体实施例结构示意图；
图8是本发明一种数字化预失真线性化器的第六具体实施例结构示意图；
图9是本发明一种数字化预失真线性化器的第七具体实施例结构示意图；
图10是本发明一种数字化预失真线性化器的第八具体实施例结构示意图；
图11是本发明一种数字化预失真线性化器的第九具体实施例结构示意图；
图12是本发明一种数字化预失真线性化器的第十具体实施例结构示意图；
图13是本发明一种数字化预失真线性化器的第十一具体实施例结构示意图；
图14是本发明一种数字化预失真线性化器的第十二具体实施例结构示意图；
图15是本发明一种数字化预失真线性化器的第十三具体实施例结构示意图；
图16是本发明一种数字化预失真线性化器的第十四具体实施例结构示意图；
图17是本发明一种数字化预失真线性化器的第十五具体实施例结构示意图；
图18是本发明一种数字化预失真线性化器的第十六具体实施例结构示意图；
图19是三个衰减器的衰减增益最优值的寻找方法示意图；
图20是功率放大器的相位失真示意图；
图21是并联二极管所产生的相位失真示意图；
图22是串联二极管所产生的相位失真示意图；
图23是本发明一种数字化预失真线性化器所产生的总的相位失真示意图。
ATT1、第一衰减器；ATT2、第二衰减器；ATT3、第三衰减器；D1、并联二极管；D2、串联二极管；R1、第一电阻；R2、第二电阻；L1、第一电感；L2、第二电感；L3、第三电感；C1、第一电容；C2、第二电容；C3、第三电容；C4、第四电容。
具体实施方式
为了解决传统预失真线性化器兼容性和灵活性低下，与功率放大器的非线性失真对消效果差等问题，本发明提出一种数字化预失真线性化器，如图2所示，其包括：
信号处理电路，用于包含有并联二极管和串联二极管；其中，所述并联二极管是指以并联连接方式连接在电路中的二极管，所述串联二极管是指以串联连接方式连接在电路中的二极管；
控制模块，用于控制调节并联二极管和/或串联二极管的输入功率；
所述并联二极管和串联二极管连接，所述控制模块与并联二极管和/或串联二极管连接。应用时，所述射频信号经信号处理电路进行处理后输出。
对于并联二极管和串联二极管之间的连接关系，其可为并联连接关系，如图3所示，接入的射频信号经过并联二极管后输出第一射频信号，接入的射频信号经过串联二极管后输出第二射频信号，然后第一射频信号和第二射频信号叠加后输出；其也可为串联连接关系，如图4所示，接入的射频信号依次经过并联二极管和串联二极管后输出，或者，如图5所示，接入的射频信号依次经过串联二极管和并联二极管后输出。
作为本实施例的优选实施方式，所述控制模块包括衰减器和用于通过控制调节衰减器的衰减增益，从而控制调节并联二极管和/或串联二极管的输入功率的处理器，所述处理器与衰减器连接，所述衰减器与并联二极管和/或串联二极管连接。
作为本实施例的优选实施方式，所述衰减器包括第一衰减器，所述处理器具体用于通过控制调节第一衰减器的衰减增益，从而控制调节并联二极管的输入功率，此时，所述第一衰减器设置在并联二极管的前端；
当并联二极管和串联二极管之间的连接关系为并联连接关系时，如图3所示，接入的射频信号依次经过第一衰减器和并联二极管后输出第一射频信号；
当并联二极管和串联二极管之间的连接关系为串联连接关系时，如图4所示，接入的射频信号依次经过第一衰减器、并联二极管、串联二极管后输出，或者，如图5所示，接入的射频信号依次经过串联二极管、第一衰减器、并联二极管后输出。
作为本实施例的优选实施方式，所述衰减器包括第二衰减器，所述处理器具体用于通过控制调节第二衰减器的衰减增益，从而控制调节串联二极管的输入功率，此时，所述第二衰减器设置在串联二极管的前端；
当并联二极管和串联二极管之间的连接关系为并联连接关系时，如图3所示，接入的射频信号依次经过第二衰减器和串联二极管后输出第二射频信号；
当并联二极管和串联二极管之间的连接关系为串联连接关系时，如图4所示，接入的射频信号依次经过并联二极管、第二衰减器、串联二极管后输出，或者，如图5所示，接入的射频信号依次经过第二衰减器、串联二极管、并联二极管后输出。
对于上述第一衰减器和第二衰减器的设置，其可根据实际情况进行相应的设置，例如，仅设置第一衰减器或第二衰减器，又或者，第一衰减器和第二衰减器同时设置。优选地，所述第一衰减器和第二衰减器同时设置。
作为本实施例的优选实施方式，还包括第三衰减器，所述第三衰减器设置在信号处理电路的信号输出端，即信号处理电路所输出的射频信号经第三衰减器处理后输出，也就是说，所述第三衰减器与并联二极管和/或串联二极管连接，具体如图3至图5所示。
作为本实施例的优选实施方式，所述第三衰减器与处理器连接，所述处理器具体还用于通过对第三衰减器的衰减增益进行控制调节，从而对并联二极管和串联二极管所产生的非线性信号的结合，即信号处理电路所输出的非线性信号，进行曲率的调整，这样能进一步地提高操作的兼容性和灵活性。
作为本实施例的优选实施方式，所述处理器还用于控制调节流经并联二极管和/或串联二极管的电流。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路与并联二极管和/或串联二极管连接。所述偏置电路主要用于为并联二极管和/或串联二极管提供偏置电压，与并联二极管和/或串联二极管结合形成回路，从而令并联二极管和/或串联二极管正常工作。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经并联二极管和/或串联二极管的电流，所述处理器与偏置电路连接。
作为本实施例的优选实施方式，所述控制调节衰减器的衰减增益，其具体为：
根据检测到的温度和输出功率，判断预存的二维表格中是否存有相对应的温度和输出功率，若有，则根据检测到的温度和输出功率，从预存的二维表格中查找出相对应的衰减器的衰减增益最优值，反之，则利用插值方法从而拟合出相对应的衰减器的衰减增益最优值；
将得到的衰减器的衰减增益最优值写入衰减器中。
作为本实施例的优选实施方式，所述预存的二维表格的两个维度分别为温度和输出功率，所述预存的二维表格中的表格内容为温度和输出功率相对应的衰减器的衰减增益最优值。
作为本实施例的优选实施方式，所述衰减器的衰减增益最优值，其获取步骤包括有：
当环境温度达到目标温度且数字化预失真线性化器的输出功率达到目标输出功率时，对衰减器的衰减增益进行扫描，并且对数字化预失真线性化器所输出的信号进行三阶交调分量的检测，当三阶交调分量结果为最小值时，当前扫描到的衰减器的衰减增益则为衰减器的衰减增益最优值。
以下结合详细实施例来对本发明的关键词提取方法做详细阐述。
实施例1
如图6所示，一种数字化预失真线性化器具体包括第一衰减器ATT1、并联二极管D1、第二衰减器ATT2、串联二极管D2及用于控制调节ATT1和ATT2的衰减增益的处理器（图6中并未示出），接入的射频信号依次经过ATT1、D1、ATT2、D2后输出；
其中，在本实施例中，D1的正极连接在ATT1输出端与ATT2输入端之间，D1的负极接地；D2的正极与ATT2的输出端连接，D2的负极作为射频信号输出端。
作为本实施例的优选实施方式，还包括第三衰减器ATT3，所述第三衰减器ATT3设置在信号处理电路的信号输出端，即如图6所示，D2的负极与ATT3的输入端连接。
作为本实施例的优选实施方式，所述ATT3与处理器连接。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路分别与D1和D2连接。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经D1和D2的电流。
实施例2
如图7所示，一种数字化预失真线性化器具体包括第一衰减器ATT1、并联二极管D1、第二衰减器ATT2、串联二极管D2及用于控制调节ATT1和ATT2的衰减增益的处理器（图7中并未示出），接入的射频信号依次经过ATT1、D1、ATT2、D2后输出；
其中，在本实施例中，D1的正极连接在ATT1输出端与ATT2输入端之间，D1的负极接地；D2的负极与ATT2的输出端连接，D2的正极作为射频信号输出端。
作为本实施例的优选实施方式，还包括第三衰减器ATT3，所述第三衰减器ATT3设置在信号处理电路的信号输出端，即如图7所示，D2的正极与ATT3的输入端连接。
作为本实施例的优选实施方式，所述ATT3与处理器连接。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路分别与D1和D2连接。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经D1和D2的电流。
实施例3
如图8所示，一种数字化预失真线性化器具体包括第一衰减器ATT1、并联二极管D1、第二衰减器ATT2、串联二极管D2及用于控制调节ATT1和ATT2的衰减增益的处理器（图8中并未示出），接入的射频信号依次经过ATT1、D1、ATT2、D2后输出；
其中，在本实施例中，D1的负极连接在ATT1输出端与ATT2输入端之间，D1的正极接地；D2的正极与ATT2的输出端连接，D2的负极作为射频信号输出端。
作为本实施例的优选实施方式，还包括第三衰减器ATT3，所述第三衰减器ATT3设置在信号处理电路的信号输出端，即如图8所示，D2的负极与ATT3的输入端连接。
作为本实施例的优选实施方式，所述ATT3与处理器连接。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路分别与D1和D2连接。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经D1和D2的电流。
实施例4
如图9所示，一种数字化预失真线性化器具体包括第一衰减器ATT1、并联二极管D1、第二衰减器ATT2、串联二极管D2及用于控制调节ATT1和ATT2的衰减增益的处理器（图9中并未示出），接入的射频信号依次经过ATT1、D1、ATT2、D2后输出；
其中，在本实施例中，D1的负极连接在ATT1输出端与ATT2输入端之间，D1的正极接地；D2的负极与ATT2的输出端连接，D2的正极作为射频信号输出端。
作为本实施例的优选实施方式，还包括第三衰减器ATT3，所述第三衰减器ATT3设置在信号处理电路的信号输出端，即如图9所示，D2的正极与ATT3的输入端连接。
作为本实施例的优选实施方式，所述ATT3与处理器连接。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路分别与D1和D2连接。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经D1和D2的电流。
由上述实施例1~实施例4可知，D1与D2之间的连接关系为串联关系，并且D1设置在D2的前端；对于连接在ATT1输出端与ATT2输出端之间的D1的一端，其可为D1的正极或负极，而D1的另一端则相对应接地；对于与ATT2输出端连接的D2的一端，其同样可为D2的正极或负极，而D2的另一端则作为射频信号输出端。另外，对于与D1、D2连接的偏置电路，其根据自身所提供的偏置电压的极性不同，从而可连接在D1（D2）的正极或负极，这根据实际情况需要进行相应连接便可。
实施例5
如图10所示，一种数字化预失真线性化器具体包括第二衰减器ATT2、串联二极管D2、第一衰减器ATT1、并联二极管D1及用于控制调节ATT1和ATT2的衰减增益的处理器（图10中并未示出），接入的射频信号依次经过ATT2、D2、ATT1、D1后输出；
其中，在本实施例中，D2的正极与ATT2的输出端连接，D2的负极与ATT1的输入端连接，D1的正极与ATT1的输出端连接，D1的负极接地；D1的正极作为射频信号输出端。
作为本实施例的优选实施方式，还包括第三衰减器ATT3，所述第三衰减器ATT3设置在信号处理电路的信号输出端，即如图10所示，D1的正极与ATT3的输入端连接。
作为本实施例的优选实施方式，所述ATT3与处理器连接。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路分别与D1和D2连接。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经D1和D2的电流。
实施例6
如图11所示，一种数字化预失真线性化器具体包括第二衰减器ATT2、串联二极管D2、第一衰减器ATT1、并联二极管D1及用于控制调节ATT1和ATT2的衰减增益的处理器（图11中并未示出），接入的射频信号依次经过ATT2、D2、ATT1、D1后输出；
其中，在本实施例中，D2的正极与ATT2的输出端连接，D2的负极与ATT1的输入端连接，D1的负极与ATT1的输出端连接，D1的正极接地；D1的负极作为射频信号输出端。
作为本实施例的优选实施方式，还包括第三衰减器ATT3，所述第三衰减器ATT3设置在信号处理电路的信号输出端，即如图11所示，D1的负极与ATT3的输入端连接。
作为本实施例的优选实施方式，所述ATT3与处理器连接。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路分别与D1和D2连接。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经D1和D2的电流。
实施例7
如图12所示，一种数字化预失真线性化器具体包括第二衰减器ATT2、串联二极管D2、第一衰减器ATT1、并联二极管D1及用于控制调节ATT1和ATT2的衰减增益的处理器（图12中并未示出），接入的射频信号依次经过ATT2、D2、ATT1、D1后输出；
其中，在本实施例中，D2的负极与ATT2的输出端连接，D2的正极与ATT1的输入端连接，D1的正极与ATT1的输出端连接，D1的负极接地；D1的正极作为射频信号输出端。
作为本实施例的优选实施方式，还包括第三衰减器ATT3，所述第三衰减器ATT3设置在信号处理电路的信号输出端，即如图12所示，D1的正极与ATT3的输入端连接。
作为本实施例的优选实施方式，所述ATT3与处理器连接。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路分别与D1和D2连接。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经D1和D2的电流。
实施例8
如图13所示，一种数字化预失真线性化器具体包括第二衰减器ATT2、串联二极管D2、第一衰减器ATT1、并联二极管D1及用于控制调节ATT1和ATT2的衰减增益的处理器（图13中并未示出），接入的射频信号依次经过ATT2、D2、ATT1、D1后输出；
其中，在本实施例中，D2的负极与ATT2的输出端连接，D2的正极与ATT1的输入端连接，D1的负极与ATT1的输出端连接，D1的正极接地；D1的负极作为射频信号输出端。
作为本实施例的优选实施方式，还包括第三衰减器ATT3，所述第三衰减器ATT3设置在信号处理电路的信号输出端，即如图13所示，D1的负极与ATT3的输入端连接。
作为本实施例的优选实施方式，所述ATT3与处理器连接。
作为本实施例的优选实施方式，还包括偏置电路，所述偏置电路分别与D1和D2连接。
作为本实施例的优选实施方式，所述处理器还用于通过控制偏置电路，从而控制调节流经D1和D2的电流。
由上述实施例5~实施例8可知，D1与D2之间的连接关系为串联关系，并且D2设置在D1的前端；对于与ATT2输出端连接的D2的一端，其可为D2的正极或负极，而D2的另一端则相对应与ATT1的输入端连接；对于与ATT1输出端连接的D1的一端，其可为D1的正极或负极，而D1的另一端则接地。另外，对于与D1、D2连接的偏置电路，其根据自身所提供的偏置电压的极性不同，从而可连接在D1（D2）的正极或负极，这根据实际情况需要进行相应连接便可。
还有，由上述实施例1~实施例8的内容可知，上述方案中D1和D2之间的连接关系为串联连接关系，而针对D1和D2之间的连接关系为并联连接关系的方案，除D1和D2之间的连接关系不同外，其它基本与上述实施例内容相同，因此基于上述实施例内容，便能得到D1和D2之间的连接关系为并联连接关系的方案的具体实施例。
实施例9
在本实施例中，D1与D2之间的连接关系为串联连接关系，D1设置在D2的前端，所述偏置电路包括用于为D1提供偏置电压的第一偏置电路，以及用于为D2提供偏置电压的第二偏置电路。
如图14所示，一种数字化预失真线性化器具体包括第一衰减器ATT1、第一偏置电路、并联二极管D1、第二衰减器ATT2、第二偏置电路、串联二极管D2、第三衰减器ATT3以及用于控制调节第一衰减器ATT1、第二衰减器ATT2及第三衰减器ATT3的衰减增益的处理器，所述处理器分别与第一衰减器ATT1、第二衰减器ATT2以及第三衰减器ATT3连接；
所述第一偏置电路与D1连接，所述第二偏置电路与D2连接，所述第一衰减器ATT1依次经过并联二极管D1、第二衰减器ATT2和串联二极管D2与第三衰减器ATT3连接。在本实施例中，具体地，ATT1的输出端分别与D1的一端和ATT2的输入端连接，D1的另一端接地，所述ATT2的输出端与D2的一端连接，D2的另一端与ATT3的输入端连接。
对于上述数字化预失真线性化器，其工作原理为：射频信号输入至第一衰减器ATT1后，依次经过D1、ATT2、D2以及ATT3进行处理后射频输出；其中，所述处理器通过控制调节ATT1、ATT2的衰减增益，从而调节信号的输入功率，令进入并联预失真二极管D1和串联预失真二极管D2的功率保持在各自所需的水平上，而由D1形成的并联预失真所产生的非线性的斜率较小，由D2形成的串联预失真产生的非线性斜率大，因此将两者有效的结合在一起，通过调节ATT1和ATT2来调节信号的输入功率，这样便可生成任意曲率的非线性分量，保证可以和不同的功率放大器对消，而且处理器还能通过控制ATT3的衰减增益，从而对D1和D2所产生的非线性信号的结合，即信号处理电路所输出的非线性信号，进行曲率上的调整。由此可得，本发明的数字化预失真线性化器的兼容性和可调灵活性高，而且预失真效果理想，并且还具有易于实现、体积小、成本低等优点。
作为本实施例的优选实施方式，如图15所示，所述第一偏置电路包括第一电压控制电路和第一电阻R1，所述第一电压控制电路的输出端与R1的一端连接，R1的另一端与D1连接。优选地，所述处理器与第一电压控制电路连接，所述处理器具体还用于通过控制调节第一电压控制电路所输出的电压，从而与R1配合来控制调节流经D1的电流。
所述第一偏置电路与第二偏置电路，两者的电路结构可相同或不相同，可根据实际需要而设置。作为本实施例的优选实施方式，所述第一偏置电路和第二偏置电路，两者的电路结构相同，即所述第二偏置电路包括第二电压控制电路和第二电阻R2，所述第二电压控制电路的输出端与R2的一端连接，R2的另一端与D2连接。优选地，所述处理器与第二电压控制电路连接，所述处理器具体还用于通过控制调节第二电压控制电路所输出的电压，从而与R2配合来控制调节流经D2的电流。
对于上述的第一电阻R1和第二电阻R2，如图16所示，其可分别利用第一电感L1和第二电感L2来替换；又或者，所述第一电阻R1和第一电感L1串联后连接在第一电压控制电路的输出端与D1之间，所述第二电阻R2和第二电感L2串联后连接在第二电压控制电路的输出端与D2之间。这样能令处理器能够通过控制电压控制电路所输出的电压，从而与电阻和/电感配合来调节流过D1和D2的电流。
本实施例中对偏置电路的限定，其可适用于其它实施例中。
实施例10
在本实施例中，为了令数字化预失真线性化器的电路工作更稳定可靠，在电路中会相应增加隔离电容和电感。对于这一技术特征，其可适用于其它实施例中。
如图17所示，一种数字化预失真线性化器，包括第一衰减器ATT1、第一电容C1、并联二极管D1、第二电容C2、第二衰减器ATT2、第三电容C3、串联二极管D2、第三电感L3、第四电容C4、第三衰减器ATT3、第一电压控制电路、第二电压控制电路、第一电阻R1、第一电感L1、第二电阻R2、第二电感L2以及用于控制第一衰减器ATT1、第二衰减器ATT2及第三衰减器ATT3的衰减增益，以及控制第一电压控制电路和第二电压控制电路所输出的电压的处理器，所述处理器分别与ATT1、ATT2、ATT3、第一电压控制电路以及第二电压控制电路连接；
所述ATT1的输出端与C1的一端连接，C1的另一端分别与D1的一端和C2的一端连接，D1的另一端接地，C2的另一端与ATT2的输入端连接，ATT2的输出端与C3的一端连接，C3的另一端与D2的一端连接，D2的另一端分别与L3的一端和C4的一端连接，L3的另一端接地，C4的另一端与ATT3的输入端连接；
所述第一电压控制电路与R1的一端连接，R1的另一端与L1的一端连接，L1的另一端与D1连接，所述第二电压控制电路与R2的一端连接，R2的另一端与L1的一端连接，L1的另一端与D2连接。其中，所述第一电压控制电路所输出的电压值为V1，第二电压控制电路所输出的电压值为V2；所述ATT1的衰减增益为att1，ATT2的衰减增益为att2，ATT3的衰减增益为att3。所述处理器能够通过控制ATT1、ATT2及ATT3的衰减增益来调节D1和D2所产生的信号非线性斜率，而且处理器还能够通过控制调节第一电压控制电路和第二电压控制电路的输出电压V1和V2，从而配合第一电阻R1、第一电感L1和第二电阻R2、第二电感L2来调节流过D1和D2的电流。由此可见，处理器可以根据每个功率放大器的非线性特点，产生出任意形式的相位失真和幅度失真，实现与功率放大器的非线性分量的对消，而且还增设了D1和D2的流经电流控制调节手段，因此调节灵活性更高，精度高，令输出信号的非线性分量与功率放大器的非线性分量，两者的匹配度更高，令功率放大器达到最佳的线性化效果。
以相位失真为例，利用本发明的数字化预失真线性化器来实现相位预失真，其具体如图20至图23所示。如图20所示，其为功率放大器所产生的相位失真，其为正。而如图21和图22所示，其分别为并联预失真二极管D1所产生的相位失真，以及串联预失真二极管D2所产生的相位失真，由图可看出，并联预失真二极管D1所产生的相位失真的幅度较小，串联预失真二极管D2所产生的相位失真的幅度较大，由此可见，若仅利用单一并联预失真二极管或串联预失真二极管，都无法简单地与功率放大器所产生的相位失真完全对消，而本发明的数字化预失真线性化器则是通过处理器调节控制衰减器的衰减增益，以及调节控制V1、V2，并且有效地将D1和D2结合在一起，因此本发明的数字化预失真线性化器所输出的相位失真，如图23所示，其能完全产生出与功率放大器相匹配的相位失真曲线。
实施例11
基于上述实施例的数字化预失真线性化器结构，本实施例的处理器中设有控制算法，通过该控制算法，可以自动生成最优的数字化的工作状态，实现了线性化器的数字化控制。
本实施例中，对于所述控制调节衰减器的衰减增益这一手段，其具体为：
根据检测到的温度和输出功率，判断预存的二维表格中是否存有相对应的温度和输出功率，若有，则根据检测到的温度和输出功率，从预存的二维表格中查找出相对应的衰减器的衰减增益最优值，反之，则利用插值方法从而拟合出相对应的衰减器的衰减增益最优值；
将得到的衰减器的衰减增益最优值写入衰减器中。
当包括ATT1、ATT2和/或ATT3时，对于所述控制调节衰减器的衰减增益这一手段，其具体为：
根据检测到的温度和输出功率，判断预存的二维表格中是否存有相对应的温度和输出功率，若有，则根据检测到的温度和输出功率，从预存的二维表格中查找出相对应的ATT1的衰减增益最优值、ATT2的衰减增益最优值和/或ATT3的衰减增益最优值，反之，则利用插值方法从而拟合出相对应的ATT1的衰减增益最优值、ATT2的衰减增益最优值和/或ATT3的衰减增益最优值；
将得到的ATT1的衰减增益最优值、ATT2的衰减增益最优值和/或ATT3的衰减增益最优值分别写入ATT1、ATT2和/或ATT3中。
对于所述预存的二维表格，其两个维度分别为温度和输出功率，而表格中的表格内容为温度和输出功率相对应的ATT1的衰减增益最优值、ATT2的衰减增益最优值和/或ATT3的衰减增益最优值。
对于上述衰减器的衰减增益最优值，其获取步骤包括有：
S1、将数字化预失真线性化器放入温箱之中，用于改变不同的温度；同时在该线性化器的输入端接入一台矢量信号源，用于产生可以评估交调输出的双音信号，在该线性化器的输出端接入频谱仪，可以直接读出三阶交调分量的大小，即三阶交调分量结果；利用外接的计算机从而分别与处理器、温箱、矢量信号源和频谱仪连接；
S2、首先根据温度的工作范围，将温度等分为T1到TN，共N个温度数值点，然后根据输出功率的范围，将输出功率分为P1到PM，共M个输出功率数值点；
S3、采用遍历的方法，通过控制温箱和台矢量信号源，分别实现目标的温度和输出功率值；当达到环境温度达到目标温度，且数字化预失真线性化器的输出功率达到目标的输出功率时，此时的变量仅有att1、att2和/或att3，对于该变量，它们可以看成一个许多点组成的立方体，立方体内的每一个节点分别对应一个具体的att1、att2和/或att3的值；
外接的计算机通过控制处理器，采用优选算法，例如Quasi-Newton算法，对att1、att2和/或att3进行扫描，同时检测频谱仪输出的三阶交调分量结果，即对数字化预失真线性化器所输出的信号进行三阶交调分量的检测，当检测出的三阶交调分量结果为最小值时，当前搜索扫描到的att1、att2和/或att3为最优值，那么这样对于每一个温度数值点和输出功率数值点，均相对应地得到att1、att2和/或att3的最优值，如图19所示。此时，建立二维表格，将其两个维度分别对应温度和输出功率，而表格内的数值则为温度和输出功率相对应的att1、att2和/或att3的最优值。
由上述可得，如图18所示，本实施例中的数字化预失真线性化器还包括有温度传感器和输出功率检测电路，所述输出功率检测电路的输入端与信号处理电路的输出端，或第三衰减器的输出端连接，所述输出功率检测电路的输出端与温度传感器的输出端均与处理器的输入端连接。工作时，将温度传感器所检测到的温度以及输出功率检测电路所检测到的输出功率，发送至处理器中。
另外，对于上述的实施例所述的衰减器，其可为数字衰减器，也可模拟衰减器。
以上是对本发明的较佳实施进行了具体说明，但本发明创造并不限于所述实施例，熟悉本领域的技术人员在不违背本发明精神的前提下还可做作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (10)

  1. 一种数字化预失真线性化器，其特征在于：包括：
    信号处理电路，用于包含有并联二极管和串联二极管；
    控制模块，用于控制调节并联二极管和/或串联二极管的输入功率；
    所述并联二极管和串联二极管连接，所述控制模块与并联二极管和/或串联二极管连接。
  2. 根据权利要求1所述一种数字化预失真线性化器，其特征在于：所述控制模块包括衰减器和用于通过控制调节衰减器的衰减增益，从而控制调节并联二极管和/或串联二极管的输入功率的处理器，所述处理器与衰减器连接，所述衰减器与并联二极管和/或串联二极管连接。
  3. 根据权利要求2所述一种数字化预失真线性化器，其特征在于：所述处理器还用于控制调节流经并联二极管和/或串联二极管的电流。
  4. 根据权利要求2所述一种数字化预失真线性化器，其特征在于：还包括偏置电路，所述偏置电路与并联二极管和/或串联二极管连接。
  5. 根据权利要求2-4任一项所述一种数字化预失真线性化器，其特征在于：所述衰减器包括第一衰减器，所述处理器具体用于通过控制调节第一衰减器的衰减增益，从而控制调节并联二极管的输入功率。
  6. 根据权利要求2-4任一项所述一种数字化预失真线性化器，其特征在于：所述衰减器包括第二衰减器，所述处理器具体用于通过控制调节第二衰减器的衰减增益，从而控制调节串联二极管的输入功率。
  7. 根据权利要求1-4任一项所述一种数字化预失真线性化器，其特征在于：还包括第三衰减器，所述第三衰减器设置在信号处理电路的信号输出端。
  8. 根据权利要求2-4任一项所述一种数字化预失真线性化器，其特征在于：所述控制调节衰减器的衰减增益，其具体为：
    根据检测到的温度和输出功率，判断预存的二维表格中是否存有相对应的温度和输出功率，若有，则根据检测到的温度和输出功率，从预存的二维表格中查找出相对应的衰减器的衰减增益最优值，反之，则利用插值方法从而拟合出相对应的衰减器的衰减增益最优值；
    将得到的衰减器的衰减增益最优值写入衰减器中。
  9. 根据权利要求8所述一种数字化预失真线性化器，其特征在于：所述预存的二维表格的两个维度分别为温度和输出功率，所述预存的二维表格中的表格内容为温度和输出功率相对应的衰减器的衰减增益最优值。
  10. 根据权利要求8所述一种数字化预失真线性化器，其特征在于：所述衰减器的衰减增益最优值，其获取步骤包括有：
    当环境温度达到目标温度且数字化预失真线性化器的输出功率达到目标输出功率时，对衰减器的衰减增益进行扫描，并且对数字化预失真线性化器所输出的信号进行三阶交调分量的检测，当三阶交调分量结果为最小值时，当前扫描到的衰减器的衰减增益则为衰减器的衰减增益最优值。
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