WO2018152936A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2018152936A1
WO2018152936A1 PCT/CN2017/079548 CN2017079548W WO2018152936A1 WO 2018152936 A1 WO2018152936 A1 WO 2018152936A1 CN 2017079548 W CN2017079548 W CN 2017079548W WO 2018152936 A1 WO2018152936 A1 WO 2018152936A1
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WIPO (PCT)
Prior art keywords
scan line
array substrate
line
scan
switch tube
Prior art date
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Ceased
Application number
PCT/CN2017/079548
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English (en)
French (fr)
Inventor
郝思坤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/518,809 priority Critical patent/US10345662B2/en
Publication of WO2018152936A1 publication Critical patent/WO2018152936A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate and a display panel.
  • Liquid crystal display (LCD, Liquid Crystal) Display) is widely used in TV, Monitor, Note book, App and other display products due to its advantages of thinness, high color gamut and low power consumption.
  • the invention provides an array substrate and a display panel, which can increase the charging time of the pixel, increase the charging rate of the pixel, reduce the risk of mischarge, and improve the display quality of the liquid crystal display.
  • a technical solution adopted by the present invention is to provide an array substrate, the array substrate comprising: a plurality of scan lines, a plurality of data lines, and a low voltage line; wherein the plurality of scan lines are orthogonal to the plurality of data lines Providing a plurality of pixel units; wherein each of the pixel units includes a first switching tube, and at least one of the pixel units further includes a second switching tube; the second switching tube includes: a first end a second end and a control end, the first end is connected to the control end of the first switch tube, the control end is connected to a subsequent scan line, and the subsequent scan line is opened in the second switch tube After the corresponding scan line of the pixel corresponding to the pixel unit, a falling edge of the scan line scan signal of the current stage corresponds to a rising edge of the scan signal of the subsequent scan line, and the second end is connected to the low voltage line;
  • the pixel unit includes a second switch tube; the array substrate further includes a scan driving circuit, and the scan driving
  • Each of the pixel units includes a second switch tube.
  • the subsequent scan line is adjacent to the current scan line.
  • the scan line is connected to the scan line of the first-level scan line at least one level, and the number of the scan lines between the subsequent scan line and the current scan line is equal to the number The ratio of the pre-charging time of the pixel unit in which the two switching tubes are located to the official charging time.
  • an array substrate comprising: a plurality of scan lines, a plurality of data lines, and a low voltage line; and the plurality of scan lines and The plurality of data lines are orthogonally disposed to form a plurality of pixel units; wherein each of the pixel units includes a first switch tube, and at least one of the pixel units further includes a second switch tube;
  • the switch tube includes: a first end, a second end, and a control end, wherein the first end is connected to the control end of the first switch tube, the control end is connected to a subsequent scan line, and the subsequent scan line is opened in the order After the current scan line corresponding to the pixel unit in which the second switch tube is located, a falling edge of the scan line scan signal of the current stage corresponds to a rising edge of the scan signal of the subsequent scan line, and the second end is connected.
  • the low voltage line is provided.
  • Each of the pixel units includes a second switch tube.
  • the subsequent scan line is adjacent to the current scan line.
  • the scan line is connected to the scan line of the first-level scan line at least one level, and the number of the scan lines between the subsequent scan line and the current scan line is equal to the number The ratio of the pre-charging time of the pixel unit in which the two switching tubes are located to the official charging time.
  • the pixel unit corresponding to the same color filter includes a second switch tube.
  • the subsequent scan line is adjacent to the current scan line.
  • the scan line is connected to the scan line of the first-level scan line at least one level, and the number of the scan lines between the subsequent scan line and the current scan line is equal to the number The ratio of the pre-charging time of the pixel unit in which the two switching tubes are located to the official charging time.
  • the array substrate further includes a scan driving circuit, and the scan driving circuit is configured to provide a scan signal to the scan line.
  • the array substrate further includes a data driving circuit, and the data driving circuit is configured to provide a gray scale signal to the data line.
  • another technical solution adopted by the present invention is to provide a display panel, the display panel including an array substrate, a counter substrate disposed opposite to the array substrate, and being sandwiched between the array substrate and the array substrate a liquid crystal layer between the opposite substrates;
  • the array substrate includes: a plurality of scan lines, a plurality of data lines, and a low voltage line; the plurality of scan lines are orthogonally disposed with the plurality of data lines to form a plurality of pixel units; wherein each The pixel unit includes a first switch tube, and at least one of the pixel units further includes a second switch tube; the second switch tube includes: a first end, a second end, and a control end, the first end Connected to the control end of the first switch, the control end is connected to a subsequent scan line, and the subsequent scan line is opened in the order of the scan line corresponding to the pixel corresponding to the pixel unit where the second switch tube is located.
  • the falling edge of the scan line scan signal of the current stage corresponds to a rising edge of the scan signal of the subsequent scan line, and the second end is connected to the low voltage line.
  • the pixel unit including the second switch tube or the corresponding color filter in each of the pixel units includes a second switch tube.
  • the subsequent scan line is adjacent to the current scan line.
  • the scan line is connected to the scan line of the first-level scan line at least one level, and the number of the scan lines between the subsequent scan line and the current scan line is equal to the number The ratio of the pre-charging time of the pixel unit in which the two switching tubes are located to the official charging time.
  • the invention has the beneficial effects of providing an array substrate and a display panel, by adding a second switch tube in the pixel unit, and controlling the control end of the second switch tube to be connected to the subsequent scan line, scanning the signal in one scan period
  • the pulse width is fixed.
  • the shortening of the falling edge time means that the time of scanning the high level of the signal becomes longer, that is, the opening time of the first switching transistor becomes longer, so that the charging of the pixel electrode is performed.
  • the time becomes longer the charging rate of the pixel is increased, the risk of wrong charging is reduced, and the display quality of the liquid crystal display is improved.
  • FIG. 1 is a schematic structural view of a first embodiment of an array substrate of the present invention
  • FIG. 2 is a timing chart of a first embodiment of the array substrate of the present invention
  • FIG. 3 is a schematic structural view of a second embodiment of the array substrate of the present invention.
  • FIG. 5 is a schematic structural view of a third embodiment of the array substrate of the present invention.
  • FIG. 6 is a schematic structural view of a fourth embodiment of an array substrate of the present invention.
  • FIG. 7 is a schematic diagram of comparison between the present invention and a prior art driving mode charging waveform
  • FIG. 8 is a schematic structural view of an embodiment of a display panel of the present invention.
  • FIG. 1 is a schematic structural view of a first embodiment of an array substrate according to the present invention.
  • the array substrate 10 includes a plurality of scanning lines 11, a plurality of data lines 12, and a low voltage line Vgl.
  • the plurality of scan lines 11 are orthogonal to the plurality of data lines 12 to form a plurality of pixel units 13.
  • Each of the pixel units 13 includes a first switch tube T1 for controlling the voltage of the pixel electrode in the array substrate 10.
  • the at least one pixel unit 13 further includes a second switch tube T2, and the second switch tube T2 includes: a first end a, a second end b, and a control end c, and the first end a is connected to the first switch tube T1.
  • the control terminal c is connected to a subsequent scan line.
  • the subsequent scan line is opened in the order of the corresponding scan line corresponding to the pixel unit 13 where the second switch tube T2 is located, and the second end b is connected to the low voltage line Vgl.
  • the subsequent scan line is turned on, the scan line of this stage is rapidly lowered to a low potential.
  • the array substrate 10 further includes a scan driving circuit 14 and a data driving circuit 15.
  • the scan driving circuit 14 is configured to provide a scan signal to the scan line
  • the data drive circuit 15 is configured to provide a gray scale signal to the data line.
  • each pixel unit 13 includes a second switch tube T2, and the subsequent scan line is opened in the same order as the pixel unit 13 where the second switch tube T2 is located. After the line, and the subsequent scan line is adjacent to the current scan line.
  • the pixel unit 13 is in a region surrounded by two adjacent low voltage lines Vgl and two adjacent data lines, and the first switching tube T1 and the pixel electrode of the pixel unit 13 are located in the phase. The area surrounded by the adjacent two data lines, the scanning line of the Nth stage pixel unit 13, and the lower stage low voltage line Vgl.
  • the second switching transistor T2 of the pixel unit 13 is located in a region surrounded by two adjacent data lines, a scanning line of the N-th pixel unit 13, and a low-voltage line Vgl of the present stage.
  • the first switch tube T1 of the Nth stage pixel unit 13 also includes a control end d, a first end e, and a second end f.
  • the control end d is connected to the scan line of the current stage, and the first end e is connected to the data line.
  • the second end f is connected to the pixel electrode.
  • the first end a of the second switch tube T2 of the Nth pixel unit 13 is connected to the control end d of the first switch tube T1, the second end b is connected to the low voltage line Vgl of the current stage, and the third end c is connected to the next level scan. line.
  • FIG. 2 is a timing diagram of the first embodiment of the array substrate of the present invention.
  • the falling edge of the scan line scan signal of the current stage corresponds to the rising edge of the scan signal of the (N+1)th scan line.
  • the scan driving circuit 14 supplies the scan signal to the scan line, that is, when the scan signal is at a high level in FIG. 2, the control terminal d of the first switch transistor T1 is turned on, and at this time, the data drive circuit 15 supplies the gray scale signal to the data.
  • the pixel is charged by the first switch tube T1, and the pixel electrode may be one of a red pixel electrode, a green pixel electrode, a blue pixel electrode, and a white pixel electrode.
  • the scan driving circuit 14 gives the N+1th scanning line a high level, so that the N+1th pixel unit is turned on, and the second switching tube T2 of the Nth pixel unit is turned on. It is also turned on, and the second terminal b of the second switching transistor T2 is connected to the low voltage line Vgl, so that the scanning signal of the scanning line of the Nth pixel unit can be quickly lowered to a low potential.
  • the pulse width of the scan signal is fixed in one scan period, and other conditions are unchanged.
  • the shortening of the time of the falling edge means that the time of scanning the high level of the signal becomes longer, that is, the opening time of the first switching tube becomes longer, so that the charging time of the pixel electrode becomes longer, the charging rate of the pixel is raised, and the error is lowered.
  • the risk of charging increases the display quality of the LCD display.
  • FIG. 3 is a schematic structural diagram of a second embodiment of an array substrate according to the present invention.
  • the embodiment is different from the first embodiment in that a subsequent scan line in the first embodiment is adjacent to the scan line of the current level. That is, the control end of the second switching transistor T2 of the Nth pixel unit is connected to the scanning line of the N+1th pixel unit.
  • the subsequent scan line in the second embodiment is connected to the scan line of the Nth pixel unit at least one scan line, and the number of scan lines between the subsequent scan line and the scan line of the current level is equal to the second switch of the current stage.
  • the ratio of the precharge time of the pixel unit in which the tube T2 is located to the official charging time.
  • the control end of the second switching transistor T2 of the Nth pixel unit is connected to the scan line of the N+2th pixel unit.
  • the array substrate 20 includes a plurality of scanning lines 21, a plurality of data lines 22, and a low voltage line Vgl.
  • the plurality of scan lines 21 are orthogonal to the plurality of data lines 22 to form a plurality of pixel units 23.
  • the array substrate 20 further includes a scan driving circuit 24 and a data driving circuit 25.
  • the scan driving circuit is configured to provide a scan signal to the scan line 21, and the data driving circuit is configured to provide a gray scale signal to the data line 22.
  • each pixel unit 23 includes a first switch tube T1 for controlling the voltage of the pixel electrode in the array substrate 20.
  • Each of the pixel units 23 further includes a second switch tube T2.
  • the second switch tube T2 includes a first end a, a second end b, and a control end c, and the first end a is connected to the first end.
  • the control terminal d of the switch tube T1 is connected to the scan line of the N+2th pixel unit, and the second end b is connected to the low voltage line Vgl for turning on the scan line of the N+2th pixel unit. At this time, the scanning line of this stage is rapidly lowered to a low potential.
  • FIG. 4 is a timing diagram of a second embodiment of the array substrate of the present invention.
  • the falling edge of the scan line scan signal of the current stage corresponds to the rising edge of the scan signal of the N+2th scan line.
  • the scan drive circuit 24 supplies a high level to the scan line of the current stage, turns on the first switch tube T1, and pre-charges the pixels of the current stage.
  • the pre-charging time t1 is equal to the official charging time t2, and can also be obtained from FIG. 5.
  • the N+1th pixel unit turns on the first switching tube T1 for pre-charging.
  • the scan driving circuit 24 gives the scan line of the N+2th pixel unit a high level, so that the N+2th pixel unit is turned on, and the Nth pixel unit is turned on.
  • the second switching transistor T2 is also turned on, and the second terminal b of the second switching transistor T2 is connected to the low voltage line Vgl, so that the scanning signal of the scanning line of the Nth pixel unit can be quickly lowered to a low potential.
  • the control terminal c of the second switching transistor T2 in the Nth pixel unit is not limited to the scan line connected to the N+2th pixel unit, and the specific connection position thereof needs to be performed by the Nth pixel unit.
  • the control terminal of the second switching transistor T2 of the cell should be connected to the scanning line of the N+mth row of pixel cells.
  • the pulse width of the scan signal is fixed in one scan period, and other conditions are unchanged.
  • the shortening of the time of the falling edge means that the time of scanning the high level of the signal becomes longer, that is, the opening time of the first switching tube becomes longer, so that the charging time of the pixel electrode becomes longer, the charging rate of the pixel is raised, and the error is lowered.
  • the risk of charging increases the display quality of the LCD display.
  • FIG. 5 is a schematic structural diagram of a third embodiment of an array substrate according to the present invention.
  • each pixel unit in the first embodiment includes a second switch tube T2.
  • the pixel unit corresponding to the same color filter includes a second switch tube T2, that is, in the Nth stage pixel unit, the second switch tube T2 can be located in the red filter, the green filter, and the blue One of the sub-pixels corresponding to the filter.
  • the specific description is as follows:
  • the array substrate 30 includes a plurality of scanning lines 31, a plurality of data lines 32, and a low voltage line Vgl.
  • the plurality of scan lines 31 are orthogonal to the plurality of data lines 32 to form a plurality of pixel units 33.
  • the array substrate 30 further includes a scan driving circuit 34 and a data driving circuit 35.
  • the scan driving circuit 34 is configured to provide a scan signal to the scan line 31, and the data drive circuit 35 is configured to provide a gray scale signal to the data line 32.
  • each pixel unit 33 includes a first switching transistor T1 for controlling the voltage of the pixel electrode in the array substrate 30.
  • the sub-pixel corresponding to the blue filter is taken as an example, that is, the second switch tube T2 is only located in the pixel unit 33.
  • the pixel unit 33 is in a region surrounded by two adjacent low voltage lines Vgl and two adjacent data lines, the first switch tube T1 and the pixel electrode of the pixel unit 33 are located in the adjacent two data lines, the Nth stage A region surrounded by the scanning line of the pixel unit 33 and the lower-order low-voltage line Vgl.
  • the second switching transistor T2 of the pixel unit 33 is located in a region surrounded by two adjacent data lines, a scanning line of the N-th pixel unit 33, and a low-voltage line Vgl of the present stage.
  • the control terminal d of the first switching transistor T1 of the Nth pixel unit 33 is connected to the scanning line of the current stage, the first end e is connected to the data line, and the second end f is connected to the pixel electrode.
  • the first end a of the second switch tube T2 is connected to the control end d of the first switch tube T1, the second end b is connected to the low-voltage line Vgl of the current stage, and the third end c is connected to the next-stage scan line.
  • the timing diagram of the array substrate of the present invention that is, when the scan signal of the Nth pixel unit is at a high level, the control terminal d of the first switching transistor T1 is turned on.
  • the data driving circuit 35 supplies a gray scale signal to the data line, and charges the pixel electrode through the first switching transistor T1.
  • the scan driving circuit 34 supplies the low level of the scan line of the current level to be turned off, and simultaneously gives the next level of the scan line a high level, so that the N+1th pixel unit is turned on.
  • the second switching transistor T2 of the Nth pixel unit is also turned on, and the second terminal b of the second switching transistor T2 is connected to the low voltage line Vgl, so that the scanning line of the Nth pixel unit can be quickly lowered to a low potential.
  • the second switch tube T2 can also be located in the pixel unit corresponding to the red and green filters, and the analysis principle is the same, and details are not described herein again.
  • the pulse width of the scan signal is fixed in one scan period, and other conditions are unchanged.
  • the shortening of the time of the falling edge means that the time of scanning the high level of the signal becomes longer, that is, the opening time of the first switching tube becomes longer, so that the charging time of the pixel electrode becomes longer, the charging rate of the pixel is raised, and the error is lowered.
  • the risk of charging increases the display quality of the LCD display.
  • FIG. 6 is a schematic structural diagram of a fourth embodiment of an array substrate according to the present invention, which is different from the third embodiment in that a subsequent scan line in the third embodiment is adjacent to the scan line of the current level, that is, the Nth
  • the control terminal of the second switching transistor T2 of the pixel unit is connected to the scanning line of the N+1th pixel unit.
  • the subsequent scan line in the third embodiment is connected to the scan line of the Nth pixel unit at least one level, and the number of scan lines between the subsequent scan line and the current scan line is equal to the second switch of the pixel unit of the current stage.
  • the control end of the second switching transistor T2 of the Nth pixel unit is connected to the scan line of the N+2th pixel unit.
  • the array substrate 40 includes a plurality of scan lines 41, a plurality of data lines 42, and a low voltage line Vgl. Among them, a plurality of scanning lines 41 are disposed orthogonally to the plurality of data lines 42 to form a plurality of pixel units 43.
  • the array substrate 40 further includes a scan driving circuit 44 and a data driving circuit 45.
  • the scan driving circuit is configured to provide a scan signal to the scan line 41
  • the data drive circuit is configured to provide a gray scale signal to the data line 42.
  • each pixel unit 43 includes a first switch tube T1 for controlling the voltage of the pixel electrode in the array substrate 40.
  • Each of the pixel units 43 further includes a second switch tube T2.
  • the second switch tube T2 includes a first end a, a second end b, and a control end c, and the first end a is connected to the first end.
  • a control terminal d of the switch T1 is connected to the scan line Gn+2 of the N+2th pixel unit
  • the second end b is connected to the low voltage line Vgl for the N+2 pixel unit
  • the timing diagram of the second embodiment of FIG. 4 may be combined in the description of the specific embodiment, and the analysis principle is similar to that of the second embodiment. For details, refer to the above description, and details are not described herein again.
  • FIG. 7 is a schematic diagram of comparison between the present invention and a prior art driving mode charging waveform.
  • the charging waveform of the driving mode A of the present invention has a shorter falling time and a lower falling speed of the falling edge.
  • the pulse width of the scanning signal is fixed, and other conditions are constant.
  • the shortening of the time of the falling edge means that the time of scanning the high level of the signal becomes longer, that is, the opening time of the first switching tube becomes longer, so that the charging time of the pixel electrode becomes longer, the charging rate of the pixel is raised, and the error is lowered.
  • the risk of charging increases the display quality of the LCD display.
  • FIG. 8 is a schematic structural diagram of an embodiment of a display panel of the present invention.
  • the present invention provides a display panel 50 comprising the array substrate B in any of the above embodiments, a common substrate 51 disposed opposite the array substrate B, and being sandwiched between the array substrate B and the common substrate 51.
  • a display panel 50 comprising the array substrate B in any of the above embodiments, a common substrate 51 disposed opposite the array substrate B, and being sandwiched between the array substrate B and the common substrate 51.
  • the present invention provides an array substrate and a display panel.
  • a second switch tube is added in the pixel unit, and the control end of the second switch tube is controlled to be connected to the subsequent In the scan line, the pulse width of the scan signal is fixed in one scan period.
  • the shortening of the time of the falling edge means that the time of the high level of the scan signal becomes longer, that is, the first switch tube
  • the opening time becomes longer, so that the charging time of the pixel electrode becomes longer, the charging rate of the pixel is increased, the risk of mischarge is reduced, and the display quality of the liquid crystal display is improved.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板（10，20，30，40）及显示面板（50），阵列基板（10，20，30，40）包括：多条扫描线（11，21，31，41）、多条数据线（12，22，32，42）及低电压线（Vgl）；多条扫描线（11，21，31，41）与多条数据线（12，22，32，42）正交设置，以形成多个像素单元（13，23，33，43）；每一像素单元（13，23，33，43）包括一第一开关管（T1），且至少一个像素单元（13，23，33，43）包括一第二开关管（T2），包括：第一端（a）、第二端（b）及控制端（c），第一端（a）连接第一开关管（T1）的控制端（c），控制端（c）连接一后续扫描线，后续扫描线的开启顺序在第二开关管（T2）所在的像素单元（13，23，33，43）对应的本级扫描线之后。能够增加像素的充电时间，提升像素的充电率。

Description

一种阵列基板及显示面板
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种阵列基板及显示面板。
【背景技术】
液晶显示器（LCD，Liquid Crystal Display）以其具有轻薄、色域高、功耗低等优点被广泛应用于TV、Monitor、Note book、App等显示产品。
随着液晶显示器的解析度越来越高、尺寸越来越大，液晶显示器的充电率越来越低，不能满足高解析度、大尺寸显示器的需求。
【发明内容】
本发明提供一种阵列基板及显示面板，能够增加像素的充电时间，提升像素的充电率、降低错充电风险，进而提升液晶显示器的显示品质。
本发明采用的一个技术方案是：提供一种阵列基板，所述阵列基板包括：多条扫描线、多条数据线及低电压线；所述多条扫描线与所述多条数据线正交设置，以形成多个像素单元；其中，每一所述像素单元包括一第一开关管，且至少一个所述像素单元进一步包括一第二开关管；所述第二开关管包括：第一端、第二端以及控制端，所述第一端连接所述第一开关管的控制端，所述控制端连接一后续扫描线，所述后续扫描线的开启顺序在所述第二开关管所在的所述像素单元对应的本级扫描线之后，所述本级扫描线扫描信号的下降沿与所述后续扫描线扫描信号的上升沿对应，所述第二端连接所述低电压线；每一所述像素单元内包含一所述第二开关管；所述阵列基板还包括扫描驱动电路，所述扫描驱动电路用以提供扫描信号至所述扫描线。
其中，每一所述像素单元内包含一所述第二开关管。
其中，所述后续扫描线与所述本级扫描线相邻。
其中，所述后续扫描线与所述本级扫描线至少间隔一级的所述扫描线连接，所述后续扫描线与所述本级扫描线之间的所述扫描线的数量等于所述第二开关管所在的所述像素单元的预充电时间与正式充电时间之比。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，所述阵列基板包括：多条扫描线、多条数据线及低电压线；所述多条扫描线与所述多条数据线正交设置，以形成多个像素单元；其中，每一所述像素单元包括一第一开关管，且至少一个所述像素单元进一步包括一第二开关管；所述第二开关管包括：第一端、第二端以及控制端，所述第一端连接所述第一开关管的控制端，所述控制端连接一后续扫描线，所述后续扫描线的开启顺序在所述第二开关管所在的所述像素单元对应的本级扫描线之后，所述本级扫描线扫描信号的下降沿与所述后续扫描线扫描信号的上升沿对应，所述第二端连接所述低电压线。
其中，每一所述像素单元内包含一所述第二开关管。
其中，所述后续扫描线与所述本级扫描线相邻。
其中，所述后续扫描线与所述本级扫描线至少间隔一级的所述扫描线连接，所述后续扫描线与所述本级扫描线之间的所述扫描线的数量等于所述第二开关管所在的所述像素单元的预充电时间与正式充电时间之比。
其中，对应同一颜色滤光片的所述像素单元内含一所述第二开关管。
其中，所述后续扫描线与所述本级扫描线相邻。
其中，所述后续扫描线与所述本级扫描线至少间隔一级的所述扫描线连接，所述后续扫描线与所述本级扫描线之间的所述扫描线的数量等于所述第二开关管所在的所述像素单元的预充电时间与正式充电时间之比。
其中，所述阵列基板还包括扫描驱动电路，所述扫描驱动电路用以提供扫描信号至所述扫描线。
其中，所述阵列基板还包括数据驱动电路，所述数据驱动电路用以提供灰阶信号至所述数据线。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种显示面板，所述显示面板包括阵列基板，与所述阵列基板相对设置的对向基板以及夹持于所述阵列基板与所述对向基板之间的液晶层；
其中，所述阵列基板包括：多条扫描线、多条数据线及低电压线；所述多条扫描线与所述多条数据线正交设置，以形成多个像素单元；其中，每一所述像素单元包括一第一开关管，且至少一个所述像素单元进一步包括一第二开关管；所述第二开关管包括：第一端、第二端以及控制端，所述第一端连接所述第一开关管的控制端，所述控制端连接一后续扫描线，所述后续扫描线的开启顺序在所述第二开关管所在的所述像素单元对应的本级扫描线之后，所述本级扫描线扫描信号的下降沿与所述后续扫描线扫描信号的上升沿对应，所述第二端连接所述低电压线。
其中，每一所述像素单元内包含一所述第二开关管或对应同一颜色滤光片的所述像素单元内含一所述第二开关管。
其中，所述后续扫描线与所述本级扫描线相邻。
其中，所述后续扫描线与所述本级扫描线至少间隔一级的所述扫描线连接，所述后续扫描线与所述本级扫描线之间的所述扫描线的数量等于所述第二开关管所在的所述像素单元的预充电时间与正式充电时间之比。
本发明的有益效果是：提供一种阵列基板及显示面板，通过在像素单元中增设第二开关管，且控制第二开关管的控制端连接至后续扫描线，在一个扫描周期内，扫描信号的脉冲宽度是固定的，其它条件不变的情况下，下降沿的时间缩短意味着扫描信号高电平的时间变长，也就是说第一开关管的开启时间变长，使得像素电极的充电时间变长，提升像素的充电率、降低错充电风险，提升液晶显示器的显示品质。
【附图说明】
图1是本发明阵列基板第一实施方式的结构示意图；
图2是本发明阵列基板第一实施方式的时序图；
图3是本发明阵列基板第二实施方式的结构示意图；
图4是本发明阵列基板第二实施方式的时序图；
图5是本发明阵列基板第三实施方式的结构示意图；
图6是本发明阵列基板第四实施方式的结构示意图；
图7是本发明与现有技术驱动方式充电波形的对比示意图；
图8是本发明显示面板一实施方式的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进级清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1是本发明阵列基板第一实施方式的结构示意图。如图1所示，该阵列基板10包括：多条扫描线11、多条数据线12及低电压线Vgl。其中，多条扫描线11与多条数据线12正交设置，以形成多个像素单元13。
其中，每一像素单元13包括一第一开关管T1，该第一开关管T1用于控制阵列基板10中像素电极的电压。且至少一个像素单元13进一步包括一第二开关管T2，该第二开关管T2包括：第一端a、第二端b以及控制端c，且第一端a连接第一开关管T1的控制端，所述控制端c连接一后续扫描线，后续扫描线的开启顺序在第二开关管T2所在的像素单元13对应的本级扫描线之后，第二端b连接低电压线Vgl，用于在后续扫描线开启时，以使得本级扫描线快速下降至低电位。
该阵列基板10还包括扫描驱动电路14及数据驱动电路15。其中，扫描驱动电路14用以提供扫描信号至扫描线，数据驱动电路15用以提供灰阶信号至数据线。
结合图1，在本发明一应用场景中，每一像素单元13内均包含一第二开关管T2，且后续扫描线的开启顺序在第二开关管T2所在的像素单元13对应的本级扫描线之后，且该后续扫描线与本级扫描线相邻。以第N级像素单元为例，该像素单元13在两相邻的低电压线Vgl和两相邻数据线所围成的区域，且该像素单元13的第一开关管T1和像素电极位于相邻两数据线、该第N级像素单元13的扫描线以及下一级低电压线Vgl所围成的区域。该像素单元13的第二开关管T2位于相邻两数据线、该第N级像素单元13的扫描线以及本级低电压线Vgl所围成的区域。
其中，该第N级像素单元13的第一开关管T1也包括控制端d、第一端e以及第二端f，该控制端d连接本级扫描线，该第一端e连接数据线，第二端f连接像素电极。该第N级像素单元13的第二开关管T2的第一端a连接第一开关管T1的控制端d，第二端b连接本级低电压线Vgl，第三端c连接下一级扫描线。
请进一步参阅图2，图2为本发明阵列基板第一实施方式的时序图。结合图1，以第N级像素单元13为例，本级扫描线扫描信号的下降沿与第N+1级扫描线扫描信号的上升沿对应。
具体有，当扫描驱动电路14提供扫描信号至扫描线，即图2中当扫描信号为高电平时，第一开关管T1的控制端d开启，此时数据驱动电路15提供灰阶信号至数据线，通过第一开关管T1给像素电极充电，该像素电极可以为红色像素电极、绿色像素电极、蓝色像素电极及白色像素电极中的一种。当该级像素电极充电完成后，扫描驱动电路14给第N+1级扫描线高电平，以使得第N+1级像素单元在开启的同时，第N级像素单元的第二开关管T2也随之开启，第二开关管T2的第二端b连接低电压线Vgl，可以使得第N级像素单元的扫描线的扫描信号快速下降至低电位。
上述实施方式，通过在像素单元中增设第二开关管，且控制第二开关管的控制端连接至后续扫描线，在一个扫描周期内，扫描信号的脉冲宽度是固定的，其它条件不变的情况下，下降沿的时间缩短意味着扫描信号高电平的时间变长，也就是说第一开关管的开启时间变长，使得像素电极的充电时间变长，提升像素的充电率、降低错充电风险，提升液晶显示器的显示品质。
请参阅图3，图3为本发明阵列基板第二实施方式的结构示意图，该实施方式与第一实施方式不同之处在于，第一实施例中的后续扫描线与本级扫描线相邻，即第N级像素单元的第二开关管T2的控制端连接第N+1级像素单元的扫描线。第二实施例中的后续扫描线与第N级像素单元的扫描线至少间隔一级的扫描线连接，且该后续扫描线与本级扫描线之间的扫描线的数量等于本级第二开关管T2所在的像素单元的预充电时间与正式充电时间之比。本实施例中，第N级像素单元的第二开关管T2的控制端连接第N+2级像素单元的扫描线。具体描述如下：
如图3，该阵列基板20包括：多条扫描线21、多条数据线22及低电压线Vgl。其中，多条扫描线21与多条数据线22正交设置，以形成多个像素单元23。该阵列基板20还包括扫描驱动电路24及数据驱动电路25。其中，扫描驱动电路用以提供扫描信号至扫描线21，数据驱动电路用以提供灰阶信号至数据线22。
以第N级像素单元23为例，每一像素单元23包括一第一开关管T1，该第一开关管T1用于控制阵列基板20中像素电极的电压。且该整列基板20中每一像素单元23进一步包括一第二开关管T2，该第二开关管T2包括：第一端a、第二端b以及控制端c，且第一端a连接第一开关管T1的控制端d，所述控制端c连接第N+2级像素单元的扫描线上，第二端b连接低电压线Vgl，用于在第N+2级像素单元的扫描线开启时，以使得本级扫描线快速下降至低电位。
请进一步结合图4，图4为本发明阵列基板第二实施方式的时序图。同理，以第N级像素单元23为例，本实施例中，本级扫描线扫描信号的下降沿与第N+2级扫描线扫描信号的上升沿对应。
具体有，当扫描线21扫描信号的上升时间过长时，通常需要采用预充电（Pre-charge）的驱动方式来给像素电极充电。所谓预充电就是本级扫描线在真正驱动寻址前，扫描驱动电路24给本级扫描线高电平，打开第一开关管T1，对本级的像素进行预充电。如图5中所示虚线部分的前半段时间t1则为本级像素电极的预充电时间，虚线后半部分为正式充电时间t2，且以本发明第二实施方式为例，该级像素单元的预充电时间t1和其正式充电时间t2相等，且由图5还可以得到，当本级像素单元进入正式充电时间时，第N+1级像素单元开启第一开关管T1进行预充电。
当第N级像素单元充电完成时，则扫描驱动电路24给第N+2级像素单元的扫描线高电平，以使得第N+2级像素单元在开启的同时，第N级像素单元的第二开关管T2也随之开启，第二开关管T2的第二端b连接低电压线Vgl，可以使得第N级像素单元扫描线的扫描信号快速下降至低电位。在其它实施例中，第N级像素单元中的第二开关管T2的控制端c不限于连接到第N+2级像素单元的扫描线，且其具体连接位置需要由第N级像素单元的预充电时间来决定，具体有当第N级像素单元的预充电时间为正式充电时间的整数倍时，即当t1=（m+1）*t2时，m为正整数，该第N级像素单元的第二开关管T2的控制端应当连接到第N+m行像素单元的扫描线上。
上述实施方式，通过在像素单元中增设第二开关管，且控制第二开关管的控制端连接至后续扫描线，在一个扫描周期内，扫描信号的脉冲宽度是固定的，其它条件不变的情况下，下降沿的时间缩短意味着扫描信号高电平的时间变长，也就是说第一开关管的开启时间变长，使得像素电极的充电时间变长，提升像素的充电率、降低错充电风险，提升液晶显示器的显示品质。
请参阅图5，图5为本发明阵列基板第三实施方式的结构示意图，与第一实施方式不同之处在于，第一实施例中每一像素单元均包含一第二开关管T2，而第三实施例中，对应同一颜色滤光片的像素单元内含一第二开关管T2，即第N级像素单元中，第二开关管T2可以位于红色滤光片、绿色滤光片以及蓝色滤光片对应的子像素中的一种。具体描述如下：
如图5所示，该阵列基板30包括：多条扫描线31、多条数据线32及低电压线Vgl。其中，多条扫描线31与多条数据线32正交设置，以形成多个像素单元33。
该阵列基板30还包括扫描驱动电路34及数据驱动电路35。其中，扫描驱动电路34用以提供扫描信号至扫描线31，数据驱动电路35用以提供灰阶信号至数据线32。
以第N级像素单元33为例，每一像素单元33包括一第一开关管T1，该第一开关管T1用于控制阵列基板30中像素电极的电压。该级像素单元中以蓝色滤光片对应的子像素为例，即第二开关管T2仅位于该像素单元33内。且该像素单元33在两相邻的低电压线Vgl和两相邻数据线所围成的区域，该像素单元33的第一开关管T1和像素电极位于相邻两数据线、该第N级像素单元33的扫描线以及下一级低电压线Vgl所围成的区域。该像素单元33的第二开关管T2位于相邻两数据线、该第N级像素单元33的扫描线以及本级低电压线Vgl所围成的区域。
其中，该第N级像素单元33的第一开关管T1的控制端d连接本级扫描线，第一端e连接数据线，第二端f连接像素电极。第二开关管T2的第一端a连接第一开关管T1的控制端d，第二端b连接本级低电压线Vgl，第三端c连接下一级扫描线。
在描述其工作原理的同时可以进一步参考图2中，本发明阵列基板的时序图，即图2中当第N级像素单元的扫描信号为高电平时，第一开关管T1的控制端d开启，此时数据驱动电路35提供灰阶信号至数据线，通过第一开关管T1给像素电极充电。当该第N级像素电极充电完成后，扫描驱动电路34给本级扫描线低电平使其关闭，同时给下一级扫描线高电平，以使得第N+1级像素单元在开启的同时，第N级像素单元的第二开关管T2也随之开启，第二开关管T2的第二端b连接低电压线Vgl，可以使得第N级像素单元的扫描线快速下降至低电位。当然在其它实施例中，第二开关管T2还可以位于红色、绿色滤光片对应的像素单元内，其分析原理一样，此处不再赘述。
上述实施方式，通过在像素单元中增设第二开关管，且控制第二开关管的控制端连接至后续扫描线，在一个扫描周期内，扫描信号的脉冲宽度是固定的，其它条件不变的情况下，下降沿的时间缩短意味着扫描信号高电平的时间变长，也就是说第一开关管的开启时间变长，使得像素电极的充电时间变长，提升像素的充电率、降低错充电风险，提升液晶显示器的显示品质。
请参阅图6，图6为本发明阵列基板第四实施方式的结构示意图，与第三实施方式不同之处在于，第三实施例中的后续扫描线与本级扫描线相邻，即第N级像素单元的第二开关管T2的控制端连接第N+1级像素单元的扫描线。第三实施例中的后续扫描线与第N级像素单元的扫描线至少间隔一级的扫描线连接，后续扫描线与本级扫描线之间的扫描线的数量等于本级像素单元第二开关管T2所在的像素单元的预充电时间与正式充电时间之比。在本实施例中，第N级像素单元的第二开关管T2的控制端连接第N+2级像素单元的扫描线。具体描述如下：
如图6，该阵列基板40包括：多条扫描线41、多条数据线42及低电压线Vgl。其中，多条扫描线41与多条数据线42正交设置，以形成多个像素单元43。该阵列基板40还包括扫描驱动电路44及数据驱动电路45。其中，扫描驱动电路用以提供扫描信号至扫描线41，数据驱动电路用以提供灰阶信号至数据线42。
以第N级像素单元43为例，每一像素单元43包括一第一开关管T1，该第一开关管T1用于控制阵列基板40中像素电极的电压。且该整列基板40中每一像素单元43进一步包括一第二开关管T2，该第二开关管T2包括：第一端a、第二端b以及控制端c，且第一端a连接第一开关管T1的控制端d，所述控制端c连接第N+2级像素单元的扫描线Gn+2上，第二端b连接低电压线Vgl，用于在第N+2级像素单元的扫描线开启时，以使得本级扫描线快速下降至低电位。在描述其具体实施方式时可以结合图4第二实施方式的时序图，且其分析原理和第二实施方式类似，可以参见上文描述，此处不再赘述。
请参阅图7，图7为本发明与现有技术驱动方式充电波形的对比示意图。如图7所示，采用本发明驱动方式A的充电波形的下降时间更短，且其下降沿的下降速度更快，在一个周期内，扫描信号的脉冲宽度是固定的，其它条件不变的情况下，下降沿的时间缩短意味着扫描信号高电平的时间变长，也就是说第一开关管的开启时间变长，使得像素电极的充电时间变长，提升像素的充电率、降低错充电风险，提升液晶显示器的显示品质。
请参阅图8，图8是本发明显示面板一实施方式的结构示意图。本发明提供的一种显示面板50，该液晶显示面板50包括上述任一实施例中的阵列基板B、与阵列基板B相对设置的公共基板51以及夹持于阵列基板B与公共基板51之间的液晶层52，具体内容请参见上文描述，此处不再赘述。
综上所述，本领域技术人员容易理解，本发明提供一种阵列基板及显示面板，上述实施方式，通过在像素单元中增设第二开关管，且控制第二开关管的控制端连接至后续扫描线，在一个扫描周期内，扫描信号的脉冲宽度是固定的，其它条件不变的情况下，下降沿的时间缩短意味着扫描信号高电平的时间变长，也就是说第一开关管的开启时间变长，使得像素电极的充电时间变长，提升像素的充电率、降低错充电风险，提升液晶显示器的显示品质。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种阵列基板，其中，所述阵列基板包括：
    多条扫描线、多条数据线及低电压线；
    所述多条扫描线与所述多条数据线正交设置，以形成多个像素单元；其中，每一所述像素单元包括一第一开关管，且至少一个所述像素单元进一步包括一第二开关管；
    所述第二开关管包括：第一端、第二端以及控制端，所述第一端连接所述第一开关管的控制端，所述控制端连接一后续扫描线，所述后续扫描线的开启顺序在所述第二开关管所在的所述像素单元对应的本级扫描线之后，所述本级扫描线扫描信号的下降沿与所述后续扫描线扫描信号的上升沿对应，所述第二端连接所述低电压线；
    每一所述像素单元内包含一所述第二开关管；
    所述阵列基板还包括扫描驱动电路，所述扫描驱动电路用以提供扫描信号至所述扫描线。
  2. 根据权利要求1所述的阵列基板，其中，所述后续扫描线与所述本级扫描线相邻。
  3. 根据权利要求1所述的阵列基板，其中，所述后续扫描线与所述本级扫描线至少间隔一级的所述扫描线连接，所述后续扫描线与所述本级扫描线之间的所述扫描线的数量等于所述第二开关管所在的所述像素单元的预充电时间与正式充电时间之比。
  4. 一种阵列基板，其中，所述阵列基板包括：
    多条扫描线、多条数据线及低电压线；
    所述多条扫描线与所述多条数据线正交设置，以形成多个像素单元；其中，每一所述像素单元包括一第一开关管，且至少一个所述像素单元进一步包括一第二开关管；
    所述第二开关管包括：第一端、第二端以及控制端，所述第一端连接所述第一开关管的控制端，所述控制端连接一后续扫描线，所述后续扫描线的开启顺序在所述第二开关管所在的所述像素单元对应的本级扫描线之后，所述本级扫描线扫描信号的下降沿与所述后续扫描线扫描信号的上升沿对应，所述第二端连接所述低电压线。
  5. 根据权利要求4所述的阵列基板，其中，每一所述像素单元内包含一所述第二开关管。
  6. 根据权利要求5所述的阵列基板，其中，所述后续扫描线与所述本级扫描线相邻。
  7. 根据权利要求5所述的阵列基板，其中，所述后续扫描线与所述本级扫描线至少间隔一级的所述扫描线连接，所述后续扫描线与所述本级扫描线之间的所述扫描线的数量等于所述第二开关管所在的所述像素单元的预充电时间与正式充电时间之比。
  8. 根据权利要求4所述的阵列基板，其中，对应同一颜色滤光片的所述像素单元内含一所述第二开关管。
  9. 根据权利要求8所述的阵列基板，其中，所述后续扫描线与所述本级扫描线相邻。
  10. 根据权利要求8所述的阵列基板，其中，所述后续扫描线与所述本级扫描线至少间隔一级的所述扫描线连接，所述后续扫描线与所述本级扫描线之间的所述扫描线的数量等于所述第二开关管所在的所述像素单元的预充电时间与正式充电时间之比。
  11. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括扫描驱动电路，所述扫描驱动电路用以提供扫描信号至所述扫描线。
  12. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括数据驱动电路，所述数据驱动电路用以提供灰阶信号至所述数据线。
  13. 一种显示面板，其中，所述显示面板包括阵列基板，与所述阵列基板相对设置的对向基板以及夹持于所述阵列基板与所述对向基板之间的液晶层；
    其中，所述阵列基板包括：
    多条扫描线、多条数据线及低电压线；
    所述多条扫描线与所述多条数据线正交设置，以形成多个像素单元；其中，每一所述像素单元包括一第一开关管，且至少一个所述像素单元进一步包括一第二开关管；
    所述第二开关管包括：第一端、第二端以及控制端，所述第一端连接所述第一开关管的控制端，所述控制端连接一后续扫描线，所述后续扫描线的开启顺序在所述第二开关管所在的所述像素单元对应的本级扫描线之后，所述本级扫描线扫描信号的下降沿与所述后续扫描线扫描信号的上升沿对应，所述第二端连接所述低电压线。
  14. 根据权利要求13所述的显示面板，其中，每一所述像素单元内包含一所述第二开关管或对应同一颜色滤光片的所述像素单元内含一所述第二开关管。
  15. 根据权利要求14所述的显示面板，其中，所述后续扫描线与所述本级扫描线相邻。
  16. 根据权利要求14所述的显示面板，其中，所述后续扫描线与所述本级扫描线至少间隔一级的所述扫描线连接，所述后续扫描线与所述本级扫描线之间的所述扫描线的数量等于所述第二开关管所在的所述像素单元的预充电时间与正式充电时间之比。
PCT/CN2017/079548 2017-02-27 2017-04-06 一种阵列基板及显示面板 Ceased WO2018152936A1 (zh)

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