WO2018152896A1 - Oled像素驱动电路及像素驱动方法 - Google Patents

Oled像素驱动电路及像素驱动方法 Download PDF

Info

Publication number
WO2018152896A1
WO2018152896A1 PCT/CN2017/076862 CN2017076862W WO2018152896A1 WO 2018152896 A1 WO2018152896 A1 WO 2018152896A1 CN 2017076862 W CN2017076862 W CN 2017076862W WO 2018152896 A1 WO2018152896 A1 WO 2018152896A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
type thin
node
scan signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/076862
Other languages
English (en)
French (fr)
Inventor
邝继木
温亦谦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US15/519,840 priority Critical patent/US10319304B2/en
Publication of WO2018152896A1 publication Critical patent/WO2018152896A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0646—Modulation of illumination source brightness and image signal correlated to each other

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an OLED pixel driving circuit and a pixel driving method.
  • OLED Organic Light Emitting Display
  • OLED Organic Light Emitting Display
  • the OLED is a current driving device.
  • the organic light emitting diode emits light, and the luminance of the light is determined by the current flowing through the organic light emitting diode itself.
  • Most existing integrated circuits (ICs) only transmit voltage signals, so the pixel driving circuit of the OLED needs to complete the task of converting the voltage signal into a current signal.
  • the conventional OLED pixel driving circuit is usually 2T1C, that is, a structure in which two thin film transistors are added with a capacitor to convert a voltage into a current.
  • a conventional 2T1C pixel driving circuit for an OLED includes a first thin film transistor T10, a second thin film transistor T20, and a capacitor C10.
  • the first thin film transistor T10 is an N-type thin film transistor and functions as a switching thin film transistor;
  • the second thin film transistor T20 is a P-type thin film transistor used as a driving thin film transistor;
  • the capacitor C10 is a storage capacitor.
  • the gate of the first thin film transistor T10 is connected to the scan signal Scan, the source is connected to the data signal Data, and the drain is electrically connected to the gate of the second thin film transistor T20 and one end of the capacitor C10;
  • the source of the thin film transistor T20 is connected to the power supply voltage VDD, the drain is electrically connected to the anode of the organic light emitting diode D10, the cathode of the organic light emitting diode D10 is connected to the common ground voltage VSS, and one end of the capacitor C10 is electrically connected to the second thin film transistor T20.
  • the gate is electrically connected to the source of the second thin film transistor T20.
  • the scan signal Scan controls the first thin film transistor T10 to be turned on, and the data signal Data passes through the first thin film transistor T10 to enter the gate of the second thin film transistor T20 and the capacitor C10, and then the first thin film transistor T10 is turned off due to the capacitor C10.
  • the gate voltage of the second thin film transistor T20 can continue to maintain the data signal voltage, so that the second thin film transistor T20 is in an on state, and the driving current enters the organic light emitting diode D10 through the second thin film transistor T20 to drive the organic light emitting diode. D10 shines.
  • I OLED K ⁇ (V gs - V th ) 2
  • I OLED represents the current flowing through the driving thin film transistor and the organic light emitting diode
  • K is an intrinsic conductive factor of the driving thin film transistor
  • V gs represents a voltage difference between the gate and the source of the driving thin film transistor
  • V th represents driving The threshold voltage of the thin film transistor. It can be seen that the size of the I OLED is related to the threshold voltage V th of the driving thin film transistor.
  • the above-mentioned conventional OLED pixel driving circuit has a simple structure and does not have a compensation function, so there are many defects, among which the driving thin film transistor of each pixel in the OLED display panel is relatively obvious due to the non-uniformity in the manufacturing process of the thin film transistor.
  • the threshold voltages are inconsistent; and because the long-term operation causes the material of the driving thin film transistor to age, causing the threshold voltage of the driving thin film transistor to drift, the OLED panel may be unevenly displayed.
  • An object of the present invention is to provide an OLED pixel driving circuit capable of eliminating the influence of a threshold voltage of a driving thin film transistor on a current flowing through an organic light emitting diode, and improving display uniformity of the OLED panel.
  • Another object of the present invention is to provide an OLED pixel driving method capable of eliminating the influence of a threshold voltage of a driving thin film transistor on a current flowing through an organic light emitting diode, and improving display uniformity of the OLED panel.
  • the present invention first provides an OLED pixel driving circuit including a first N-type thin film transistor, a second N-type thin film transistor, a third N-type thin film transistor, a fourth N-type thin film transistor, and a fifth P-type film.
  • the gate of the first N-type thin film transistor is connected to the third scan signal, the source is connected to the data signal, and the drain is electrically connected to the first node;
  • the gate of the second N-type thin film transistor is connected to the second scan signal, the source is electrically connected to the first node, and the drain is electrically connected to the second node;
  • the gate of the third N-type thin film transistor is connected to the light emission control signal, the source is connected to the high voltage of the power source, and the drain is electrically connected to the third node;
  • the gate of the fourth N-type thin film transistor is connected to the second scan signal, the source is electrically connected to the third node, and the drain is electrically connected to the fifth node;
  • the gate of the fifth P-type thin film transistor is connected to the light emission control signal, the source is electrically connected to the fourth node, and the drain is connected to the common ground voltage;
  • the gate of the sixth N-type thin film transistor is connected to the first scan signal, and the source is electrically connected to the fifth section Point, drain time sharing power supply low voltage or light brightness adjustment voltage;
  • the gate of the seventh P-type thin film transistor is electrically connected to the first node, the source is electrically connected to the third node, and the drain is electrically connected to the second node;
  • the anode of the organic light emitting diode is electrically connected to the second node, and the cathode is connected to a common ground voltage;
  • One end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the fourth node;
  • One end of the second capacitor is electrically connected to the fourth node, and the other end is electrically connected to the fifth node.
  • the combination of the first scan signal, the second scan signal, the third scan signal, the illumination control signal, and the data signal sequentially corresponds to a reset phase, a threshold voltage detection phase, a data writing phase, and an illumination phase;
  • the first scan signal is high, the second scan signal is low, the third scan signal is low, the illumination control signal is low, and the data signal is low;
  • the sixth N-type film The drain of the transistor is connected to the low voltage of the power supply;
  • the first scan signal is low, the second scan signal is high, the third scan signal is low, the illumination control signal is low, and the data signal is low;
  • the first scan signal is low, the second scan signal is low, the third scan signal is high, the illumination control signal is low, and the data signal is high;
  • the first scan signal is high, the second scan signal is low, the third scan signal is low, the illumination control signal is high, and the data signal is low;
  • the sixth N-type film The drain of the transistor is connected to the light-emitting brightness adjustment voltage;
  • the power supply low voltage is higher than a sum of a threshold voltage of the seventh P-type thin film transistor and a threshold voltage of the organic light emitting diode.
  • the common ground voltage is not higher than the light-emitting brightness adjustment voltage, and the light-emitting brightness adjustment voltage is lower than a sum of a power source high voltage and a threshold voltage of the organic light-emitting diode minus a high-potential voltage value provided by the data signal.
  • the first scan signal, the second scan signal, the third scan signal, the illumination control signal, and the data signal are all generated by an external timing controller.
  • the transistors are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the invention also provides an OLED pixel driving method, comprising the following steps:
  • Step 1 Providing an OLED pixel driving circuit
  • the OLED pixel driving circuit includes a first N-type thin film transistor, a second N-type thin film transistor, a third N-type thin film transistor, a fourth N-type thin film transistor, a fifth P-type thin film transistor, and a sixth N-type thin film transistor, a seven-P thin film transistor, a first capacitor, a second capacitor, and an organic light emitting diode; the seventh P-type thin film transistor is used as a driving thin film transistor of an organic light emitting diode;
  • the gate of the first N-type thin film transistor is connected to the third scan signal, the source is connected to the data signal, and the drain is electrically connected to the first node;
  • the gate of the second N-type thin film transistor is connected to the second scan signal, the source is electrically connected to the first node, and the drain is electrically connected to the second node;
  • the gate of the third N-type thin film transistor is connected to the light emission control signal, the source is connected to the high voltage of the power source, and the drain is electrically connected to the third node;
  • the gate of the fourth N-type thin film transistor is connected to the second scan signal, the source is electrically connected to the third node, and the drain is electrically connected to the fifth node;
  • the gate of the fifth P-type thin film transistor is connected to the light emission control signal, the source is electrically connected to the fourth node, and the drain is connected to the common ground voltage;
  • the gate of the sixth N-type thin film transistor is connected to the first scan signal, the source is electrically connected to the fifth node, and the drain is time-divisionally connected to the power supply low voltage or the light-emitting brightness adjustment voltage;
  • the gate of the seventh P-type thin film transistor is electrically connected to the first node, the source is electrically connected to the third node, and the drain is electrically connected to the second node;
  • the anode of the organic light emitting diode is electrically connected to the second node, and the cathode is connected to a common ground voltage;
  • One end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the fourth node;
  • One end of the second capacitor is electrically connected to the fourth node, and the other end is electrically connected to the fifth node;
  • Step 2 enter the reset phase
  • the first scan signal provides a high potential
  • the second scan signal provides a low potential
  • the third scan signal provides a low potential
  • the illumination control signal provides a low potential
  • the data signal provides a low potential
  • the sixth N-type thin film transistor has a drain input Power supply low voltage
  • the fifth P-type thin film transistor and the sixth N-type thin film transistor are turned on, the other thin film transistors are turned off, the power supply low voltage is charged to the second capacitor, and the second capacitor is initialized, and the voltage difference between the second capacitor is reset to VDDL-VSS.
  • VDDL represents the low voltage of the power supply
  • VSS represents the common ground voltage
  • Step 3 Enter a threshold voltage detection phase
  • the first scan signal transitions to a low potential
  • the second scan signal transitions to a high potential
  • the third scan signal remains at a low potential
  • the illumination control signal remains at a low potential
  • the data signal remains at a low potential
  • the second N-type thin film transistor, the fourth N-type thin film transistor, the fifth P-type thin film transistor, and the seventh P-type thin film transistor are all turned on, the first N-type thin film transistor, the third N-type thin film transistor, and the sixth N-type
  • the thin film transistor is turned off, and the storage voltage of the second capacitor discharged to the seventh P-type thin film transistor to the second capacitor is V th +V th — OLED , wherein V th is the threshold voltage of the seventh P-type thin film transistor, and V th —OLED is organic The threshold voltage of the light emitting diode;
  • Step 4 entering the data writing phase
  • the first scan signal remains at a low potential
  • the second scan signal transitions to a low potential
  • the third scan signal transitions to a high potential
  • the illumination control signal remains at a low potential
  • the data signal transitions to a high potential
  • the first N-type thin film transistor and the fifth P-type thin film transistor are turned on, and the other thin film transistors are turned off, and the data signal is charged to the first capacitor to the storage voltage of the first capacitor and the potential of the first node is V Data , V Data is a high potential voltage value provided by the data signal;
  • Step 5 entering the lighting stage
  • the first scan signal transitions to a high potential, the second scan signal remains at a low potential, the third scan signal transitions to a low potential, the illumination control signal transitions to a high potential, and the data signal transitions to a low potential;
  • the sixth N-type thin film transistor The drain is connected to the light-emitting brightness adjustment voltage;
  • the third N-type thin film transistor, the sixth N-type thin film transistor, and the seventh P-type thin film transistor are both turned on, the first N-type thin film transistor, the second N-type thin film transistor, the fourth N-type thin film transistor, and the fifth P-type
  • the thin film transistors are turned off, and the brightness adjustment voltage is sent to the fifth node, and the potential of the first node becomes:
  • Va Vr+V Data -V th -V th_OLED
  • Va represents the potential of the first node
  • Vr represents the luminance adjustment voltage of the light
  • the organic light emitting diode emits light, and a current flowing through the organic light emitting diode is independent of a threshold voltage of the seventh P type thin film transistor.
  • the power supply low voltage is higher than a sum of a threshold voltage of the seventh P-type thin film transistor and a threshold voltage of the organic light emitting diode.
  • the common ground voltage is not higher than the light-emitting brightness adjustment voltage, and the light-emitting brightness adjustment voltage is lower than a sum of a power source high voltage and a threshold voltage of the organic light-emitting diode minus a high-potential voltage value provided by the data signal.
  • the first scan signal, the second scan signal, the third scan signal, the illumination control signal, and the data signal are all generated by an external timing controller;
  • the transistors are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the present invention also provides an OLED pixel driving circuit including a first N-type thin film transistor, a second N-type thin film transistor, a third N-type thin film transistor, a fourth N-type thin film transistor, a fifth P-type thin film transistor, a sixth N-type thin film transistor, a seventh P-type thin film transistor, a first capacitor, a second capacitor, And an organic light emitting diode; the seventh P type thin film transistor is used as a driving thin film transistor of the organic light emitting diode;
  • the gate of the first N-type thin film transistor is connected to the third scan signal, the source is connected to the data signal, and the drain is electrically connected to the first node;
  • the gate of the second N-type thin film transistor is connected to the second scan signal, the source is electrically connected to the first node, and the drain is electrically connected to the second node;
  • the gate of the third N-type thin film transistor is connected to the light emission control signal, the source is connected to the high voltage of the power source, and the drain is electrically connected to the third node;
  • the gate of the fourth N-type thin film transistor is connected to the second scan signal, the source is electrically connected to the third node, and the drain is electrically connected to the fifth node;
  • the gate of the fifth P-type thin film transistor is connected to the light emission control signal, the source is electrically connected to the fourth node, and the drain is connected to the common ground voltage;
  • the gate of the sixth N-type thin film transistor is connected to the first scan signal, the source is electrically connected to the fifth node, and the drain is time-divisionally connected to the power supply low voltage or the light-emitting brightness adjustment voltage;
  • the gate of the seventh P-type thin film transistor is electrically connected to the first node, the source is electrically connected to the third node, and the drain is electrically connected to the second node;
  • the anode of the organic light emitting diode is electrically connected to the second node, and the cathode is connected to a common ground voltage;
  • One end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the fourth node;
  • One end of the second capacitor is electrically connected to the fourth node, and the other end is electrically connected to the fifth node;
  • the first scan signal, the second scan signal, the third scan signal, the illumination control signal, and the data signal are sequentially combined to correspond to a reset phase, a threshold voltage detection phase, a data writing phase, and a light emission. stage;
  • the first scan signal is high, the second scan signal is low, the third scan signal is low, the illumination control signal is low, and the data signal is low;
  • the sixth N-type film The drain of the transistor is connected to the low voltage of the power supply;
  • the first scan signal is low, the second scan signal is high, the third scan signal is low, the illumination control signal is low, and the data signal is low;
  • the first scan signal is low, the second scan signal is low, the third scan signal is high, the illumination control signal is low, and the data signal is high;
  • the first scan signal is at a high potential, and the second scan signal is at a low level Bit, the third scan signal is low, the light emission control signal is high, and the data signal is low; the drain of the sixth N-type thin film transistor is connected to the light emission brightness adjustment voltage;
  • the first scan signal, the second scan signal, the third scan signal, the illumination control signal, and the data signal are all generated by an external timing controller.
  • the invention provides an OLED pixel driving circuit and a pixel driving method, which adopts a 7T2C structure pixel driving circuit, a first scanning signal, a second scanning signal, a third scanning signal, an illumination control signal, and data.
  • the signal phase combination successively corresponds to a reset phase, a threshold voltage detection phase, a data writing phase, and an illumination phase, which can eliminate the influence of the threshold voltage of the driving thin film transistor on the current flowing through the organic light emitting diode, and improve the display of the OLED panel. Uniformity.
  • 1 is a circuit diagram of a conventional 2T1C structure OLED pixel driving circuit
  • FIG. 2 is a circuit diagram of an OLED pixel driving circuit of the present invention
  • FIG. 3 is a timing diagram of an OLED pixel driving circuit of the present invention.
  • FIG. 4 is a schematic diagram of the OLED pixel driving circuit of the present invention in a reset phase and a schematic diagram of step 2 of the OLED pixel driving method of the present invention
  • FIG. 5 is a schematic diagram of a OLED pixel driving circuit of the present invention at a threshold voltage detecting stage and a schematic diagram of step 3 of the OLED pixel driving method of the present invention
  • FIG. 6 is a schematic diagram of an OLED pixel driving circuit of the present invention in a data writing phase and a schematic diagram of step 4 of the OLED pixel driving method of the present invention
  • FIG. 7 is a schematic diagram of an OLED pixel driving circuit of the present invention in an illuminating phase and a step 5 of the OLED pixel driving method of the present invention.
  • the present invention firstly provides an OLED pixel driving circuit, which adopts a 7T2C structure, including a first N-type thin film transistor T1, a second N-type thin film transistor T2, a third N-type thin film transistor T3, and a first Four N-type thin film transistor T4, fifth P-type thin film transistor T5, a sixth N-type thin film transistor T6, a seventh P-type thin film transistor T7, a first capacitor C1, a second capacitor C2, and an organic light emitting diode D1.
  • a 7T2C structure including a first N-type thin film transistor T1, a second N-type thin film transistor T2, a third N-type thin film transistor T3, and a first Four N-type thin film transistor T4, fifth P-type thin film transistor T5, a sixth N-type thin film transistor T6, a seventh P-type thin film transistor T7, a first capacitor C1, a second capacitor C2, and an organic light emitting diode D1.
  • the gate of the first N-type thin film transistor T1 is connected to the third scan signal Scan3, the source is connected to the data signal Data, the drain is electrically connected to the first node a, and the gate of the second N-type thin film transistor T2 is connected to the second Scanning signal Scan2, the source is electrically connected to the first node a, the drain is electrically connected to the second node b; the gate of the third N-type thin film transistor T3 is connected to the light emission control signal EM, and the source is connected to the power supply high voltage VDDH, The drain is electrically connected to the third node c; the gate of the fourth N-type thin film transistor T4 is connected to the second scan signal Scan2, the source is electrically connected to the third node c, and the drain is electrically connected to the fifth node e;
  • the gate of the P-type thin film transistor T5 is connected to the light-emission control signal EM, the source is electrically connected to the fourth node d, the drain is connected to the common
  • the source is electrically connected to the fifth node e
  • the drain is time-divisionally connected to the power supply low voltage VDDL or the light-emitting brightness adjustment voltage Vr
  • the seventh P-type thin film transistor T7 is a driving thin film transistor directly driving the organic light-emitting diode D1, the gate thereof Very electrically connected to the first node a, the source is electrically connected to the third section Point c, the drain is electrically connected to the second node b; the anode of the organic light emitting diode D1 is electrically connected to the second node b, and the cathode is connected to the common ground voltage VSS; one end of the first capacitor C1 is electrically connected to the first node a, and the other One end is electrically connected to the fourth node d; one end of the second capacitor C2 is electrically connected to the fourth node d, and the other end is electrically connected to the fifth node e.
  • the transistor T6 and the seventh P-type thin film transistor T7 are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors; the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3
  • the illumination control signal EM and the data signal Data are all generated by an external timing controller.
  • the combination of the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, the illumination control signal EM, and the data signal Data sequentially corresponds to a reset phase S1, a threshold voltage detection phase S2, and a data write. Stage S3, and a lighting stage S4.
  • the first scan signal Scan1 is at a high potential
  • the second scan signal Scan2 is at a low potential
  • the third scan signal Scan3 is at a low potential
  • the light emission control signal EM is at a low potential
  • the data signal Data is at a low potential
  • the sixth N-type thin film transistor The drain of T6 is connected to the power supply low voltage VDDL.
  • the fifth P-type thin film transistor T5 and the sixth N-type thin film transistor T6 are turned on, and the other thin film transistors are turned off, and the power supply low voltage VDDL is charged to the second capacitor C2 via the turned-on sixth N-type thin film transistor T6, and the second capacitor C2 is charged.
  • the voltage difference between the fifth node e and the fourth node d after the completion of charging is the voltage difference V ed :
  • V ed VDDL-VSS
  • the power supply low voltage VDDL is higher than the sum of the threshold voltage of the seventh P-type thin film transistor T7, that is, the driving thin film transistor and the threshold voltage of the organic light emitting diode D1, that is,
  • V th represents a threshold voltage of the seventh P-type thin film transistor T7
  • V th — OLED is a threshold voltage of the organic light emitting diode D1.
  • the first scan signal Scan1 is at a low potential
  • the second scan signal Scan2 is at a high potential
  • the third scan signal Scan3 is at a low potential
  • the light emission control signal EM is at a low potential
  • the data signal Data is Low potential.
  • the second N-type thin film transistor T2, the fourth N-type thin film transistor T4, the fifth P-type thin film transistor T5, and the seventh P-type thin film transistor T7 are all turned on, and the first N-type thin film transistor T1 and the third N-type thin film transistor T3 And the sixth N-type thin film transistor T6 is turned off, and the fourth N-type thin film transistor T4 that is turned on at the fifth node e is connected to the source of the third node c, that is, the seventh P-type thin film transistor T7, the first node a That is, the second N-type thin film transistor T2 whose gate of the seventh P-type thin film transistor T7 is turned on is in communication with the anode of the second node b, that is, the organic light emitting diode D1, and the second capacitor C2 is discharged to the seventh P-type thin film transistor T7.
  • V ed between the fifth node e and the fourth node d is:
  • V ed V th +V th_OLED
  • the storage voltage of the second capacitor C2 is V th +V th — OLED .
  • the first scan signal Scan1 is at a low potential
  • the second scan signal Scan2 is at a low potential
  • the third scan signal Scan3 is at a high potential
  • the light emission control signal EM is at a low potential
  • the data signal Data is at a high potential.
  • the first N-type thin film transistor T1 and the fifth P-type thin film transistor T5 are turned on, and the other thin film transistors are turned off, and the data signal Data is charged to the first capacitor C1 by the first N-type thin film transistor T1 that is turned on to the first capacitor C1.
  • the storage voltage and the potential of the first node a are the high-potential voltage values V Data supplied by the data signal Data .
  • the second capacitor C2 is in a floating state.
  • the first scan signal Scan1 is at a high potential
  • the second scan signal Scan2 is at a low potential
  • the third scan signal Scan3 is at a low potential
  • the illumination control signal EM is at a high potential
  • the data signal Data is It is low potential
  • the drain of the sixth N-type thin film transistor T6 is connected to the light-emission luminance adjustment voltage Vr.
  • the third N-type thin film transistor T3, the sixth N-type thin film transistor T6, and the seventh P-type thin film transistor T7 are both turned on, the first N-type thin film transistor T1, the second N-type thin film transistor T2, and the fourth N-type thin film transistor T4 And the fifth P-type thin film transistor T5 is turned off, the light-emitting brightness adjustment voltage Vr is sent to the fifth node e via the turned-on sixth N-type thin film transistor T6, and the potential Va of the first node a is the seventh P-type thin film transistor
  • the gate potential of T7 becomes:
  • the power supply high voltage VDDH is turned on to the third node c, that is, the source of the seventh P-type thin film transistor T7 via the turned-on third N-type thin film transistor T3:
  • Vc represents the voltage of the source of the third node c, that is, the seventh P-type thin film transistor T7.
  • I OLED K ⁇ (Vc - Va - V th ) 2
  • the I OLED represents a current flowing through the driving thin film transistor, that is, the seventh P-type thin film transistor T7 and the organic light emitting diode D1, and K is an intrinsic conductive factor of the driving thin film transistor, that is, the seventh P-type thin film transistor T7.
  • the organic light emitting diode D1 emits light, and the current I OLED flowing through the organic light emitting diode D1 is independent of the threshold voltage V th of the driving thin film transistor, that is, the seventh P type thin film transistor T7, and can eliminate the threshold voltage of the driving thin film transistor.
  • the influence of the current of the organic light emitting diode improves the display uniformity of the OLED panel.
  • the common ground voltage VSS is not higher than the light-emitting brightness adjustment voltage Vr, and the light-emitting brightness adjustment voltage Vr is lower than the sum of the power supply high voltage VDDH and the threshold voltage V th_OLED of the organic light-emitting diode D1 minus the data signal.
  • Data provided to the high potential voltage value V Data namely:
  • the luminous efficiency solves the problem of reduced luminous efficiency.
  • the present invention also provides an OLED pixel driving method, including Next steps:
  • Step 1 Provide an OLED pixel driving circuit.
  • the OLED pixel driving circuit adopts a 7T2C structure, and includes a first N-type thin film transistor T1, a second N-type thin film transistor T2, a third N-type thin film transistor T3, and a fourth N-type thin film transistor T4.
  • the gate of the first N-type thin film transistor T1 is connected to the third scan signal Scan3, the source is connected to the data signal Data, the drain is electrically connected to the first node a, and the gate of the second N-type thin film transistor T2 is connected to the second Scanning signal Scan2, the source is electrically connected to the first node a, the drain is electrically connected to the second node b; the gate of the third N-type thin film transistor T3 is connected to the light emission control signal EM, and the source is connected to the power supply high voltage VDDH, The drain is electrically connected to the third node c; the gate of the fourth N-type thin film transistor T4 is connected to the second scan signal Scan2, the source is electrically connected to the third node c, and the drain is electrically connected to the fifth node e;
  • the gate of the P-type thin film transistor T5 is connected to the light-emission control signal EM, the source is electrically connected to the fourth node d, the drain is connected to the common
  • the source is electrically connected to the fifth node e
  • the drain is time-divisionally connected to the power supply low voltage VDDL or the light-emitting brightness adjustment voltage Vr
  • the seventh P-type thin film transistor T7 is a driving thin film transistor directly driving the organic light-emitting diode D1, the gate thereof Very electrically connected to the first node a, the source is electrically connected to the third section Point c, the drain is electrically connected to the second node b; the anode of the organic light emitting diode D1 is electrically connected to the second node b, and the cathode is connected to the common ground voltage VSS; one end of the first capacitor C1 is electrically connected to the first node a, and the other One end is electrically connected to the fourth node d; one end of the second capacitor C2 is electrically connected to the fourth node d, and the other end is electrically connected to the fifth node e.
  • the transistor T6 and the seventh P-type thin film transistor T7 are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors; the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3
  • the illumination control signal EM and the data signal Data are all generated by an external timing controller.
  • Step 2 Please refer to Figure 3 and Figure 4 at the same time to enter the reset phase S1.
  • the first scan signal Scan1 provides a high potential
  • the second scan signal Scan2 provides a low potential
  • the third scan signal Scan3 provides a low potential
  • the illumination control signal EM provides a low potential
  • the data signal Data provides a low potential
  • the sixth N-type thin film transistor The drain of T6 is connected to the power supply low voltage VDDL.
  • the fifth P-type thin film transistor T5 and the sixth N-type thin film transistor T6 are turned on, and the other thin film transistors are turned off, and the power supply low voltage VDDL is charged to the second capacitor C2 via the turned-on sixth N-type thin film transistor T6, and the second capacitor C2 is charged.
  • the voltage difference between the fifth node e and the fourth node d after the completion of charging is the voltage difference V ed :
  • V ed VDDL-VSS
  • the power supply low voltage VDDL is higher than the sum of the threshold voltage of the seventh P-type thin film transistor T7, that is, the driving thin film transistor and the threshold voltage of the organic light emitting diode D1, that is,
  • V th represents a threshold voltage of the seventh P-type thin film transistor T7
  • V th — OLED is a threshold voltage of the organic light emitting diode D1.
  • Step 3 in conjunction with FIG. 3 and FIG. 5, enter the threshold voltage detection phase S2.
  • the first scan signal Scan1 transitions to a low potential
  • the second scan signal Scan2 transitions to a high potential
  • the third scan signal Scan3 remains at a low potential
  • the light emission control signal EM remains at a low potential
  • the data signal Data remains at a low potential.
  • the second N-type thin film transistor T2, the fourth N-type thin film transistor T4, the fifth P-type thin film transistor T5, and the seventh P-type thin film transistor T7 are all turned on, and the first N-type thin film transistor T1 and the third N-type thin film transistor T3 And the sixth N-type thin film transistor T6 is turned off, and the fourth N-type thin film transistor T4 that is turned on at the fifth node e is connected to the source of the third node c, that is, the seventh P-type thin film transistor T7, the first node a That is, the second N-type thin film transistor T2 whose gate of the seventh P-type thin film transistor T7 is turned on is in communication with the anode of the second node b, that is, the organic light emitting diode D1, and the second capacitor C2 is discharged to the seventh P-type thin film transistor T7.
  • V ed between the fifth node e and the fourth node d is:
  • V ed V th +V th_OLED
  • the storage voltage of the second capacitor C2 is V th +V th — OLED .
  • Step 4 in conjunction with FIG. 3 and FIG. 6, enters the data writing phase S3.
  • the first scan signal Scan1 is kept at a low potential
  • the second scan signal Scan2 is turned to a low potential
  • the third scan signal Scan3 is turned to a high potential
  • the light emission control signal EM is kept at a low potential
  • the data signal Data is turned to a high potential.
  • the first N-type thin film transistor T1 and the fifth P-type thin film transistor T5 are turned on, and the other thin film transistors are turned off, and the data signal Data is charged to the first capacitor C1 by the first N-type thin film transistor T1 that is turned on to the first capacitor C1.
  • the storage voltage and the potential of the first node a are the high-potential voltage values V Data supplied by the data signal Data .
  • the second capacitor C2 is in a floating state.
  • Step 5 in conjunction with FIG. 3 and FIG. 7, enters the illumination phase S4.
  • the first scan signal Scan1 transitions to a high potential
  • the second scan signal Scan2 remains at a low potential
  • the third scan signal Scan3 transitions to a low potential
  • the light emission control signal EM transitions to a high potential
  • the data signal Data transitions to a low potential
  • the drain of the N-type thin film transistor T6 is connected to the light-emission luminance adjustment voltage Vr.
  • the third N-type thin film transistor T3, the sixth N-type thin film transistor T6, and the seventh P-type thin film transistor T7 are both turned on, the first N-type thin film transistor T1, the second N-type thin film transistor T2, and the fourth N-type thin film transistor T4 And the fifth P-type thin film transistor T5 is turned off, the light-emitting brightness adjustment voltage Vr is sent to the fifth node e via the turned-on sixth N-type thin film transistor T6, and the potential Va of the first node a is the seventh P-type thin film transistor
  • the gate potential of T7 becomes:
  • the power supply high voltage VDDH is turned on to the third node c, that is, the source of the seventh P-type thin film transistor T7 via the turned-on third N-type thin film transistor T3:
  • Vc represents the voltage of the source of the third node c, that is, the seventh P-type thin film transistor T7.
  • I OLED K ⁇ (Vc - Va - V th ) 2
  • the I OLED represents a current flowing through the driving thin film transistor, that is, the seventh P-type thin film transistor T7 and the organic light emitting diode D1, and K is an intrinsic conductive factor of the driving thin film transistor, that is, the seventh P-type thin film transistor T7.
  • the organic light emitting diode D1 emits light, and flowing through the organic light emitting diode D1 and the driving current I OLED that is independent of the seventh thin film transistor P-type thin film transistor threshold voltage V th T7, it is possible to eliminate the threshold voltage of the driving thin film transistor flowing through The influence of the current of the organic light emitting diode improves the display uniformity of the OLED panel.
  • the common ground voltage VSS is not higher than emission brightness adjustment voltages Vr
  • the light emission data signals add and subtract brightness adjusting voltage Vr is lower than the threshold voltage V th_OLED high supply voltage VDDH
  • the organic light emitting diode D1 is The high voltage value V Data provided by Data is:
  • the OLED pixel driving circuit and the pixel driving method of the present invention adopt a pixel driving circuit of a 7T2C structure, and the first scanning signal, the second scanning signal, the third scanning signal, the light emission control signal, and the data signal are sequentially combined.
  • a threshold voltage detection phase, a data writing phase, and an illumination phase the influence of the threshold voltage of the driving thin film transistor on the current flowing through the organic light emitting diode can be eliminated, and the display uniformity of the OLED panel is improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种OLED像素驱动电路及像素驱动方法。OLED像素驱动电路采用7T2C结构，包括第一N型薄膜晶体管(T1)、第二N型薄膜晶体管(T2)、第三N型薄膜晶体管(T3)、第四N型薄膜晶体管(T4)、第五P型薄膜晶体管(T5)、第六N型薄膜晶体管(T6)、第七P型薄膜晶体管(T7)、第一电容(C1)、第二电容(C2)、及有机发光二极管(D1)，第一扫描信号(Scan1)、第二扫描信号(Scan2)、第三扫描信号(Scan3)、发光控制信号(EM)、及数据信号(Data)相组合先后对应于一复位阶段(S1)、一阈值电压检测阶段(S2)、一数据写入阶段(S3)、及一发光阶段(S4)，能够消除驱动薄膜晶体管的阈值电压对流经有机发光二极管(D1)的电流的影响，提高OLED面板的显示均匀性。

Description

OLED像素驱动电路及像素驱动方法 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED像素驱动电路及像素驱动方法。
背景技术
有机发光二极管(Organic Light Emitting Display，OLED)显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED是电流驱动器件，当有电流流经有机发光二极管时，有机发光二极管发光，且发光亮度由流经有机发光二极管自身的电流决定。大部分已有的集成电路(Integrated Circuit，IC)都只传输电压信号，故OLED的像素驱动电路需要完成将电压信号转变为电流信号的任务。传统的OLED像素驱动电路通常为2T1C，即两个薄膜晶体管加一个电容的结构，将电压变换为电流。
如图1所示，传统的用于OLED的2T1C像素驱动电路包括：第一薄膜晶体管T10、第二薄膜晶体管T20、及电容C10。所述第一薄膜晶体管T10为N型薄膜晶体管，用作开关薄膜晶体管；所述第二薄膜晶体管T20为P型薄膜晶体管，用作驱动薄膜晶体管；所述电容C10为存储电容。具体地，第一薄膜晶体管T10的栅极接入扫描信号Scan，源极接入数据信号Data，漏极与第二薄膜晶体管T20的栅极、及电容C10的一端电性连接；所述第二薄膜晶体管T20的源极接入电源电压VDD，漏极电性连接有机发光二极管D10的阳极；有机发光二极管D10的阴极接入公共接地电压VSS；电容C10的一端电性连接第二薄膜晶体管T20的栅极，另一端电性连接第二薄膜晶体管T20的源极。OLED显示时，扫描信号Scan控制第一薄膜晶体管T10导通，数据信号Data经过第一薄膜晶体管T10进入到第二薄膜晶体管T20的栅极及电容C10，然后第一薄膜晶体管T10截止，由于电容C10的存储作用，第二薄膜晶体管T20的栅极电压仍可继续保持数据信号电压，使得第二薄膜晶体管T20处于导通状态，驱动电流通过第二薄膜晶体管T20进入有机发光二极管D10，驱动有机发光二极管D10发光。
根据计算流经驱动薄膜晶体管及有机发光二极管电流的公式：
IOLED＝K×(Vgs-Vth)2
其中：IOLED代表流经驱动薄膜晶体管及有机发光二极管的电流，K为驱动薄膜晶体管的本征导电因子，Vgs代表驱动薄膜晶体管的栅极与源极之间的电压差，Vth代表驱动薄膜晶体管的阈值电压。可见，IOLED的大小与驱动薄膜晶体管的阈值电压Vth有关。
上述传统的OLED像素驱动电路的结构较简单，不具有补偿功能，所以存在很多缺陷，其中比较明显的是：由于薄膜晶体管制造过程中的非均一性，OLED显示面板内每个像素的驱动薄膜晶体管的阈值电压不一致；又因为长时间工作会使驱动薄膜晶体管的材料老化，导致驱动薄膜晶体管的阈值电压漂移，会造成OLED面板显示不均匀的现象。
发明内容
本发明的目的在于提供一种OLED像素驱动电路，能够消除驱动薄膜晶体管的阈值电压对流经有机发光二极管的电流的影响，提高OLED面板的显示均匀性。
本发明的另一目的在于提供一种OLED像素驱动方法，能够消除驱动薄膜晶体管的阈值电压对流经有机发光二极管的电流的影响，提高OLED面板的显示均匀性。
为实现上述目的，本发明首先提供一种OLED像素驱动电路，包括第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、第七P型薄膜晶体管、第一电容、第二电容、及有机发光二极管；所述第七P型薄膜晶体管用作有机发光二极管的驱动薄膜晶体管；
第一N型薄膜晶体管的栅极接入第三扫描信号，源极接入数据信号，漏极电性连接第一节点；
第二N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第一节点，漏极电性连接第二节点；
第三N型薄膜晶体管的栅极接入发光控制信号，源极接入电源高电压，漏极电性连接第三节点；
第四N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第三节点，漏极电性连接第五节点；
第五P型薄膜晶体管的栅极接入发光控制信号，源极电性连接第四节点，漏极接入公共接地电压；
第六N型薄膜晶体管的栅极接入第一扫描信号，源极电性连接第五节 点，漏极分时接入电源低电压或发光亮度调节电压；
第七P型薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极电性连接第二节点；
有机发光二极管的阳极电性连接第二节点，阴极接入公共接地电压；
第一电容的一端电性连接第一节点，另一端电性连接第四节点；
第二电容的一端电性连接第四节点，另一端电性连接第五节点。
所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号相组合先后对应于一复位阶段、一阈值电压检测阶段、一数据写入阶段、及一发光阶段；
在所述复位阶段，所述第一扫描信号为高电位，第二扫描信号为低电位，第三扫描信号为低电位，发光控制信号为低电位，数据信号为低电位；第六N型薄膜晶体管的漏极接入电源低电压；
在所述阈值电压检测阶段，所述第一扫描信号为低电位，第二扫描信号为高电位，第三扫描信号为低电位，发光控制信号为低电位，数据信号为低电位；
在所述数据写入阶段，所述第一扫描信号为低电位，第二扫描信号为低电位，第三扫描信号为高电位，发光控制信号为低电位，数据信号为高电位；
在所述发光阶段，所述第一扫描信号为高电位，第二扫描信号为低电位，第三扫描信号为低电位，发光控制信号为高电位，数据信号为低电位；第六N型薄膜晶体管的漏极接入发光亮度调节电压；
所述电源低电压高于第七P型薄膜晶体管的阈值电压与有机发光二极管的阈值电压的加和。
所述公共接地电压不高于发光亮度调节电压，所述发光亮度调节电压低于电源高电压与有机发光二极管的阈值电压的加和减去数据信号提供的高电位的电压值。
所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号均通过外部时序控制器产生。
所述第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、及第七P型薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
本发明还提供一种OLED像素驱动方法，包括如下步骤：
步骤1、提供一OLED像素驱动电路；
所述OLED像素驱动电路包括第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、第七P型薄膜晶体管、第一电容、第二电容、及有机发光二极管；所述第七P型薄膜晶体管用作有机发光二极管的驱动薄膜晶体管；
第一N型薄膜晶体管的栅极接入第三扫描信号，源极接入数据信号，漏极电性连接第一节点；
第二N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第一节点，漏极电性连接第二节点；
第三N型薄膜晶体管的栅极接入发光控制信号，源极接入电源高电压，漏极电性连接第三节点；
第四N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第三节点，漏极电性连接第五节点；
第五P型薄膜晶体管的栅极接入发光控制信号，源极电性连接第四节点，漏极接入公共接地电压；
第六N型薄膜晶体管的栅极接入第一扫描信号，源极电性连接第五节点，漏极分时接入电源低电压或发光亮度调节电压；
第七P型薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极电性连接第二节点；
有机发光二极管的阳极电性连接第二节点，阴极接入公共接地电压；
第一电容的一端电性连接第一节点，另一端电性连接第四节点；
第二电容的一端电性连接第四节点，另一端电性连接第五节点；
步骤2、进入复位阶段；
所述第一扫描信号提供高电位，第二扫描信号提供低电位，第三扫描信号提供低电位，发光控制信号提供低电位，数据信号提供低电位；第六N型薄膜晶体管的漏极接入电源低电压；
第五P型薄膜晶体管与第六N型薄膜晶体管打开，其它薄膜晶体管均关断，电源低电压向第二电容充电对第二电容进行初始化赋值，第二电容两端的电压差复位为VDDL-VSS，其中VDDL表示电源低电压，VSS表示公共接地电压；
步骤3、进入阈值电压检测阶段；
所述第一扫描信号转变为低电位，第二扫描信号转变为高电位，第三扫描信号保持低电位，发光控制信号保持低电位，数据信号保持低电位；
第二N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、 及第七P型薄膜晶体管均打开，第一N型薄膜晶体管、第三N型薄膜晶体管、及第六N型薄膜晶体管均关断，第二电容向第七P型薄膜晶体管放电至第二电容的储能电压为Vth+Vth_OLED，其中Vth为第七P型薄膜晶体管的阈值电压，Vth_OLED为有机发光二极管的阈值电压；
步骤4、进入数据写入阶段；
所述第一扫描信号保持低电位，第二扫描信号转变为低电位，第三扫描信号转变为高电位，发光控制信号保持低电位，数据信号转变为高电位；
第一N型薄膜晶体管与第五P型薄膜晶体管打开，其它薄膜晶体管均关断，数据信号向第一电容充电至第一电容的储能电压及第一节点的电位为VData，VData为数据信号提供的高电位的电压值；
步骤5、进入发光阶段；
所述第一扫描信号转变为高电位，第二扫描信号保持低电位，第三扫描信号转变为低电位，发光控制信号转变为高电位，数据信号转变为低电位；第六N型薄膜晶体管的漏极接入发光亮度调节电压；
第三N型薄膜晶体管、第六N型薄膜晶体管、及第七P型薄膜晶体管均打开，第一N型薄膜晶体管、第二N型薄膜晶体管、第四N型薄膜晶体管、及第五P型薄膜晶体管均关断，发光亮度调节电压送入第五节点，第一节点的电位变为：
Va＝Vr+VData-Vth-Vth_OLED
其中，Va表示第一节点的电位，Vr表示发光亮度调节电压；
所述有机发光二极管发光，且流经所述有机发光二极管的电流与第七P型薄膜晶体管的阈值电压无关。
所述电源低电压高于第七P型薄膜晶体管的阈值电压与有机发光二极管的阈值电压的加和。
所述公共接地电压不高于发光亮度调节电压，所述发光亮度调节电压低于电源高电压与有机发光二极管的阈值电压的加和减去数据信号提供的高电位的电压值。
所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号均通过外部时序控制器产生；
所述第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、及第七P型薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
本发明还提供一种OLED像素驱动电路，包括第一N型薄膜晶体管、 第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、第七P型薄膜晶体管、第一电容、第二电容、及有机发光二极管；所述第七P型薄膜晶体管用作有机发光二极管的驱动薄膜晶体管；
第一N型薄膜晶体管的栅极接入第三扫描信号，源极接入数据信号，漏极电性连接第一节点；
第二N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第一节点，漏极电性连接第二节点；
第三N型薄膜晶体管的栅极接入发光控制信号，源极接入电源高电压，漏极电性连接第三节点；
第四N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第三节点，漏极电性连接第五节点；
第五P型薄膜晶体管的栅极接入发光控制信号，源极电性连接第四节点，漏极接入公共接地电压；
第六N型薄膜晶体管的栅极接入第一扫描信号，源极电性连接第五节点，漏极分时接入电源低电压或发光亮度调节电压；
第七P型薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极电性连接第二节点；
有机发光二极管的阳极电性连接第二节点，阴极接入公共接地电压；
第一电容的一端电性连接第一节点，另一端电性连接第四节点；
第二电容的一端电性连接第四节点，另一端电性连接第五节点；
其中，所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号相组合先后对应于一复位阶段、一阈值电压检测阶段、一数据写入阶段、及一发光阶段；
在所述复位阶段，所述第一扫描信号为高电位，第二扫描信号为低电位，第三扫描信号为低电位，发光控制信号为低电位，数据信号为低电位；第六N型薄膜晶体管的漏极接入电源低电压；
在所述阈值电压检测阶段，所述第一扫描信号为低电位，第二扫描信号为高电位，第三扫描信号为低电位，发光控制信号为低电位，数据信号为低电位；
在所述数据写入阶段，所述第一扫描信号为低电位，第二扫描信号为低电位，第三扫描信号为高电位，发光控制信号为低电位，数据信号为高电位；
在所述发光阶段，所述第一扫描信号为高电位，第二扫描信号为低电 位，第三扫描信号为低电位，发光控制信号为高电位，数据信号为低电位；第六N型薄膜晶体管的漏极接入发光亮度调节电压；
其中，所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号均通过外部时序控制器产生。
本发明的有益效果：本发明提供的一种OLED像素驱动电路及像素驱动方法，采用7T2C结构的像素驱动电路，第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号相组合先后对应于一复位阶段、一阈值电压检测阶段、一数据写入阶段、及一发光阶段，能够消除驱动薄膜晶体管的阈值电压对流经有机发光二极管的电流的影响，提高OLED面板的显示均匀性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为传统的2T1C结构的OLED像素驱动电路的电路图；
图2为本发明的OLED像素驱动电路的电路图；
图3为本发明的OLED像素驱动电路的时序图；
图4为本发明的OLED像素驱动电路在复位阶段的示意图暨本发明的OLED像素驱动方法的步骤2的示意图；
图5为本发明的OLED像素驱动电路在阈值电压检测阶段的示意图暨本发明的OLED像素驱动方法的步骤3的示意图；
图6为本发明的OLED像素驱动电路在数据写入阶段的示意图暨本发明的OLED像素驱动方法的步骤4的示意图；
图7为本发明的OLED像素驱动电路在发光阶段的示意图暨本发明的OLED像素驱动方法的步骤5的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图2与图3，本发明首先提供一种OLED像素驱动电路，采用7T2C结构，包括第一N型薄膜晶体管T1、第二N型薄膜晶体管T2、第三N型薄膜晶体管T3、第四N型薄膜晶体管T4、第五P型薄膜晶体管 T5、第六N型薄膜晶体管T6、第七P型薄膜晶体管T7、第一电容C1、第二电容C2、及有机发光二极管D1。
第一N型薄膜晶体管T1的栅极接入第三扫描信号Scan3，源极接入数据信号Data，漏极电性连接第一节点a；第二N型薄膜晶体管T2的栅极接入第二扫描信号Scan2，源极电性连接第一节点a，漏极电性连接第二节点b；第三N型薄膜晶体管T3的栅极接入发光控制信号EM，源极接入电源高电压VDDH，漏极电性连接第三节点c；第四N型薄膜晶体管T4的栅极接入第二扫描信号Scan2，源极电性连接第三节点c，漏极电性连接第五节点e；第五P型薄膜晶体管T5的栅极接入发光控制信号EM，源极电性连接第四节点d，漏极接入公共接地电压VSS；第六N型薄膜晶体管T6的栅极接入第一扫描信号Scan1，源极电性连接第五节点e，漏极分时接入电源低电压VDDL或发光亮度调节电压Vr；第七P型薄膜晶体管T7为直接驱动有机发光二极管D1的驱动薄膜晶体管，其栅极电性连接第一节点a，源极电性连接第三节点c，漏极电性连接第二节点b；有机发光二极管D1的阳极电性连接第二节点b，阴极接入公共接地电压VSS；第一电容C1的一端电性连接第一节点a，另一端电性连接第四节点d；第二电容C2的一端电性连接第四节点d，另一端电性连接第五节点e。
具体地，所述第一N型薄膜晶体管T1、第二N型薄膜晶体管T2、第三N型薄膜晶体管T3、第四N型薄膜晶体管T4、第五P型薄膜晶体管T5、第六N型薄膜晶体管T6、及第七P型薄膜晶体管T7均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管；所述第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3、发光控制信号EM、及数据信号Data均通过外部时序控制器产生。
所述第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3、发光控制信号EM、及数据信号Data相组合先后对应于一复位阶段S1、一阈值电压检测阶段S2、一数据写入阶段S3、及一发光阶段S4。
进一步地，结合图3与图4，在所述复位阶段S1：
所述第一扫描信号Scan1为高电位，第二扫描信号Scan2为低电位，第三扫描信号Scan3为低电位，发光控制信号EM为低电位，数据信号Data为低电位；第六N型薄膜晶体管T6的漏极接入电源低电压VDDL。
第五P型薄膜晶体管T5与第六N型薄膜晶体管T6打开，其它薄膜晶体管均关断，电源低电压VDDL经导通的第六N型薄膜晶体管T6向第二电容C2充电，第二电容C2充电完成后两端的电压差即第五节点e与第四节点d之间的电压差Ved为：
Ved＝VDDL-VSS
完成对第二电容C2的复位与初始化赋值。
值得注意的是，所述电源低电压VDDL高于第七P型薄膜晶体管T7即驱动薄膜晶体管的阈值电压与有机发光二极管D1的阈值电压的加和，即：
VDDL>Vth+Vth_OLED
其中，Vth表示第七P型薄膜晶体管T7的阈值电压，Vth_OLED为有机发光二极管D1的阈值电压。
结合图3与图5，在所述阈值电压检测阶段S2：
在所述阈值电压检测阶段S2，所述第一扫描信号Scan1为低电位，第二扫描信号Scan2为高电位，第三扫描信号Scan3为低电位，发光控制信号EM为低电位，数据信号Data为低电位。
第二N型薄膜晶体管T2、第四N型薄膜晶体管T4、第五P型薄膜晶体管T5、及第七P型薄膜晶体管T7均打开，第一N型薄膜晶体管T1、第三N型薄膜晶体管T3、及第六N型薄膜晶体管T6均关断，第五节点e经导通的第四N型薄膜晶体管T4与第三节点c即第七P型薄膜晶体管T7的源极连通，第一节点a即第七P型薄膜晶体管T7的栅极经导通的第二N型薄膜晶体管T2与第二节点b即有机发光二极管D1的阳极连通，第二电容C2向第七P型薄膜晶体管T7放电，直至第五节点e与第四节点d之间的电压差Ved为：
Ved＝Vth+Vth_OLED
此时，第二电容C2的储能电压即为Vth+Vth_OLED。
结合图3与图6，在所述数据写入阶段S3：
所述第一扫描信号Scan1为低电位，第二扫描信号Scan2为低电位，第三扫描信号Scan3为高电位，发光控制信号EM为低电位，数据信号Data为高电位。
第一N型薄膜晶体管T1与第五P型薄膜晶体管T5打开，其它薄膜晶体管均关断，数据信号Data经导通的第一N型薄膜晶体管T1向第一电容C1充电至第一电容C1的储能电压及第一节点a的电位为数据信号Data提供的高电位的电压值VData。
在该数据写入阶段S3，所述第二电容C2处于浮空状态。
结合图3与图7，在所述发光阶段S4：
所述第一扫描信号Scan1为高电位，第二扫描信号Scan2为低电位，第三扫描信号Scan3为低电位，发光控制信号EM为高电位，数据信号Data 为低电位；第六N型薄膜晶体管T6的漏极接入发光亮度调节电压Vr。
第三N型薄膜晶体管T3、第六N型薄膜晶体管T6、及第七P型薄膜晶体管T7均打开，第一N型薄膜晶体管T1、第二N型薄膜晶体管T2、第四N型薄膜晶体管T4、及第五P型薄膜晶体管T5均关断，发光亮度调节电压Vr经导通的第六N型薄膜晶体管T6送入第五节点e，第一节点a的电位Va即第七P型薄膜晶体管T7的栅极电位变为：
Va＝Vr+(VData-(Vth+Vth_OLED))＝Vr+VData-Vth-Vth_OLED
电源高电压VDDH经导通的第三N型薄膜晶体管T3送入第三节点c即第七P型薄膜晶体管T7的源极：
Vc＝VDDH
其中Vc表示第三节点c即第七P型薄膜晶体管T7的源极的电压。
根据计算流经P型的驱动薄膜晶体管及有机发光二极管电流的公式：
IOLED＝K×(Vc-Va-Vth)2
＝K×(VDDH-(Vr+VData-Vth-Vth_OLED)-Vth)2
＝K×(VDDH–Vr-VData+Vth_OLED)2
其中，IOLED代表流经驱动薄膜晶体管即第七P型薄膜晶体管T7、及有机发光二极管D1的电流，K为驱动薄膜晶体管即第七P型薄膜晶体管T7的本征导电因子。
所述有机发光二极管D1发光，且流经所述有机发光二极管D1的电流IOLED与驱动薄膜晶体管即第七P型薄膜晶体管T7的阈值电压Vth无关，能够消除驱动薄膜晶体管的阈值电压对流经有机发光二极管的电流的影响，提高OLED面板的显示均匀性。
值得注意的是：所述公共接地电压VSS不高于发光亮度调节电压Vr，所述发光亮度调节电压Vr低于电源高电压VDDH与有机发光二极管D1的阈值电压Vth_OLED的加和减去数据信号Data提供的高电位的电压值VData，即：
VSS≤Vr＜VDDH-VData+Vth_OLED
另外，上述计算IOLED的表达式IOLED＝K×(VDDH–Vr-VData+Vth_OLED)2中包含有机发光二极管D1的阈值电压Vth_OLED这一项，由于有机发光二极管D1长时间使用会老化，使得有机发光二极管D1的阈值电压Vth_OLED上升引起发光效率下降，但从IOLED的表达式可知Vth_OLED上升使流经有机发光二极管D1的电流IOLED增长，增长的电流可以用来补偿下降的发光效率，解决发光效率下降的问题。
基于同一发明构思，本发明还提供一种OLED像素驱动方法，包括如 下步骤：
步骤1、提供一OLED像素驱动电路。
如图2所示，所述OLED像素驱动电路采用7T2C结构，包括第一N型薄膜晶体管T1、第二N型薄膜晶体管T2、第三N型薄膜晶体管T3、第四N型薄膜晶体管T4、第五P型薄膜晶体管T5、第六N型薄膜晶体管T6、第七P型薄膜晶体管T7、第一电容C1、第二电容C2、及有机发光二极管D1。
第一N型薄膜晶体管T1的栅极接入第三扫描信号Scan3，源极接入数据信号Data，漏极电性连接第一节点a；第二N型薄膜晶体管T2的栅极接入第二扫描信号Scan2，源极电性连接第一节点a，漏极电性连接第二节点b；第三N型薄膜晶体管T3的栅极接入发光控制信号EM，源极接入电源高电压VDDH，漏极电性连接第三节点c；第四N型薄膜晶体管T4的栅极接入第二扫描信号Scan2，源极电性连接第三节点c，漏极电性连接第五节点e；第五P型薄膜晶体管T5的栅极接入发光控制信号EM，源极电性连接第四节点d，漏极接入公共接地电压VSS；第六N型薄膜晶体管T6的栅极接入第一扫描信号Scan1，源极电性连接第五节点e，漏极分时接入电源低电压VDDL或发光亮度调节电压Vr；第七P型薄膜晶体管T7为直接驱动有机发光二极管D1的驱动薄膜晶体管，其栅极电性连接第一节点a，源极电性连接第三节点c，漏极电性连接第二节点b；有机发光二极管D1的阳极电性连接第二节点b，阴极接入公共接地电压VSS；第一电容C1的一端电性连接第一节点a，另一端电性连接第四节点d；第二电容C2的一端电性连接第四节点d，另一端电性连接第五节点e。
具体地，所述第一N型薄膜晶体管T1、第二N型薄膜晶体管T2、第三N型薄膜晶体管T3、第四N型薄膜晶体管T4、第五P型薄膜晶体管T5、第六N型薄膜晶体管T6、及第七P型薄膜晶体管T7均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管；所述第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3、发光控制信号EM、及数据信号Data均通过外部时序控制器产生。
步骤2、请同时参阅图3与图4，进入复位阶段S1。
所述第一扫描信号Scan1提供高电位，第二扫描信号Scan2提供低电位，第三扫描信号Scan3提供低电位，发光控制信号EM提供低电位，数据信号Data提供低电位；第六N型薄膜晶体管T6的漏极接入电源低电压VDDL。
第五P型薄膜晶体管T5与第六N型薄膜晶体管T6打开，其它薄膜晶体管均关断，电源低电压VDDL经导通的第六N型薄膜晶体管T6向第二 电容C2充电，第二电容C2充电完成后两端的电压差即第五节点e与第四节点d之间的电压差Ved为：
Ved＝VDDL-VSS
完成对第二电容C2的复位与初始化赋值。
值得注意的是，所述电源低电压VDDL高于第七P型薄膜晶体管T7即驱动薄膜晶体管的阈值电压与有机发光二极管D1的阈值电压的加和，即：
VDDL>Vth+Vth_OLED
其中，Vth表示第七P型薄膜晶体管T7的阈值电压，Vth_OLED为有机发光二极管D1的阈值电压。
步骤3、结合图3与图5，进入阈值电压检测阶段S2。
所述第一扫描信号Scan1转变为低电位，第二扫描信号Scan2转变为高电位，第三扫描信号Scan3保持低电位，发光控制信号EM保持低电位，数据信号Data保持低电位。
第二N型薄膜晶体管T2、第四N型薄膜晶体管T4、第五P型薄膜晶体管T5、及第七P型薄膜晶体管T7均打开，第一N型薄膜晶体管T1、第三N型薄膜晶体管T3、及第六N型薄膜晶体管T6均关断，第五节点e经导通的第四N型薄膜晶体管T4与第三节点c即第七P型薄膜晶体管T7的源极连通，第一节点a即第七P型薄膜晶体管T7的栅极经导通的第二N型薄膜晶体管T2与第二节点b即有机发光二极管D1的阳极连通，第二电容C2向第七P型薄膜晶体管T7放电，直至第五节点e与第四节点d之间的电压差Ved为：
Ved＝Vth+Vth_OLED
此时，第二电容C2的储能电压即为Vth+Vth_OLED。
步骤4、结合图3与图6，进入数据写入阶段S3。
所述第一扫描信号Scan1保持低电位，第二扫描信号Scan2转变为低电位，第三扫描信号Scan3转变为高电位，发光控制信号EM保持低电位，数据信号Data转变为高电位。
第一N型薄膜晶体管T1与第五P型薄膜晶体管T5打开，其它薄膜晶体管均关断，数据信号Data经导通的第一N型薄膜晶体管T1向第一电容C1充电至第一电容C1的储能电压及第一节点a的电位为数据信号Data提供的高电位的电压值VData。
在该数据写入阶段S3，所述第二电容C2处于浮空状态。
步骤5、结合图3与图7，进入发光阶段S4。
所述第一扫描信号Scan1转变为高电位，第二扫描信号Scan2保持低电位，第三扫描信号Scan3转变为低电位，发光控制信号EM转变为高电位，数据信号Data转变为低电位；第六N型薄膜晶体管T6的漏极接入发光亮度调节电压Vr。
第三N型薄膜晶体管T3、第六N型薄膜晶体管T6、及第七P型薄膜晶体管T7均打开，第一N型薄膜晶体管T1、第二N型薄膜晶体管T2、第四N型薄膜晶体管T4、及第五P型薄膜晶体管T5均关断，发光亮度调节电压Vr经导通的第六N型薄膜晶体管T6送入第五节点e，第一节点a的电位Va即第七P型薄膜晶体管T7的栅极电位变为：
Va＝Vr+(VData-(Vth+Vth_OLED))＝Vr+VData-Vth-Vth_OLED
电源高电压VDDH经导通的第三N型薄膜晶体管T3送入第三节点c即第七P型薄膜晶体管T7的源极：
Vc＝VDDH
其中Vc表示第三节点c即第七P型薄膜晶体管T7的源极的电压。
根据计算流经P型的驱动薄膜晶体管及有机发光二极管电流的公式：
IOLED＝K×(Vc-Va-Vth)2
＝K×(VDDH-(Vr+VData-Vth-Vth_OLED)-Vth)2
＝K×(VDDH–Vr-VData+Vth_OLED)2
其中，IOLED代表流经驱动薄膜晶体管即第七P型薄膜晶体管T7、及有机发光二极管D1的电流，K为驱动薄膜晶体管即第七P型薄膜晶体管T7的本征导电因子。
所述有机发光二极管D1发光，且流经所述有机发光二极管D1的电流IOLED与驱动薄膜晶体管即第七P型薄膜晶体管T7的阈值电压Vth无关，能够消除驱动薄膜晶体管的阈值电压对流经有机发光二极管的电流的影响，提高OLED面板的显示均匀性。
值得注意的是：所述公共接地电压VSS不高于发光亮度调节电压Vr，所述发光亮度调节电压Vr低于电源高电压VDDH与有机发光二极管D1的阈值电压Vth_OLED的加和减去数据信号Data提供的高电位的电压值VData，即：
VSS≤Vr＜VDDH-VData+Vth_OLED
另外，上述计算IOLED的表达式IOLED＝K×(VDDH–Vr-VData+Vth_OLED)2中包含有机发光二极管D1的阈值电压Vth_OLED这一项，由于有机发光二极管D1长时间使用会老化，使得有机发光二极管D1的阈值电压Vth_OLED上升引起发光效率下降，但从IOLED的表达式可知Vth_OLED上升使流经有机发 光二极管D1的电流IOLED增长，增长的电流可以用来补偿下降的发光效率，解决发光效率下降的问题。
综上所述，本发明的OLED像素驱动电路及像素驱动方法，采用7T2C结构的像素驱动电路，第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号相组合先后对应于一复位阶段、一阈值电压检测阶段、一数据写入阶段、及一发光阶段，能够消除驱动薄膜晶体管的阈值电压对流经有机发光二极管的电流的影响，提高OLED面板的显示均匀性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种OLED像素驱动电路，包括第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、第七P型薄膜晶体管、第一电容、第二电容、及有机发光二极管；所述第七P型薄膜晶体管用作有机发光二极管的驱动薄膜晶体管；
    第一N型薄膜晶体管的栅极接入第三扫描信号，源极接入数据信号，漏极电性连接第一节点；
    第二N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第一节点，漏极电性连接第二节点；
    第三N型薄膜晶体管的栅极接入发光控制信号，源极接入电源高电压，漏极电性连接第三节点；
    第四N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第三节点，漏极电性连接第五节点；
    第五P型薄膜晶体管的栅极接入发光控制信号，源极电性连接第四节点，漏极接入公共接地电压；
    第六N型薄膜晶体管的栅极接入第一扫描信号，源极电性连接第五节点，漏极分时接入电源低电压或发光亮度调节电压；
    第七P型薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极电性连接第二节点；
    有机发光二极管的阳极电性连接第二节点，阴极接入公共接地电压；
    第一电容的一端电性连接第一节点，另一端电性连接第四节点；
    第二电容的一端电性连接第四节点，另一端电性连接第五节点。
  2. 如权利要求1所述的OLED像素驱动电路，其中，所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号相组合先后对应于一复位阶段、一阈值电压检测阶段、一数据写入阶段、及一发光阶段；
    在所述复位阶段，所述第一扫描信号为高电位，第二扫描信号为低电位，第三扫描信号为低电位，发光控制信号为低电位，数据信号为低电位；第六N型薄膜晶体管的漏极接入电源低电压；
    在所述阈值电压检测阶段，所述第一扫描信号为低电位，第二扫描信号为高电位，第三扫描信号为低电位，发光控制信号为低电位，数据信号 为低电位；
    在所述数据写入阶段，所述第一扫描信号为低电位，第二扫描信号为低电位，第三扫描信号为高电位，发光控制信号为低电位，数据信号为高电位；
    在所述发光阶段，所述第一扫描信号为高电位，第二扫描信号为低电位，第三扫描信号为低电位，发光控制信号为高电位，数据信号为低电位；第六N型薄膜晶体管的漏极接入发光亮度调节电压。
  3. 如权利要求1所述的OLED像素驱动电路，其中，所述电源低电压高于第七P型薄膜晶体管的阈值电压与有机发光二极管的阈值电压的加和。
  4. 如权利要求3所述的OLED像素驱动电路，其中，所述公共接地电压不高于发光亮度调节电压，所述发光亮度调节电压低于电源高电压与有机发光二极管的阈值电压的加和减去数据信号提供的高电位的电压值。
  5. 如权利要求1所述的OLED像素驱动电路，其中，所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号均通过外部时序控制器产生。
  6. 如权利要求1所述的OLED像素驱动电路，其中，所述第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、及第七P型薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
  7. 一种OLED像素驱动方法，包括如下步骤：
    步骤1、提供一OLED像素驱动电路；
    所述OLED像素驱动电路包括第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、第七P型薄膜晶体管、第一电容、第二电容、及有机发光二极管；所述第七P型薄膜晶体管用作有机发光二极管的驱动薄膜晶体管；
    第一N型薄膜晶体管的栅极接入第三扫描信号，源极接入数据信号，漏极电性连接第一节点；
    第二N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第一节点，漏极电性连接第二节点；
    第三N型薄膜晶体管的栅极接入发光控制信号，源极接入电源高电压，漏极电性连接第三节点；
    第四N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第三节 点，漏极电性连接第五节点；
    第五P型薄膜晶体管的栅极接入发光控制信号，源极电性连接第四节点，漏极接入公共接地电压；
    第六N型薄膜晶体管的栅极接入第一扫描信号，源极电性连接第五节点，漏极分时接入电源低电压或发光亮度调节电压；
    第七P型薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极电性连接第二节点；
    有机发光二极管的阳极电性连接第二节点，阴极接入公共接地电压；
    第一电容的一端电性连接第一节点，另一端电性连接第四节点；
    第二电容的一端电性连接第四节点，另一端电性连接第五节点；
    步骤2、进入复位阶段；
    所述第一扫描信号提供高电位，第二扫描信号提供低电位，第三扫描信号提供低电位，发光控制信号提供低电位，数据信号提供低电位；第六N型薄膜晶体管的漏极接入电源低电压；
    第五P型薄膜晶体管与第六N型薄膜晶体管打开，其它薄膜晶体管均关断，电源低电压向第二电容充电对第二电容进行初始化赋值，第二电容两端的电压差复位为VDDL-VSS，其中VDDL表示电源低电压，VSS表示公共接地电压；
    步骤3、进入阈值电压检测阶段；
    所述第一扫描信号转变为低电位，第二扫描信号转变为高电位，第三扫描信号保持低电位，发光控制信号保持低电位，数据信号保持低电位；
    第二N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、及第七P型薄膜晶体管均打开，第一N型薄膜晶体管、第三N型薄膜晶体管、及第六N型薄膜晶体管均关断，第二电容向第七P型薄膜晶体管放电至第二电容的储能电压为Vth+Vth_OLED，其中Vth为第七P型薄膜晶体管的阈值电压，Vth_OLED为有机发光二极管的阈值电压；
    步骤4、进入数据写入阶段；
    所述第一扫描信号保持低电位，第二扫描信号转变为低电位，第三扫描信号转变为高电位，发光控制信号保持低电位，数据信号转变为高电位；
    第一N型薄膜晶体管与第五P型薄膜晶体管打开，其它薄膜晶体管均关断，数据信号向第一电容充电至第一电容的储能电压及第一节点的电位为VData，VData为数据信号提供的高电位的电压值；
    步骤5、进入发光阶段；
    所述第一扫描信号转变为高电位，第二扫描信号保持低电位，第三扫 描信号转变为低电位，发光控制信号转变为高电位，数据信号转变为低电位；第六N型薄膜晶体管的漏极接入发光亮度调节电压；
    第三N型薄膜晶体管、第六N型薄膜晶体管、及第七P型薄膜晶体管均打开，第一N型薄膜晶体管、第二N型薄膜晶体管、第四N型薄膜晶体管、及第五P型薄膜晶体管均关断，发光亮度调节电压送入第五节点，第一节点的电位变为：
    Va＝Vr+VData-Vth-Vth_OLED
    其中，Va表示第一节点的电位，Vr表示发光亮度调节电压；
    所述有机发光二极管发光，且流经所述有机发光二极管的电流与第七P型薄膜晶体管的阈值电压无关。
  8. 如权利要求7所述的OLED像素驱动方法，其中，所述电源低电压高于第七P型薄膜晶体管的阈值电压与有机发光二极管的阈值电压的加和。
  9. 如权利要求8所述的OLED像素驱动方法，其中，所述公共接地电压不高于发光亮度调节电压，所述发光亮度调节电压低于电源高电压与有机发光二极管的阈值电压的加和减去数据信号提供的高电位的电压值。
  10. 如权利要求7所述的OLED像素驱动方法，其中，所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号均通过外部时序控制器产生；
    所述第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、及第七P型薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
  11. 一种OLED像素驱动电路，包括第一N型薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、第七P型薄膜晶体管、第一电容、第二电容、及有机发光二极管；所述第七P型薄膜晶体管用作有机发光二极管的驱动薄膜晶体管；
    第一N型薄膜晶体管的栅极接入第三扫描信号，源极接入数据信号，漏极电性连接第一节点；
    第二N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第一节点，漏极电性连接第二节点；
    第三N型薄膜晶体管的栅极接入发光控制信号，源极接入电源高电压，漏极电性连接第三节点；
    第四N型薄膜晶体管的栅极接入第二扫描信号，源极电性连接第三节 点，漏极电性连接第五节点；
    第五P型薄膜晶体管的栅极接入发光控制信号，源极电性连接第四节点，漏极接入公共接地电压；
    第六N型薄膜晶体管的栅极接入第一扫描信号，源极电性连接第五节点，漏极分时接入电源低电压或发光亮度调节电压；
    第七P型薄膜晶体管的栅极电性连接第一节点，源极电性连接第三节点，漏极电性连接第二节点；
    有机发光二极管的阳极电性连接第二节点，阴极接入公共接地电压；
    第一电容的一端电性连接第一节点，另一端电性连接第四节点；
    第二电容的一端电性连接第四节点，另一端电性连接第五节点；
    其中，所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号相组合先后对应于一复位阶段、一阈值电压检测阶段、一数据写入阶段、及一发光阶段；
    在所述复位阶段，所述第一扫描信号为高电位，第二扫描信号为低电位，第三扫描信号为低电位，发光控制信号为低电位，数据信号为低电位；第六N型薄膜晶体管的漏极接入电源低电压；
    在所述阈值电压检测阶段，所述第一扫描信号为低电位，第二扫描信号为高电位，第三扫描信号为低电位，发光控制信号为低电位，数据信号为低电位；
    在所述数据写入阶段，所述第一扫描信号为低电位，第二扫描信号为低电位，第三扫描信号为高电位，发光控制信号为低电位，数据信号为高电位；
    在所述发光阶段，所述第一扫描信号为高电位，第二扫描信号为低电位，第三扫描信号为低电位，发光控制信号为高电位，数据信号为低电位；第六N型薄膜晶体管的漏极接入发光亮度调节电压；
    其中，所述第一扫描信号、第二扫描信号、第三扫描信号、发光控制信号、及数据信号均通过外部时序控制器产生。
  12. 如权利要求11所述的OLED像素驱动电路，其中，所述电源低电压高于第七P型薄膜晶体管的阈值电压与有机发光二极管的阈值电压的加和。
  13. 如权利要求12所述的OLED像素驱动电路，其中，所述公共接地电压不高于发光亮度调节电压，所述发光亮度调节电压低于电源高电压与有机发光二极管的阈值电压的加和减去数据信号提供的高电位的电压值。
  14. 如权利要求11所述的OLED像素驱动电路，其中，所述第一N型 薄膜晶体管、第二N型薄膜晶体管、第三N型薄膜晶体管、第四N型薄膜晶体管、第五P型薄膜晶体管、第六N型薄膜晶体管、及第七P型薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
PCT/CN2017/076862 2017-02-24 2017-03-16 Oled像素驱动电路及像素驱动方法 Ceased WO2018152896A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/519,840 US10319304B2 (en) 2017-02-24 2017-03-16 OLED pixel driving circuit and pixel driving method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710104789.9A CN106710522A (zh) 2017-02-24 2017-02-24 Oled像素驱动电路及像素驱动方法
CN201710104789.9 2017-02-24

Publications (1)

Publication Number Publication Date
WO2018152896A1 true WO2018152896A1 (zh) 2018-08-30

Family

ID=58917246

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/076862 Ceased WO2018152896A1 (zh) 2017-02-24 2017-03-16 Oled像素驱动电路及像素驱动方法

Country Status (3)

Country Link
US (1) US10319304B2 (zh)
CN (1) CN106710522A (zh)
WO (1) WO2018152896A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111081722A (zh) * 2019-12-31 2020-04-28 广州新视界光电科技有限公司 一种阵列基板行驱动电路以及显示装置

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393479B (zh) * 2017-08-29 2019-10-25 深圳市华星光电半导体显示技术有限公司 像素驱动电路及有机发光二极管显示器
CN107657921B (zh) * 2017-11-17 2019-09-24 深圳市华星光电半导体显示技术有限公司 Amoled像素驱动电路及其驱动方法
CN110322839B (zh) * 2018-03-28 2020-12-15 上海和辉光电股份有限公司 一种amoled时序控制电路及时序控制方法
KR102514242B1 (ko) * 2018-06-20 2023-03-28 삼성전자주식회사 픽셀 및 이를 포함하는 유기전계발광 표시장치
CN109493806B (zh) * 2019-01-28 2019-08-23 苹果公司 包括具有氧化物晶体管阈值电压补偿的显示器的电子设备
CN110335565B (zh) * 2019-05-09 2021-03-16 京东方科技集团股份有限公司 像素电路及其驱动方法、和显示装置
CN111210773A (zh) * 2020-01-20 2020-05-29 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
KR102832800B1 (ko) 2020-09-25 2025-07-11 삼성디스플레이 주식회사 표시 장치
CN112419983B (zh) * 2020-12-01 2022-08-02 重庆邮电大学 一种新型amoled像素驱动电路及驱动方法
CN112992055B (zh) * 2021-04-27 2021-07-27 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
TWI771075B (zh) * 2021-06-23 2022-07-11 友達光電股份有限公司 光感測畫素與具光感測功能的顯示裝置
TWI849991B (zh) * 2023-06-20 2024-07-21 大陸商北京歐錸德微電子技術有限公司 Amoled像素補償電路、oled顯示裝置及資訊處理裝置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101256732A (zh) * 2007-03-02 2008-09-03 三星Sdi株式会社 有机发光显示器
KR20080082118A (ko) * 2007-03-07 2008-09-11 엘지디스플레이 주식회사 유기 발광다이오드 표시장치와 그 구동방법
CN103208255A (zh) * 2013-04-15 2013-07-17 京东方科技集团股份有限公司 像素电路、像素电路驱动方法及显示装置
CN103544917A (zh) * 2013-07-08 2014-01-29 京东方科技集团股份有限公司 发光二极管像素单元电路、其驱动方法及显示面板
CN105304012A (zh) * 2014-07-31 2016-02-03 上海和辉光电有限公司 Oled像素补偿电路和oled像素驱动方法
KR20160031063A (ko) * 2014-09-11 2016-03-22 엘지디스플레이 주식회사 유기발광다이오드 표시장치와 그 구동방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700345B (zh) * 2013-12-27 2015-09-23 京东方科技集团股份有限公司 有机发光二极管像素电路及其驱动方法、显示面板
CN104091560B (zh) * 2014-06-23 2016-08-24 上海天马有机发光显示技术有限公司 有机发光二极管像素补偿电路及其显示面板、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101256732A (zh) * 2007-03-02 2008-09-03 三星Sdi株式会社 有机发光显示器
KR20080082118A (ko) * 2007-03-07 2008-09-11 엘지디스플레이 주식회사 유기 발광다이오드 표시장치와 그 구동방법
CN103208255A (zh) * 2013-04-15 2013-07-17 京东方科技集团股份有限公司 像素电路、像素电路驱动方法及显示装置
CN103544917A (zh) * 2013-07-08 2014-01-29 京东方科技集团股份有限公司 发光二极管像素单元电路、其驱动方法及显示面板
CN105304012A (zh) * 2014-07-31 2016-02-03 上海和辉光电有限公司 Oled像素补偿电路和oled像素驱动方法
KR20160031063A (ko) * 2014-09-11 2016-03-22 엘지디스플레이 주식회사 유기발광다이오드 표시장치와 그 구동방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111081722A (zh) * 2019-12-31 2020-04-28 广州新视界光电科技有限公司 一种阵列基板行驱动电路以及显示装置
CN111081722B (zh) * 2019-12-31 2022-08-16 广州新视界光电科技有限公司 一种阵列基板行驱动电路以及显示装置

Also Published As

Publication number Publication date
US10319304B2 (en) 2019-06-11
CN106710522A (zh) 2017-05-24
US20180301091A1 (en) 2018-10-18

Similar Documents

Publication Publication Date Title
WO2018152896A1 (zh) Oled像素驱动电路及像素驱动方法
CN113838421B (zh) 像素电路及其驱动方法、显示面板
US10147356B2 (en) OLED pixel driving circuit and OLED display device
CN114155813B (zh) 像素电路、像素电路的驱动方法和显示面板
WO2016119304A1 (zh) Amoled像素驱动电路及像素驱动方法
US20190019453A1 (en) Amoled pixel driving circuit and pixel driving method
WO2019037300A1 (zh) Amoled像素驱动电路
CN107767819A (zh) 像素驱动电路及方法、显示装置
JP2019532357A (ja) Ａｍｏｌｅｄ画素駆動回路および駆動方法
WO2018133144A1 (zh) Amoled像素驱动系统及amoled像素驱动方法
WO2016155053A1 (zh) Amoled像素驱动电路及像素驱动方法
CN106782340B (zh) 一种像素驱动电路及oled显示装置
CN109256092B (zh) 基于otft的实现阈值电压补偿的像素驱动电路及驱动方法
WO2020001027A1 (zh) 像素驱动电路及方法、显示装置
US20190019454A1 (en) Amoled pixel driving circuit and pixel driving method
US20190228708A1 (en) Pixel circuit, pixel driving method and display device
WO2018068392A1 (zh) Amoled像素驱动电路及驱动方法
CN108777131B (zh) Amoled像素驱动电路及驱动方法
US10056033B2 (en) AMOLED pixel driving circuit and pixel driving method
WO2019095451A1 (zh) Amoled像素驱动电路及其驱动方法
WO2016119305A1 (zh) Amoled像素驱动电路及像素驱动方法
US20190012963A1 (en) Amoled pixel driving circuit and pixel driving method
US20180247592A1 (en) Pixel Driving Circuit and Driving Method Thereof, Array Substrate, and Display Device
CN104537983A (zh) 像素电路及其驱动方法、显示装置
TWI685831B (zh) 畫素電路及其驅動方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15519840

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17897785

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17897785

Country of ref document: EP

Kind code of ref document: A1