WO2018152872A1 - 阵列基板、液晶显示面板和液晶显示装置 - Google Patents

阵列基板、液晶显示面板和液晶显示装置 Download PDF

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Publication number
WO2018152872A1
WO2018152872A1 PCT/CN2017/076084 CN2017076084W WO2018152872A1 WO 2018152872 A1 WO2018152872 A1 WO 2018152872A1 CN 2017076084 W CN2017076084 W CN 2017076084W WO 2018152872 A1 WO2018152872 A1 WO 2018152872A1
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Prior art keywords
array substrate
shape
sub
liquid crystal
crystal display
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PCT/CN2017/076084
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English (en)
French (fr)
Inventor
孙艳阳
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武汉华星光电技术有限公司
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Priority to US15/522,655 priority Critical patent/US10216056B2/en
Publication of WO2018152872A1 publication Critical patent/WO2018152872A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a liquid crystal display panel, and a liquid crystal display device.
  • the corresponding engineering inspection checks whether each process and the complete product are defective, and judges whether or not to perform Array Repair based on the inspection result.
  • the present invention provides an array substrate, a liquid crystal display panel, and a liquid crystal display device, which can repair the array substrate by removing polysilicon between the first portions of the adjacent two sub-data lines. It is beneficial to reduce the scrapping of the array substrate and reduce the loss of productivity.
  • an array substrate comprising a plurality of data lines, a plurality of scan lines, and a plurality of pixel units, each of the data lines being divided into a plurality of consecutive sub-data lines, each of the pixel units including one a pixel switch, and each sub-data line corresponds to one pixel switch and one scan line;
  • Each of the sub-data lines is divided into a first portion and a second portion that are connected end to end; the second portion is located in a region of the pixel switch corresponding to the sub-data line to which it belongs, and the shape of the second portion is a curve.
  • the shape of the second portion is an axisymmetric pattern.
  • the axis of symmetry of the shape of the second portion is a scan line corresponding to the sub data line to which the second portion belongs.
  • the shape of the second portion is a centrally symmetrical pattern.
  • the symmetric center of the shape of the second portion is the intersection of the sub data line to which the second portion belongs and the scan line corresponding to the sub data line to which the second portion belongs.
  • the shape of the second portion is curved, trapezoidal or triangular.
  • the shape of the second portion is S-shaped.
  • the shape of the first portion is a straight line.
  • a liquid crystal display panel comprising:
  • liquid crystal layer disposed between the array substrate and the color filter substrate.
  • liquid crystal display device comprising the liquid crystal display panel described above.
  • the present invention removes the two adjacent nodes by setting the data lines in the pixel switch area to a curved shape.
  • the polysilicon between the first portions of the data lines eliminates the short circuit problem between adjacent data lines, thereby realizing the repair of the array substrate, reducing the scrapping of the array substrate, and reducing the loss of productivity.
  • FIG. 1 is a partial structural diagram showing short circuit of adjacent data lines caused by residual polysilicon in the array plate of the prior art. intention
  • FIG. 2 is a partial structural schematic view of a first array substrate in the implementation of the present invention.
  • FIG. 3 is a partial structural schematic view showing short circuit of adjacent data lines caused by residual polysilicon in the first array substrate in the implementation of the present invention
  • FIG. 4 is a partial structural schematic view of the first array substrate after repair in the implementation of the present invention.
  • FIG. 5 is a partial structural schematic view of a second array substrate in the implementation of the present invention.
  • FIG. 6 is a partial structural schematic view of a third array substrate in the implementation of the present invention.
  • FIG. 7 is a partial structural schematic view of a fourth array substrate in the implementation of the present invention.
  • FIG. 8 is a partial schematic structural view of a fifth array substrate in the implementation of the present invention.
  • the present embodiment provides an array substrate.
  • 2 is a partial structural schematic view of a first array substrate in the implementation of the present invention. The specific structure of the array substrate 200 will be described in detail below with reference to FIG.
  • the array substrate 200 includes a plurality of data lines 210, a plurality of scan lines 220, a plurality of U-type polysilicon 230, a plurality of vias 240, and a plurality of pixel units (not shown).
  • the criss-crossed data lines 210 and the scan lines 220 divide the entire display area into a plurality of pixel units.
  • Each pixel unit corresponds to one U-shaped polysilicon 230 and one via 240.
  • the via 240 covers the upper end of the left side of the U-shaped polysilicon 230 for connecting the U-shaped polysilicon 230 and the pixel electrode of the pixel unit.
  • each data line 210 is preferably divided into a plurality of consecutive sub-data lines 211.
  • each of the data lines 210 is preferably equally divided into a plurality of segments (each segment is referred to as a segment of sub-data lines 211), and each segment of the sub-data lines 211 is connected end to end with each segment of the sub-data lines 211.
  • each pixel unit includes one pixel switch, and each segment of the sub data line 211 corresponds to one pixel switch, one scan line 220, and one U-type polysilicon 230.
  • each of the sub-data lines 211 is preferably divided into a first portion 211.1 and a second portion 211.2 which are connected end to end. Specifically, the bottom end of the first portion 211.1 is connected to the top end of the second portion 211.2.
  • the second portion 211.2 is located in the region of the pixel switch corresponding to the sub-data line 211 to which it belongs, and the shape of the second portion 211.2 is a curve such that the second portion 211.2 corresponds to the sub-data line 211 to which the sub-data line 211 belongs.
  • the projection of the right edge of the polysilicon 230 on the same plane e.g., the plane in which the sub data lines 211 are located, the plane in which the U-shaped polysilicon 230 is located, or a plane parallel to the plane) does not completely coincide.
  • the pixel switch in this embodiment refers to a thin film transistor in a pixel unit. Therefore, the pixel switch region in this embodiment refers to the region where the thin film transistor is located. Specifically, the region where the thin film transistor is located refers to a region including only one thin film transistor. Therefore, the pixel switch region in this embodiment refers to a region including only one thin film transistor.
  • the shape of the second portion 211.2 in the present embodiment is a curve, as long as the length of the second portion 211.2 is greater than the shortest distance between the first portions 211.1 of the adjacent two sub-data lines 211 (at this time, the second portion 211.2 The shape must be a curved figure).
  • the shape of the second portion 211.2 in this embodiment is a non-linear shape.
  • the second portion 211.2 is insulated from the via 240. Specifically, the second portion 211.2 has no intersection with the via 240, that is, the second portion 211.2 is not connected to the via 240. Moreover, the second portion 211.2 is in the same plane as the remaining U-shaped polysilicon 230 (polysilicon 230 corresponding to the sub-data line 211 to which the second portion 211.2 belongs) (for example, the plane where the sub-data line 211 is located, the plane of the U-shaped polysilicon 230, or The projections on the plane parallel to the above plane have no intersection. Specifically, the entire second portion 211.2 is completely uncovered over the remaining U-shaped polysilicon 230.
  • the present embodiment preferably sets the shape of the first portion 211.1 to a straight line.
  • the shape of the first portion 211.1 may also be a curve.
  • the shape 211.1 of the first portion may preferably be set to a curve. This is because when the flexible array substrate is bent under the action of the tensile force, the above design can effectively prevent the data line 210 from being broken. Therefore, in a specific implementation process, a person skilled in the art can set the shape of the first portion 211.1 according to actual needs.
  • the adjacent data lines 210 short-circuited by the polysilicon covered under the scan lines 220 will be described in detail below with reference to FIGS. 3 and 4. In the case of how to achieve repair of the array substrate.
  • the residual polysilicon 110 is a whole, so a portion of the scan line 221 in the scan line 220 is covered with a portion of the polysilicon (not shown in the perspective of FIG. 3). Since the prior art cannot remove the polysilicon covered under the scanning line 221 (the prior art can directly remove the remaining portion of the residual polysilicon 110 by using a laser), the adjacent data line 210 is short-circuited, as shown in FIG.
  • the present embodiment sets the shape of the second portion 211.2 as a curve, and then removes the polysilicon between the first portions 211.1 of the adjacent two sub-data lines 211 by using a laser (see the area in FIG. 4 for details).
  • A at this time, the pixel corresponding to the pixel electrode connected to the U-type polysilicon 430 is a dark spot), and at the same time, the polysilicon not covered by the scan line 220 (ie, the portion of the residual polysilicon 110 not covered by the scan line 220) is directly used by the laser. Disconnected or completely removed, thereby eliminating the short circuit problem between adjacent data lines 210, and realizing the repair of the array substrate.
  • the second portion 211.2 of the present embodiment has a curve that has no influence on the conductivity of the data line 210, and the normal display of other pixels (ie, pixels corresponding to the pixel electrode connected to the U-type polysilicon 430) is not displayed. The impact has no effect on the process.
  • the array substrate described in this embodiment can be used to remove the connection between the first portions 211.1 of the adjacent two sub-data lines 211.
  • the polysilicon eliminates the short circuit problem between adjacent data lines 210, thereby realizing the repair of the array substrate, reducing the scrapping of the array substrate, and reducing the loss of productivity.
  • This embodiment further optimizes the shape of the second portion 211.2 in the first embodiment.
  • the shape of the second portion 211.2 in the first embodiment is a curve. Based on this, the shape of the second portion 211.2 is further defined in this embodiment.
  • the shape of the second portion 211.2 is an axisymmetric pattern, and the axis of symmetry is the scan line 220 corresponding to the sub data line 211 to which the second portion 211.2 belongs.
  • the axis of symmetry of the shape of the second portion 211.2 is the central axis of the scan line 220 corresponding to the sub-data line 211 to which the second portion 211.2 belongs.
  • the shape of the second portion 211.2 may preferably be curved, trapezoidal or triangular. As shown in FIG. 5, the shape of the second portion 211.2 is curved. As shown in Fig. 6, the shape of the second portion 211.2 is trapezoidal. As shown in Fig. 7, the shape of the second portion 211.2 is a triangle. Of course, in other embodiments, the shape of the second portion 211.2 can also be set to other axisymmetric patterns.
  • the three preferred figures in this embodiment are only used to teach those skilled in the art how to implement the invention in detail, but it does not mean that only the shape of the second portion 211.2 can be set to the above three figures. In the specific implementation process, those skilled in the art can determine it according to actual needs.
  • the array substrate described in this embodiment can be used to remove the connection between the first portions 211.1 of the adjacent two sub-data lines 211.
  • the polysilicon eliminates the short circuit between the adjacent data lines 210, thereby realizing the repair of the array substrate and reducing the array substrate. Scrap, reduce the loss of production capacity.
  • This embodiment further optimizes the shape of the second portion 211.2 in the first embodiment.
  • the shape of the second portion 211.2 in the first embodiment is a curve. Based on this, the shape of the second portion 211.2 is further defined in this embodiment.
  • the shape of the second portion 211.2 is a central symmetrical pattern, and the center of symmetry is the intersection of the sub-data line 211 to which the second portion 211.2 belongs and the scan line 220 corresponding to the sub-data line 211 to which the second portion 211.2 belongs.
  • the center of symmetry of the shape of the second portion 211.2 is the intersection of the central axis of the sub-data line 211 to which the second portion 211.2 belongs and the central axis of the scan line 220 corresponding to the sub-data line 211 to which the second portion 211.2 belongs.
  • the shape of the second portion 211.2 is preferably S-shaped as shown in FIG.
  • the shape of the second portion 211.2 can also be set to other centrally symmetric patterns.
  • the S shape in this embodiment is only used to teach those skilled in the art how to implement the present invention, but it does not mean that the shape of the second portion can only be set to an S shape. In the specific implementation process, those skilled in the art can determine it according to actual needs.
  • the array substrate described in this embodiment can be used to remove the connection between the first portions 211.1 of the adjacent two sub-data lines 211.
  • the polysilicon eliminates the short circuit problem between adjacent data lines 210, thereby realizing the repair of the array substrate, reducing the scrapping of the array substrate, and reducing the loss of productivity.
  • the invention also provides a liquid crystal display panel.
  • the liquid crystal display panel of the present embodiment includes the array substrate according to any one of the first to third embodiments, further comprising a color filter substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the liquid crystal display panel according to the embodiment can be used to remove the first portion 211.1 connecting the adjacent two sub-data lines 211.
  • the inter-polysilicon eliminates the short-circuit problem between adjacent data lines 210, thereby realizing the repair of the array substrate, reducing the scrapping of the array substrate, and reducing the loss of productivity.
  • the present invention also provides a liquid crystal display device.
  • the liquid crystal display device of this embodiment includes the liquid crystal display panel of the fourth embodiment.
  • the liquid crystal display device is preferably a product having a display function such as a mobile phone, a tablet computer, a television, and a navigator.
  • the liquid crystal display device in the case where the adjacent data line 210 is short-circuited by the polysilicon covered under the scan line 220, the liquid crystal display device according to the embodiment can be used to remove the first portion 211.1 connecting the adjacent two sub-data lines 211.
  • the inter-polysilicon eliminates the short-circuit problem between adjacent data lines 210, thereby realizing the repair of the array substrate, reducing the scrapping of the array substrate, and reducing the loss of productivity.

Abstract

一种阵列基板（200）、液晶显示面板和液晶显示装置。阵列基板（200）包括多条数据线（210）和多个像素单元。其中，每条数据线（210）被划分为多段连续的子数据线（211），每个像素单元包括一个像素开关；每段子数据线（211）被划分为首尾相连的第一部分（211.1）和第二部分（211.2），第二部分（211.2）位于其所属的子数据线（211）对应的像素开关的区域内，且第二部分（211.2）的形状为曲线。

Description

阵列基板、液晶显示面板和液晶显示装置
本申请要求享有2017年2月22日提交的名称为“阵列基板、液晶显示面板和液晶显示装置”的中国专利申请CN201710095154.7的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板、液晶显示面板和液晶显示装置。
背景技术
在形成阵列基板的整个过程中，为了保证每一道工序的工艺结果都在管控范围之内，避免不合格产品在生产线上大面积出现，一般在完成一道工序后都要进行相应的工程检查。工程检查即检查各道工序及完整的产品是否发生不良现象，从而根据检查结果判断是否进行阵列修补(Array Repair)。
在阵列修补的过程中，经常会遇到如图1所示的多晶硅(Ploy Si)残留(即图1中的110)问题。在图1所示的这种情况下，由于被栅极(Gate)线覆盖的多晶硅无法使用激光器(Laser)移除，从而造成了相邻数据线间的短路(Data-Data Short)，使得整个阵列基板报废，造成产能的浪费。
综上，亟需一种新的阵列基板设计方案以解决上述问题。
发明内容
针对上述技术问题，本发明提出了一种阵列基板、液晶显示面板和液晶显示装置，通过移除连接相邻的两子数据线的第一部分之间的多晶硅来实现对阵列基板的修复，从而有利于减少阵列基板的报废，降低产能的损失。
根据本发明的一个方面，提供了一种阵列基板，包括多条数据线、多条扫描线和多个像素单元，每条数据线被划分为多段连续的子数据线，每个像素单元包括一个像素开关，且每段子数据线对应一个像素开关和一条扫描线；其中，
每段子数据线被划分为首尾相连的第一部分和第二部分；所述第二部分位于其所属的子数据线对应的像素开关的区域内，且所述第二部分的形状为曲线。
根据本发明的实施例，所述第二部分的形状为轴对称图形。
根据本发明的实施例，所述第二部分的形状的对称轴为所述第二部分所属的子数据线对应的扫描线。
根据本发明的实施例，所述第二部分的形状为中心对称图形。
根据本发明的实施例，所述第二部分的形状的对称中心为所述第二部分所属的子数据线与所述第二部分所属的子数据线对应的扫描线的交叉点。
根据本发明的实施例，所述第二部分的形状为弧形、梯形或三角形。
根据本发明的实施例，所述第二部分的形状为S形。
根据本发明的实施例，所述第一部分的形状为直线。
根据本发明的第二个方面，还提供了一种液晶显示面板，包括：
以上所述的阵列基板；
彩膜基板；以及
设置在所述阵列基板和所述彩膜基板之间的液晶层。
根据本发明的第三个方面，还提供了一种液晶显示装置，包括以上所述的液晶显示面板。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
在由扫描线(即栅极线)下方覆盖的多晶硅导致的相邻数据线短路的情况下，本发明通过将像素开关区域内的数据线设置为曲线形状，来移除连接相邻的两子数据线的第一部分之间的多晶硅，从而消除了相邻数据线之间的短路问题，进而实现对阵列基板的修复，减少阵列基板的报废，降低产能的损失。
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是现有技术中的阵列极板由残留的多晶硅引起的相邻数据线短路的局部结构示 意图；
图2是本发明的实施中第一种阵列基板的局部结构示意图；
图3是本发明的实施中第一种阵列基板由残留的多晶硅引起的相邻数据线短路的局部结构示意图；
图4是本发明的实施中第一种阵列基板修复后的局部结构示意图；
图5是本发明的实施中第二种阵列基板的局部结构示意图；
图6是本发明的实施中第三种阵列基板的局部结构示意图；
图7是本发明的实施中第四种阵列基板的局部结构示意图；
图8是本发明的实施中第五种阵列基板的局部结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一
为解决现有技术中由扫描线下方覆盖的多晶硅导致的相邻数据线短路且无法修复的难题，本实施例提供了一种阵列基板。图2是本发明的实施中第一种阵列基板的局部结构示意图。下面结合图2详细地说明该阵列基板200的具体结构。
该阵列基板200，包括多条数据线210、多条扫描线220、多个U型多晶硅230、多个过孔240和多个像素单元(图中未显示)。其中，纵横交错的数据线210和扫描线220将整个显示区域划分成多个像素单元。每个像素单元对应一个U型多晶硅230和一个过孔240。具体地，过孔240覆盖在U型多晶硅230左侧的上端，用于使U型多晶硅230和像素单元的像素电极相连通。
在本实施例中，每条数据线210优选地被划分为多段连续的子数据线211。具体地，每条数据线210优选地被等间距的划分为多段(每段称为一段子数据线211)，且每段子数据线211与每段子数据线211之间首尾相连。同时，每个像素单元包括一个像素开关，且每段子数据线211对应一个像素开关、一条扫描线220和一个U型多晶硅230。
在本实施例中，每段子数据线211优选地被划分为首尾相连的第一部分211.1和第二部分211.2。具体而言，第一部分211.1的底端与第二部分211.2的顶端相连。
进一步地，第二部分211.2位于其所属的子数据线211对应的像素开关的区域内，且第二部分211.2的形状为曲线，以使第二部分211.2与其所属的子数据线211对应的U型多晶硅230的右侧边缘在同一平面(例如子数据线211所在平面、U型多晶硅230所在平面、或者与上述平面平行的平面)上的投影不完全重合。在此需要说明以下三点：
首先，本实施例中的像素开关指的是像素单元中的薄膜晶体管。因此本实施例中的像素开关区域即指薄膜晶体管所在的区域。具体地，薄膜晶体管所在的区域是指仅包含一个薄膜晶体管的区域。因此本实施例中像素开关区域指的是仅包含一个薄膜晶体管的区域。
其次，本实施例中第二部分211.2的形状为曲线是指，只要第二部分211.2的长度大于相邻的两子数据线211的第一部分211.1之间的最短距离(此时第二部分211.2的形状一定为弯曲的图形)即可。换句话说，本实施例中第二部分211.2的形状为非直线形状。
最后，第二部分211.2与过孔240绝缘设置。具体而言，第二部分211.2与过孔240无交集，即第二部分211.2与过孔240无连接。并且，第二部分211.2与其余的U型多晶硅230(除去第二部分211.2所属的子数据线211对应的多晶硅230)在同一平面(例如子数据线211所在平面、U型多晶硅230所在平面、或者与上述平面平行的平面)上的投影无交集。具体地，整个第二部分211.2完全没有覆盖在其余的U型多晶硅230的上方。
本实施例为了简化制作工艺，优选地将第一部分211.1的形状设置为直线。需要指出的是，在其它的实施例中，第一部分211.1的形状也可以为曲线。例如，当阵列基板为柔性阵列基板时，可以优选地将第一部分的形状211.1设置为曲线。这是由于当柔性阵列基板在拉伸力的作用下发生弯折时，采用上述设计能够有效地避免数据线210发生断裂。因此，在具体实施过程中，本领域技术人员可以根据实际需求来设定第一部分211.1的形状。
进一步地，为了清楚地说明本实施例中阵列基板的设计原理以及其达到的有益效果，下面结合图3和图4详细地说明在由扫描线220下方覆盖的多晶硅导致的相邻数据线210短路的情况下，如何实现对阵列基板的修复。
在具体展开说明之前，首先对图3中残留的多晶硅110进行说明。残留的多晶硅110为一个整体，因此扫描线220中的一段扫描线221的下方覆盖着部分多晶硅(以图3视角未能示出)。由于现有技术无法去除该段扫描线221下方覆盖的多晶硅(现有技术可以直接利用激光器将残留的多晶硅110的其余部分去除)，从而导致相邻的数据线210短路，如图3所示。
针对于此，本实施例将第二部分211.2的形状设置为曲线，然后利用激光器将连接相邻的两子数据线211的第一部分211.1之间的多晶硅移除(具体请见图4中的区域A，此时与U型多晶硅430所连通的像素电极对应的像素做暗点)，同时直接利用激光器将未被扫描线220覆盖的多晶硅(即残留的多晶硅110中未被扫描线220覆盖的部分)断开或者完全移除，从而消除相邻数据线210之间的短路问题，实现对阵列基板的修复。应指出的是，本实施例将第二部分211.2设置为曲线对数据线210的导电性无影响，对其他像素(即除去与U型多晶硅430所连通的像素电极对应的像素)的正常显示无影响，同时对制程也无影响。
综上，在由扫描线220下方覆盖的多晶硅导致的相邻数据线210短路情况下，应用本实施例所述的阵列基板能够移除连接相邻的两子数据线211的第一部分211.1之间的多晶硅，消除相邻数据线210之间的短路问题，从而实现对阵列基板的修复，减少阵列基板的报废，降低产能的损失。
实施例二
本实施例对实施例一中的第二部分211.2的形状进行了进一步优化。
实施例一中第二部分211.2的形状为曲线。在此基础上，本实施例对第二部分211.2的形状进行了进一步地限定。优选地，第二部分211.2的形状为轴对称图形，并且对称轴为第二部分211.2所属的子数据线211对应的扫描线220。进一步地，第二部分211.2的形状的对称轴为第二部分211.2所属的子数据线211对应的扫描线220的中心轴。
在本实施例中，第二部分211.2的形状可以选优地为弧形、梯形或三角形。如图5所示，第二部分211.2的形状为弧形。如图6所示，第二部分211.2的形状为梯形。如图7所示，第二部分211.2的形状为三角形。当然，在其它的实施例中，还可以将第二部分211.2的形状设置为其他的轴对称图形。本实施例中的三种优选图形仅用于教导本领域技术人员如何具体实施本发明，但并不意味着仅能将第二部分211.2的形状设置为上述三种图形。在具体实施过程中，本领域技术人员可以结合实际需要来确定。
另外，需要说明的是，本实施例的具体实施方式与实施例一的具体实施方式类似，具体请参见实施例一部分的描述。为了减少冗余，在此不做赘述。
综上，在由扫描线220下方覆盖的多晶硅导致的相邻数据线210短路情况下，应用本实施例所述的阵列基板能够移除连接相邻的两子数据线211的第一部分211.1之间的多晶硅，消除相邻数据线210之间的短路问题，从而实现对阵列基板的修复，减少阵列基板的 报废，降低产能的损失。
实施例三
本实施例对实施例一中的第二部分211.2的形状进行了进一步优化。
实施例一中第二部分211.2的形状为曲线。在此基础上，本实施例对第二部分211.2的形状进行了进一步地限定。优选地，第二部分211.2的形状为中心对称图形，并且对称中心为第二部分211.2所属的子数据线211与第二部分211.2所属的子数据线211对应的扫描线220的交叉点。进一步地，第二部分211.2的形状的对称中心为第二部分211.2所属的子数据线211的中心轴与第二部分211.2所属的子数据线211对应的扫描线220的中心轴的交叉点。
在本实施例中，第二部分211.2的形状优选地为S形，如图8所示。当然，在其它的实施例中，还可以将第二部分211.2的形状设置为其他的中心对称图形。本实施例中的S形仅用于教导本领域技术人员如何具体实施本发明，但并不意味着仅能将第二部分的形状设置为S形。在具体实施过程中，本领域技术人员可以结合实际需要来确定。
另外，需要说明的是，本实施例的具体实施方式与实施例一的具体实施方式类似，具体请参见实施例一部分的描述。为了减少冗余，在此不做赘述。
综上，在由扫描线220下方覆盖的多晶硅导致的相邻数据线210短路情况下，应用本实施例所述的阵列基板能够移除连接相邻的两子数据线211的第一部分211.1之间的多晶硅，消除相邻数据线210之间的短路问题，从而实现对阵列基板的修复，减少阵列基板的报废，降低产能的损失。
实施例四
本发明还提供了一种液晶显示面板。本实施例的液晶显示面板包括实施例一至实施例三中任一实施例所述的阵列基板，还包括彩膜基板以及设置在所述阵列基板和彩膜基板之间的液晶层。
综上，在由扫描线220下方覆盖的多晶硅导致的相邻数据线210短路情况下，应用本实施例所述的液晶显示面板能够移除连接相邻的两子数据线211的第一部分211.1之间的多晶硅，消除相邻数据线210之间的短路问题，从而实现对阵列基板的修复，减少阵列基板的报废，降低产能的损失。
实施例五
本发明还提供了一种液晶显示装置。本实施例的液晶显示装置包括实施例四所述的液晶显示面板。该液晶显示装置优选地为手机、平板电脑、电视机以及导航仪等具有显示功能的产品。
综上，在由扫描线220下方覆盖的多晶硅导致的相邻数据线210短路情况下，应用本实施例所述的液晶显示装置能够移除连接相邻的两子数据线211的第一部分211.1之间的多晶硅，消除相邻数据线210之间的短路问题，从而实现对阵列基板的修复，减少阵列基板的报废，降低产能的损失。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括多条数据线、多条扫描线和多个像素单元，每条数据线被划分为多段连续的子数据线，每个像素单元包括一个像素开关，且每段子数据线对应一个像素开关和一条扫描线；其中，
    每段子数据线被划分为首尾相连的第一部分和第二部分；所述第二部分位于其所属的子数据线对应的像素开关的区域内，且所述第二部分的形状为曲线。
  2. 根据权利要求1所述的阵列基板，其中，所述第二部分的形状为轴对称图形。
  3. 根据权利要求2所述的阵列基板，其中，所述第二部分的形状的对称轴为所述第二部分所属的子数据线对应的扫描线。
  4. 根据权利要求1所述的阵列基板，其中，所述第二部分的形状为中心对称图形。
  5. 根据权利要求4所述的阵列基板，其中，所述第二部分的形状的对称中心为所述第二部分所属的子数据线与所述第二部分所属的子数据线对应的扫描线的交叉点。
  6. 根据权利要求1所述的阵列基板，其中，所述第二部分的形状为弧形、梯形或三角形。
  7. 根据权利要求2所述的阵列基板，其中，所述第二部分的形状为弧形、梯形或三角形。
  8. 根据权利要求3所述的阵列基板，其中，所述第二部分的形状为弧形、梯形或三角形。
  9. 根据权利要求4所述的阵列基板，其中，所述第二部分的形状为S形。
  10. 根据权利要求5所述的阵列基板，其中，所述第二部分的形状为S形。
  11. 根据权利要求1所述的阵列基板，其中，所述第一部分的形状为直线。
  12. 一种液晶显示面板，包括阵列基板、彩膜基板以及设置在所述阵列基板和所述彩膜基板之间的液晶层；其中，
    所述阵列基板包括多条数据线、多条扫描线和多个像素单元，每条数据线被划分为多段连续的子数据线，每个像素单元包括一个像素开关，且每段子数据线对应一个像素开关和一条扫描线；其中，
    每段子数据线被划分为首尾相连的第一部分和第二部分；所述第二部分位于其所属的子数据线对应的像素开关的区域内，且所述第二部分的形状为曲线。
  13. 根据权利要求12所述的液晶显示面板，其中，所述第二部分的形状为轴对称图形。
  14. 根据权利要求13所述的液晶显示面板，其中，所述第二部分的形状的对称轴为所述第二部分所属的子数据线对应的扫描线。
  15. 根据权利要求12所述的液晶显示面板，其中，所述第二部分的形状为中心对称图形。
  16. 根据权利要求15所述的液晶显示面板，其中，所述第二部分的形状的对称中心为所述第二部分所属的子数据线与所述第二部分所属的子数据线对应的扫描线的交叉点。
  17. 一种液晶显示装置，包括液晶显示面板，所述液晶显示面板包括阵列基板、彩膜基板以及设置在所述阵列基板和所述彩膜基板之间的液晶层；其中，
    所述阵列基板包括多条数据线、多条扫描线和多个像素单元，每条数据线被划分为多段连续的子数据线，每个像素单元包括一个像素开关，且每段子数据线对应一个像素开关和一条扫描线；其中，
    每段子数据线被划分为首尾相连的第一部分和第二部分；所述第二部分位于其所属的子数据线对应的像素开关的区域内，且所述第二部分的形状为曲线。
  18. 根据权利要求17所述的液晶显示装置，其中，所述第二部分的形状为轴对称图形。
  19. 根据权利要求18所述的液晶显示装置，其中，所述第二部分的形状的对称轴为所述第二部分所属的子数据线对应的扫描线。
  20. 根据权利要求17所述的液晶显示装置，其中，所述第二部分的形状为中心对称图形。
PCT/CN2017/076084 2017-02-22 2017-03-09 阵列基板、液晶显示面板和液晶显示装置 WO2018152872A1 (zh)

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