WO2018152697A1 - 基于过渡金属氧化物的选择器及其制备方法 - Google Patents

基于过渡金属氧化物的选择器及其制备方法 Download PDF

Info

Publication number
WO2018152697A1
WO2018152697A1 PCT/CN2017/074401 CN2017074401W WO2018152697A1 WO 2018152697 A1 WO2018152697 A1 WO 2018152697A1 CN 2017074401 W CN2017074401 W CN 2017074401W WO 2018152697 A1 WO2018152697 A1 WO 2018152697A1
Authority
WO
WIPO (PCT)
Prior art keywords
transition metal
metal oxide
selector
tungsten plug
based selector
Prior art date
Application number
PCT/CN2017/074401
Other languages
English (en)
French (fr)
Inventor
吕杭炳
罗庆
许晓欣
龙世兵
刘琦
刘明
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to PCT/CN2017/074401 priority Critical patent/WO2018152697A1/zh
Priority to US16/486,614 priority patent/US20200058704A1/en
Publication of WO2018152697A1 publication Critical patent/WO2018152697A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/22—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the metal-insulator-metal type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a preparation method of a transition metal oxide based selector and a selector prepared by the method.
  • Semiconductor memories can be classified into two categories based on whether they can retain stored information when they are powered down: volatile memory and non-volatile memory. With the popularity of portable electronic devices, the share of non-volatile memory in the memory market is also growing.
  • the current FLASH technology is the mainstream of the non-volatile memory market.
  • the FLASH technology is encountering a series of bottleneck problems, such as large operating voltage, size cannot be reduced, and the holding time is not long enough.
  • the resistive memory has become the research focus of the new non-volatile memory due to its low operating voltage, non-destructive reading, fast operation speed, simple structure and easy integration.
  • the resistive memory array has a relatively serious crosstalk problem. Take a 2 ⁇ 2 cross-storage array as an example ( Figure 3).
  • the memory device with the coordinates (1, 1) is in the high-impedance state (HRS), and the remaining three adjacent devices (1, 2), (2, 2), and (2, 1) are in the low-impedance state (LRS). .
  • HRS high-impedance state
  • LRS low-impedance state
  • HRS high-impedance state
  • the method for solving the crosstalk problem is a resistive memory (1T1R structure) with an integrated MOS transistor, a resistive memory of the external diode (1D1R structure), and a resistive memory (1S1R structure) connected in series with one selector.
  • the area of the memory cell mainly depends on the area of the transistor, and the advantage of the simple device area of the RRAM structure cannot be exerted.
  • the 1D1R is weak in terms of limiting the crosstalk current with respect to the 1S1R.
  • the 1S1R structure is currently an ideal structure for solving crosstalk problems.
  • the technical problem to be solved by the present invention is to overcome the crosstalk problem in the RRAM array.
  • the present invention provides a method for preparing a transition metal oxide based selector, comprising the following steps:
  • the transition metal is at least one of Ta, Ti, Zr, Hf, and Nb.
  • the transition metal layer has a thickness of from 2 nm to 8 nm.
  • the step S3 converts the transition metal layer into a transition metal oxide layer by an annealing treatment.
  • the annealing treatment is carried out in a plasma oxygen environment.
  • the annealing treatment is carried out under conditions of a temperature of from 350 ° C to 400 ° C and a time of from 60 seconds to 400 seconds.
  • the transition metal oxide formed has a trapezoidal energy band.
  • the upper electrode is at least one of Pt, W, Ru, Al, TiN, TaN, IrO 2 , ITO, and IZO.
  • the present invention also proposes a transition metal oxide based selector prepared by the above-described method for preparing a transition metal oxide based selector.
  • the resistive memory has 1S1R structure.
  • the invention also proposes a resistive memory comprising the transition metal oxide based selector.
  • the present invention has the following beneficial effects:
  • the invention has simple preparation process and low process cost, and is favorable for integration of the memory.
  • the present invention can provide a bidirectional rectifying device for the 1S1R structure bipolar resistive memory, suppressing read crosstalk.
  • the present invention can provide a higher current density and a higher selection ratio for the 1S1R structure bipolar resistive memory, which is advantageous for larger integration of the RRAM.
  • the present invention can provide a selector compatible with a standard CMOS process for a 1S1R structure bipolar resistive memory, which is convenient for industrial production.
  • the invention can provide an ultra-high uniformity selector for the 1S1R structure bipolar resistive memory, which reduces the difficulty of circuit design and facilitates industrial production and application.
  • FIG. 1 is a schematic view showing a preparation method of a selector provided by the present invention
  • 2 to 5 are schematic views showing a process of preparing a selector
  • Figure 6 is a schematic diagram of the principle of the selector provided by the present invention.
  • FIG. 8 is a graph showing current and voltage curves of a selector and a resistive device provided in series according to the present invention.
  • the preparation method of the transition metal oxide based selector proposed by the invention comprises the following steps:
  • a tungsten plug can be formed by a quasi-CMOS process, including a process of forming a tungsten plug hole, depositing a diffusion barrier layer, filling a hole by a PECVD process, and chemical on-board polishing.
  • a transition metal layer can be grown by magnetron sputtering on the tungsten plug, wherein the transition metal can be Ta, Ti, Zr, Hf, Nb, etc., and has a thickness of 2 nm to 8 nm. Since the lower electrode of the present invention is a tungsten plug, it is not necessary to specially prepare a lower electrode.
  • This step can form a transition metal oxide by annealing the device.
  • the annealing environment may be plasma oxygen with an annealing temperature of 350 to 400 degrees (CMOS process compatible).
  • the annealing time depends on the thickness of the transition metal (the thicker the longer the time), and the annealing time is 300 s in the case where the oxidation temperature is 400 degrees in the case of 8 nm.
  • the upper electrode material may be a material such as W, Ru, Al, Ti, or a conductive metal compound such as TiN, TaN, IrO 2 , ITO, or IZO.
  • the upper electrode material can be prepared by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and sputtering. Its thickness is generally from 30 nm to 200 nm.
  • This step may further include the step of patterning the upper electrode and the transition metal oxide.
  • the drawings are a schematic representation of an idealized embodiment of the present invention, and the illustrated embodiments of the present invention should not be considered limited to the specific shapes of the regions shown in the drawings, but rather include the resulting shapes, such as deviation.
  • the curve obtained by dry etching generally has the characteristics of being curved or rounded, but in the illustrations of the embodiments of the present invention, both are represented by rectangles, and the representations in the figures are schematic, but this should not be considered as limiting the invention. range.
  • FIG. 1 is a schematic flow chart showing a preparation method of a transition metal oxide-based selector provided by the present invention. Meanwhile, FIG. 2 to FIG. 5 respectively illustrate the preparation of the resistive memory. The schematic structure of the method at each step.
  • a method of manufacturing a resistive memory will be described in detail with reference to FIGS. 1 to 5.
  • the preparation method of the embodiment of the present invention mainly includes:
  • This step produces a tungsten plug using a standard CMOS process. Specifically, the following sub-steps are included:
  • a diffusion barrier layer in the tungsten plug hole in this embodiment, a Ti/TiN layer or a Ti layer and a TiN layer, and the thickness ranges from 3 nm to 50 nm.
  • the thickness of the tungsten is 50-5000 nm
  • the surface of the tungsten plug is chemically polished.
  • Part a of Figure 2 shows a cross-sectional view through a conventional CMOS process until the end of the tungsten plug. Subsequent process steps are performed on the upper surface of the tungsten plug 21 shown in part b of Fig. 2.
  • the transition metal layer 22 can be grown on the tungsten plug 21 by magnetron sputtering, wherein the transition metal can be Ta, Ti, Zr, Hf, Nb, etc., and has a thickness of 2 nm to 8 nm. Since the lower electrode of the present invention is a tungsten plug, it is not necessary to specially prepare a lower electrode.
  • the transition metal layer is converted into a transition metal oxide layer by annealing the device in a plasma oxygen atmosphere.
  • the annealing conditions are: (1) the temperature is between 350 degrees Celsius and 400 degrees Celsius. (2) The time is from 60 seconds to 400 seconds (depending on the oxidation temperature and the thickness of the transition metal). (3) Atmosphere: plasma oxygen.
  • the transition metal oxide is rapidly oxidized in the environment of plasma oxygen and oxidized rapidly. The oxidation process is completely and completely oxidized by the outer and inner surfaces. The transition metal oxide is oxidized at a lower distance from the surface. Things appear.
  • the trapezoidal energy band is formed due to the difference in the forbidden band width of the transition metal oxides of different components (the more the oxidation band is wider, the wider the band gap).
  • Figure 6 shows the energy band diagram of the transition metal oxide layer.
  • the energy band of the transition metal oxide layer is trapezoidal, and such an energy band structure results in a non-linear current-voltage relationship.
  • the voltage is relatively small, mainly based on the tunneling current.
  • the tunneling current is small.
  • the forward current is relatively large, the current is suddenly increased by the excitation of the hot electrons, and a high nonlinearity is formed.
  • FIG. 6b when the reverse voltage is applied, since the barrier is relatively high, the hot electron excitation current is relatively small, so the reverse current density is smaller than the forward current density.
  • the upper electrode 25 is made of at least one of Pt, W, Ru, Al or a conductive metal compound TiN, TaN, IrO 2 , ITO, or IZO.
  • the step of patterning the upper electrode it can be completed by conventional semiconductor photolithography and etching.
  • Figure 7 illustrates a graph of current and voltage curves for one embodiment of a transition metal oxide based selector of the present invention.
  • the voltage sweep of the device was performed 1000 times, and the uniformity of the device was very good.
  • Figure 8 is a graph showing the current-voltage curve of one embodiment of the resistive switching device provided by the present invention, demonstrating that the device can operate normally in an array of 1S1R structures, as an example showing the basic properties of the type selector.
  • the present invention utilizes PECVD to oxidize a transition metal to form a transition metal oxide, followed by growth of the upper electrode.
  • the transition metal oxide based selector of the present invention can provide a high current density and has good uniformity, and the formation of the 1S1R structure can effectively suppress the crosstalk phenomenon in the resistive memory array without increasing the memory cell area. Effectively increase storage density and improve device integration.
  • the selector for the resistive memory of the invention has the advantages of simple structure, easy integration, low cost, good uniformity, compatibility with the CMOS process, and the like, and is beneficial to the wide application of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种基于过渡金属氧化物的选择器的制备方法及该方法制备的选择器。所述制备方法包括：S1、在晶体管上形成钨栓塞；S2、以钨栓塞作为下电极，并在钨栓塞上制备过渡金属层；S3、氧化过渡金属层，使之转化为过渡金属氧化物层；S4、在过渡金属氧化物上沉积上电极，图形化上电极和过渡金属氧化物。本发明的选择器能够提供较高的电流密度，有很好的均一性，形成1S1R结构能有效抑制阻变存储器阵列中的串扰现象，在不增加存储单元面积的情况下有效提高存储密度，提高器件集成度。此外本发明用于阻变存储器的选择器具有结构简单、易集成、成本低、均一性好、CMOS工艺兼容等优点。

Description

基于过渡金属氧化物的选择器及其制备方法 技术领域
本发明属于集成电路制造技术领域，具体涉及一种基于过渡金属氧化物的选择器的制备方法及该方法制备的选择器。
背景技术
半导体存储器，根据其掉电是否能够保持存储信息，可以分为两类：挥发性存储器和非挥发性存储器。随着便携式电子设备的普及，非挥发存储器在存储器市场中的份额也越来越大。当前FLASH技术是非挥发存储器市场的主流，然而FLASH技术正遇到一系列的瓶颈问题，比如操作电压大，尺寸无法缩小，保持时间不够长等。阻变存储器由于操作电压低、非破坏性读取、操作速度快和结构简单、易于集成等优点成为新型非挥发性存储器的研究重点。而阻变存储器阵列存在比较严重的串扰(Crosstalk)问题。以一个2×2的交叉存储阵列为例(图3)。假设坐标为(1，1)的存储器件处于高阻态(HRS)，其余三个相邻器件(1，2)、(2，2)和(2，1)都处于低阻态(LRS)。如果在(1，1)器件所在字线(Word Line)上加电压读时，电压会沿着低阻通道(2，1)→(2，2)→(1，2)进行传导，造成误读。读到的(1，1)器件的为低阻态(LRS)，而实际为高阻态(HRS)。这样的串扰问题会随着阵列的扩大而更加严重，严重影响了RRAM存储器的可靠性，阻碍其迈向应用。
解决串扰问题的方法有集成MOS管的阻变存储器(1T1R结构)、外界二极管的阻变存储器(1D1R结构)和串联一个选择器的阻变存储器(1S1R结构)。1T1R结构中，存储单元的面积主要取决于晶体管的面积，无法发挥RRAM结构简单器件面积小的优点，1D1R相对1S1R来说在限制串扰电流方面能力偏弱。1S1R结构是目前比较理想的解决串扰问题的结构。
但目前报道的选择器多不能CMOS兼容，且少有兼有高电流密度、 高选择比、高耐久性等优点的。而且均一性不好使现存大部分选择器所存在的问题。对于RRAM阵列解决串扰问题并且走上应用而言，一个高性能的均一性可靠性良好并且可以和标准CMOS工艺兼容的选择器是非常重要的。
发明内容
本发明要解决的技术问题是克服RRAM阵列中的串扰问题。
为解决上述技术问题，本发明提出一种基于过渡金属氧化物的选择器的制备方法，包括如下步骤：
S1、在晶体管上形成钨栓塞；
S2、以钨栓塞作为下电极，并在钨栓塞上制备过渡金属层；
S3、氧化过渡金属层，使之转化为过渡金属氧化物层；
S4、在过渡金属氧化物上沉积上电极，图形化上电极和过渡金属氧化物。
根据本发明的优选实施方式，所述过渡金属为Ta、Ti、Zr、Hf、Nb中的至少一种。
根据本发明的优选实施方式，所述过渡金属层的厚度为2nm至8nm。
根据本发明的优选实施方式，所述步骤S3通过退火处理使过渡金属层转化为过渡金属氧化物层。
根据本发明的优选实施方式，在等离子氧环境中进行所述退火处理。
根据本发明的优选实施方式，所述退火处理的条件为：温度在350摄氏度至400摄氏度、时间为60秒至400秒。
根据本发明的优选实施方式，所形成的过渡金属氧化物具有梯形能带。
根据本发明的优选实施方式，所述上电极为Pt、W、Ru、Al、TiN、TaN、IrO2、ITO、IZO中的至少一种。
本发明还提出由上述基于过渡金属氧化物的选择器的制备方法所制备的基于过渡金属氧化物的选择器。优选地，该阻变存储器具有1S1R 结构。
本发明还提出一种阻变存储器，包括所述的基于过渡金属氧化物的选择器。
从上述技术方案来看，本发明有以下有益效果：
1、本发明，制备工艺简单，工艺成本低，有利于存储器的集成。
2、本发明能够为1S1R结构双极性阻变存储器提供双向整流器件，抑制读串扰。
3、本发明能够为1S1R结构双极性阻变存储器提供较高的电流密度和较高的选择比，有利于RRAM的更大规模的集成。
4、本发明能够为1S1R结构双极性阻变存储器提供与标准CMOS工艺兼容的选择器，便于工业化生产。
5、本发明能够为1S1R结构双极性阻变存储器提供超高均一性的选择器，降低了电路设计的难度，便于工业化生产和应用。
附图说明
图1是本发明提供的选择器的制备方法示意图；
图2至图5是选择器的制备方法过程示意图；
图6是本发明提供的选择器的原理示意图；
图7是本发明提供的选择器的的电流电压曲线实测图；
图8是本发明提供的选择器的和阻变器件串联后的电流电压曲线实测图。
具体实施方式
本发明提出的基于过渡金属氧化物的选择器的制备方法包括如下步骤：
S1、在晶体管上形成钨栓塞。
该步骤可采用准的CMOS工艺形成钨栓塞，具体包括形成钨栓塞孔洞、沉积扩散阻挡层、利用PECVD工艺填充孔洞及化学机载抛光等工艺。
S2、以钨栓塞作为下电极，并在钨栓塞上制备过渡金属层。
该步骤在钨栓塞上可通过磁控溅射生长过渡金属层，其中过渡金属可以采用Ta、Ti、Zr、Hf、Nb等，厚度为2nm至8nm。由于本发明下电极为钨栓塞，不需要特别制备下电极。
S3、氧化过渡金属层，使之转化为过渡金属氧化物层。
该步骤可通过对器件进行退火处理来形成过渡金属氧化物。所述退火环境可以为等离子氧，退火的温度为350度至400度(CMOS工艺兼容)。退火时间依过渡金属的厚度而定(越厚时间越长)，以8nm为例氧化温度为400度的情况下退火时间为300s。
S4、在过渡金属氧化物上沉积上电极。
所述上电极材料可以为W、Ru、Al、Ti等材料，也可以是导电金属化合物，如TiN、TaN、IrO2、ITO、IZO。上电极材料可以通过电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积、溅射方法中的一种制备完成。其厚度一般为30nm～200nm。
该步骤后续还可包括图形化上电极和过渡金属氧化物的步骤。
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。在图中，为了清楚放大了层和区域的厚度，但作为示意图不应该被认为严格反映了几何尺寸的比例关系。
在此参考图是本发明的理想化实施例的示意图，本发明所示的实施例不应该被认为仅限于图中所示的区域的特定形状，而是包括所得到的形状，比如制造引起的偏差。例如干法刻蚀得到的曲线通常具有弯曲或圆润的特点，但在本发明实施例图示中，均以矩形表示，图中的表示是示意性的，但这不应该被认为限制本发明的范围。
图1所示为本发明提供的基于过渡金属氧化物的选择器的制备方法的流程示意图。同时，图2至图5则分别示意了该电阻型存储器的制备 方法在各步骤时的示意结构。以下结合图1至图5详细说明电阻型存储器的制造方法。
如图所示，本发明的实施例的制备方法主要包括：
S1、在晶体管上形成钨栓塞。
该步骤采用标准CMOS工艺制备钨栓塞。具体包括如下分步骤：
S11、通过光刻、刻蚀工艺在MOS器件上方形成钨栓塞孔洞。
S12、在钨栓塞孔洞内沉积扩散阻挡层，在该实施例中为Ti/TiN合层或Ti层、TiN层，厚度范围为3nm～50nm。
S13、采用PECVD工艺在孔洞内填满金属钨，钨的厚度为50～5000nm；
S14、对钨栓塞表面经过化学机械抛光。
图2的a部分展示了经过常规CMOS工艺进行到钨栓塞结束后的剖面图。后续的工艺步骤是在图2的b部分所示钨栓塞21上表面进行的。
S2、以钨栓塞作为下电极，并在钨栓塞上制备过渡金属层。
该步骤在钨栓塞21上可通过磁控溅射生长过渡金属层22，其中过渡金属可以采用Ta、Ti、Zr、Hf、Nb等，厚度为2nm至8nm。由于本发明下电极为钨栓塞，不需要特别制备下电极。
S3、氧化过渡金属层，使之转化为过渡金属氧化物层。
在该步骤中，如图4所示，通过对器件在等离子氧环境中退火处理，使过渡金属层转化为过渡金属氧化物层。其退火条件为：(1)温度在350摄氏度至400摄氏度。(2)时间为60秒至400秒(依氧化温度和过渡金属的厚度而定)。(3)氛围：等离子氧气。过渡金属氧化物在等离子氧的环境中快速退火迅速被氧化，氧化的过程由外及内，表面氧化比较彻底得到完全氧化的过渡金属氧化物，离表面越远的地方低价态的过渡金属氧化物出现。由于不同组分的过渡金属氧化物禁带宽度不同(氧化越充分禁带宽度越宽)，形成了梯形能带。
图6显示了过渡金属氧化物层的能带图。如图所示，过渡金属氧化物层的能带为梯形，这样的能带结构导致了非线性的电流电压的关系。如图6的a图所示，在加正向电压时，电压比较小时主要以隧穿电流为 主，由于器件厚度比较厚隧穿电流很小，当正向电流比较大时，电流以热电子激发为主电流突然增大，形成了高非线性。如图6的b图所示，在加反向电压时，由于势垒比较高，热电子激发电流比较小，所以反向电流密度小于正向电流密度。
S4、在过渡金属氧化物上沉积上电极。
在该实施例中，如图5所示，上电极25采用Pt、W、Ru、Al或导电金属化合物TiN、TaN、IrO2、ITO、IZO中的至少一种。在构图形成上电极的步骤中，可以采用半导体常规工艺光刻和刻蚀完成。
图7展示了本发明的基于过渡金属氧化物的选择器的一个实施例的电流电压曲线实测图。对器件进行了电压扫面1000次，可以看到器件的均一性非常好。
图8展示了本发明提供的阻变器件的一个实施例的电流电压曲线实测图，证明该器件可以正常工作在1S1R结构的阵列中，作为一个实例展示了类型选择器的基本性质。
综合上述可知，本发明利用PECVD对过渡金属进行氧化形成过渡金属氧化物，随后生长上电极。本发明的基于过渡金属氧化物的选择器能够提供较高的的电流密度，有很好的均一性，形成1S1R结构能有效抑制阻变存储器阵列中的串扰现象，在不增加存储单元面积的情况下有效提高存储密度，提高器件集成度。此外本发明用于阻变存储器的选择器具有结构简单，易集成，成本低，均一性好，CMOS工艺兼容等优点，有利于本发明的广泛推广应用。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种基于过渡金属氧化物的选择器的制备方法，包括如下步骤：
    S1、在晶体管上形成钨栓塞；
    S2、以钨栓塞作为下电极，并在钨栓塞上制备过渡金属层；
    S3、氧化过渡金属层，使之转化为过渡金属氧化物层；
    S4、在过渡金属氧化物上沉积上电极，图形化上电极和过渡金属氧化物。
  2. 如权利要求1所述的基于过渡金属氧化物的选择器的制备方法，其中，所述过渡金属为Ta、Ti、Zr、Hf、Nb中的至少一种。
  3. 如权利要求2所述的基于过渡金属氧化物的选择器的制备方法，其中，所述过渡金属层的厚度为2nm至8nm。
  4. 如权利要求1所述的基于过渡金属氧化物的选择器的制备方法，其中，所述步骤S3通过退火处理使过渡金属层转化为过渡金属氧化物层。
  5. 如权利要求4所述的基于过渡金属氧化物的选择器的制备方法，其中，在等离子氧环境中进行所述退火处理。
  6. 如权利要求5所述的基于过渡金属氧化物的选择器的制备方法，其中，所述退火处理的条件为：温度在350摄氏度至400摄氏度、时间为60秒至400秒。
  7. 如权利要求4所述的基于过渡金属氧化物的选择器的制备方法，其中，所形成的过渡金属氧化物具有梯形能带。
  8. 如权利要求1所述的基于过渡金属氧化物的选择器的制备方法，其中，所述上电极为Pt、W、Ru、Al、TiN、TaN、IrO2、ITO、IZO中的至少一种。
  9. 一种基于过渡金属氧化物的选择器，由权利要求1至8中任一项所述的基于过渡金属氧化物的选择器的制备方法所制备。
  10. 一种阻变存储器，包括如权利要求9所述的基于过渡金属氧化物的选择器。
PCT/CN2017/074401 2017-02-22 2017-02-22 基于过渡金属氧化物的选择器及其制备方法 WO2018152697A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2017/074401 WO2018152697A1 (zh) 2017-02-22 2017-02-22 基于过渡金属氧化物的选择器及其制备方法
US16/486,614 US20200058704A1 (en) 2017-02-22 2017-02-22 Selector based on transition metal oxide and preparation method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/074401 WO2018152697A1 (zh) 2017-02-22 2017-02-22 基于过渡金属氧化物的选择器及其制备方法

Publications (1)

Publication Number Publication Date
WO2018152697A1 true WO2018152697A1 (zh) 2018-08-30

Family

ID=63252340

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/074401 WO2018152697A1 (zh) 2017-02-22 2017-02-22 基于过渡金属氧化物的选择器及其制备方法

Country Status (2)

Country Link
US (1) US20200058704A1 (zh)
WO (1) WO2018152697A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11404639B2 (en) * 2018-08-28 2022-08-02 Intel Corporation Selector devices with integrated barrier materials

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1641882A (zh) * 2004-01-12 2005-07-20 三星电子株式会社 半导体器件中的节点接触结构及其制造方法
CN101068039A (zh) * 2006-05-05 2007-11-07 旺宏电子股份有限公司 双稳态电阻随机存取存储器的结构与方法
CN102683584A (zh) * 2011-03-18 2012-09-19 中国科学院微电子研究所 集成标准cmos工艺的金属氧化物电阻存储器及其制备方法
WO2016048330A1 (en) * 2014-09-25 2016-03-31 Intel Corporation 1s1r memory cells incorporating a barrier layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1641882A (zh) * 2004-01-12 2005-07-20 三星电子株式会社 半导体器件中的节点接触结构及其制造方法
CN101068039A (zh) * 2006-05-05 2007-11-07 旺宏电子股份有限公司 双稳态电阻随机存取存储器的结构与方法
CN102683584A (zh) * 2011-03-18 2012-09-19 中国科学院微电子研究所 集成标准cmos工艺的金属氧化物电阻存储器及其制备方法
WO2016048330A1 (en) * 2014-09-25 2016-03-31 Intel Corporation 1s1r memory cells incorporating a barrier layer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
QING LUO ET AL.: "Fully BEOL Compatible TaOx-based Selector with High Unifor- mity and Robust Performance", 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM, 7 December 2016 (2016-12-07), XP033054963, ISSN: 2156-017X *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11404639B2 (en) * 2018-08-28 2022-08-02 Intel Corporation Selector devices with integrated barrier materials

Also Published As

Publication number Publication date
US20200058704A1 (en) 2020-02-20

Similar Documents

Publication Publication Date Title
KR100718155B1 (ko) 두 개의 산화층을 이용한 비휘발성 메모리 소자
JP5339716B2 (ja) 抵抗メモリ素子及びその製造方法
US9324944B2 (en) Selection device and nonvolatile memory cell including the same and method of fabricating the same
TWI402980B (zh) 具有緩衝層之電阻式記憶結構
US7498600B2 (en) Variable resistance random access memory device and a method of fabricating the same
KR101176542B1 (ko) 비휘발성 메모리 소자 및 이를 포함하는 메모리 어레이
KR100982424B1 (ko) 저항 메모리 소자의 제조 방법
CN105826468B (zh) 一种自选通阻变存储器件及其制备方法
US9177998B2 (en) Method of forming an asymmetric MIMCAP or a Schottky device as a selector element for a cross-bar memory array
JP2007300100A (ja) 可変抵抗物質を含む不揮発性メモリ素子
JP2007300082A (ja) 下部電極上に形成されたバッファ層を備える可変抵抗メモリ素子
US20130214235A1 (en) Resistive memory having rectifying characteristics or an ohmic contact layer
US9978941B2 (en) Self-rectifying resistive random access memory cell structure
Tran et al. Self-Selection Unipolar $\hbox {HfO} _ {x} $-Based RRAM
CN101159309A (zh) 一种低功耗电阻存储器的实现方法
US20140353566A1 (en) ReRAM materials stack for low-operating-power and high-density applications
KR101485024B1 (ko) 저항 변화 메모리 소자
JP2007311772A (ja) 金属／半導体／金属の積層構造を有する双方向ショットキーダイオード及びその形成方法
US10720578B2 (en) Self-gating resistive storage device having resistance transition layer in vertical trench in stacked structure of insulating dielectric layers and electrodes
JP2007158325A (ja) 双方向ショットキーダイオードを備えるクロスポイント型抵抗メモリ装置
CN106910759A (zh) 基于过渡金属氧化物的选择器及其制备方法
CN107204397B (zh) 用于双极性阻变存储器的选择器件及其制备方法
WO2018152697A1 (zh) 基于过渡金属氧化物的选择器及其制备方法
WO2017156755A1 (zh) 用于双极性阻变存储器的选择器件及其制备方法
KR100647332B1 (ko) 저항 변환 물질을 포함하는 ｒｒａｍ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17897878

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17897878

Country of ref document: EP

Kind code of ref document: A1