WO2018149029A1 - 一种高可靠性hemt制作方法 - Google Patents

一种高可靠性hemt制作方法 Download PDF

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WO2018149029A1
WO2018149029A1 PCT/CN2017/081592 CN2017081592W WO2018149029A1 WO 2018149029 A1 WO2018149029 A1 WO 2018149029A1 CN 2017081592 W CN2017081592 W CN 2017081592W WO 2018149029 A1 WO2018149029 A1 WO 2018149029A1
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layer
hemt
high reliability
dielectric layer
metal
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PCT/CN2017/081592
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French (fr)
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彭虎
张耀辉
莫海锋
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昆山华太电子技术有限公司
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Publication of WO2018149029A1 publication Critical patent/WO2018149029A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Definitions

  • the invention relates to a high reliability HEMT manufacturing method and belongs to the field of field effect transistor fabrication.
  • High electron mobility transistors also known as modulation doped field effect transistors (MODFETs), also known as two-dimensional electron gas field effect transistors (2DEGFETs)
  • MODFETs modulation doped field effect transistors
  • 2DEGFETs two-dimensional electron gas field effect transistors
  • HEMT channel field effect transistor
  • HEMT High Efficiency Magnetoresistive Tunneling
  • a wide bandgap material such as AlGaAs
  • a narrow bandgap material such as GaAs
  • a wide band gap material doped with an N-type impurity in the heterojunction serves as a supply layer for electrons to supply a large amount of electrons to the undoped narrow band gap material.
  • the two-dimensional electron gas with no impurity scattering is used as the conductive channel, and the electron concentration in the channel is modulated by the gate voltage, and the source region and the drain region are disposed on both sides of the gate.
  • the field effect transistor is the HEMT.
  • the two-dimensional electron gas electron concentration of HEMT is caused by the difference of conduction energy between two semiconductor materials.
  • the polarization effect of AlGaN and GaN also produces two-dimensional electron gas, and external stress causes electrons in two-dimensional electron gas.
  • the concentration changes.
  • the gate region of the device is covered by a thin dielectric layer and a passivation layer, that is, the region indicated by 1 in the figure.
  • the existing process scheme can reduce the influence of the dielectric layer and the passivation layer on the device performance, but since the dielectric layer and the passivation layer are too thin, the reliability of the device in a humid environment is very poor.
  • the present invention provides a high reliability HEMT manufacturing method.
  • a high reliability HEMT manufacturing method comprising the following steps,
  • Step 1 depositing a dielectric layer on the formed HEMT device, and planarizing the dielectric layer;
  • Step 2 etching a plurality of through holes or grooves on the planarized dielectric layer
  • Step 3 depositing a metal layer in the via hole or the trench, and planarizing the metal layer;
  • step 4 a passivation layer is deposited on the planarized metal layer and the dielectric layer.
  • the top surface of the planarized metal layer is flush with the top surface of the planarized dielectric layer.
  • the stress of the dielectric layer ranges from -1 x 10 9 to 1 x 10 9 dyne/cm 2 .
  • the dielectric layer includes a plurality of layers of media, and a dielectric barrier layer is disposed between adjacent two layers of media.
  • the bottom of the metal layer is provided with a metal barrier layer.
  • the passivation layer is SiN and/or SiON. .
  • the invention adopts metal filling after opening first, and then depositing a passivation layer, and by optimizing the structure of the passivation layer, the moisture resistance of the device can be ensured, and the device has high reliability in working in a humid environment. At the same time, by adjusting the thickness and stress of the passivation layer, adjustment and optimization of device performance can be achieved.
  • Figure 1 shows an existing HEMT.
  • FIG. 2 is a schematic view of a low stress dielectric layer after deposition and planarization.
  • FIG. 3 is a schematic view after etching a through hole or a groove.
  • Figure 4 is a schematic view of the metal after deposition.
  • Fig. 5 is a schematic view of the metal after planarization treatment.
  • Figure 6 is a HEMT of the present invention.
  • a high reliability HEMT manufacturing method includes the following steps:
  • Step 1 As shown in FIG. 2, a dielectric layer is deposited on the formed HEMT device, and the dielectric layer 2 is planarized.
  • CMP Chemical Mechanical Polishing
  • the dielectric layer 2 includes one or more layers of dielectrics having a stress range of -1 ⁇ 10 9 to 1 ⁇ 10 9 dyne / cm 2 , if
  • a dielectric barrier layer is disposed between two adjacent layers of media.
  • Step 2 as shown in FIG. 3, a plurality of through holes or grooves 5 are etched on the dielectric layer 2 after the planarization process.
  • Step 3 as shown in FIGS. 4 and 5, a metal layer 3 is deposited in the via hole or trench 5, and the metal layer 3 is planarized.
  • the top surface of the planarized metal layer 3 is flush with the top surface of the planarized dielectric layer 2, and the metal layer 3 may be gold, copper, aluminum, etc., and the bottom of the metal layer 3 is provided with a metal barrier layer such as titanium. And or titanium nitride.
  • Step 4 as shown in FIG. 6, a passivation layer 4 is deposited on the metal layer 3 and the dielectric layer 2 after the planarization process, and the passivation layer 4 is SiN and/or SiON.
  • the above method adopts metal filling after opening first, and then depositing the passivation layer 4.
  • the moisture resistance of the device can be ensured, and the device has high reliability in a humid environment;
  • Layer 4 thickness and stress can be optimized for device performance.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种高可靠性HEMT制作方法，包括步骤1，在成型后的HEMT器件上淀积介质层（2），并对介质层（2）进行平坦化处理；步骤2，在平坦化处理后的介质层（2）上刻蚀若干通孔或槽（5）；步骤3，在通孔或槽（5）中淀积金属层（3），并对金属层（3）进行平坦化处理；步骤4，在平坦化处理后的金属层（3）和介质层（2）上淀积钝化层（4）。采用先开孔后金属填充，然后淀积钝化层（4），通过优化钝化层（4）结构，可以保障器件的防潮能力，使器件具有在潮湿环境工作的高可靠性；同时通过调节钝化层（4）的厚度和应力，可以实现对器件性能的调节优化。

Description

一种高可靠性HEMT制作方法 技术领域
本发明涉及一种高可靠性HEMT制作方法，属于场效应晶体管制作领域。
背景技术
高电子迁移率晶体管也称调制掺杂场效应管(MODFET)，又称二维电子气场效应管(2DEGFET)，它是利用调制掺杂方法，在异质结界面形成的三角形势阱中的二维电子气作为沟道的场效应晶体管，简称HEMT。这种器件及其集成电路都能够工作于超高频(毫米波)、超高速领域，原因就在于它是利用具有很高迁移率的所谓二维电子气来工作的。
载流子的迁移率主要受晶格热振动和电离杂质两种散射作用而降低。电离杂质散射是增加载流子浓度和提高载流子迁移率矛盾产生的根源。HEMT与其它场效应管的主要区别是它包含一个由宽带隙材料(如AlGaAs)和窄带隙材料(如GaAs)构成的异质结。在该异质结中掺N型杂质的宽带隙材料作为电子的提供层向不掺杂窄带隙材料提供大量电子。这些电子积累在由两种材料导带底能量差(ΔEC)形成的三角形势阱中形成二维电子气(2DEG)。由于电子脱离了提供它的宽带隙材料中带正电的施主电离中心进入了不掺杂(无电离杂质散射)窄带隙材料的势阱中，不再受到电离杂质散射作用，而呈现出很高的迁移率。利用这种无杂质散射的二维电子气作为导电沟道，沟道中的电子浓度受到栅电压的调制，在栅极两侧设置源区和漏区，这种场效应管就是HEMT。
HEMT二维电子气电子浓度是由两种半导体材料导带能量差引起，尤其在GaN HEMT中，AlGaN和GaN的极化效应也会产生二维电子气，外部应力会导致二维电子气中电子浓度变化。如图1所示，现有HEMT工艺中，为了减小应 力对二维电子气的影响，器件栅极区域采用较薄的介质层和钝化层覆盖，即图中1所指的区域。现有工艺方案能减小介质层和钝化层对器件性能的影响，但由于介质层和钝化层太薄，器件在潮湿环境的可靠性非常差。
发明内容
为了解决上述技术问题，本发明提供了一种高可靠性HEMT制作方法。
为了达到上述目的，本发明所采用的技术方案是：
一种高可靠性HEMT制作方法，包括以下步骤，
步骤1，在成型后的HEMT器件上淀积介质层，并对介质层进行平坦化处理；
步骤2，在平坦化处理后的介质层上刻蚀若干通孔或槽；
步骤3，在通孔或槽中淀积金属层，并对金属层进行平坦化处理；
步骤4，在平坦化处理后的金属层和介质层上淀积钝化层。
平坦化处理后的金属层顶面与平坦化处理后的介质层顶面齐平。
所述介质层的应力范围为-1×109～1×109dyne/cm2。
所述介质层包括多层介质，相邻两层介质之间设置有介质阻挡层。
所述金属层的底部设置有金属阻挡层。
所述钝化层为SiN和/或SiON。。
本发明所达到的有益效果：本发明采用先开孔后金属填充，然后淀积钝化层，通过优化钝化层结构，可以保障器件的防潮能力，使器件具有在潮湿环境工作的高可靠性；同时通过调节钝化层的厚度和应力，可以实现对器件性能的调节优化。
附图说明
图1为现有的HEMT。
图2为低应力介质层淀积和平坦化处理后的示意图。
图3为刻蚀通孔或槽后的示意图。
图4为金属淀积后的示意图。
图5为金属平坦化处理后的示意图。
图6为本发明的HEMT。
具体实施方式
下面结合附图对本发明作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。
一种高可靠性HEMT制作方法，包括以下步骤：
步骤1，如图2所示，，在成型后的HEMT器件上淀积介质层，并对介质层2进行平坦化处理。
这里采用进行CMP(化学机械抛光)进行平坦化处理，介质层2包括一层或多层介质，该介质层2的应力范围为-1×109～1×109dyne/cm2，如果是多层介质，则相邻两层介质之间设置有介质阻挡层。
步骤2，如图3所示，在平坦化处理后的介质层2上刻蚀若干通孔或槽5。
步骤3，如图4和5所示，在通孔或槽5中淀积金属层3，并对金属层3进行平坦化处理。
平坦化处理后的金属层3顶面与平坦化处理后的介质层2顶面齐平，该金属层3可以为金、铜、铝等，金属层3的底部设置有金属阻挡层，如钛和或氮化钛。
步骤4，如图6所示，在在平坦化处理后的金属层3和介质层2上淀积钝化层4，钝化层4为SiN和/或SiON。
上述方法采用先开孔后金属填充，然后淀积钝化层4，通过优化钝化层4结构，可以保障器件的防潮能力，使器件具有在潮湿环境工作的高可靠性；同时通过调节钝化层4的厚度和应力，可以实现对器件性能的调节优化。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和变形，这些改进和变形也应视为本发明的保护范围。

Claims (6)

  1. 一种高可靠性HEMT制作方法，其特征在于：包括以下步骤，
    步骤1，在成型后的HEMT器件上淀积介质层，并对介质层进行平坦化处理；
    步骤2，在平坦化处理后的介质层上刻蚀若干通孔或槽；
    步骤3，在通孔或槽中淀积金属层，并对金属层进行平坦化处理；
    步骤4，在平坦化处理后的金属层和介质层上淀积钝化层。
  2. 根据权利要求1所述的一种高可靠性HEMT制作方法，其特征在于：平坦化处理后的金属层顶面与平坦化处理后的介质层顶面齐平。
  3. 根据权利要求1或2所述的一种高可靠性HEMT制作方法，其特征在于：所述介质层的应力范围为-1×109～1×109dyne/cm2。
  4. 根据权利要求3所述的一种高可靠性HEMT制作方法，其特征在于：所述介质层包括多层介质，相邻两层介质之间设置有介质阻挡层。
  5. 根据权利要求1或2所述的一种高可靠性HEMT制作方法，其特征在于：所述金属层的底部设置有金属阻挡层。
  6. 根据权利要求1所述的一种高可靠性HEMT制作方法，其特征在于：所述钝化层为SiN和/或SiON。
PCT/CN2017/081592 2017-02-17 2017-04-24 一种高可靠性hemt制作方法 WO2018149029A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162695A (zh) * 2006-10-09 2008-04-16 西安能讯微电子有限公司 氮化镓hemt器件表面钝化及提高器件击穿电压的工艺
CN102237405A (zh) * 2010-05-07 2011-11-09 富士通半导体股份有限公司 复合半导体器件及其制造方法
CN102714219A (zh) * 2009-12-10 2012-10-03 特兰斯夫公司 反侧设计的iii-氮化物器件
CN103904110A (zh) * 2014-01-20 2014-07-02 西安电子科技大学 加栅场板耗尽型绝缘栅AlGaN/GaN器件结构及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162695A (zh) * 2006-10-09 2008-04-16 西安能讯微电子有限公司 氮化镓hemt器件表面钝化及提高器件击穿电压的工艺
CN102714219A (zh) * 2009-12-10 2012-10-03 特兰斯夫公司 反侧设计的iii-氮化物器件
CN102237405A (zh) * 2010-05-07 2011-11-09 富士通半导体股份有限公司 复合半导体器件及其制造方法
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