WO2018148995A1 - 液晶显示面板及其像素电路结构 - Google Patents

液晶显示面板及其像素电路结构 Download PDF

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Publication number
WO2018148995A1
WO2018148995A1 PCT/CN2017/075929 CN2017075929W WO2018148995A1 WO 2018148995 A1 WO2018148995 A1 WO 2018148995A1 CN 2017075929 W CN2017075929 W CN 2017075929W WO 2018148995 A1 WO2018148995 A1 WO 2018148995A1
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Prior art keywords
electrode
scan line
circuit structure
pixel electrode
liquid crystal
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English (en)
French (fr)
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应见见
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/510,666 priority Critical patent/US10303026B2/en
Publication of WO2018148995A1 publication Critical patent/WO2018148995A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the technical field of liquid crystal displays, and in particular to a liquid crystal display panel and a pixel circuit structure thereof.
  • High resolution, high PPI (Pixel per Inch)'s panel display is fine and delicate, so as to achieve ultra-high-definition display, which is a direction of display technology development.
  • the corresponding pixel size is also reduced with the increase of resolution and PPI.
  • the pixel size is reduced, and the metal per unit area. As the area increases, the corresponding aperture ratio decreases, and the corresponding transmittance decreases. Therefore, the transmittance is a key consideration in high-resolution and high-PPI pixel design.
  • VA Vertical Alignment mode is based on the consideration of large viewing angles. Generally, there is a design with large viewing angle compensation, that is, there is a discharge capacitor (Cdown). In the existing design scheme, the discharge capacitor is generally set on the Com (common electrode) line. Sacrifice the aperture ratio of the pixel, which in turn reduces product penetration.
  • the embodiments of the present invention provide a liquid crystal display panel and a pixel circuit structure thereof to solve the technical problem that the liquid crystal display panel has low transmittance due to low pixel aperture ratio in the prior art.
  • an embodiment of the present invention provides a pixel circuit structure having a high transmittance, the pixel circuit structure including a data line, a first scan line, and a second scan line, wherein the first scan
  • the lines are respectively connected to the gates of the main pixel electrode and the sub-pixel electrode, the second scan line is connected to the gate of the distribution electrode, and the sources of the main pixel electrode and the sub-pixel electrode are respectively connected to the data line
  • the drain is respectively connected to the equivalent liquid crystal capacitor; the source of the distribution electrode is connected to the drain of the sub-pixel electrode, and the first discharge capacitor is disposed between the source and the first scan line.
  • another aspect of the present invention provides a liquid crystal display panel including the pixel circuit structure described in the above embodiments.
  • the liquid crystal display panel and the pixel circuit structure thereof provided by the invention optimize the design position of the discharge capacitor without changing the large viewing angle effect, and design it on the scan line (Gate) without occupying the in-plane
  • the opening area can greatly increase the aperture ratio, thereby increasing the transmittance of the liquid crystal panel.
  • FIG. 1 is a circuit diagram of a first embodiment of a pixel circuit structure having high transmittance according to the present invention
  • FIG. 2 is a wiring diagram of a pixel circuit structure in the embodiment of FIG. 1;
  • FIG. 3 is a circuit diagram of a second embodiment of a pixel circuit structure having high transmittance according to the present invention.
  • FIG. 4 is a wiring diagram of a pixel circuit structure in the embodiment of FIG. 3;
  • Fig. 5 is a circuit control waveform diagram of a pixel circuit structure.
  • FIG. 1 is a circuit diagram of a first embodiment of a pixel circuit structure having high transmittance according to the present invention
  • FIG. 2 is a circuit diagram of a pixel circuit structure in the embodiment of FIG. 1.
  • the pixel circuit structure The first scan line 101, the second scan line 102, and the data line 103 are included.
  • the first scan lines 101 are respectively connected to the gates of the main pixel electrode 104 and the sub-pixel electrode 105 switch, and the first scan line 101 is used to control the main pixel electrode 104 (Main) and the sub-pixel electrode 105 (Sub).
  • a switch of the TFT the second scan line 102 is connected to the gate of the distribution electrode 106, and the second scan line 102 is used to control the switch of the distribution electrode 106 (Sharing TFT) to the Sub PE (Pixel electrode) discharge.
  • the sources of the main pixel electrode 104 and the sub-pixel electrode 105 are connected to the data line 103, respectively, and the drain is connected to the equivalent liquid crystal capacitor 107, respectively.
  • the source of the switch 106 of the distribution electrode is connected to the drain of the switch of the sub-pixel electrode 105, and the first discharge capacitor 108 is provided between the source and the first scan line 101.
  • One end of the equivalent liquid crystal capacitor 107 is connected to the drains of the main pixel electrode 104 and the sub-pixel electrode 105, respectively, and the other end is connected to a common electrode (not shown) of the color filter substrate.
  • the drains of the main pixel electrode 104 and the sub-pixel electrode 105 are respectively connected to one end of the holding capacitor 109, and the other end of the holding capacitor 109 is connected to the common electrode 110.
  • the first discharge capacitor 108 and the distribution electrode 106 are respectively disposed on different scan lines (101 or 102).
  • the first discharge capacitor 108 and the distribution electrode 106 may also be disposed on the same scan line.
  • the first discharge capacitor 108 is disposed on the first scan line 101
  • the distribution electrode 106 is disposed on the second scan line 102. It should be noted that the main inventive point of the present invention lies in the first The discharge capacitor 108 and the distribution electrode 106 are disposed on the scan line, and as to which scan line the first discharge capacitor 108 and the distribution electrode 106 are specifically disposed, which are within the understanding of those skilled in the art, will not be enumerated here.
  • Pixel(m,n) is a Pixel corresponding to Gate(m) and Data(n), which corresponds to Gate1(m) and Gate2(m), and Gate1(m) controls the switching of the main pixel electrode 104 and the sub-pixel electrode 105, Gate2 (m) only used to control the distribution electrode 106 (Sharing TFT) switch, and Gate2(m) is turned on later than Gate1(m) when one frame is displayed, so when Gate1(m) is on, Data line pair Sub (sub-pixel electrode 105) and Main PE (main pixel electrode 104) is charged to saturation, then Gate1(m) is turned off, and the potential of Sub and Main PE is equivalent.
  • the Gate line is opaque metal material; and Sub and Main PE is an ITO transparent electrode.
  • FIG. 3 is a circuit diagram of a second embodiment of a pixel circuit structure having high transmittance according to the present invention
  • FIG. 4 is a circuit diagram of a pixel circuit structure in the embodiment of FIG. 3.
  • the pixel circuit structure The first scan line 101, the second scan line 102, and the data line 103 are also included.
  • the first scan lines 101 are respectively connected to the gates of the main pixel electrode 104 and the sub-pixel electrode 105 switch, and the first scan line 101 is used to control the main pixel electrode 104 (Main) and the sub-pixel electrode 105 (Sub).
  • a switch of the TFT the second scan line 102 is connected to the gate of the distribution electrode 106, and the second scan line 102 is used to control the switch of the distribution electrode 106 (Sharing TFT) to the Sub PE (Pixel electrode) discharge.
  • the sources of the main pixel electrode 104 and the sub-pixel electrode 105 are connected to the data line 103, respectively, and the drain is connected to the equivalent liquid crystal capacitor 107, respectively.
  • the source of the switch 106 of the distribution electrode is connected to the drain of the switch of the sub-pixel electrode 105, and the first discharge capacitor 108 is provided between the source and the first scan line 101.
  • One end of the equivalent liquid crystal capacitor 107 is connected to the drains of the main pixel electrode 104 and the sub-pixel electrode 105, respectively, and the other end is connected to a common electrode (not shown) of the color filter substrate.
  • the drains of the main pixel electrode 104 and the sub-pixel electrode 105 are respectively connected to one end of the holding capacitor 109, and the other end of the holding capacitor 109 is connected to the common electrode 110.
  • the first discharge capacitor 108 and the distribution electrode 106 are respectively disposed on different scan lines (101 or 102).
  • the first discharge capacitor 108 and the distribution electrode 106 may also be disposed on the same scan line.
  • the first discharge capacitor 108 is disposed on the first scan line 101
  • the distribution electrode 106 is disposed on the second scan line 102. It should be noted that the main inventive point of the present invention lies in the first The discharge capacitor 108 and the distribution electrode 106 are disposed on the scan line, and as to which scan line the first discharge capacitor 108 and the distribution electrode 106 are specifically disposed, which are within the understanding of those skilled in the art, will not be enumerated here.
  • the pixel circuit structure in this embodiment further includes a second discharge capacitor 111 disposed between the main pixel electrode 104 and the drain of the distribution electrode 106, and the second discharge
  • the function of the capacitor 111 is: at the sub-pixel electrode 105 (Sub PE)
  • the potential change will have a certain influence on the main pixel electrode 104 (Main PE). Due to the presence of the second discharge capacitor 111, the difference between the Main PE and Sub PE potentials can still be ensured.
  • the second discharge capacitor 111 can be disposed on the first scan line 101 or the second scan line 102. In this embodiment, the second discharge capacitor 111 is disposed on the first scan line 101. Of course, in other implementations. In the example, the second discharge capacitor 111 may also be disposed on the second scan line 102.
  • FIG. 5 is a circuit control waveform diagram of a pixel circuit structure.
  • the resolution of 60HZ and FHD (1920*1080) is taken as an example in the circuit of this embodiment.
  • the Gate switch voltage is 27V, -6V, 255 gray-scale Data signal positive polarity is 14.2V, com potential is 7V, 255 gray-scale negative polarity voltage can be set according to the actual situation (negative polarity and Com potential can be based on actual The situation is adjusted to ensure the symmetry of the positive and negative frames.
  • Pixel(m,n) is the Pixel corresponding to Gate(m) and Data(n), which corresponds to Gate1(m) and Gate2(m), and Gate1(m) controls Main and Sub.
  • TFT switch Gate2(m) is only used to control Sharing When the TFT is switched, and one frame is displayed, Gate2(m) is turned on later than Gate1(m).
  • Gate2(m) is set to be turned on after Gate1(m), so when Gate1(m) is on, Data( 14.2V) on Sub And Main PE are charged, assuming a charge rate of 96%, Main and Sub
  • the PE potentials are 13.6V and 13.4V respectively (there will be differences due to different TFT parameters), Gate1(m) is turned off after 14.8us, and when Gate2(m) is turned on, Sharing When the TFT is turned on, the Sub PE is discharged to the Cdown capacitor (the first discharge capacitor 108), and the Cdown is saturated.
  • the pixel circuit structure provided by the embodiment optimizes the design position of the first discharge capacitor without changing the large viewing angle effect, and is designed on the scan line (Gate) without occupying the open area of the surface.
  • the aperture ratio can be greatly increased, thereby increasing the transmittance of the liquid crystal panel.
  • by providing a second discharge capacitor between the main pixel electrode and the drain of the distribution electrode it is possible to ensure the main when the potential of the sub-pixel electrode changes.
  • the difference between the potential of PE and Sub PE makes the liquid crystal display panel display normally.
  • the embodiment of the present invention further provides a liquid crystal display panel including a liquid crystal panel, a backlight panel, and a pixel circuit structure and the like in the above embodiments.
  • a liquid crystal display panel including a liquid crystal panel, a backlight panel, and a pixel circuit structure and the like in the above embodiments.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种液晶显示面板及其像素电路结构，该像素电路结构包括数据线（103）、第一扫描线（101）以及第二扫描线（102），其中第一扫描线（101）分别与主像素电极以及副像素电极的开关（104、105）的栅极连接，第二扫描线（102）与分配电极的开关（106）的栅极连接，分配电极的开关（106）的源极与副像素电极的开关（105）的漏极连接，漏极与第一扫描线（101）之间设有第一放电电容（108）。该液晶显示面板及其像素电路结构，在不改变大视角效果前提下，将放电电容设计在扫描线上，不占用面内开口区，可以大幅度提升开口率，进而提高液晶面板的穿透率。

Description

液晶显示面板及其像素电路结构
【技术领域】
本发明涉及液晶显示器的技术领域，具体是涉及一种液晶显示面板及其像素电路结构。
【背景技术】
高分辨率，高PPI（Pixel per Inch）的面板显示画面精细和细腻，从而达到超高清显示，是显示科技发展的一个方向，对应的像素尺寸也随着分辨率和PPI的提高而减小，像素尺寸减小，单位面积的金属面积增加，相应开口率降低，对应的穿透率会降低，因此穿透率的是高分辨率高PPI像素设计一个重点考量因素。VA（Vertical Alignment）模式基于大视角的考虑，一般都会有大视角补偿的设计，即有放电电容（Cdown），现有设计方案中，一般将放电电容设置在Com（公共电极）线上，这种设计会牺牲像素的开口率，进而降低产品穿透率。
【发明内容】
有鉴于此，本发明实施例提供一种液晶显示面板及其像素电路结构，以解决现有技术中液晶显示面板由于像素开口率低而导致穿透率低的技术问题。
为解决上述问题，本发明实施例一方面提供了一种具有高穿透率的像素电路结构，所述像素电路结构包括数据线、第一扫描线以及第二扫描线，其中所述第一扫描线分别与主像素电极以及副像素电极的栅极连接，所述第二扫描线与分配电极的栅极连接，所述主像素电极和所述副像素电极的源极分别与所述数据线连接，漏极分别连接等效液晶电容；所述分配电极的源极与所述副像素电极的漏极连接，源极与所述第一扫描线之间设有第一放电电容。
为解决上述技术问题，本发明实施例另一方面提供一种液晶显示面板，所述液晶显示面板包括上述实施例中所述的像素电路结构。
相对于现有技术，本发明提供的液晶显示面板及其像素电路结构，在不改变大视角效果前提下，优化放电电容的设计位置，将其设计在扫描线（Gate）上，不占用面内开口区，可以大幅度提升开口率，进而提高液晶面板的穿透率。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明具有高穿透率的像素电路结构第一实施例的电路图；
图2是图1实施例中像素电路结构的布线图；
图3是本发明具有高穿透率的像素电路结构第二实施例的电路图；
图4是图3实施例中像素电路结构的布线图；
图5是像素电路结构的电路控制波形图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
像素电路结构实施例1
请一并参阅图1和图2，图1是本发明具有高穿透率的像素电路结构第一实施例的电路图，图2是图1实施例中像素电路结构的布线图；该像素电路结构包括第一扫描线101、第二扫描线102以及数据线103。
具体而言，该第一扫描线101分别与主像素电极104以及副像素电极105开关的栅极连接，第一扫描线101用于控制主像素电极104（Main）和副像素电极105（Sub TFT）的开关；而第二扫描线102与分配电极106的栅极连接，第二扫描线102用于控制分配电极106（Sharing TFT）的开关，给Sub PE（Pixel electrode）放电。
主像素电极104和副像素电极105的源极分别与数据线103连接，漏极分别连接等效液晶电容107。
分配电极的开关106的源极与副像素电极105开关的漏极连接，源极与第一扫描线101之间设有第一放电电容108。等效液晶电容107的一端与分别与主像素电极104和副像素电极105开关的漏极连接，另一端分别与彩膜基板的公共电极（图中未示）连接。
主像素电极104和副像素电极105开关的漏极分别与保持电容109的一端连接，保持电容109的另一端则与公共电极110连接。
优选地，本实施例中第一放电电容108与分配电极106分别设于不同的扫描线（101或者102）上。当然，在其他实施例中，第一放电电容108与分配电极106也可以设于同一扫描线上。
进一步优选地，本实施例中第一放电电容108设于第一扫描线101上，而分配电极106则设于第二扫描线102上，需要说明的是，本发明的主要发明点在于第一放电电容108和分配电极106设于扫描线上，而至于第一放电电容108和分配电极106具体设置在哪一条扫描线上，在本领技术人员的理解范围内，此处不再一一列举。
一个像素对应设计两根Gate（扫描）线（101、102）。Pixel（m，n）即对应Gate（m）和Data（n）的Pixel，其对应Gate1（m）和Gate2（m），Gate1（m）控制主像素电极104和副像素电极105的开关，Gate2（m）仅用来控制分配电极106（Sharing TFT）的开关，且一帧画面时，Gate2（m）比Gate1（m）晚打开，因此Gate1（m）开时，Data线对Sub （副像素电极105）和Main PE（主像素电极104）都充电，至饱和，然后Gate1（m）关闭，此时Sub和Main PE的电位相当，当Gate2（m）打开时，Sharing TFT开，会对Sub PE放电至Cdown电容（第一放电电容108），从而保证Sub PE电位低于Main PE，从而达到视角补偿的效果。
如图2所示，Gate线为不透光金属材料；而Sub 和Main PE则是ITO透明电极。传统大视角补偿设计，Cdown设计在com（公共）电极上，com电极面积增大，会占用像素开口区，相比较而言，本实施例提供的像素电路结构，通过将第一放电电容Cdown的一端设计在Gate2（m）线上，不占用com的面积，因而可以有效增加像素开口区域，提升穿透率。
像素电路结构实施例2
请一并参阅图3和图4，图3是本发明具有高穿透率的像素电路结构第二实施例的电路图，图4是图3实施例中像素电路结构的布线图；该像素电路结构同样包括第一扫描线101、第二扫描线102以及数据线103。
具体而言，该第一扫描线101分别与主像素电极104以及副像素电极105开关的栅极连接，第一扫描线101用于控制主像素电极104（Main）和副像素电极105（Sub TFT）的开关；而第二扫描线102与分配电极106的栅极连接，第二扫描线102用于控制分配电极106（Sharing TFT）的开关，给Sub PE（Pixel electrode）放电。
主像素电极104和副像素电极105的源极分别与数据线103连接，漏极分别连接等效液晶电容107。
分配电极的开关106的源极与副像素电极105开关的漏极连接，源极与第一扫描线101之间设有第一放电电容108。等效液晶电容107的一端与分别与主像素电极104和副像素电极105开关的漏极连接，另一端分别与彩膜基板的公共电极（图中未示）连接。
主像素电极104和副像素电极105开关的漏极分别与保持电容109的一端连接，保持电容109的另一端则与公共电极110连接。
优选地，本实施例中第一放电电容108与分配电极106分别设于不同的扫描线（101或者102）上。当然，在其他实施例中，第一放电电容108与分配电极106也可以设于同一扫描线上。
进一步优选地，本实施例中第一放电电容108设于第一扫描线101上，而分配电极106则设于第二扫描线102上，需要说明的是，本发明的主要发明点在于第一放电电容108和分配电极106设于扫描线上，而至于第一放电电容108和分配电极106具体设置在哪一条扫描线上，在本领技术人员的理解范围内，此处不再一一列举。
与上一实施例不同的是，本实施例中的像素电路结构还包括第二放电电容111，该第二放电电容111设于主像素电极104和分配电极106的漏极之间，第二放电电容111的作用为：在副像素电极105（Sub PE）电位变化时会对主像素电极104（Main PE）产生一定的影响，由于第二放电电容111的存在，仍然可保证Main PE和Sub PE电位的不同。
优选地，该第二放电电容111可以设于第一扫描线101或者第二扫描线102上，在本实施例中，第二放电电容111设于第一扫描线101上，当然，在其他实施例中，第二放电电容111也可以设于第二扫描线102上。
请参阅图5，图5是像素电路结构的电路控制波形图。本实施例的电路中以60HZ，FHD（1920*1080）的分辨率为例。其中，Gate开关电压分别为27V，-6V，255灰阶Data信号正极性为14.2V，com电位为7V，255灰阶负极性电压可根据实际情况来设定（负极性和Com电位可根据实际情况进行调节，保证正负帧的对称性），则一帧中Gate可开启的时间为14.8us（1s/60/1080=15.4us，扣除blinking时间约为14.8us）即图5中t=14.8us。
电路中一个像素对应设计两根Gate线。Pixel（m，n）即对应Gate（m）和Data（n）的Pixel，其对应Gate1（m）和Gate2（m），Gate1（m）控制Main和Sub TFT的开关，Gate2（m）仅用来控制Sharing TFT的开关，且一帧画面时，Gate2（m）比Gate1（m）晚打开，在此设定为Gate2（m）在Gate1（m）后相继打开，因此Gate1（m）开时，Data（14.2V）对Sub 和Main PE都充电，假定充电率为96%则Main和Sub PE电位分别为13.6V和13.4V（因TFT参数不同电位会有差别），Gate1（m）开启14.8us后关闭，当Gate2（m）相继打开，Sharing TFT开，会对Sub PE放电至Cdown电容（第一放电电容108），Cdown饱和后Sub PE保持9V电压（假定Vsub/Vmain=72%，该参数可以通过调整Cdown电容大小调节），从而达到视角补偿的效果。
当下一帧Gate1（m）开时，Cdown电容一端电位(Gate1(m)电位)从-6V变为27V，ΔV=33V，电容耦合效应Sub PE电位上升约为33V，则约为42V。随后Gate1(m)关闭时，ΔV=-33V，Sub PE下降至9V。Sub PE电位为42V的时间约为14.8us，而液晶的偏转响应时间为ms量级，该处的电容耦合效应不会影响液晶的偏转，不会出现显示异常。
相对于现有技术，本实施例提供的像素电路结构，在不改变大视角效果前提下，优化第一放电电容的设计位置，将其设计在扫描线（Gate）上，不占用面内开口区，可以大幅度提升开口率，进而提高液晶面板的穿透率，另外，还通过在主像素电极和分配电极的漏极之间设置第二放电电容，可以在副像素电极电位变化时，保证Main PE和Sub PE电位的不同，进而使液晶显示面板可以正常显示。
进一步地，本发明实施例还提供一种液晶显示面板，该液晶显示面板包括液晶面板、背光板以及上述实施例中的像素电路结构等结构，其中，像素电路结构的详细技术特征请参阅上述实施例中的具体描述，而关于液晶显示面板其他部分的结构特征，在本领域技术人员的理解范围内，此处不再赘述。
以上所述仅为本发明的部分实施例，并非因此限制本发明的保护范围，凡是利用本发明说明书及附图内容所作的等效装置或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种具有高穿透率的像素电路结构，其特征在于，所述像素电路结构包括数据线、第一扫描线以及第二扫描线，其中所述第一扫描线分别与主像素电极以及副像素电极的栅极连接，所述第二扫描线与分配电极的栅极连接，所述主像素电极和所述副像素电极的源极分别与所述数据线连接，漏极分别连接等效液晶电容；所述分配电极的源极与所述副像素电极的漏极连接，源极与所述第一扫描线之间设有第一放电电容，所述主像素电极和所述分配电极的漏极之间设有第二放电电容；所述第一放电电容与所述分配电极分别设于不同的扫描线上。
  2. 一种具有高穿透率的像素电路结构，其特征在于，所述像素电路结构包括数据线、第一扫描线以及第二扫描线，其中所述第一扫描线分别与主像素电极以及副像素电极的栅极连接，所述第二扫描线与分配电极的栅极连接，所述主像素电极和所述副像素电极的源极分别与所述数据线连接，漏极分别连接等效液晶电容；所述分配电极的源极与所述副像素电极的漏极连接，源极与所述第一扫描线之间设有第一放电电容。
  3. 根据权利要求2所述的像素电路结构，其特征在于，所述第一放电电容与所述分配电极分别设于不同的扫描线上。
  4. 根据权利要求3所述的像素电路结构，其特征在于，所述第一放电电容设于所述第一扫描线上。
  5. 根据权利要求4所述的像素电路结构，其特征在于，所述分配电极设于所述第二扫描线上。
  6. 根据权利要求2所述的像素电路结构，其特征在于，所述主像素电极和所述分配电极的漏极之间设有第二放电电容。
  7. 根据权利要求6所述的像素电路结构，其特征在于，所述第二放电电容设于所述第一扫描线或者所述第二扫描线上。
  8. 根据权利要求7所述的像素电路结构，其特征在于，所述第二放电电容设于所述第一扫描线上。
  9. 根据权利要求2所述的像素电路结构，其特征在于，所述等效液晶电容的一端与分别与所述主像素电极和所述副像素电极的漏极连接，另一端分别与彩膜基板的公共电极连接。
  10. 根据权利要求2所述的像素电路结构，其特征在于，所述主像素电极和所述副像素电极的漏极分别与保持电容的一端连接，所述保持电容的另一端与公共电极连接。
  11. 一种液晶显示面板，其特征在于，所述液晶显示面板包括具有高穿透率的像素电路结构，所述像素电路结构包括数据线、第一扫描线以及第二扫描线，其中所述第一扫描线分别与主像素电极以及副像素电极的栅极连接，所述第二扫描线与分配电极的栅极连接，所述主像素电极和所述副像素电极的源极分别与所述数据线连接，漏极分别连接等效液晶电容；所述分配电极的源极与所述副像素电极的漏极连接，源极与所述第一扫描线之间设有第一放电电容。
  12. 根据权利要求11所述的液晶显示面板，其特征在于，所述第一放电电容与所述分配电极分别设于不同的扫描线上。
  13. 根据权利要求12所述的液晶显示面板，其特征在于，所述第一放电电容设于所述第一扫描线上。
  14. 根据权利要求13所述的液晶显示面板，其特征在于，所述分配电极设于所述第二扫描线上。
  15. 根据权利要求11所述的液晶显示面板，其特征在于，所述主像素电极和所述分配电极的漏极之间设有第二放电电容。
  16. 根据权利要求15所述的液晶显示面板，其特征在于，所述第二放电电容设于所述第一扫描线或者所述第二扫描线上。
  17. 根据权利要求16所述的液晶显示面板，其特征在于，所述第二放电电容设于所述第一扫描线上。
  18. 根据权利要求11所述的液晶显示面板，其特征在于，所述等效液晶电容的一端与分别与所述主像素电极和所述副像素电极的漏极连接，另一端分别与彩膜基板的公共电极连接。
  19. 根据权利要求11所述的液晶显示面板，其特征在于，所述主像素电极和所述副像素电极的漏极分别与保持电容的一端连接，所述保持电容的另一端与公共电极连接。
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