WO2018137663A1 - 一种编码方法、译码方法、编码装置及译码装置 - Google Patents

一种编码方法、译码方法、编码装置及译码装置 Download PDF

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WO2018137663A1
WO2018137663A1 PCT/CN2018/074026 CN2018074026W WO2018137663A1 WO 2018137663 A1 WO2018137663 A1 WO 2018137663A1 CN 2018074026 W CN2018074026 W CN 2018074026W WO 2018137663 A1 WO2018137663 A1 WO 2018137663A1
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Prior art keywords
sequence
information
matrix
identification
encoding
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PCT/CN2018/074026
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English (en)
French (fr)
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张朝龙
黄凌晨
罗禾佳
李榕
王俊
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华为技术有限公司
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Priority to EP18744966.5A priority Critical patent/EP3553984B1/en
Publication of WO2018137663A1 publication Critical patent/WO2018137663A1/zh
Priority to US16/521,605 priority patent/US10972130B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1157—Low-density generator matrices [LDGM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
    • H04L1/0008—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length by supplementing frame payload, e.g. with padding bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy

Definitions

  • the present application relates to the field of communications technologies, and in particular, to an encoding method, a decoding method, an encoding device, and a decoding device.
  • Low Density Parity Check (LDPC) code a class of linear block codes with sparse check matrix proposed by Dr. Robert G. Gallage in 1963, not only has good performance close to Shannon limit, but also translates The code has low complexity and flexible structure. It is a research hotspot in the field of channel coding in recent years. It has been widely used in deep space communication, optical fiber communication, satellite digital video and audio broadcasting.
  • 5G fifth generation
  • eMBB Enhanced Mobile Broadband
  • the check matrix corresponding to the quasi-Cyclic Low Density Parity Check (QC-LDPC) code based on the base graph structure has the advantages of simple description and easy construction.
  • FIG. 2 is a schematic diagram of an LDPC check matrix constructed based on a base matrix, wherein the mesh portion in the figure is the position of padding bits.
  • these redundant information bit positions that is, the mesh portion of the drawing, are usually filled with 0, which is a so-called zero-padding method.
  • the receiving end decodes it is padded with 0 (if hard decoding is used) or 0 corresponding soft value (if soft decoding is used) to the corresponding position for decoding. This does not fully play the role of the extra information bits, that is, the padding bits.
  • the technical problem to be solved by the embodiments of the present application is to provide an encoding method, an encoding device, a decoding method, and a decoding device, which implement the function expansion of the LDPC check matrix.
  • an embodiment of the present application provides an encoding method, which may include:
  • the identification sequence is a non-zero sequence.
  • the check matrix Since the check matrix is constructed based on the information sequence and the identification sequence, the check matrix will contain information of the identification sequence, and the information sequence and the identification sequence are encoded by using the check matrix, so that the output coded code word can be
  • the terminal can quickly determine that the information is sent to itself when receiving the information, such as using the base station cell identification sequence and information. Sequence coding, when the terminal receives the information, it can quickly determine whether the message is the information sent by the cell that it needs to receive, and does not process the information sent by other cells, thereby improving the efficiency of information processing in the transmission process.
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, and a sequence for identifying a device group to which the sender device belongs. a sequence for identifying a device group to which the receiving device belongs, and a non-zero sequence of the transmitting device and the receiving device, wherein the transmitting device encodes the information sequence and the identification sequence.
  • the device, the receiving device is a device that receives a sequence of information and an identification sequence after encoding.
  • the identification sequence may be a wireless network temporary identifier, which facilitates the decoding end device to recognize the received information.
  • the physical cell identifier may also reduce inter-cell interference, so that the terminal can quickly determine whether the received information belongs to itself, reduce interference of information sent by other cells that does not belong to the terminal to the terminal, or may be a device group identifier. Thereby improving the identification of information in the entire group of devices.
  • the identifier sequence is repeatedly padded to an extra information bit position of the check matrix
  • the extra information bit positions of the check matrix are filled using an all 0 sequence or an all 1 sequence.
  • the recognition degree of the encoded code word can be further improved.
  • an embodiment of the present application provides a decoding method, which may include:
  • the size of the shift matrix is determined according to the following formula:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, and a sequence for identifying a device group to which the sender device belongs. a sequence for identifying a device group to which the receiving device belongs, and a non-zero sequence of the transmitting device and the receiving device, wherein the transmitting device encodes the information sequence and the identification sequence.
  • the device, the receiving device is a device that receives a sequence of information and an identification sequence after encoding.
  • an encoding apparatus which may include:
  • a determining unit configured to determine a size of the shift matrix according to a length of the information sequence and a length of the identification sequence
  • a constructing unit configured to construct a check matrix according to the size of the shift matrix and the base matrix
  • a coding unit configured to perform low-density parity check LDPC coding on the information sequence and the identification sequence based on the check matrix
  • the identification sequence is a non-zero sequence.
  • the determining unit is specifically configured to:
  • the size of the shift matrix is determined according to the following formula:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, and a sequence for identifying a device group to which the sender device belongs. a sequence for identifying a device group to which the receiving device belongs, and a non-zero sequence of the transmitting device and the receiving device, wherein the transmitting device encodes the information sequence and the identification sequence.
  • the device, the receiving device is a device that receives a sequence of information and an identification sequence after encoding.
  • the construction unit is further configured to:
  • the identification sequence is repeatedly padded to redundant information bit positions of the check matrix
  • the extra information bit positions of the check matrix are filled using an all 0 sequence or an all 1 sequence.
  • a fourth aspect of the embodiments of the present application provides an encoding apparatus, which may include:
  • a processor a memory, a transceiver, and a bus
  • the processor, the memory, and the transceiver are connected by a bus
  • the memory is configured to store a set of program codes
  • the transceiver is configured to send and receive information
  • the processor is configured to call
  • the program code stored in the memory performs the following operations:
  • the identification sequence is a non-zero sequence.
  • the processor is specifically configured to:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, and a sequence for identifying a device group to which the sender device belongs. a sequence for identifying a device group to which the receiving device belongs, and a non-zero sequence of the transmitting device and the receiving device, wherein the transmitting device encodes the information sequence and the identification sequence.
  • the device, the receiving device is a device that receives a sequence of information and an identification sequence after encoding.
  • the processor is further configured to:
  • the identification sequence is repeatedly padded to redundant information bit positions of the check matrix
  • the extra information bit positions of the check matrix are filled using an all 0 sequence or an all 1 sequence.
  • a fifth aspect of the embodiments of the present application is a decoding apparatus, which may include:
  • a determining unit configured to determine a size of the shift matrix according to a length of the information sequence and a length of the identification sequence
  • a constructing unit configured to construct a check matrix according to the size of the shift matrix and the base matrix
  • a decoding unit configured to perform low-density parity check LDPC decoding on the received data according to the check matrix, where the received data includes information of the identifier sequence and information of the information sequence .
  • the determining unit is specifically configured to:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, and a sequence for identifying a device group to which the sender device belongs. a sequence for identifying a device group to which the receiving device belongs, and a non-zero sequence of the transmitting device and the receiving device, wherein the transmitting device encodes the information sequence and the identification sequence.
  • the device, the receiving device is a device that receives a sequence of information and an identification sequence after encoding.
  • a sixth aspect of the embodiments of the present application provides a decoding apparatus, which may include:
  • a processor a memory, a transceiver, and a bus
  • the processor, the memory, and the transceiver are connected by a bus
  • the memory is configured to store a set of program codes
  • the transceiver is configured to send and receive information
  • the processor is configured to call
  • the program code stored in the memory performs the following operations:
  • the processor is specifically configured to:
  • the size of the shift matrix is determined according to the following formula:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, and a sequence for identifying a device group to which the sender device belongs. a sequence for identifying a device group to which the receiving device belongs, and a non-zero sequence of the transmitting device and the receiving device, wherein the transmitting device encodes the information sequence and the identification sequence.
  • the device, the receiving device is a device that receives a sequence of information and an identification sequence after encoding.
  • a seventh aspect of the embodiment of the present application discloses a base station, which may include:
  • the encoding device according to any one of the implementation manners of the third aspect of the present application, and/or the decoding device according to any implementation manner of the fifth aspect of the embodiment of the present application.
  • a terminal which may include:
  • the encoding device according to any one of the implementation manners of the third aspect of the present application, and/or the decoding device according to any implementation manner of the fifth aspect of the embodiment of the present application.
  • a ninth aspect is a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform any of the first aspect or any of the possible implementations of the first aspect The method in .
  • a tenth aspect is a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform any of the second or second aspects of the above-described possible implementations The method in .
  • An eleventh aspect provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of any of the first aspect or the first aspect of the first aspect.
  • a twelfth aspect provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of any of the second aspect or the second aspect of the second aspect.
  • FIG. 1 is a schematic structural diagram of a communication system according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an LDPC check matrix constructed based on a base matrix
  • FIG. 3 is a schematic flowchart of an encoding method provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of another coding method provided by an embodiment of the present application.
  • 5 is a performance test diagram for filling padding bits in a check matrix with different sequences and decoding using different sequences
  • FIG. 7 is a schematic flowchart of a decoding method provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an encoding apparatus according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another encoding apparatus according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another decoding apparatus according to an embodiment of the present application.
  • the QC-LDPC code not only has good performance close to the Shannon limit, but also has low decoding complexity and flexible structure. It is a research hotspot in the field of channel coding in recent years, and has been widely used in deep space communication, optical fiber communication, satellite digital video and audio. Broadcasting and other fields.
  • H For the QC-LDPC code, we can use H to represent the final m b ⁇ Z ⁇ n b ⁇ Z size check matrix, the form can be expressed as:
  • a ij is the shift factor of the shift matrix
  • n b and m b are the number of columns and the number of rows of the base matrix.
  • It is a shift matrix Z which can be obtained by cyclically shifting a ij to the unit matrix I.
  • a ij ranges from -1 ⁇ a ij ⁇ Z.
  • An all-zero matrix O of Z x Z can be defined as P -1 , where Z is the size of the shift matrix. If H is a full rank matrix, then (n b -m b ).
  • each information bit position in the extended LDPC check matrix is used to place information bits; if K is not divisible by k b , ⁇ k b >K, then there will be (Z ⁇ k b -K) redundant information bit positions in the extended LDPC check matrix, which can be called padding bits.
  • 0 is used to fill the excess information bit positions in the check matrix, that is, padding bits, which cannot play a greater role.
  • FIG. 1 is a schematic structural diagram of a communication system provided by an embodiment of the present application, where the communication system may include but is not limited to:
  • a base station and at least one terminal which may also be referred to as a User Equipment (UE).
  • UE User Equipment
  • the transmitting end device and the receiving end device in the embodiments of the present application may be any type of transmitting end device and receiving end device that perform data transmission in a wireless manner.
  • the transmitting device and the receiving device may be any device with wireless transceiver function, including but not limited to: base station NodeB, evolved base station eNodeB, base station in the fifth generation (5G) communication system, and future communication.
  • a base station or a network device in the system an access node in a WiFi system, a wireless relay node, a wireless backhaul node, and a user equipment (UE).
  • the UE may also be referred to as a terminal terminal, a mobile station (MS), a mobile terminal (MT), or the like.
  • the UE may communicate with one or more core networks via a radio access network (RAN), or may access the distributed network in an ad hoc or unlicensed manner, and the UE may also access the wireless network through other means.
  • RAN radio access network
  • the UE can also directly perform wireless communication with other UEs, which is not limited by the embodiment of the present application.
  • the sender device and the sink device in the embodiments of the present application may be deployed on land, including indoors or outdoors, handheld or on-board; or may be deployed on the water; or may be deployed on aircraft, balloons, and satellites in the air.
  • the UE in the embodiment of the present application may be a mobile phone, a tablet, a computer with a wireless transceiver function, a virtual reality (VR) terminal device, and an augmented reality (AR) terminal device.
  • wireless terminal in industrial control wireless terminal in self driving, wireless terminal in remote medical, wireless terminal in smart grid, transportation security Wireless terminal in safety), wireless terminal in smart city, wireless terminal in smart home, and the like.
  • the embodiment of the present application does not limit the application scenario.
  • the embodiments of the present application can be applied to downlink data transmission, and can also be applied to uplink data transmission, and can also be applied to device to device (D2D) data transmission.
  • D2D device to device
  • the transmitting device is a base station, and the corresponding receiving device is a UE.
  • the transmitting device is a UE, and the corresponding receiving device is a base station.
  • the transmitting device is a UE, and the corresponding receiving device is also a UE.
  • Both the transmitting device and the receiving device in the present application may include encoding means and/or decoding means, so that the information to be transmitted may be modulated and encoded, and the received encoded information may be demodulated and Decoding, implementing and transmitting information between the transmitting device and the receiving device.
  • the embodiment of the present application does not limit this.
  • FIG. 3 is an encoding method provided by an embodiment of the present application, where the encoding method is implemented based on a QC-LDPC code, including but not limited to the following steps:
  • the information sequence is converted by the sending end device to the data to be sent, and the obtained identity sequence of the binary sequence to be encoded is a non-zero sequence.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, a sequence for identifying a device group to which the sender device belongs, and identifier for receiving a sequence of the device group to which the end device belongs and a non-zero sequence of the signaling device and the receiving device, wherein the transmitting device is a device that encodes the information sequence and the identification sequence, The receiving device is a device that receives the sequence of information and the sequence of identifications including the encoding.
  • the identifier sequence may be a physical cell identity (PCI), or may be a radio network temporary identity (RNTI) of the terminal that receives the information sent by the base station, and may also be The identifier of the device group of the terminal that receives the information sent by the base station; when the device is the terminal, the identifier sequence may be the RNTI of the terminal, the RNTI of the peer device, or the base station that receives the information from the terminal.
  • the PCI can also be the identifier of the device group to which the terminal belongs.
  • the size of the shift matrix can be determined in conjunction with the basis matrix according to the capacity requirement. After determining the size of the shift matrix, the magnitude of the shift factor can be further determined.
  • the shift factor can be constructed according to an existing algorithm, such as determining the size of the shift factor according to the size of the shift matrix, and then cyclically shifting the base matrix according to the shift factor to obtain a check matrix or constructing together with other algorithms.
  • the example is not limited.
  • the shift factor can also be called the expansion factor.
  • the research of early LDPC codes mainly focuses on the performance field.
  • the constructed codewords often have high codec complexity and require large storage space, which limits their application in practical systems to some extent.
  • the appearance of the QC-LDPC code effectively reduces the codec complexity and requires only a small storage space.
  • the LDPC code can be directly produced by the check matrix, eliminating the intermediate process of obtaining the generator matrix, and further reducing the coding complexity.
  • the identification sequence may be repeatedly filled into The redundant information bit position of the check matrix; or the extra information bit position of the check matrix is filled using an all 0 sequence or an all 1 sequence.
  • the Gaussian elimination method or other methods can be used to convert H into a generator matrix G, and then use u .
  • G c to generate an encoded codeword, where u is the input information sequence and the identification sequence, c Is the codeword.
  • the check matrix in this embodiment is constructed based on the information sequence and the identifier sequence, the check matrix will contain information of the identifier sequence, and the check sequence is used to encode the information sequence and the identifier sequence, so that the output can be made.
  • the high degree of recognition of the coded codeword is beneficial to improve the target of information transmission in each scene and the efficiency of information processing in the transmission process.
  • the RNTI can be used as the identifier of the terminal, and the PCI can be used as the identifier of the base station cell.
  • the identifier sequence can also be a device group identification sequence.
  • the transmitting device for example, the base station sends the downlink information to the terminal, and the terminal sends the uplink information to the base station.
  • the identifier may include the identifier sequence of the sending device or the receiving end.
  • the identification sequence of the device is used to improve the identification of the coded codeword, which is not limited in any embodiment of the present application.
  • a device group identification sequence may be shared by multiple devices in the group.
  • the base station includes a device group identification sequence in the check matrix. If the devices in the group are aware of the identification sequence of other terminals in the group, When the base station sends information to the device group, the identification sequence of two or more devices in the group may also be included in an agreed order. Of course, for two or more terminals that are not in the group but are aware of other terminal identification sequences, The base station can also include the identification sequence of two or more terminals in the check matrix in the order of the check.
  • H is the check matrix
  • c is the decoded codeword
  • T is the transpose of the matrix.
  • interference between cells can be reduced, which facilitates the terminal to quickly determine whether the received information belongs to itself, and reduces interference of information sent by other cells that does not belong to the terminal to the terminal.
  • a specific identification sequence is placed in the check matrix. Conducive to speeding up the blind inspection process. If at the same time, there are potentially multiple users transmitting information on the same time-frequency resource, the comparison result of the Hc T can be determined at the decoding end to determine which users are possible users, thereby narrowing the target user range. If a user may place information in multiple locations, the information of multiple locations may be decoded, and only if the Hc T requirement is met, further decoding may be performed, which may also reduce the decoding delay.
  • URLLC ultra reliable & low latency communication
  • FIG. 4 is another encoding method provided by the embodiment of the present application. Steps S403-S404 in the encoding method are the same as S302-S303 in FIG. 3, and details are not described herein again.
  • the determining shift is specifically described.
  • the size of the matrix and the step of determining the size of the shift factor specifically include:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the matrix formed by the shift factor can be defined as
  • the magnitude of the shift factor can be calculated according to the following formula:
  • the magnitude of the shift factor can also be calculated according to the following formula:
  • t is the maximum shift matrix Z max corresponding basis matrix
  • I the check matrix corresponding to Z max
  • Check matrix The element values corresponding to the i-th row and the j-th column.
  • the check matrix can be constructed in conjunction with the base matrix.
  • a scheme of specifically determining the size of the shift matrix and two schemes for specifically determining the magnitude of the shift factor are given, since the length of the information sequence is based on determining the size of the shift matrix.
  • the lengths of the identification sequences are jointly determined, so that information in the check matrix constructed based on the shift factor corresponding to the shift matrix can accommodate the information sequence and the identification sequence.
  • simulation can be used to verify the performance of system encoding and decoding.
  • FIG. 5 is a performance test diagram for filling padding bits in a check matrix with different sequences and decoding using different sequences. If the 0 sequence padding can be used, the identification sequence padding in the embodiment of FIG. 3 and FIG. 4 can also be used.
  • the check matrix and the length of the information sequence and the length of the identification sequence in the embodiment are determined.
  • the check matrix constructed after the size of the shift matrix is the same.
  • the abscissa Es/No is the symbol signal to noise ratio, and the ordinate.
  • the circled curve is a commonly used scheme of filling with 0 sequence, using 0 sequence decoding, and the curve with asterisk is filled with the identification sequence such as RNTI or PCI, and the effect of decoding using the corresponding identification sequence is shown. It can be seen that the above two curves substantially coincide, that is, using the encoding method described in the embodiments of the present application does not cause any loss to system performance.
  • the curve with squares is a schematic diagram of the effect of decoding using the sequence of 0, and the block error rate and symbol signal-to-noise ratio are not ideal, and the system performance loss is large.
  • FIG. 6 is a performance test diagram before and after the padding bit of the check matrix is increased.
  • the check matrix constructed in the embodiment of FIG. 3 and FIG. 4 is the same as adding a padding bit to the existing check matrix and filling the identification sequence to form a check matrix.
  • the abscissa Es/No is the symbol signal to noise ratio, and the ordinate is the block error rate.
  • FIG. 7 is a decoding method provided by an embodiment of the present application, where the decoding method includes but is not limited to the following steps:
  • S701 Determine a size of the shift matrix according to the length of the information sequence and the length of the identification sequence.
  • the size of the shift matrix may be determined according to the following formula:
  • Z is a shift matrix size
  • K is the length of the information sequence
  • the number of columns and L is the length of sequence identity
  • n b is the basis matrix
  • B is the number of rows m of the base matrix.
  • S702 Construct a check matrix according to the size of the shift matrix and the base matrix.
  • S703 Perform low-density parity check LDPC decoding on the received data according to the check matrix.
  • the received data includes information of the identification sequence and information of the information sequence.
  • the soft information or the hard information corresponding to the identification sequence may be filled into a position corresponding to the padding bit in the check matrix, and then combined with the check matrix after the soft information or the hard information is filled. And iterative decoding is performed on the received information sequence filled with the soft information.
  • hard decoding uses hard decision
  • the demodulator receives the received according to its decision threshold.
  • the signal waveform is directly judged and output 0 or 1, that is, the demodulator supplies the decoder as each symbol for decoding, taking only 0 or 1 values, and decoding the Hamming distance between the sequences as a metric. Can be applied to binary symmetric channels.
  • soft decoding the soft decision method is used.
  • the demodulator does not perform the decision, directly outputs the analog quantity, or multi-level quantizes the demodulator output waveform (not a simple 0, 1 two-level quantization), and then Sent to the decoder, ie the output of the code channel is a "soft message" that has not been judged.
  • the soft decision decoder uses the Euclidean distance as the metric to decode.
  • the path metric of the soft decision decoding algorithm uses "soft distance” instead of Hamming distance. The most commonly used Euclidean distance is the reception.
  • the geometric distance between the waveform and the possible transmitted waveform is a decoding method suitable for discrete memoryless channels.
  • the hard decision is implemented by intercepting the sign bit of the demodulated quantized signal, which can be considered as one-level quantization, while the soft decision can be considered as multi-level quantization, including the high-order sign bit, and also contains the significant bits of the channel information.
  • the soft decision avoids the influence of misjudgment after demodulation and is directly sent to the decoder for decoding processing.
  • hard decision decoding is simpler and easier to implement than soft decision decoding.
  • soft decision decoding can increase the performance by 2 to 3 dB by making full use of the information of the channel output signal.
  • the received data may be decoded according to a message passing algorithms (MP) algorithm.
  • MP message passing algorithms
  • BP common error back propagation
  • belief propagation algorithm the belief propagation algorithm
  • minimum sum algorithm may be used for decoding.
  • the embodiment of the present application does not limit the present invention.
  • H is a check matrix
  • the size of the shift matrix corresponding to the check matrix is determined according to the length of the information sequence and the length of the identifier sequence
  • the identifier sequence is a non-zero sequence
  • c is a code obtained by decoding.
  • Word, T represents the transpose of the matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, a sequence for identifying a device group to which the sender device belongs, and identifier for receiving a sequence of the device group to which the end device belongs and a non-zero sequence of the signaling device and the receiving device, wherein the transmitting device is a device that encodes the information sequence and the identification sequence, The receiving device is a device that receives the sequence of information and the sequence of identifications including the encoding.
  • the identification sequence may be a wireless network temporary identification sequence, a physical layer cell identification sequence, or a device group identification sequence.
  • FIG. 8 is a schematic diagram of a composition of an encoding apparatus according to an embodiment of the present application.
  • the encoding apparatus may include a determining unit 100, a constructing unit 200, and an encoding unit 300. Among them, the detailed description of each unit is as follows.
  • a determining unit 100 configured to determine a size of the shift matrix according to a length of the information sequence and a length of the identification sequence
  • the constructing unit 200 is configured to construct a check matrix according to the size of the shift matrix and the base matrix;
  • the encoding unit 300 is configured to perform low-density parity check LDPC encoding on the information sequence and the identification sequence based on the check matrix;
  • the identification sequence is a non-zero sequence.
  • the determining unit 100 is specifically configured to:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the magnitude of the shift factor can be determined
  • the matrix formed by the shift factor is
  • H Z (a ij), where, H Z is a shift matrix of size Z ⁇ Z parity check matrix;
  • the magnitude of the shift factor is calculated according to the following formula:
  • the determining unit 100 may further determine the size of the shift factor according to the following manner:
  • the matrix formed by the shift factor is
  • the magnitude of the shift factor is calculated according to the following formula:
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, a sequence for identifying a device group to which the sender device belongs, and identifier for receiving a sequence of the device group to which the end device belongs and a non-zero sequence of the signaling device and the receiving device, wherein the transmitting device is a device that encodes the information sequence and the identification sequence, The receiving device is a device that receives the sequence of information and the sequence of identifications including the encoding.
  • the identifier sequence is a radio network temporary identifier sequence, a physical layer cell identifier sequence, or a device group identifier sequence.
  • the constructing unit 200 is further configured to:
  • the identification sequence is repeatedly padded to redundant information bit positions of the check matrix
  • the extra information bit positions of the check matrix are filled using an all 0 sequence or an all 1 sequence.
  • each unit may also correspond to the corresponding description of the method embodiments shown in FIG. 3 and FIG. 4 .
  • the encoding device in the embodiment of the present application may exist independently or may be integrated on a base station or a terminal.
  • FIG. 9 is a schematic diagram of another encoding apparatus provided by an embodiment of the present application.
  • the encoding apparatus may include a processor 110, a memory 120, a transceiver 130, and a bus 140.
  • the processor 110, the memory 120, and the transceiver 130 pass The bus 140 is connected, and a detailed description of each unit is as follows.
  • the memory 120 includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an Erasable Programmable Read Only Memory (EPROM), or A Compact Disc Read-Only Memory (CD-ROM) for storing a set of program codes and related data.
  • the transceiver 130 is configured to send and receive information.
  • the processor 110 may be one or more central processing units (CPUs).
  • CPUs central processing units
  • the CPU may be a single core CPU or a multi-core CPU.
  • the processor 110 in the encoding device is configured to read the program code stored in the memory 120, and perform the following operations:
  • the identification sequence is a non-zero sequence.
  • the processor 110 is specifically configured to:
  • Z is a shift matrix size
  • K is the length of the information sequence
  • the number of columns and L is the length of sequence identity
  • n b is the basis matrix
  • B is the number of rows m of the base matrix.
  • the magnitude of the shift factor can then also be determined in the following manner: the matrix formed by the shift factor is
  • the magnitude of the shift factor is calculated according to the following formula:
  • the matrix formed by the shift factor is
  • the magnitude of the shift factor is calculated according to the following formula:
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, a sequence for identifying a device group to which the sender device belongs, and identifier for receiving a sequence of the device group to which the end device belongs and a non-zero sequence of the signaling device and the receiving device, wherein the transmitting device is a device that encodes the information sequence and the identification sequence, The receiving device is a device that receives the sequence of information and the sequence of identifications including the encoding.
  • the identifier sequence is a radio network temporary identifier sequence, a physical layer cell identifier sequence, or a device group identifier sequence.
  • the processor 110 is further configured to:
  • the identification sequence is repeatedly padded to redundant information bit positions of the check matrix
  • the extra information bit positions of the check matrix are filled using an all 0 sequence or an all 1 sequence.
  • each operation may also correspond to the corresponding description of the method embodiments shown in FIG. 3 and FIG.
  • FIG. 10 is a schematic diagram of a composition of a decoding apparatus according to an embodiment of the present disclosure, where the decoding apparatus may include:
  • a determining unit 400 configured to determine a size of the shift matrix according to a length of the information sequence and a length of the identification sequence
  • the constructing unit 500 is configured to construct a check matrix according to the size of the shift matrix and the base matrix;
  • the decoding unit 600 is configured to perform low-density parity check LDPC decoding on the received data according to the check matrix, where the received data includes information of the identifier sequence and the information sequence. information.
  • the determining unit 400 is specifically configured to:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, a sequence for identifying a device group to which the sender device belongs, and identifier for receiving a sequence of the device group to which the end device belongs and a non-zero sequence of the signaling device and the receiving device, wherein the transmitting device is a device that encodes the information sequence and the identification sequence, The receiving device is a device that receives the sequence of information and the sequence of identifications including the encoding.
  • the identifier sequence is a radio network temporary identifier sequence, a physical layer cell identifier sequence, or a device group identifier sequence.
  • each unit may also correspond to the corresponding description of the method embodiment shown in FIG. 7 .
  • the decoding device in the embodiment of the present application exists independently, and may also be integrated on a base station or a terminal.
  • the decoding apparatus may include a processor 210, a memory 220, a transceiver 230, and a bus 240.
  • the processor 210, the memory 220, and the transceiver 230 is connected by a bus 240, wherein a detailed description of each unit is as follows.
  • the memory 220 includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an Erasable Programmable Read Only Memory (EPROM), or A Compact Disc Read-Only Memory (CD-ROM) for storing a set of program codes and related data.
  • the transceiver 230 is configured to send and receive information.
  • the processor 210 may be one or more central processing units (CPUs). In the case where the processor 210 is a CPU, the CPU may be a single core CPU or a multi-core CPU.
  • the processor 210 in the encoding device is configured to read the program code stored in the memory 220, and perform the following operations:
  • the processor 210 is specifically configured to:
  • the size of the shift matrix is determined according to the following formula:
  • K is the length of the information sequence
  • L is the length of the identification sequence
  • n b is the number of columns of the base matrix
  • m b is the number of rows of the base matrix.
  • the identifier sequence is one of the following sequence: a sequence for identifying a sender device, a sequence for identifying a receiver device, a sequence for identifying a device group to which the sender device belongs, and identifier for receiving a sequence of the device group to which the end device belongs and a non-zero sequence of the signaling device and the receiving device, wherein the transmitting device is a device that encodes the information sequence and the identification sequence, The receiving device is a device that receives the sequence of information and the sequence of identifications including the encoding.
  • the identifier sequence is a radio network temporary identifier sequence, a physical layer cell identifier sequence, or a device group identifier sequence.
  • each operation may also correspond to the corresponding description of the method embodiment shown in FIG. 7.
  • An embodiment of the present application also discloses a base station comprising an encoding device as shown in FIG. 8 and/or a decoding device as shown in FIG.
  • Embodiments of the present application also disclose a terminal including an encoding device as shown in FIG. 8 and/or a decoding device as shown in FIG.
  • the configuration may be performed according to the existing algorithm.
  • the base matrix is cyclically shifted according to the shift factor to obtain the first check matrix or is combined with other algorithms.
  • the embodiment of the present application does not limit the present invention.
  • the shift factor can also be called the expansion factor.
  • the research of early LDPC codes mainly focuses on the performance field.
  • the constructed codewords often have high codec complexity and require large storage space, which limits their application in practical systems to some extent.
  • the appearance of the QC-LDPC code effectively reduces the codec complexity and requires only a small storage space.
  • the LDPC code can be directly produced by the check matrix, eliminating the intermediate process of obtaining the generator matrix, and further reducing the coding complexity.
  • the length of the padding bits in the second check matrix is greater than or equal to the length of the identification sequence.
  • the first check matrix without the padding bits may be extended to obtain a second check matrix including padding bits.
  • the padding bit of the second check matrix when the first check matrix is extended, it may be performed according to the length of the identifier sequence, thereby ensuring the length of the padding bit in the second check matrix obtained by the extension. Greater than or equal to the length of the identification sequence.
  • the identifier sequence is used to indicate identity information of the device group to which the sender device, the receiver device, or the device to which the sender device belongs.
  • the identification sequence here is a sequence or a known sequence set known to both the source device and the receiver device.
  • the identification sequence may be an RNTI sequence, a PCI sequence, or a device group identity (GI) sequence.
  • the RNTI can be used as the identifier of the terminal, and the PCI can be used as the identifier of the base station cell.
  • the identifier sequence can also be a device group identification sequence.
  • the base station sends the downlink information to the terminal, and the terminal sends the uplink information to the base station.
  • the identifier may be filled in the check matrix with the identifier sequence of the sending device or the receiving end.
  • the identification sequence of the device is used to improve the identification of the coded codeword, which is not limited in any embodiment of the present application.
  • a device group identification sequence can be shared by multiple devices in the group.
  • the base station fills the device group identification sequence in the check matrix. If the devices in the group know the identification sequence of other terminals in the group, When the base station sends information to the device group, the identification sequence of two or more devices in the group may also be filled in an agreed order.
  • the base station can also fill the identification sequence of two or more terminals in the check matrix in the agreed order.
  • S130 Encode the input information bits according to the second check matrix, and output the information bits.
  • H is the check matrix
  • c is the decoded codeword
  • T is the transpose of the matrix.
  • a second check matrix including padding bits and a padding bit length greater than the length of the identification sequence is obtained, and then the flag sequence is padded to the second check.
  • the padding bits of the matrix are such that the padding bits are included in the second check matrix and can accommodate the identification sequence; when the input information bits are encoded according to the second parity matrix, the identification of the coded codewords can be increased, which facilitates decoding.
  • the end device identifies the received information.
  • the steps S210-S220 are the same as the S110-S120, and the steps S240-S250 are the same as the S130-S140 in FIG. 3, and are not described here.
  • the method further includes the following steps:
  • S230 If there is a padding bit in the first check matrix, compare a length of the padding bit in the first check matrix with a length of the identifier sequence; if the length of the padding bit in the first check matrix is smaller than The length of the identification sequence is extended according to the length of the identification sequence to obtain a second parity check matrix including padding bits.
  • the first check matrix may not have padding bits, there may be padding bits.
  • the length of the padding bits in the first check matrix and the length of the identification sequence may be compared first. If the length of the first check matrix padding bit is greater than or equal to the length of the identification sequence, a complete identification sequence may be padded to the position of the first check matrix padding bit, thereby improving the identification of the coded codeword; If the length of the check matrix padding bit is smaller than the length of the identifier sequence, the padding bits of the first check matrix need to be extended, and the length of the identifier sequence may be referred to when expanding.
  • the first check matrix when the first check matrix is extended according to the length of the identifier sequence to obtain a second check matrix including padding bits, the first check matrix may be extended by using the following method:
  • n is an integer greater than 1;
  • n and m can be determined based on the length of the identification sequence.
  • the length K of the information sequence in the current first check matrix is 1600
  • v of the RNTI sequence is 50, which is greater than 32
  • Z is incremented by 1 to obtain a padding bit, and a complete RNTI sequence cannot be filled.
  • Z+2 can be obtained as 52, and then extended to obtain 64 padding bits to be filled.
  • RNTI sequence For a check matrix with padding bits but whose length is smaller than RNTI, the above method can also be used for extension.
  • two cases in which the first check matrix needs to be expanded are mainly described, that is, there is no padding bit and there is a padding bit but the length thereof is smaller than the length of the identification sequence.
  • a specific extension method is provided to extend the padding bits of the first check matrix to obtain a second check matrix, and the length of the padding bits is greater than or equal to the length of the identifier sequence, and finally the identifier sequence is implemented.
  • the purpose of filling the padding bits of the second parity check matrix improves the recognition of the coded codewords.
  • the identifier sequence may be repeatedly padded to the remaining padding bits of the second check matrix.
  • the length of the padding bit of the second check matrix is greater than or equal to the length of the identifier sequence, if the length of the padding bit of the second check matrix is greater than the length of the identifier sequence, there may be redundant padding bits, and the identifier sequence may be The filling is repeated repeatedly into the remaining padding bits. For example, if the padding bit length is 32 and the RNTI sequence length is 30, after filling 30, the remaining 2 padding bit positions can be filled with the first 2 bits of the RNTI sequence.
  • the RNTI sequence is a sequence known to both the transmitting device and the receiving device, and both know the length of the padding bit and the RNTI sequence, the receiving device can know even if it cannot fill a number of complete RNTI sequences. Which corresponding sequence is used to fill the check matrix and complete the check. Moreover, the more the known sequence information is filled at the transmitting end, the more advantageous it is to increase the recognition degree of the encoded codeword.
  • the remaining padding bits of the second check matrix may be filled with the 0 sequence, except that the padding bit is filled in the manner of the padding.
  • simulation can also be used to verify the performance of the system encoding and decoding.
  • FIG. 6 is a performance test diagram for filling padding bits in a check matrix with different sequences and decoding with different sequences.
  • the abscissa Es/No is the symbol signal to noise ratio, and the ordinate.
  • the circled curve is a commonly used scheme of filling with 0 sequence, using 0 sequence decoding, and the curve with asterisk is filled with the identification sequence such as RNTI or PCI, and the effect of decoding using the corresponding identification sequence is shown. It can be seen that the above two curves substantially coincide, that is, using the encoding method described in the embodiments of the present application does not cause any loss to system performance.
  • the curve with squares is a schematic diagram of the effect of decoding using the sequence of 0, and the block error rate and symbol signal-to-noise ratio are not ideal, and the system performance loss is large.
  • FIG. 7 is a performance test diagram before and after the padding bit of the check matrix is increased.
  • the length K of the information sequence is 1600
  • the abscissa Es/No is the symbol signal to noise ratio
  • the ordinate is the block error rate.
  • the encoding device introduced in this embodiment may be used to implement some or all of the processes in the method embodiments introduced in conjunction with FIG. 3 and FIG. 4, and perform some or all of the functions in the device embodiment introduced in conjunction with FIG.
  • the decoding device introduced in this embodiment may be used to implement some or all of the processes in the method embodiment introduced in conjunction with FIG. 7 in this application, and perform some or all of the functions in the device embodiment introduced in conjunction with FIG. I will not repeat them here.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

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Abstract

本申请实施例公开了一种编码方法、编码装置、译码方法和译码装置，编码方法包括：根据信息序列的长度和标识序列的长度确定移位矩阵的大小；根据所述移位矩阵的大小和基矩阵构造校验矩阵；基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；其中，所述标识序列为非全零序列。采用本申请实施例，可扩展LDPC校验矩阵的功能，提升编码码字的辨识度。

Description

一种编码方法、译码方法、编码装置及译码装置 技术领域
本申请涉及通信技术领域，尤其涉及一种编码方法、解码方法、编码装置及解码装置。
背景技术
低密度奇偶校验(Low Density Parity Check，LDPC)码，是由Robert G.Gallager博士于1963年提出的一类具有稀疏校验矩阵的线性分组码，不仅有逼近香农限的良好性能，而且译码复杂度较低,结构灵活，是近年信道编码领域的研究热点，目前已广泛应用于深空通信、光纤通信、卫星数字视频和音频广播等领域。且在第五代(the fifth generation，5G)移动通信系统中增强型移动宽带(Enhance Mobile Broadband，eMBB)业务的数据信道的编码有良好应用。而其中基于基矩阵(base graph)构造的准循环低密度奇偶校验(Quasi-CyclicLow Density Parity Check，QC-LDPC)码对应的校验矩阵具有描述简单，易于构造等优点。这种矩阵的一个通用的形式如图2所示，图2为基于基矩阵构建的LDPC校验矩阵示意图，其中，图中的网格部分为填充比特(padding bits)的位置。在现有技术中，通常用0来填充这些多余的信息比特位置即图纸的网格部分，这就是所谓的zero-padding方法。接收端译码时，用0(如果采用硬译码)或者0对应的软值(如果采用软译码)填充到对应的位置进行译码。这样没有充分发挥多余信息比特即填充比特的作用。
发明内容
本申请实施例所要解决的技术问题在于，提供一种编码方法、编码装置、解码方法及解码装置，实现了LDPC校验矩阵的功能扩展。
第一方面，本申请的实施例提供了一种基于编码方法，可包括：
根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
根据所述移位矩阵的大小和基矩阵构造校验矩阵；
基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；
其中，所述标识序列为非全零序列。
由于校验矩阵是基于信息序列和标识序列构造的，因此，该校验矩阵中将包含标识序列的信息，使用该校验矩阵对信息序列和标识序列进行编码，可以使得输出的编码码字中含有标识序列的信息，接收端设备的译码时，更容易识别编码码字对应的信息是否为发送给该接收端设备的信息，从而使得编码码字的辨识度较高，利于提升各个场景下信息传输的目标性以及传输过程中信息处理的效率，如使用终端标识序列和信息序列编码，该终端在接收到信息时可快速确定该信息是发送给自己的，如使用基站小区标识序列和信息序列编码，终端在接收到信息时，可快速确定该消息是否是自己需要接收的小区发送的信息，不再对其他小区发送的信息进行处理，从而提高传输过程中信息处理的效率。
在一种可能的实现方式中，所述移位矩阵的大小根据如下公式确定：Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基 矩阵的列数，m b为所述基矩阵的行数。
在一种可能的实现方式中，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
标识序列可以是无线网络临时标识，利于译码端设备识别接收到的信息。也可以是物理小区标识可以降低小区间的干扰，利于终端快速确定接收到的信息是否属于自己，减少其他小区发送的不属于该终端的信息对该终端的干扰，或者还可以是设备组标识，从而提升整个组内设备对信息的辨识度。
在一种可能的实现方式中，当所述校验矩阵存在多余信息比特位置时，将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者
使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
当使用标识序列重复填充多余信息比特位置时，可进一步提升编码码字的辨识度。
第二方面，本申请的实施例提供了一种译码方法，可包括：
根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
根据所述移位矩阵的大小和基矩阵构造校验矩阵；
根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码，其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
在一种可能的实现方式中，所述移位矩阵的大小根据如下公式确定：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
在一种可能的实现方式中，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
第三方面，本申请的实施例提供了一种编码装置，可包括：
确定单元，用于根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
构造单元，用于根据所述移位矩阵的大小和基矩阵构造校验矩阵；
编码单元，用于基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；
其中，所述标识序列为非全零序列。
在一种可能的实现方式中，所述确定单元具体用于：
根据如下公式确定所述移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基 矩阵的列数，m b为所述基矩阵的行数。
在一种可能的实现方式中，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
在一种可能的实现方式中，所述构造单元还用于：
当所述校验矩阵存在多余信息比特位置时，将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者
使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
本申请的实施例第四方面提供了一种编码装置，可包括：
处理器、存储器、收发器和总线，所述处理器、存储器、收发器通过总线连接，其中，所述存储器用于存储一组程序代码，所述收发器用于收发信息，所述处理器用于调用所述存储器中存储的程序代码，执行以下操作：
根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
根据所述移位矩阵的大小和基矩阵构造校验矩阵；
基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；
其中，所述标识序列为非全零序列。
在一种可能的实现方式中，所述处理器具体用于：
根据如下公式计算移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
在一种可能的实现方式中，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
在一种可能的实现方式中，所述处理器还用于：
当所述校验矩阵存在多余信息比特位置时，将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者
使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
本申请的实施例第五方面了一种译码装置，可包括：
确定单元，用于根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
构造单元，用于根据所述移位矩阵的大小和基矩阵构造校验矩阵；
译码单元，用于根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码，其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
在一种可能的实现方式中，所述确定单元具体用于：
根据如下公式确定移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
在一种可能的实现方式中，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
本申请的实施例第六方面提供了一种译码装置，可包括：
处理器、存储器、收发器和总线，所述处理器、存储器、收发器通过总线连接，其中，所述存储器用于存储一组程序代码，所述收发器用于收发信息，所述处理器用于调用所述存储器中存储的程序代码，执行以下操作：
根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
根据所述移位矩阵的大小和基矩阵构造校验矩阵；
根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码，其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
在一种可能的实现方式中，所述处理器具体用于：
根据如下公式确定所述移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
在一种可能的实现方式中，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
本申请的实施例第七方面公开了一种基站，可包括：
如本申请的实施例第三方面任一实现方式所述的编码装置和/或如本申请的实施例第五方面任一实现方式所述的译码装置。
本申请的实施例第八方面公开了一种终端，可包括：
如本申请的实施例第三方面任一实现方式所述的编码装置和/或如本申请的实施例第五方面任一实现方式所述的译码装置。
第九方面供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面或第一方面的任意可能的实现方式中的方法。
第十方面供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第二方面或第二方面的任意可能的实现方式中 的方法。
第十一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面或第一方面的任意可能的实现方式中的方法。
第十二方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第二方面或第二方面的任意可能的实现方式中的方法。
附图说明
为了更清楚地说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1本申请实施例提供的一种通信系统架构示意图；
图2是基于基矩阵构建的LDPC校验矩阵示意图；
图3是本申请实施例提供的一种编码方法的流程示意图；
图4是本申请实施例提供的另一种编码方法的流程示意图；
图5是采用不同序列填充校验矩阵中填充比特并采用不同序列进行译码的性能测试图；
图6是校验矩阵的填充比特增加前后的性能测试图；
图7是本申请实施例提供的一种译码方法的流程示意图；
图8是本申请实施例提供的一种编码装置的组成示意图；
图9是本申请实施例提供的另一种编码装置的组成示意图；
图10是本申请实施例提供的一种译码装置的组成示意图；
图11是本申请实施例提供的另一种译码装置的组成示意图。
具体实施方式
随着通信技术的不断发展，业务规模、消息数量和终端数量飞速增长，在未来5G通信系统或更高级别的通信系统中，消息的辨识度将变得越来越重要，其可以提高信息发送的目的性，并提升信息传输过程中对信息处理的效率。QC-LDPC码不仅有逼近香农限的良好性能，而且译码复杂度较低，结构灵活，是近年信道编码领域的研究热点，目前已广泛应用于深空通信、光纤通信、卫星数字视频和音频广播等领域。对于QC-LDPC码，我们可以用H表示最终的m b·Z×n b·Z大小的校验矩阵，其形式可以表述为：
Figure PCTCN2018074026-appb-000001
其中a ij是移位矩阵的移位因子,n b和m b是基矩阵的列数和行数。
Figure PCTCN2018074026-appb-000002
是移位矩阵Z，可以通过对单位矩阵I循环移位a ij得到。其中a ij的范围是-1≤a ij<Z。可定义Z×Z的全零矩阵O为P -1，其中Z为移位矩阵的大小。如果H是满秩矩阵,则可以在基矩阵上(n b-m b)列放(n b-m b).Z个信息比特。我们称这k b＝(n b-m b)的基矩阵列为信息列。采用QC-LDPC码时，如果信息序列的长度K被k b整除，那么在扩展后的LDPC校验矩阵中每一个信息比特位置都用来放置信息比特；如果K不被k b整除，导致Z·k b>K，那么在扩展后LDPC校 验矩阵中会有(Z·k b-K)的多余信息比特位置，可称为填充比特。在构造QC-LDPC码的校验矩阵中，通常使用0来填充校验矩阵中多余的信息比特位置即填充比特(padding bits)，无法发挥其更大的作用。
下面结合本申请实施例中的附图对本申请的实施例进行描述。本申请的说明书和权利要求书及上述附图中的术语“第一”和“第二”等是用于区别不同对象，而非用于描述特定顺序。此外，“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
图1是本申请实施例提供的一种通信系统架构示意图，该通信系统可以包括但不限于：
基站和至少一个终端，终端也可称之为用户设备(User Equipment，UE)。
本申请各实施例中的发送端设备和接收端设备可以为以无线方式进行数据传输的任意一种发送端的设备和接收端的设备。发送端设备和接收端设备可以是任意一种具有无线收发功能的设备，包括但不限于：基站NodeB、演进型基站eNodeB、第五代(the fifth generation，5G)通信系统中的基站、未来通信系统中的基站或网络设备、WiFi系统中的接入节点、无线中继节点、无线回传节点以及用户设备(user equipment，UE)。其中，UE也可以称之为终端Terminal、移动台(mobile station，MS)、移动终端(mobile terminal，MT)等。UE可以经无线接入网(radio access network，RAN)与一个或多个核心网进行通信，或者可以通过自组织或免授权的方式接入分布式网络，UE还可以通过其它方式接入无线网络进行通信，UE也可以与其它UE直接进行无线通信，本申请的实施例对此不作限定。
本申请的实施例中的发送端设备和接收端设备可以部署在陆地上，包括室内或室外、手持或车载；也可以部署在水面上；还可以部署在空中的飞机、气球和卫星上。本申请的实施例中的UE可以是手机(mobile phone)、平板电脑(Pad)、带无线收发功能的电脑、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等等。本申请的实施例对应用场景不做限定。
本申请的实施例可以适用于下行数据传输，也可以适用于上行数据传输，还可以适用于设备到设备(device to device，D2D)的数据传输。对于下行数据传输，发送设备是基站，对应的接收设备是UE。对于上行数据传输，发送设备是UE，对应的接收设备是基站。对于D2D的数据传输，发送设备是UE，对应的接收设备也是UE。本申请中的发送端设备和接收端设备都可以包括编码装置和/或译码装置，从而可以对需要发送出去的信息进行调制和编码，也还可以对接收到的已编码信息进行解调和译码，实现和发送端设备和接收端设备之间的信息传输。本申请的实施例对此不做限定。
图3是本申请实施例提供的一种编码方法，该编码方法基于QC-LDPC码实现，包括但不限于如下步骤：
S301，根据信息序列的长度和标识序列的长度确定移位矩阵的大小。
其中，信息序列是由发送端设备对准备发送的数据进行转化，得到的待编码的二进制序列所述标识序列为非全零序列。
可选地，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
例如，当发送端设备为基站时，标识序列可以为物理小区标识(physicalcell identity，PCI)，也可以为接收该基站发送信息的终端的无线网络临时标识(radio network temporary identity，RNTI)，还可以为接收该基站发送信息的终端所述设备组的标识；当发送端设备为终端时，标识序列可以为终端的RNTI，也可以为对端设备的RNTI，还可以为接收该终端发送信息的基站的PCI，还可以为该终端所属设备组的标识。
当确定了信息序列的长度和标识序列的长度之后，便可以根据容量需要，结合基矩阵确定移位矩阵的大小。确定了移位矩阵的大小之后，便可以进一步确定移位因子的大小。
S302，根据所述移位矩阵的大小和基矩阵构造校验矩阵。
此处可以根据现有算法进行构造，如根据移位矩阵的大小确定移位因子的大小，然后将基矩阵根据移位因子进行循环移位得到校验矩阵或结合其他算法共同构造，本申请实施例不作任何限定。其中，移位因子也可以称为扩展因子。
早期LDPC码的研究主要集中在性能领域，构造出的码字往往具有较高的编解码复杂度且需要较大的存储空间，这在一定程度上限制了其在实际系统中的应用，近年来，QC-LDPC码的出现，有效降低了编解码复杂度并且只需要较小的存储空间。且通过将校验矩阵右半部设计为双对角线或三对角线形式，可以由校验矩阵直接生产LDPC码，省去了得到生成矩阵的中间过程，更进一步降低了编码复杂度。
可选地，当校验矩阵构造完成，在其信息比特的位置包含信息序列和标识序列的信息之后，可能还存在多余的信息比特即填充比特，此时，可以将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
S303，基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码。
当确定了校验矩阵H之后，可以利用高斯消元法或者其他方法把H转换成生成矩阵G，然后利用u .G＝c生成编码码字，其中u为输入的信息序列和标识序列，c为编码码字。
或者，还可以根据Hc T＝0,通过解线性方程组确定编码码字c中每一个编码比特的值。
由于本实施例中的校验矩阵是基于信息序列和标识序列构造的，因此，该校验矩阵中将包含标识序列的信息，使用该校验矩阵对信息序列和标识序列进行编码，可以使得输出的编码码字辨识度较高，利于提升各个场景下信息传输的目标性以及传输过程中信息处理的效率。
例如，RNTI可以作为终端的标识，PCI可以作为基站小区的标识，在一些基站针对多个终端组成的设备组发送信息时，标识序列还可以是设备组标识序列。且对于发送端设备 而言，例如基站发送下行信息给终端，终端发送上行信息给基站，终端与终端通信的场景中，既可以在校验矩阵中包含发送端设备的标识序列也可以包含接收端设备的标识序列来提升编码码字的辨识度，本申请实施例不作任何限定。对于一个组内的设备，也可以直接由组内多个设备共用一个设备组标识序列，基站在校验矩阵中包含设备组标识序列，如果该组内设备均知晓组内其他终端的标识序列，则在基站向该设备组发送信息时，也可以按照约定顺序包含组内2个或以上设备的标识序列，当然，对于不在组内，但相互知晓其他终端标识序列的2个或多个终端，基站同样可以在校验矩阵中按照约定的顺序包含2个或多个终端的标识序列。
当校验矩阵中包含了RNTI序列时，因此输出的编码码字将具有明显的辨识度，使得译码端设备在进行译码时，由于标识序列只有目标用户才知道，因此译码端设备可以通过Hc T＝0的校验方程的校验结果，更可靠的区分接收到的消息是否属于目标用户，利于译码端设备识别接收到的信息。其中，H为校验矩阵，c为译码得到的码字，T表示矩阵的转置。
当校验矩阵中包含了PCI序列时，可以降低小区间的干扰，利于终端快速确定接收到的信息是否属于自己，减少其他小区发送的不属于该终端的信息对该终端的干扰。
此外，对于一些需要进行盲检的场景如低时延高可靠通信(ultra reliable&low latency communication，URLLC)或者免授权接入(grant-free)的场景中，放置特定的标识序列到校验矩阵中有利于加速盲检过程。如果同时潜在有多个用户在同一时频资源上发送信息，在译码端通过比较Hc T的校验结果可以判定有哪些用户是可能的用户，进而缩小目标用户范围。如果一个用户可能在多个位置放置信息，可以对多个位置的信息进行译码，只有满足Hc T要求的才会进一步译码，这样做还可以降低译码延迟。
图4是本申请实施例提供的另一种编码方法，该编码方法中步骤S403-S404与图3中S302-S303相同，此处不再赘述，在本实施例中，具体描述了确定移位矩阵的大小以及确定移位因子的大小的步骤，具体包括：
S401，根据(K+L)/(n b-m b)计算移位矩阵的大小Z。
具体在计算时，由于基矩阵的列数n b和基矩阵的行数m b已知，为了确保校验矩阵中可容纳信息序列和标识序列，因此可以根据(K+L)/(n b-m b)来确定移位矩阵的大小Z。
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
S402，根据预设算法计算所述移位因子的大小。
可以定义所述移位因子构成的矩阵为
Figure PCTCN2018074026-appb-000003
简写为E(H Z)＝(a ij),其中，H Z是移位矩阵大小为Z×Z的校验矩阵；
可选地，可以根据如下公式计算所述移位因子的大小：
Figure PCTCN2018074026-appb-000004
其中，
Figure PCTCN2018074026-appb-000005
表示最大的移位矩阵Z max对应的移位因子，mod表示取模运算。
需要说明的是，当a ij<0时，即a ij＝-1，此时移位矩阵P -1为零矩阵。
或者，还可以根据如下公式计算所述移位因子的大小：
Figure PCTCN2018074026-appb-000006
其中，t为最大的移位矩阵Z max对应的基矩阵，且
Figure PCTCN2018074026-appb-000007
Figure PCTCN2018074026-appb-000008
为Z max对应的校验矩阵，
Figure PCTCN2018074026-appb-000009
为校验矩阵
Figure PCTCN2018074026-appb-000010
第i行和第j列对应的元素值。
当移位因子的大小确定之后，便可以结合基矩阵构造校验矩阵。
在本实施例中，给出了具体地确定移位矩阵的大小的方案以及两种具体地确定移位因子的大小的方案，由于在确定移位矩阵的大小时，是基于信息序列的长度和标识序列的长度共同确定的，因此可以确保基于与移位矩阵对应的移位因子所构造的校验矩阵中可容纳下信息序列和标识序列的信息。
对于上述图3-图4实施例中所述的编码方法，可以采用仿真来验证系统编码和译码的性能。
具体请参见图5和图6，其中图5是采用不同序列填充校验矩阵中填充比特并采用不同序列进行译码的性能测试图。如可以使用0序列填充，也可以使用图3和图4实施例中的标识序列填充，当使用标识序列填充时，该校验矩阵和本实施例中基于信息序列的长度和标识序列的长度确定移位矩阵的大小后构造的校验矩阵相同。
如图5所示，信息序列的长度K即码长为1000，码率R＝1/3，校验矩阵中存在24个填充比特，图中横坐标Es/No为符号信噪比，纵坐标为误块率。带圆圈的曲线为常用的使用0序列填充，使用0序列译码的效果示意图，带星号的曲线为使用标识序列如RNTI或PCI等进行填充，使用对应的标识序列进行译码的效果示意图，可以看到，以上两条曲线基本重合，即使用本申请的实施例中所述的编码方法不会对系统性能造成任何损失。而带方块的曲线为使用0序列填充，使用标识序列进行译码的效果示意图，误块率和符号信噪比均不理想，系统性能损失较大。
图6为校验矩阵的填充比特增加前后的性能测试图，图3和图4的实施例中构造的校验矩阵与对现有校验矩阵增加填充比特并填充标识序列形成校验矩阵相同。
如图6所示，信息序列的长度K为1600，码率R＝1/3，移位矩阵的大小Z0＝50，信息列k b为1600/50＝32。此时不存在填充比特。图中横坐标Es/No为符号信噪比，纵坐标为误块率。当对Z0进行增大分别得到Z1＝51，Z2＝52之后，Z1对应的校验矩阵中存在32个填 充比特，Z2对应的校验矩阵中存在64个填充比特。图7中带圆圈的曲线为Z0＝50时的效果示意图，带星号的曲线为Z1＝51的效果示意图，带方框的曲线为Z2＝52的效果示意图，可以看到，以上三条曲线基本重合，并且Z值较大时，导致校验矩阵较大，生产的码字距离也较大，因此系统性能还稍好。
图7是本申请实施例提供的一种译码方法，该译码方法包括但不限于如下步骤：
S701：根据信息序列的长度和标识序列的长度确定移位矩阵的大小。
可选地，可以根据如下公式确定所述移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
S702：根据所述移位矩阵的大小和基矩阵构造校验矩阵。
以上，确定移位矩阵和构造校验矩阵的方法具体描述可参见图3所示实施例中的描述，此处不再赘述。
S703：根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码。
其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
在进行译码时，可以将所述标识序列对应的软信息或硬信息填充到所述校验矩阵中填充比特对应的位置，然后结合填充了所述软信息或硬信息之后的校验矩阵，以及填充了所述软信息的接收信息序列进行迭代译码。
此处使用不同类型的标识序列的信息如硬信息或软信息填充时，分别对应硬译码和软译码，硬译码时使用硬判决的方式，解调器根据其判决门限对接收到的信号波形直接进行判决后输出0或1，即解调器供给译码器作为译码用的每个码元只取0或1两个值，以序列之间的汉明距离作为度量进行译码，可适用于二进制对称信道。而软译码时使用软判决的方式，解调器不进行判决，直接输出模拟量，或是将解调器输出波形进行多电平量化(不是简单的0、1两电平量化)，然后送往译码器，即编码信道的输出是没有经过判决的“软信息”。软判决译码器以欧几里德距离作为度量进行译码，软判决译码算法的路径度量采用“软距离”而不是汉明距离，最常采用的是欧几里德距离，也就是接收波形与可能的发送波形之间的几何距离，是一种适合于离散无记忆信道的译码方法。
对于数字电路，硬判决的实现是通过截取解调量化信号的符号位，可以认为是一级量化，而软判决可认为多级量化，包括高位符号位在内，还含有信道信息的有效位。软判决避免了解调后误判影响，直接送入译码器进行译码处理。一般而言，硬判决译码较软判决译码简单而易于实现，但软判决译码由于充分利用了信道输出信号的信息，在性能上可增加2～3dB。
可选地，可以根据消息传递(message passing algorithms，MP)算法对接收到的数据进行译码。
当然，此处也可以选择常见的误差反向传播(error back propagation，BP)算法、置信传播算法或最小和算法等进行译码，本申请的实施例不作任何限定。
当译码的结果满足Hc T＝0的校验方程时，译码完成。
其中，H为校验矩阵，且所述校验矩阵对应的移位矩阵的大小根据信息序列的长度和标识序列的长度确定，所述标识序列为非全零序列，c为译码得到的码字，T表示矩阵的转置。
此处c是变化的，每迭代1次，c变化1次。
当然，除了满足校验方程后停止译码，也可以在采用消息传递算法时，达到最大迭代次数时停止译码。
可选地，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
例如，标识序列可以为无线网络临时标识序列、物理层小区标识序列或设备组标识序列。
上述详细阐述了本申请实施例的方法，下面阐述本申请实施例的装置。
图8是本申请实施例提供的一种编码装置的组成示意图，该编码装置可以包括确定单元100、构造单元200以及编码单元300。其中，各个单元的详细描述如下。
确定单元100，用于根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
构造单元200，用于根据所述移位矩阵的大小和基矩阵构造校验矩阵；
编码单元300，用于基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；
其中，所述标识序列为非全零序列。
可选地，所述确定单元100具体用于：
根据如下公式计算所述移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
当确定了移位矩阵的大小之后，可以确定移位因子的大小；
所述移位因子构成的矩阵为
Figure PCTCN2018074026-appb-000011
简写为E(H Z)＝(a ij),其中，H Z是移位矩阵大小为Z×Z的校验矩阵；
根据如下公式计算所述移位因子的大小：
Figure PCTCN2018074026-appb-000012
其中，
Figure PCTCN2018074026-appb-000013
表示最大的移位矩阵Z max对应的移位因子，mod表示取模运算。
可选地，所述确定单元100还可以根据如下方式确定移位因子的大小：
所述移位因子构成的矩阵为
Figure PCTCN2018074026-appb-000014
简写为E(H Z)＝(a ij),其中，H Z是移位矩阵大小为Z×Z的校验矩阵；
根据如下公式计算所述移位因子的大小：
Figure PCTCN2018074026-appb-000015
其中，t为最大的移位矩阵Z max对应的基矩阵，且
Figure PCTCN2018074026-appb-000016
Figure PCTCN2018074026-appb-000017
为Z max对应的校验矩阵，
Figure PCTCN2018074026-appb-000018
为校验矩阵
Figure PCTCN2018074026-appb-000019
第i行和第j列对应的元素值。
可选地，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
可选地，所述标识序列为无线网络临时标识序列、物理层小区标识序列或设备组标识序列。
可选地，所述构造单元200还用于：
当所述校验矩阵存在多余信息比特位置时，将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者
使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
需要说明的是，各个单元的实现还可以对应参照图3和图4所示的方法实施例的相应描述。
本申请的实施例中的编码装置可以独立存在，也可以集成在基站或终端上。
图9是本申请实施例提供的另一种编码装置的组成示意图，该编码装置可以包括处理器110、存储器120、收发器130和总线140，所述处理器110、存储器120、收发器130通过总线140连接，其中，各个单元的详细描述如下。
存储器120包括但不限于是随机存储记忆体(Random Access Memory，RAM)、只读存储器(Read-Only Memory，ROM)、可擦除可编程只读存储器(Erasable Programmable Read Only Memory，EPROM)、或便携式只读存储器(Compact Disc Read-Only Memory，CD-ROM)，该存储器120用于存储一组程序代码及相关数据。收发器130用于收发信息。
处理器110可以是一个或多个中央处理器(Central Processing Unit，CPU)，在处理器110是一个CPU的情况下，该CPU可以是单核CPU，也可以是多核CPU。
该编码装置中的处理器110用于读取所述存储器120中存储的程序代码，执行以下操作：
根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
根据所述移位矩阵的大小和基矩阵构造校验矩阵；
基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；
其中，所述标识序列为非全零序列。
可选地，所述处理器110具体用于：
根据如下公式计算所述移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
之后还可以根据以下方式确定移位因子的大小：所述移位因子构成的矩阵为
Figure PCTCN2018074026-appb-000020
简写为E(H Z)＝(a ij),其中，H Z是移位矩阵大小为Z×Z的校验矩阵；
根据如下公式计算所述移位因子的大小：
Figure PCTCN2018074026-appb-000021
其中，
Figure PCTCN2018074026-appb-000022
表示最大的移位矩阵Z max对应的移位因子，mod表示取模运算。
可选地，另一种确定移位因子的方式如下：
根据信息序列的长度K和标识序列的长度L确定移位矩阵的大小Z；
所述移位因子构成的矩阵为
Figure PCTCN2018074026-appb-000023
简写为E(H Z)＝(a ij),其中，H Z是移位矩阵大小为Z×Z的校验矩阵；
根据如下公式计算所述移位因子的大小：
Figure PCTCN2018074026-appb-000024
其中，t为最大的移位矩阵Z max对应的基矩阵，且
Figure PCTCN2018074026-appb-000025
Figure PCTCN2018074026-appb-000026
为Z max对应的校验矩阵，
Figure PCTCN2018074026-appb-000027
为校验矩阵
Figure PCTCN2018074026-appb-000028
第i行和第j列对应的元素值。
可选地，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
可选地，所述标识序列为无线网络临时标识序列、物理层小区标识序列或设备组标识序列。
所述处理器110还用于：
当所述校验矩阵存在多余信息比特位置时，将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者
使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
需要说明的是，各个操作的实现还可以对应参照图3和图4所示的方法实施例的相应描述。
图10是本申请实施例提供的一种译码装置的组成示意图，该译码装置可以包括：
确定单元400，用于根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
构造单元500，用于根据所述移位矩阵的大小和基矩阵构造校验矩阵；
译码单元600，用于根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码，其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
其中，所述确定单元400具体用于：
根据如下公式确定移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
可选地，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
可选地，所述标识序列为无线网络临时标识序列、物理层小区标识序列或设备组标识序列。
需要说明的是，各个单元的实现还可以对应参照图7所示的方法实施例的相应描述。
本申请的实施例中的译码装置独立存在，也可以集成在基站或终端上。
图11是本申请实施例提供的另一种译码装置的组成示意图，该译码装置可以包括处理器210、存储器220、收发器230和总线240，所述处理器210、存储器220、收发器230通过总线240连接，其中，各个单元的详细描述如下。
存储器220包括但不限于是随机存储记忆体(Random Access Memory，RAM)、只读 存储器(Read-Only Memory，ROM)、可擦除可编程只读存储器(Erasable Programmable Read Only Memory，EPROM)、或便携式只读存储器(Compact Disc Read-Only Memory，CD-ROM)，该存储器220用于存储一组程序代码及相关数据。收发器230用于收发信息。
处理器210可以是一个或多个中央处理器(Central Processing Unit，CPU)，在处理器210是一个CPU的情况下，该CPU可以是单核CPU，也可以是多核CPU。
该编码装置中的处理器210用于读取所述存储器220中存储的程序代码，执行以下操作：
根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
根据所述移位矩阵的大小和基矩阵构造校验矩阵；
根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码，其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
所述处理器210具体用于：
根据如下公式确定所述移位矩阵的大小：
Z＝(K+L)/(n b-m b)
其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
可选地，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
可选地，所述标识序列为无线网络临时标识序列、物理层小区标识序列或设备组标识序列。
需要说明的是，各个操作的实现还可以对应参照图7所示的方法实施例的相应描述。
本申请的实施例还公开了一种基站，包括如8所示的编码装置和/或图10所示的译码装置。
本申请的实施例还公开了一种终端，包括如8所示的编码装置和/或图10所示的译码装置。
当然，除了上述直接基于信息序列的长度和标识序列的长度来确定移位矩阵的大小并构造相应的校验矩阵之外，还可以通过对现有常规的校验矩阵进行改造，得到如图3-图4实施例中所述的校验矩阵。具体步骤描述如下：
S110：根据基矩阵和移位矩阵构造第一校验矩阵。
此处可以根据现有算法进行构造，如将基矩阵根据移位因子进行循环移位得到第一校验矩阵或结合其他算法共同构造，本申请实施例不作任何限定。其中，移位因子也可以称为扩展因子。
早期LDPC码的研究主要集中在性能领域，构造出的码字往往具有较高的编解码复杂度且需要较大的存储空间，这在一定程度上限制了其在实际系统中的应用，近年来， QC-LDPC码的出现，有效降低了编解码复杂度并且只需要较小的存储空间。且通过将校验矩阵右半部设计为双对角线或三对角线形式，可以由校验矩阵直接生产LDPC码，省去了得到生成矩阵的中间过程，更进一步降低了编码复杂度。
S120：若所述第一校验矩阵中不存在填充比特，则根据标识序列的长度对所述第一校验矩阵进行扩展，得到包括填充比特的第二校验矩阵。
具体地，所述第二校验矩阵中填充比特的长度大于或等于所述标识序列的长度。
当第一校验矩阵不存在填充比特时，则表示信息序列的长度K可以被信息列k b整除，此处，没有多余的信息比特位置。为了扩展现有校验矩阵的功能，提升编码码字的辨识度，在本实施例中，可以对不存在填充比特的第一校验矩阵进行扩展，得到包括填充比特的第二校验矩阵。
且为了第二校验矩阵的填充比特足够填充标识序列，在对第一校验矩阵进行扩展时，可以根据标识序列的长度来进行，从而确保扩展得到的第二校验矩阵中填充比特的长度大于或等于所述标识序列的长度。
其中，所述标识序列用于指示发送端设备、接收端设备或发送端设备所属设备组的身份信息。
需要说明的是，此处的标识序列是发送端设备和接收端设备均已知的序列或已知的序列集合。例如，所述标识序列可以为RNTI序列、PCI序列或设备组标识(group identity，GI)序列。RNTI可以作为终端的标识，PCI可以作为基站小区的标识，在一些基站针对多个终端组成的设备组发送信息时，标识序列还可以是设备组标识序列。且对于发送端设备而言，例如基站发送下行信息给终端，终端发送上行信息给基站，终端与终端通信的场景中，既可以在校验矩阵中填充发送端设备的标识序列也可以发送接收端设备的标识序列来提升编码码字的辨识度，本申请实施例不作任何限定。对于一个组内的设备，也可以直接由组内多个设备共用一个设备组标识序列，基站在校验矩阵中填充设备组标识序列，如果该组内设备均知晓组内其他终端的标识序列，则在基站向该设备组发送信息时，也可以按照约定顺序填充组内2个或以上设备的标识序列，当然，对于不在组内，但相互知晓其他终端标识序列的2个或多个终端，基站同样可以在校验矩阵中按照约定的顺序填充2个或多个终端的标识序列。
S130：根据所述第二校验矩阵对输入的信息比特进行编码后输出。
由于在第二校验矩阵中填充了标识序列，因此输出的编码码字将具有明显的辨识度，使得译码端设备在进行译码时，由于填充比特填充的具体序列只有目标用户才知道，因此译码端设备可以通过Hc T＝0的校验方程的校验结果，更可靠的区分接收到的消息是否属于目标用户。其中，H为校验矩阵，c为译码得到的码字，T表示矩阵的转置。
在该方法中，通过对不存在填充比特的第一校验矩阵进行扩展，从而得到包括填充比特且填充比特长度大于标识序列长度的第二校验矩阵，然后将标志序列填充到第二校验矩阵的填充比特，使得第二校验矩阵中必然包含填充比特且可容纳标识序列；当根据第二校验矩阵对输入的信息比特进行编码后，可以增加编码码字的辨识度，利于译码端设备识别接收到的信息。
具体扩展第一校验矩阵的方法可以参见如下实施例的描述：
该编码方法中步骤S210-S220与S110-S120相同，步骤S240-S250与图3中S130-S140相同，此处不再赘述，在本实施例中，还包括步骤：
S230：若所述第一校验矩阵中存在填充比特，则比较所述第一校验矩阵中填充比特的长度与标识序列的长度；若所述第一校验矩阵中填充比特的长度小于所述标识序列的长度，则根据标识序列的长度对所述第一校验矩阵进行扩展，得到包括填充比特的第二校验矩阵。
由于第一校验矩阵可能不存在填充比特，也可能存在填充比特，当存在填充比特的时候，可以先比较一下第一校验矩阵中填充比特的长度和标识序列的长度。如果第一校验矩阵填充比特的长度大于或等于标识序列的长度，则可以将一个完整的标识序列填充到第一校验矩阵填充比特的位置，从而提升编码码字的辨识度；如果第一校验矩阵填充比特的长度小于标识序列的长度，则需要对第一校验矩阵的填充比特进行扩展，在扩展时可以参考标识序列的长度。
可选地，在根据标识序列的长度对所述第一校验矩阵进行扩展，得到包括填充比特的第二校验矩阵时，可以采用以下方法对第一校验矩阵进行扩展：
将移位矩阵的大小增加n，根据所述基矩阵和增大后的移位矩阵构造包括填充比特的第二校验矩阵，其中，n为大于1的整数；或者
将所述移位矩阵的大小乘以m后向上取整或向下取整或进行四舍五入运算，根据所述基矩阵和增大后的移位因子构造包括填充比特的第二校验矩阵，其中，m大于1。
n和m的取值可以根据标识序列的长度来进行确定。
例如，当前第一校验矩阵中信息序列的长度K为1600，RNTI序列的长度v为30，信息列k b＝32，对应的移位矩阵的大小Z＝K/k b＝50，由于K被k b整除，因此第一校验矩阵中不存在填充比特即填充比特的长度u＝(Z·k b-K)＝0；此时可以对其第一移位矩阵进行扩展，例如将增大移位矩阵来增加填充比特的数量，新的移位矩阵Z′＝Z+1＝51，此时，填充比特的长度u＝(Z′·k b-K)＝51*32-1600＝32，大于RNTI的长度30，因此扩展后的第二校验矩阵满足需求，可以将标识序列填充到第二校验矩阵的填充比特。如果RNTI序列的长度v为50，大于32，则将Z加1进行扩展得到填充比特还无法填充一个完整的RNTI序列，此时可以将Z+2得到52，进而扩展得到64的填充比特来填充RNTI序列。而对于具备填充比特但其长度小于RNTI的校验矩阵，同样可以采用上述方法进行扩展。
当然，除了上述对Z进行增加n的方式来扩展之外，还可以对Z进行乘法后取整来扩展，例如Z＝50，可以将Z*1.05＝52.5，然后向下取整得到52来进行扩展，也可以将Z*1.025＝51.25向上取整得到52来扩展，也可以向下取整得到51来扩展，或者还可以对乘积结果进行四舍五入来进行扩展，本申请实施例不作任何限定。
在上述实施例中，重点描述了需要对第一校验矩阵需要进行扩展的两种情况，分别为不存在填充比特以及存在填充比特但其长度小于标识序列的长度，在这两种情况下，本实施例给出了具体的扩展方法来对第一校验矩阵的填充比特进行扩展，从而得到第二校验矩阵，且其填充比特的长度大于或等于标识序列的长度，最终实现将标识序列填充到第二校验矩阵的填充比特的目的，提升编码码字的辨识度。
由第一校验矩阵扩展后得到的第二校验矩阵中，可能存在多余的填充比特，此时可以将所述标识序列重复填充到所述第二校验矩阵的剩余填充比特。
由于第二校验矩阵填充比特的长度大于或等于标识序列的长度，在第二校验矩阵填充比特的长度大于标识序列的长度的情况下，会存在多余的填充比特，此时可以将标识序列连续地重复地填充到剩余的填充比特中。例如，填充比特长度为32，RNTI序列长度为30，则在填满30之后，可以再在剩余的2个填充比特位置填充RNTI序列的前2位。
且由于RNTI序列为发送端设备和接收端设备均已知的序列，且二者也知道填充比特和RNTI序列的长度，因此，即便无法填满若干个完整的RNTI序列，接收端设备也可以知道使用何种对应的序列来进行填充校验矩阵并完成校验。且在发送端填充的已知序列信息越多，越有利于增加编码码字的辨识度。
当然，除了使用标识序列重复填充的方式来填满填充比特之外，还可以使用0序列来填充第二校验矩阵的剩余填充比特，本申请实施例不作任何限定。
对于上述对第一校验矩阵扩展得到第二校验矩阵的实施例中所述的编码方法，同样可以采用仿真来验证系统编码和译码的性能。
具体请参见图5和图6，其中图6是采用不同序列填充校验矩阵中填充比特并采用不同序列进行译码的性能测试图。
如图6所示，信息序列的长度K即码长为1000，码率R＝1/3，校验矩阵中存在24个填充比特，图中横坐标Es/No为符号信噪比，纵坐标为误块率。带圆圈的曲线为常用的使用0序列填充，使用0序列译码的效果示意图，带星号的曲线为使用标识序列如RNTI或PCI等进行填充，使用对应的标识序列进行译码的效果示意图，可以看到，以上两条曲线基本重合，即使用本申请的实施例中所述的编码方法不会对系统性能造成任何损失。而带方块的曲线为使用0序列填充，使用标识序列进行译码的效果示意图，误块率和符号信噪比均不理想，系统性能损失较大。
图7为校验矩阵的填充比特增加前后的性能测试图，如图7所示，信息序列的长度K为1600，码率R＝1/3，Z0＝50，信息列k b为1600/50＝32。此时不存在填充比特。图中横坐标Es/No为符号信噪比，纵坐标为误块率。当对Z0进行增大分别得到Z1＝51，Z2＝52之后，Z1对应的校验矩阵中存在32个填充比特，Z2对应的校验矩阵中存在64个填充比特。图7中带圆圈的曲线为Z0＝50时的效果示意图，带星号的曲线为Z1＝51的效果示意图，带方框的曲线为Z2＝52的效果示意图，可以看到，以上三条曲线基本重合，并且Z值较大时，导致校验矩阵较大，生产的码字距离也较大，因此系统性能还稍好。
本实施例中介绍的编码装置可以用以实施本申请结合图3和图4介绍的方法实施例中的部分或全部流程，以及执行本申请结合图8介绍的装置实施例中的部分或全部功能，本实施例中介绍的译码装置可以用以实施本申请结合图7介绍的方法实施例中的部分或全部流程，以及执行本申请结合图10介绍的装置实施例中的部分或全部功能，在此不再赘述。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算 机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。“与A对应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种编码方法，其特征在于，包括：
    根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
    根据所述移位矩阵的大小和基矩阵构造校验矩阵；
    基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；
    其中，所述标识序列为非全零序列。
  2. 根据权利要求1所述的编码方法，其特征在于，所述移位矩阵的大小根据如下公式确定：
    Z＝(K+L)/(n b-m b)
    其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
  3. 根据权利要求1或2所述的编码方法，其特征在于，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
  4. 根据权利要求1-3任一项所述的编码方法，其特征在于，当所述校验矩阵存在多余信息比特位置时，将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者
    使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
  5. 一种译码方法，其特征在于，包括：
    根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
    根据所述移位矩阵的大小和基矩阵构造校验矩阵；
    根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码，其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
  6. 根据权利要求5所述的译码方法，其特征在于，所述移位矩阵的大小根据如下公式确定：
    Z＝(K+L)/(n b-m b)
    其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
  7. 根据权利要求5或6所述的译码方法，其特征在于，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所 属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
  8. 一种编码装置，其特征在于，包括：
    确定单元，用于根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
    构造单元，用于根据所述移位矩阵的大小和基矩阵构造校验矩阵；
    编码单元，用于基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；
    其中，所述标识序列为非全零序列。
  9. 根据权利要求8所述的编码装置，其特征在于，所述确定单元具体用于：
    根据如下公式确定所述移位矩阵的大小：
    Z＝(K+L)/(n b-m b)
    其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
  10. 根据权利要求8或9所述的编码装置，其特征在于，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
  11. 根据权利要求8-10任一项所述的编码装置，其特征在于，所述构造单元还用于：
    当所述校验矩阵存在多余信息比特位置时，将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者
    使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
  12. 一种编码装置，其特征在于，包括：
    处理器、存储器、收发器和总线，所述处理器、存储器、收发器通过总线连接，其中，所述存储器用于存储一组程序代码，所述收发器用于收发信息，所述处理器用于调用所述存储器中存储的程序代码，执行以下操作：
    根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
    根据所述移位矩阵的大小和基矩阵构造校验矩阵；
    基于所述校验矩阵对所述信息序列和标识序列进行低密度奇偶校验LDPC编码；
    其中，所述标识序列为非全零序列。
  13. 根据权利要求12所述的编码装置，其特征在于，所述处理器具体用于：
    根据如下公式计算移位矩阵的大小：
    Z＝(K+L)/(n b-m b)
    其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
  14. 根据权利要求12或13所述的编码装置，其特征在于，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
  15. 根据权利要求12-14任一项所述的编码装置，其特征在于，所述处理器还用于：
    当所述校验矩阵存在多余信息比特位置时，将所述标识序列重复填充到所述校验矩阵的多余信息比特位置；或者
    使用全0序列或全1序列填充到所述校验矩阵的多余信息比特位置。
  16. 一种译码装置，其特征在于，包括：
    确定单元，用于根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
    构造单元，用于根据所述移位矩阵的大小和基矩阵构造校验矩阵；
    译码单元，用于根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码，其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
  17. 根据权利要求16所述的译码装置，其特征在于，所述确定单元具体用于：
    根据如下公式确定移位矩阵的大小：
    Z＝(K+L)/(n b-m b)
    其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
  18. 根据权利要求16或17所述的译码装置，其特征在于，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
  19. 一种译码装置，其特征在于，包括：
    处理器、存储器、收发器和总线，所述处理器、存储器、收发器通过总线连接，其中，所述存储器用于存储一组程序代码，所述收发器用于收发信息，所述处理器用于调用所述存储器中存储的程序代码，执行以下操作：
    根据信息序列的长度和标识序列的长度确定移位矩阵的大小；
    根据所述移位矩阵的大小和基矩阵构造校验矩阵；
    根据所述校验矩阵对接收到的数据进行低密度奇偶校验LDPC译码，其中，所述接收到的数据中包括所述标识序列的信息和所述信息序列的信息。
  20. 根据权利要求19所述的译码装置，其特征在于，所述处理器具体用于：
    根据如下公式确定所述移位矩阵的大小：
    Z＝(K+L)/(n b-m b)
    其中，Z为移位矩阵的大小，K为信息序列的长度，L为标识序列的长度，n b为所述基矩阵的列数，m b为所述基矩阵的行数。
  21. 根据权利要求19或20所述的译码装置，其特征在于，所述标识序列为以下序列中的一种：用于标识发送端设备的序列、用于标识接收端设备的序列、用于标识发送端设备所属设备组的序列、用于标识接收端设备所属设备组的序列以及发送端设备和接收端设备通过信令约定的非全零序列，其中，所述发送端设备为对所述信息序列和所述标识序列进行编码的设备，所述接收端设备为接收包含有编码之后的信息序列和标识序列的设备。
  22. 一种基站，其特征在于，包括：
    根据权利要求8-11任一项所述的编码装置和/或根据权利要求16-18任一项所述的译码装置。
  23. 一种终端，其特征在于，包括：
    根据权利要求8-11任一项所述的编码装置和/或根据权利要求16-18任一项所述的译码装置。
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