WO2018107709A1 - 一种用于非冗余电源实现冗余的电路 - Google Patents

一种用于非冗余电源实现冗余的电路 Download PDF

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Publication number
WO2018107709A1
WO2018107709A1 PCT/CN2017/089288 CN2017089288W WO2018107709A1 WO 2018107709 A1 WO2018107709 A1 WO 2018107709A1 CN 2017089288 W CN2017089288 W CN 2017089288W WO 2018107709 A1 WO2018107709 A1 WO 2018107709A1
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power supply
circuit
capacitor
control chip
terminal
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PCT/CN2017/089288
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English (en)
French (fr)
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梁红涛
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威创集团股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations

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  • the present invention relates to the field of redundant power supplies, and more particularly to a circuit for implementing redundancy for a non-redundant power supply.
  • the function of the ATX power supply is to convert the AC 220V power to the DC 5V, 12V, 24V power supply used inside the computer. Compared with the AT power supply, the ATX power supply has increased "+3.3V, +5VSB, PS-ON.
  • Isolation redundancy means that one or more uninterruptible power supplies (UPS) are used as the first-level power protection device, and the other is used as the secondary power supply for standby use.
  • the primary power supplies have their own load buses, and the secondary power supplies provide bypass power to all primary power supplies.
  • the secondary power supply operates at no load during operation, but it is required to carry a load from 0% to 100% over a period of one cycle. When the primary power is switched from the mains mode to the bypass mode, the transfer switch automatically disconnects it from the secondary supply.
  • Embodiments of the present invention provide a circuit for implementing redundancy for a non-redundant power supply, which is used to solve the technical problem that the prior art cannot use a non-redundant ATX power supply in a system requiring redundancy.
  • Embodiments of the present invention provide a circuit for implementing redundancy for a non-redundant power supply, including: at least two isolation circuits and an output end;
  • the isolation circuit includes: a control chip having an ORING function; a MOS tube having the same number as the control chip; and an input terminal having the same number as the control chip;
  • the VDD end of the control chip is grounded through a first capacitor and connected to the input terminal through a first resistor;
  • the RSET terminal, the RSVD terminal, and the GND terminal of the control chip are grounded;
  • the BYP end of the control chip is connected to the input end through a second capacitor
  • the A terminal of the control chip is connected to the input terminal and connected to the output terminal through a third capacitor and grounded through a fourth capacitor;
  • the C terminal of the control chip is connected to the output end
  • the GATE end of the control chip is connected to the gate of the MOS transistor
  • a source of the MOS transistor is connected to the input end
  • the drain of the MOS transistor is connected to the output end
  • the source of the MOS transistor is connected to the anode of the first diode, and the drain of the MOS transistor is connected to the cathode of the first diode.
  • the isolation circuit further includes a second resistor
  • the RSET terminal of the control chip is grounded through the second resistor.
  • the input of the isolation circuit is grounded through a fifth capacitor.
  • the fifth capacitor is a storage capacitor.
  • the output is grounded through a sixth capacitor.
  • the sixth capacitor is a storage capacitor.
  • the isolation circuit is specifically two isolation circuits, and the two isolation circuits are connected by the drain of the MOS transistor.
  • the isolation circuit specifically includes a first isolation circuit and a second isolation circuit
  • the first isolation circuit includes: a first control chip U1 having an ORING function, a first MOS transistor MOS1, and a first input terminal VIN1;
  • the VDD end of the first control chip is grounded through a capacitor C3 and connected to the first input terminal through a resistor R1;
  • the RSET end, the RSVD end, and the GND end of the first control chip are grounded;
  • the BYP end of the first control chip is connected to the first input end through a capacitor C1;
  • the A terminal of the first control chip is connected to the first input terminal and connected to the output terminal through a capacitor C2 and grounded through a capacitor C4;
  • the C terminal of the first control chip is connected to the output end
  • the GATE end of the first control chip is connected to the gate of the first MOS transistor
  • the source of the first MOS transistor is connected to the first input end
  • the drain of the first MOS transistor is connected to the output end
  • the source of the first MOS transistor is connected to the anode of the first diode, and the drain of the first MOS transistor is connected to the cathode of the first diode;
  • the second isolation circuit includes: a second control chip U2 having an ORING function, a second MOS transistor MOS2, and a second input terminal VIN2;
  • the VDD terminal of the second control chip is grounded through a capacitor C7 and connected to the second input terminal through a resistor R4;
  • the RSET end, the RSVD end, and the GND end of the second control chip are grounded;
  • the BYP end of the second control chip is connected to the second input end through a capacitor C8;
  • the A terminal of the second control chip is connected to the second input terminal and connected to the output terminal through a capacitor C6 and grounded through a capacitor C5;
  • the C terminal of the second control chip is connected to the output end
  • the GATE end of the second control chip is connected to the gate of the second MOS transistor
  • a source of the second MOS transistor is connected to the second input end
  • the drain of the second MOS transistor is connected to the output end
  • the source of the second MOS transistor is connected to the anode of the second diode, and the drain of the second MOS transistor is connected to the cathode of the second diode.
  • the two isolation circuits further include a resistor R2 and a resistor R3;
  • the RSET end of the first control chip is specifically grounded through the R2;
  • the RSET end of the second control chip is specifically grounded through the R3.
  • the two isolation circuits further include a capacitor EC1, a capacitor EC2, a capacitor EC3, and a capacitor EC4;
  • the first input terminal is grounded through the capacitor EC1;
  • the output ends are grounded through the capacitor EC2 and the capacitor EC3, respectively;
  • the second input is grounded through the capacitor EC4.
  • the capacitor EC1, the capacitor EC2, the capacitor EC3, and the capacitor EC4 are specifically storage capacitors.
  • Embodiments of the present invention provide a system for implementing redundancy for a non-redundant power supply, including the above-mentioned circuit for implementing redundancy for a non-redundant power supply, and the same number of ATX power supplies as the isolation circuit;
  • the power output ends of the ATX power supply are respectively connected to the isolation circuit for outputting electrical energy through the isolation circuit.
  • the system further comprises an ATX power supply system
  • An output of the circuit for implementing redundancy for a non-redundant power supply is connected to the ATX power supply system;
  • the ATX power supply system is used to provide a power output to the load.
  • control chip with the ORING function controls to turn off or turn on the MOS tube with the same number of the control chip, thereby realizing redundancy of two or more power sources, and solving the problem that the prior art cannot replace the non-redundant ATX power supply. For technical problems in systems that require redundancy.
  • the embodiment of the present invention also stores and filters the input end and the output end through the storage capacitor.
  • a system for implementing redundancy for a non-redundant power supply uses an ATX power supply to pass through an isolation circuit, thereby outputting power, and supplies power to the load, thereby implementing redundant power supply of the non-redundant power supply.
  • FIG. 1 is a circuit diagram of an embodiment of a circuit for implementing redundancy for a non-redundant power supply according to an embodiment of the present invention
  • FIG. 2 is a circuit diagram of another embodiment of a circuit for implementing redundancy for a non-redundant power supply according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram of another embodiment of a circuit for implementing redundancy for a non-redundant power supply according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of an embodiment of a system for implementing redundancy for a non-redundant power supply according to an embodiment of the present invention.
  • Embodiments of the present invention provide a circuit for implementing redundancy for a non-redundant power supply, which is used to solve the technical problem that the prior art cannot use a non-redundant ATX power supply in a system requiring redundancy.
  • an embodiment of the present invention provides a schematic diagram of an embodiment of a circuit for implementing redundancy for a non-redundant power supply.
  • the circuit provided in this embodiment includes: at least two isolation circuits and an output end;
  • the isolation circuit includes: a control chip with an ORING function, a MOS tube having the same number of control chips, and an input terminal having the same number of control chips;
  • the VDD terminal of the control chip is grounded through the first capacitor and connected to the input terminal through the first resistor;
  • the RSET terminal, the RSVD terminal, and the GND terminal of the control chip are grounded;
  • the BYP end of the control chip is connected to the input terminal through the second capacitor
  • the A terminal of the control chip is connected to the input terminal and connected to the output terminal through the third capacitor and grounded through the fourth capacitor;
  • the C terminal of the control chip is connected to the output end
  • the GATE end of the control chip is connected to the gate of the MOS transistor
  • the source of the MOS transistor is connected to the input terminal;
  • the drain of the MOS transistor is connected to the output terminal
  • the source of the MOS transistor is connected to the anode of the first diode, and the drain of the MOS transistor is connected to the cathode of the first diode.
  • another embodiment of the present invention provides a circuit for implementing redundancy for a non-redundant power supply, including: at least two isolation circuits and an output terminal;
  • the isolation circuit includes: a control chip with an ORING function, a MOS tube having the same number of control chips, and an input terminal having the same number of control chips;
  • the VDD terminal of the control chip is grounded through the first capacitor and connected to the input terminal through the first resistor;
  • the RSET terminal, the RSVD terminal, and the GND terminal of the control chip are grounded;
  • the BYP end of the control chip is connected to the input terminal through the second capacitor
  • the A terminal of the control chip is connected to the input terminal and connected to the output terminal through the third capacitor and grounded through the fourth capacitor;
  • the C terminal of the control chip is connected to the output end
  • the GATE end of the control chip is connected to the gate of the MOS transistor
  • the source of the MOS transistor is connected to the input terminal;
  • the drain of the MOS transistor is connected to the output terminal
  • the source of the MOS transistor is connected to the anode of the first diode, and the drain of the MOS transistor is connected to the cathode of the first diode.
  • the isolation circuit further includes a second resistor
  • the RSET terminal of the control chip is grounded through a second resistor.
  • the input of the isolation circuit is grounded through a fifth capacitor.
  • the fifth capacitor is a storage capacitor.
  • the output is grounded through a sixth capacitor.
  • the sixth capacitor is a storage capacitor.
  • the inverted triangle symbol in Figure 1 is the ground symbol.
  • another embodiment of the present invention provides a circuit for implementing redundancy for a non-redundant power supply, comprising: two isolation circuits, the two isolation circuits passing through the drain phase of the MOS transistor Connecting, specifically comprising a first isolation circuit and a second isolation circuit, the output terminal VOUT1;
  • the first isolation circuit includes: a first control chip U1 having an ORING function, a first MOS transistor MOS1, and a first input terminal VIN1;
  • the VDD terminal of the first control chip is grounded through the capacitor C3 and connected to the first input terminal VIN1 through the resistor R1;
  • the RSET terminal, the RSVD terminal, and the GND terminal of the first control chip are grounded;
  • the BYP end of the first control chip is connected to the first input terminal VIN1 through the capacitor C1;
  • the first terminal of the first control chip is connected to the first input terminal VIN1 and is connected to the output terminal VOUT1 through the capacitor C2 and grounded through the capacitor C4;
  • the C terminal of the first control chip is connected to the output terminal VOUT1;
  • the GATE end of the first control chip is connected to the gate of the first MOS transistor
  • the source of the first MOS transistor is connected to the first input terminal VIN1;
  • the drain of the first MOS transistor is connected to the output terminal VOUT1;
  • the source of the first MOS transistor is connected to the anode of the first diode, and the drain of the first MOS transistor is connected to the cathode of the first diode;
  • the second isolation circuit includes: a second control chip U2 having an ORING function, a second MOS transistor MOS2, and a second input terminal VIN2;
  • the VDD terminal of the second control chip is grounded through the capacitor C7 and connected to the second input terminal VIN2 through the resistor R4;
  • the RSET terminal, the RSVD terminal, and the GND terminal of the second control chip are grounded;
  • the BYP end of the second control chip is connected to the second input terminal VIN2 through the capacitor C8;
  • the second terminal of the second control chip is connected to the second input terminal VIN2 and is connected to the output terminal VOUT1 through the capacitor C6 and grounded through the capacitor C5;
  • the C terminal of the second control chip is connected to the output terminal VOUT1;
  • the GATE end of the second control chip is connected to the gate of the second MOS transistor
  • the source of the second MOS transistor is connected to the second input terminal VIN2;
  • the drain of the second MOS transistor is connected to the output terminal VOUT1;
  • the source of the second MOS transistor is connected to the anode of the second diode, and the drain of the second MOS transistor is connected to the cathode of the second diode.
  • the two isolation circuits further include a resistor R2 and a resistor R3;
  • the RSET end of the first control chip is specifically grounded through R2;
  • the RSET terminal of the second control chip is specifically grounded through R3.
  • the two isolation circuits further include a capacitor EC1, a capacitor EC2, a capacitor EC3, and a capacitor EC4;
  • the first input terminal VIN1 is grounded through the capacitor EC1;
  • the output terminal VOUT1 is grounded through the capacitor EC2 and the capacitor EC3, respectively;
  • the second input terminal VIN2 is grounded through a capacitor EC4.
  • the capacitor EC1, the capacitor EC2, the capacitor EC3, and the capacitor EC4 are specifically storage capacitors.
  • VIN1 and VIN2 represent the inputs of different power sources, and the control chips (U1 and U2) with ORING function are used to control the conduction of the N-channel MOS transistor.
  • the MOS transistor When the MOS transistor is turned on, The VOUT1 voltage is supplied to the system, and EC1, EC2, EC3 and EC4 are energy storage and filter capacitors.
  • Embodiments of the present invention provide an embodiment of a system for implementing redundancy for a non-redundant power supply, including the above-mentioned circuit for implementing redundancy for a non-redundant power supply, and an ATX power supply having the same number of isolation circuits;
  • the power output terminals of the ATX power supply are respectively connected to an isolation circuit for outputting power through the isolation circuit.
  • the system also includes an ATX power supply system
  • An output of a circuit for implementing redundancy for a non-redundant power supply is connected to an ATX power supply system according to an embodiment of the present invention
  • the ATX power supply system is used to provide power output to the load.
  • an application example of a system for implementing redundancy for a non-redundant power supply includes two ATX power supplies including a first power source and a second power source, and four embodiments of the present invention provide A circuit for implementing redundancy for a non-redundant power supply (the circuit of the present invention in FIG. 4), and an ATX power supply system.
  • Each of the circuits for redundancy of the non-redundant power supply includes two isolation circuits, and the two isolation circuits are respectively connected to the output of the first power supply and the output of the second power supply: 5VSB1, 12V1, 5V1, 3.3 in FIG. V1 is the output of the first power supply, 5VSB2, 12V2, 5V2, 3.3V2 are the output terminals of the second power supply, and 5VSB1 and 5VSB2 are respectively connected to two isolation circuits in the circuit for redundancy of the non-redundant power supply.
  • each circuit for redundancy that is used for non-redundant power supplies is connected to the ATX power supply system: first The output of the circuit for redundancy of non-redundant power supplies is 5VSB; the output of the second circuit for redundancy of non-redundant power supplies is 12V; the third is used for redundancy of non-redundant power supplies.
  • the output of the circuit is 5V; the output of the fourth circuit for redundancy with non-redundant power supplies is 3.3V.
  • the function of this solution is to use the power of the non-redundant ATX architecture for the system requirements with redundancy.
  • the embodiment of the invention realizes that the non-redundant power supply satisfies the use of the redundant system; the different ATX power sources can be used on the same system; the power consumption is small, and the system power supply efficiency is high.

Abstract

一种用于非冗余电源实现冗余的电路，用于解决现有技术无法将非冗余ATX电源用于需要冗余功能的系统中的技术问题。该电路包括：至少两个隔离电路、输出端（VOUT1）；所述隔离电路包括：具备ORING功能的控制芯片（U1，U2）、与所述控制芯片（U1，U2）数量相同的MOS管（MOS1，MOS2）、与所述控制芯片（U1，U2）数量相同的输入端（VIN1，VIN2）。通过具备ORING功能的控制芯片（U1，U2）控制关断或导通与所述控制芯片（U1，U2）数量相同的MOS管（MOS1，MOS2），从而实现两个以上电源的冗余。

Description

一种用于非冗余电源实现冗余的电路
本申请要求于2016年12月13日提交中国专利局、申请号为201611147498.X、发明名称为“一种用于非冗余电源实现冗余的电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及冗余电源领域，尤其涉及一种用于非冗余电源实现冗余的电路。
背景技术
ATX电源作用是把交流220V的电源转换为计算机内部使用的直流5V，12V，24V的电源。与AT电源相比，ATX电源增加了“+3.3V、+5VSB、PS－ON。
隔离冗余方式是指一台或者多台不间断电源(UPS，Uninterruptible Power System)作为第一级电源保护设备，另外一台机器作为二级电源，备用使用。一级电源有各自的负载总线，二级电源为所有一级电源设备提供旁路电源。工作时二级电源空载运行，但是，在一个周波的时间内要求它可以承担从0％到100％的负载。当一级电源从市电模式切换到旁路模式时，转换开关会自动将其与二级电源断开。
然而现有非冗余ATX电源一般不使用冗余功能，若用户需要使用具备有冗余功能的ATX电源，需要重新购买价格昂贵的电源。
发明内容
本发明实施例提供了一种用于非冗余电源实现冗余的电路，用于解决现有技术无法将非冗余ATX电源用于需要冗余功能的系统中的技术问题。
本发明实施例提供一种用于非冗余电源实现冗余的电路，包括：至少两个隔离电路、输出端；
所述隔离电路包括：具备ORING功能的控制芯片、与所述控制芯片数量相同的MOS管、与所述控制芯片数量相同的输入端；
所述控制芯片的VDD端通过第一电容接地并通过第一电阻连接所述输入端；
所述控制芯片的RSET端、RSVD端、GND端接地；
所述控制芯片的BYP端通过第二电容连接所述输入端；
所述控制芯片的A端连接所述输入端并通过第三电容连接所述输出端并通过第四电容接地；
所述控制芯片的C端连接所述输出端；
所述控制芯片的GATE端连接所述MOS管的栅极；
所述MOS管的源极连接所述输入端；
所述MOS管的漏极连接所述输出端；
所述MOS管的源极连接第一二极管的正极，所述MOS管的漏极连接所述第一二极管的负极。
优选地，所述隔离电路还包括第二电阻；
所述控制芯片的RSET端通过所述第二电阻接地。
优选地，所述隔离电路的输入端通过第五电容接地。
优选地，所述第五电容为储能电容。
优选地，所述输出端通过第六电容接地。
优选地，所述第六电容为储能电容。
优选地，所述隔离电路具体为两个隔离电路，两隔离电路通过自身所述MOS管的漏极相连接。
所述隔离电路具体包括第一隔离电路和第二隔离电路；
所述第一隔离电路包括：具备ORING功能的第一控制芯片U1、第一MOS管MOS1、第一输入端VIN1；
所述第一控制芯片的VDD端通过电容C3接地并通过电阻R1连接所述第一输入端；
所述第一控制芯片的RSET端、RSVD端、GND端接地；
所述第一控制芯片的BYP端通过电容C1连接所述第一输入端；
所述第一控制芯片的A端连接所述第一输入端并通过电容C2连接所述输出端并通过电容C4接地；
所述第一控制芯片的C端连接所述输出端；
所述第一控制芯片的GATE端连接所述第一MOS管的栅极；
所述第一MOS管的源极连接所述第一输入端；
所述第一MOS管的漏极连接所述输出端；
所述第一MOS管的源极连接第一二极管的正极，所述第一MOS管的漏极连接所述第一二极管的负极；
所述第二隔离电路包括：具备ORING功能的第二控制芯片U2、第二MOS管MOS2、第二输入端VIN2；
所述第二控制芯片的VDD端通过电容C7接地并通过电阻R4连接所述第二输入端；
所述第二控制芯片的RSET端、RSVD端、GND端接地；
所述第二控制芯片的BYP端通过电容C8连接所述第二输入端；
所述第二控制芯片的A端连接所述第二输入端并通过电容C6连接所述输出端并通过电容C5接地；
所述第二控制芯片的C端连接所述输出端；
所述第二控制芯片的GATE端连接所述第二MOS管的栅极；
所述第二MOS管的源极连接所述第二输入端；
所述第二MOS管的漏极连接所述输出端；
所述第二MOS管的源极连接第二二极管的正极，所述第二MOS管的漏极连接所述第二二极管的负极。
优选地，所述两个隔离电路还包括电阻R2和电阻R3；
所述第一控制芯片的RSET端具体通过所述R2接地；
所述第二控制芯片的RSET端具体通过所述R3接地。
优选地，所述两个隔离电路还包括电容EC1、电容EC2、电容EC3、电容EC4；
所述第一输入端通过所述电容EC1接地；
所述输出端分别通过所述电容EC2、所述电容EC3接地；
所述第二输入端通过所述电容EC4接地。
优选地，所述电容EC1、所述电容EC2、所述电容EC3、所述电容EC4具体为储能电容。
本发明实施例提供一种用于非冗余电源实现冗余的系统，包括上述的一种用于非冗余电源实现冗余的电路、与所述隔离电路数量相同的ATX电源；
所述ATX电源的电源输出端分别连接所述隔离电路，用于通过所述隔离电路输出电能。
优选地，本系统还包括ATX供电系统；
所述一种用于非冗余电源实现冗余的电路的输出端连接所述ATX供电系统；
所述ATX供电系统用于提供电源输出至负载。
从以上技术方案可以看出，本发明实施例具有以下优点：
本发明实施例通过具备ORING功能的控制芯片控制关断或导通与所述控制芯片数量相同的MOS管，从而实现两个以上电源的冗余，解决了现有技术无法将非冗余ATX电源用于需要冗余功能的系统中的技术问题。
此外，本发明实施例还通过储能电容为输入端和输出端储能与滤波。
本发明实施例提供的一种用于非冗余电源实现冗余的系统采用ATX电源通过隔离电路，进而输出电能，为负载供电，实现了非冗余电源的冗余供电。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例中提供的一种用于非冗余电源实现冗余的电路的一个实施例的电路示意图；
图2为本发明实施例中提供的一种用于非冗余电源实现冗余的电路的另一个实施例的电路示意图；
图3为本发明实施例中提供的一种用于非冗余电源实现冗余的电路的另一个实施例的电路示意图；
图4为本发明实施例中提供的一种用于非冗余电源实现冗余的系统的一个实施例的示意图。
具体实施方式
本发明实施例提供了一种用于非冗余电源实现冗余的电路，用于解决现有技术无法将非冗余ATX电源用于需要冗余功能的系统中的技术问题。
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，下面所描述的实施例仅仅是本发明一部分实施例，而非全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图1，本发明实施例提供一种用于非冗余电源实现冗余的电路的一个实施例示意图。
本实施例提供的电路包括：至少两个隔离电路、输出端；
隔离电路包括：具备ORING功能的控制芯片、与控制芯片数量相同的MOS管、与控制芯片数量相同的输入端；
控制芯片的VDD端通过第一电容接地并通过第一电阻连接输入端；
控制芯片的RSET端、RSVD端、GND端接地；
控制芯片的BYP端通过第二电容连接输入端；
控制芯片的A端连接输入端并通过第三电容连接输出端并通过第四电容接地；
控制芯片的C端连接输出端；
控制芯片的GATE端连接MOS管的栅极；
MOS管的源极连接输入端；
MOS管的漏极连接输出端；
MOS管的源极连接第一二极管的正极，MOS管的漏极连接第一二极管的负极。
以上是对本发明实施例提供的一种用于非冗余电源实现冗余的电路的一个实施例进行详细的描述，以下将对本发明实施例提供的一种用于非冗余电源实现冗余的电路的另一个实施例进行详细的描述。
请参阅图2，本发明实施例提供一种用于非冗余电源实现冗余的电路的另一个实施例，包括：至少两个隔离电路、输出端；
隔离电路包括：具备ORING功能的控制芯片、与控制芯片数量相同的MOS管、与控制芯片数量相同的输入端；
控制芯片的VDD端通过第一电容接地并通过第一电阻连接输入端；
控制芯片的RSET端、RSVD端、GND端接地；
控制芯片的BYP端通过第二电容连接输入端；
控制芯片的A端连接输入端并通过第三电容连接输出端并通过第四电容接地；
控制芯片的C端连接输出端；
控制芯片的GATE端连接MOS管的栅极；
MOS管的源极连接输入端；
MOS管的漏极连接输出端；
MOS管的源极连接第一二极管的正极，MOS管的漏极连接第一二极管的负极。
隔离电路还包括第二电阻；
控制芯片的RSET端通过第二电阻接地。
隔离电路的输入端通过第五电容接地。
第五电容为储能电容。
输出端通过第六电容接地。
第六电容为储能电容。
图1中的倒三角符号是接地符号。
以上是对本发明实施例提供的一种用于非冗余电源实现冗余的电路的另一个实施例进行详细的描述，以下将对本发明实施例提供的一种用于非冗余电源实现冗余的电路的另一个实施例进行详细的描述。
请参阅图3，本发明实施例提供一种用于非冗余电源实现冗余的电路的另一个实施例，包括：两个隔离电路，两个隔离电路通过自身所述MOS管的漏极相连接，具体包括第一隔离电路和第二隔离电路，输出端VOUT1；
第一隔离电路包括：具备ORING功能的第一控制芯片U1、第一MOS管MOS1、第一输入端VIN1；
第一控制芯片的VDD端通过电容C3接地并通过电阻R1连接第一输入端VIN1；
第一控制芯片的RSET端、RSVD端、GND端接地；
第一控制芯片的BYP端通过电容C1连接第一输入端VIN1；
第一控制芯片的A端连接第一输入端VIN1并通过电容C2连接输出端VOUT1并通过电容C4接地；
第一控制芯片的C端连接输出端VOUT1；
第一控制芯片的GATE端连接第一MOS管的栅极；
第一MOS管的源极连接第一输入端VIN1；
第一MOS管的漏极连接输出端VOUT1；
第一MOS管的源极连接第一二极管的正极，第一MOS管的漏极连接第一二极管的负极；
第二隔离电路包括：具备ORING功能的第二控制芯片U2、第二MOS管MOS2、第二输入端VIN2；
第二控制芯片的VDD端通过电容C7接地并通过电阻R4连接第二输入端VIN2；
第二控制芯片的RSET端、RSVD端、GND端接地；
第二控制芯片的BYP端通过电容C8连接第二输入端VIN2；
第二控制芯片的A端连接第二输入端VIN2并通过电容C6连接输出端VOUT1并通过电容C5接地；
第二控制芯片的C端连接输出端VOUT1；
第二控制芯片的GATE端连接第二MOS管的栅极；
第二MOS管的源极连接第二输入端VIN2；
第二MOS管的漏极连接输出端VOUT1；
第二MOS管的源极连接第二二极管的正极，第二MOS管的漏极连接第二二极管的负极。
两个隔离电路还包括电阻R2和电阻R3；
第一控制芯片的RSET端具体通过R2接地；
第二控制芯片的RSET端具体通过R3接地。
两个隔离电路还包括电容EC1、电容EC2、电容EC3、电容EC4；
第一输入端VIN1通过电容EC1接地；
输出端VOUT1分别通过电容EC2、电容EC3接地；
第二输入端VIN2通过电容EC4接地。
电容EC1、电容EC2、电容EC3、电容EC4具体为储能电容。
需要说明的是，在图3中VIN1与VIN2代表不同电源的输入，经过由具备ORING功能的控制芯片(U1和U2)，去控制N沟道MOS管的导通，当MOS管导通后，合为VOUT1电压给系统供电，EC1、EC2、EC3和EC4为储能与滤波电容。
以上是对本发明实施例提供的一种用于非冗余电源实现冗余的电路的另一个实施例进行详细的描述，以下将对本发明实施例提供的一种用于非冗余电源实现冗余的系统的一个实施例进行详细的描述。
本发明实施例提供一种用于非冗余电源实现冗余的系统的一个实施例，包括上述的一种用于非冗余电源实现冗余的电路、与隔离电路数量相同的ATX电源；
ATX电源的电源输出端分别连接隔离电路，用于通过隔离电路输出电能。
本系统还包括ATX供电系统；
本发明实施例提供的一种用于非冗余电源实现冗余的电路的输出端连接ATX供电系统；
ATX供电系统用于提供电源输出至负载。
请参阅图4，本发明实施例提供的一种用于非冗余电源实现冗余的系统的其中一个应用例包括两个ATX电源包括第一电源和第二电源、4个本发明实施例提供的一种用于非冗余电源实现冗余的电路(图4中的本发明电路)，以及ATX供电系统。
每个用于非冗余电源实现冗余的电路中包括两个隔离电路，两个隔离电路分别连接第一电源的输出端和第二电源的输出端：图4中5VSB1、12V1、5V1、3.3V1都是第一电源的输出端，5VSB2、12V2、5V2、3.3V2都是第二电源的输出端，5VSB1和5VSB2分别连接一个用于非冗余电源实现冗余的电路中的两个隔离电路；12V1和12V2分别连接另一个用于非冗余电源实现冗余的电路中的两个隔离电路；5V1和5V2分别连接另一个用于非冗余电源实现冗余的电路中的两个隔离电路；3.3V1和3.3V2分别连接另一个用于非冗余电源实现冗余的电路中的两个隔离电路。
每个用于非冗余电源实现冗余的电路的输出端连接ATX供电系统：第一 个用于非冗余电源实现冗余的电路的输出端为5VSB；第二个用于非冗余电源实现冗余的电路的输出端为12V；第三个用于非冗余电源实现冗余的电路的输出端为5V；第四个用于非冗余电源实现冗余的电路的输出端为3.3V。
需要说明的是，本方案功能是将非冗余ATX构架的电源用于具备冗余的系统需求中。本发明实施例实现非冗余电源满足冗余系统的使用；实现不同的ATX电源可用于同一系统上；实现使用功耗小，系统供电效率高。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (10)

  1. 一种用于非冗余电源实现冗余的电路，其特征在于，包括：至少两个隔离电路、输出端；
    所述隔离电路包括：具备ORING功能的控制芯片、与所述控制芯片数量相同的MOS管、与所述控制芯片数量相同的输入端；
    所述控制芯片的VDD端通过第一电容接地并通过第一电阻连接所述输入端；
    所述控制芯片的A端连接所述输入端并通过第三电容连接所述输出端并通过第四电容接地；
    所述MOS管的源极连接所述输入端；
    所述MOS管的漏极连接所述输出端；
    所述MOS管的源极连接第一二极管的正极，所述MOS管的漏极连接所述第一二极管的负极。
  2. 根据权利要求1所述的一种用于非冗余电源实现冗余的电路，其特征在于，所述隔离电路还包括第二电阻；
    所述控制芯片的RSET端通过所述第二电阻接地。
  3. 根据权利要求1所述的一种用于非冗余电源实现冗余的电路，其特征在于，所述隔离电路还包括第二电容；
    所述控制芯片的BYP端通过所述第二电容连接所述输入端。
  4. 根据权利要求1所述的一种用于非冗余电源实现冗余的电路，其特征在于，所述控制芯片的RSVD端和GND端均接地；
    所述控制芯片的C端连接所述输出端；
    所述控制芯片的GATE端连接所述MOS管的栅极。
  5. 根据权利要求1所述的一种用于非冗余电源实现冗余的电路，其特征在于，所述隔离电路的输入端通过第五电容接地。
  6. 根据权利要求5所述的一种用于非冗余电源实现冗余的电路，其特征在于，所述第五电容为储能电容。
  7. 根据权利要求1所述的一种用于非冗余电源实现冗余的电路，其特征在于，所述输出端通过第六电容接地；
    所述第六电容为储能电容。
  8. 根据权利要求1至7中任意一项所述的一种用于非冗余电源实现冗余的电路，其特征在于，所述隔离电路具体为两个隔离电路，所述两个隔离电路通过自身的所述MOS管的漏极相连接。
  9. 一种用于非冗余电源实现冗余的系统，其特征在于，包括如权利要求1至7中任意一项所述的一种用于非冗余电源实现冗余的电路、与所述隔离电路数量相同的ATX电源；
    所述ATX电源的电源输出端分别连接所述隔离电路，用于通过所述隔离电路输出电能。
  10. 根据权利要求9所述的一种用于非冗余电源实现冗余的系统，其特征在于，还包括ATX供电系统；
    所述一种用于非冗余电源实现冗余的电路的输出端连接所述ATX供电系统；
    所述ATX供电系统用于提供电源输出至负载。
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