WO2018098773A1 - 一种侦测时序错误的电路、触发器和锁存器 - Google Patents

一种侦测时序错误的电路、触发器和锁存器 Download PDF

Info

Publication number
WO2018098773A1
WO2018098773A1 PCT/CN2016/108226 CN2016108226W WO2018098773A1 WO 2018098773 A1 WO2018098773 A1 WO 2018098773A1 CN 2016108226 W CN2016108226 W CN 2016108226W WO 2018098773 A1 WO2018098773 A1 WO 2018098773A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
control module
output
module
input
Prior art date
Application number
PCT/CN2016/108226
Other languages
English (en)
French (fr)
Inventor
张健
唐样洋
张臣雄
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201680082727.6A priority Critical patent/CN108702152A/zh
Priority to PCT/CN2016/108226 priority patent/WO2018098773A1/zh
Publication of WO2018098773A1 publication Critical patent/WO2018098773A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

Definitions

  • Embodiments of the present invention relate to the field of electronic technologies, and in particular, to a circuit, a flip-flop, and a latch for detecting a timing error.
  • the power consumption of the chip can be reduced to reduce the power consumption of the chip.
  • the chip may have a timing error, so that the chip cannot work normally.
  • a positive edge trigger that detects timing errors can be set in the chip (ie, when the clock signal changes from low level to high level, the output signal is equal to the trigger of the input signal), and the clock signal is During a high level period, by detecting whether the input signal of the positive edge flip-flop has changed (for example, the input signal changes from a low level to a high level, or from a high level to a low level) Detect if the chip has a timing error. Exemplarily, as shown in FIG.
  • the transistor T1 and the transistor T4 are turned off, and during the change of the input signal D of the positive edge flip-flop, due to the transistor T2
  • the transistor T3 will be turned on at the same time, so the voltages of the VVDD point and the VVSS point will be nearly equal (that is, the VVDD point and the VVSS point are both low or both high), and the positive edge is triggered at this time.
  • the detection signal outputted by the device (indicated as error in Figure 1) is high, indicating that the chip has a timing error.
  • the transistor T1 and the transistor T4 are turned off during the period in which CLK is at a high level
  • the transistor T2 and the transistor T3 are simultaneously turned on
  • the VVDD point and The voltage at the VVSS point cannot be VDD (ideal high level) or GND (ideal low level), that is, the voltages at the VVDD point and the VVSS point cannot reach the ideal high level or the ideal low level, which will make
  • the positive edge trigger detects a timing error and is slower and may result in detection results. An error occurred.
  • the present application provides a circuit, a flip-flop and a latch for detecting timing errors, which can detect timing errors occurring in the chip more accurately and quickly.
  • a circuit for detecting a timing error may include: a first control module, a second control module, a third control module, and a detection module.
  • the input end of the first control module is connected to the power supply voltage
  • the output end of the first control module is connected to the input end of the third control module and the first input end of the detection module
  • the input end of the second control module is grounded
  • the second control The output of the module is connected to the output of the third control module and the second input of the detection module.
  • the first control module is configured to control the output end of the first control module to be connected or disconnected from the input end of the first control module according to the input voltage input to the control end of the first control module;
  • the second control module is configured to input the second according to the input Controlling an input voltage of the control terminal of the module, controlling an output end of the second control module to be disconnected or connected to an input end of the second control module;
  • a third control module is configured to input a clock signal at a control end of the third control module In the case of level or low level, the output of the third control module is disconnected from the input of the third control module;
  • the detection module is used to output the voltage of the output of the first control module and the second control module
  • the output voltage of the output terminal is calculated to generate a detection signal for indicating whether the circuit for detecting the timing error has a timing error.
  • the circuit for detecting timing error provided by the present application can control the output end of the third control module and the third control module because the clock signal input to the control terminal of the third control module is high level or low level.
  • the input end is disconnected, and the first control module can control the output end of the first control module and the input end of the first control module according to the voltage input to the control end of the first control module (the power supply voltage is connected to the input end of the first control module) Connecting or disconnecting, and the second control module can control the output of the second control module to be disconnected from the input end of the second control module (the input end of the second control module is grounded) according to the voltage input to the control terminal of the second control module. Or connect.
  • the voltage input to the control terminal of the first control module and the control of the input second control module can be made
  • the voltage of the terminal changes from a low level to a high level
  • the output end of the first control module is disconnected from the input end of the first control module
  • the output end of the second control module and the input end of the second control module From disconnection to connection, the voltage outputted by the output of the first control module is the power supply voltage (ie, the voltage outputted by the output of the first control module is the output of the first control module and the first control module)
  • the output of the second control module is grounded before the input is changed from disconnection to disconnection, and the output of the second control module is grounded to ensure that the output voltage of the output of the first control module can be an ideal high level.
  • the voltage outputted from the output of the second control module may be an ideal low level (ground); and the voltage that can be input to the control terminal of the first control module and the voltage input to the control terminal of the second control module
  • supply voltage the voltage outputted from the output of the second control module
  • ground the voltage that can be input to the control terminal of the first control module and the voltage input to the control terminal of the second control module
  • the output end of the first control module is disconnected from the input end of the first control module, and the output end of the second control module and the second control module The input terminal is disconnected from the connection.
  • the output voltage of the output of the first control module is the power supply voltage
  • the output of the second control module is grounded (that is, the output voltage of the output of the second control module is the second.
  • the output of the control module and the input of the second control module are disconnected from the output of the second control module before the connection is turned off to ensure that the output voltage of the output of the first control module can be ideally high.
  • Level (supply voltage) the output of the output of the second control module can be ideally low (ground). Therefore, the circuit for detecting timing errors provided by the embodiment of the present invention can detect the timing error of the chip where the circuit is located more accurately and quickly.
  • the first control module in the circuit for detecting timing errors provided by the present application may include a first transistor, where a gate of the first transistor is a control end of the first control module, The first transistor of the first transistor is at the input of the first control module, and the second of the first transistor is the output of the first control module.
  • the control according to the first control module can be realized by controlling the method of turning on or off the first transistor according to the voltage input to the gate of the first transistor.
  • the voltage of the terminal controls the output end of the first control module to be connected or disconnected from the input end of the first control module.
  • the first transistor may be a P-channel MOS transistor. Specifically, when the voltage input to the gate of the first transistor is a low level, the first transistor can be controlled to be turned on; when the voltage input to the gate of the first crystal is at a high level, the first transistor can be controlled to be turned off.
  • the second control module in the circuit for detecting timing errors provided by the present application may include a second transistor, and a gate of the second transistor is a control end of the second control module, The first transistor of the second transistor is at the input of the second control module, and the second of the second transistor is the output of the second control module.
  • the control according to the second control module can be realized by controlling the method of turning on or off the second transistor according to the voltage input to the gate of the second transistor.
  • the voltage of the terminal controls the output end of the second control module to be connected or disconnected from the input end of the second control module.
  • the second transistor may be an N-channel MOS transistor. Specifically, when the voltage input to the gate of the second transistor is at a high level, the second transistor can be controlled to be turned on; when the voltage input to the gate of the second crystal is at a low level, the second transistor can be controlled to be turned off.
  • the detecting module in the circuit for detecting timing errors provided by the present application may include a first inverter and a NOR gate, where the input end of the first inverter is The first input end of the detecting module, the output end of the first inverter is connected to the first input end of the NOR gate; the second input end of the NOR gate is the second input end of the detecting module, and the output of the NOR gate The end is the output of the detection module.
  • the voltage outputted from the output of the first control module can be input to the input end of the first inverter, after the first reverse The operation can be input to the first input terminal of the NOR gate, and since the output end of the second control module is connected to the second input end of the NOR gate, the voltage outputted from the output end of the second control module can be input to the NOR gate.
  • a second input terminal wherein the NOR gate can logically calculate the voltage of the first input terminal of the input NOR gate and the voltage of the second input terminal of the input NOR gate to generate a detection signal, thereby detecting The timing error of the chip where the circuit that detects the timing error is present.
  • the detecting module in the circuit for detecting a timing error may include: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a second In the inverter, the gate of the third transistor is connected to the control signal, the first pole of the third transistor is connected to the power supply voltage, and the second pole of the third transistor is connected to the input terminal of the second pole of the fourth transistor and the second inverter;
  • the gate of the fourth transistor is the first input end of the detecting module, the first pole of the fourth transistor is connected to the first pole of the fifth transistor, the gate of the fifth transistor is the second input end of the detecting module, and the fifth transistor is The second pole is connected to the second pole of the sixth transistor; the gate of the sixth transistor is connected to the control signal, the first pole of the sixth transistor is grounded; and the output end of the second inverter is the output end of the detecting module.
  • the third transistor and the fifth transistor may be P-channel MOS transistors
  • the fourth transistor and the sixth transistor may be N-channel MOS transistors.
  • the third transistor when the circuit for detecting the timing error is in the detection window (ie, the control signal is at a high level), the third transistor is turned off, and the sixth transistor is turned on, and at this time, if the output of the first control module is output The voltage is high (ie, the gate of the fourth transistor is high), the output voltage of the output of the second control module is low (ie, the gate of the fifth transistor is low), then the fourth transistor and The fifth transistor is turned on. Since the fourth transistor, the fifth transistor, and the sixth transistor are both turned on, and the first electrode of the sixth transistor is grounded, the voltage of the second electrode of the fourth transistor is equal to the first pole of the sixth transistor.
  • the third control module in the circuit for detecting timing error provided by the present application may include a seventh transistor, and a gate of the seventh transistor is a control end of the third control module.
  • the first terminal of the seventh transistor is the input terminal of the third control module, and the second transistor is the output terminal of the third control module.
  • the third control module can be implemented by the seventh transistor, the method of controlling the seventh transistor to be turned off according to the case where the clock signal input to the gate of the seventh transistor is at a high level or a low level can be used.
  • the output of the third control module is controlled to be disconnected from the input end of the third control module.
  • the seventh transistor may be a P-channel MOS transistor or an N-channel MOS transistor.
  • the seventh transistor when the seventh transistor is a P-channel MOS transistor, when the clock signal input to the gate of the seventh transistor is at a high level, the seventh transistor can be controlled to be turned off, and the gate of the seventh transistor is input. When the polarity of the clock signal is low, the seventh transistor can be controlled to be turned on.
  • the seventh transistor is an N-channel MOS transistor, when the clock signal input to the gate of the seventh transistor is at a low level, the seventh transistor can be controlled to be turned off, and the clock at the gate of the seventh transistor is input. When the signal is high, the seventh transistor can be controlled to be turned on.
  • the third control module in the circuit for detecting timing errors provided by the present application may include an eighth transistor, a ninth transistor, and a third inverter;
  • the gate is the control end of the third control module, the first terminal of the eighth transistor is the input terminal of the third control module, the second electrode of the eighth transistor is connected to the second pole of the ninth transistor; the input end of the third inverter is connected a gate of the eighth transistor, an output of the third inverter connected to the gate of the ninth transistor; a first terminal of the ninth transistor having an output of the third control module, wherein the clock at the control terminal of the third control module is input When the signal is high, the third control module controls the output end of the third control module to be disconnected from the input end of the third control module; or the gate of the ninth transistor is the control end of the third control module, and the ninth The first end of the transistor is the output terminal of the third control module, the second electrode of the ninth transistor is connected to the second electrode of the eighth transistor; the input end of the third inverter
  • the first one of the two different structures of the third control module may be used, that is, the gate of the eighth transistor is the control end of the third control module, and the first terminal of the eighth transistor is the third control module.
  • the second pole of the eighth transistor is connected to the second pole of the ninth transistor;
  • the input end of the third inverter is connected to the gate of the eighth transistor, and the output end of the third inverter is connected to the gate of the ninth transistor
  • the output of the first extremely third control module of the ninth transistor is referred to as a first structure
  • the second of the two different structures of the third control module may be used (ie, the gate of the ninth transistor is the third a control terminal of the control module, an output terminal of the first extremely third control module of the ninth transistor, a second electrode of the ninth transistor is connected to the second electrode of the eighth transistor; and an input end of the third inverter is connected to the ninth transistor
  • the gate, the output of the third inverter is connected to the gate of the eighth transistor; the input of the first extremely third control
  • the first structure described above may also be implemented by another structure.
  • the third control module includes an eighth transistor and a ninth transistor, and a gate of the eighth transistor is a control end of the third control module, an input end of the first extremely third control module of the eighth transistor, and an eighth transistor
  • the second pole is connected to the second pole of the ninth transistor; the gate of the ninth transistor is connected to the clock signal of the phase opposite to the clock signal period of the control terminal of the third control module; the first extremely third control module of the ninth transistor Output.
  • the foregoing second structure may also be implemented by another structure.
  • the third control module includes an eighth transistor and a ninth transistor, and a gate of the ninth transistor is a control end of the third control module, and an output terminal of the first extremely third control module of the ninth transistor, the ninth transistor
  • the second pole is connected to the second pole of the eighth transistor;
  • the gate of the eighth transistor is connected to the clock signal of the phase opposite to the clock signal period of the control terminal of the third control module;
  • the first transistor of the eighth transistor is the third control module Input.
  • the eighth transistor and the ninth transistor can be controlled to be turned off according to the case where the clock signal input to the gate of the eighth transistor is at a high level.
  • Method for controlling the third when the clock signal input to the control terminal of the third control module is high or low The output end of the control module is disconnected from the input end of the third control module; when the structure of the third control module is the second structure, the condition may be low according to the clock signal at the gate of the input ninth transistor
  • the eighth transistor may be a P-channel MOS transistor
  • the ninth transistor may be an N-channel MOS transistor.
  • the structure of the third control module is the first structure
  • the clock signal input to the gate of the eighth transistor is at a high level
  • after the third inverter is passed the gate of the ninth transistor is input.
  • the pole clock signal is low, so that the eighth transistor and the ninth transistor can be turned off when the clock signal is high.
  • the structure of the third control module is the second structure described above, in the case where the clock signal input to the gate of the ninth transistor is at a low level, after the third inverter is passed, the clock of the gate of the eighth transistor is input.
  • the signal is high, so that the eighth transistor and the ninth transistor can be turned off when the clock signal is low.
  • a trigger comprising the first aspect or the first possible implementation of the first aspect to any one of the possible implementations of the fifth possible implementation of the first aspect
  • the circuit for detecting a timing error and the first trigger module wherein the control end of the first control module in the circuit is an input end of the trigger, and the control end of the first trigger module is connected to the second control module in the circuit
  • the output end is connected to the output end of the first control module in the circuit, the first input end of the first trigger module is connected to the power supply voltage, the second input end of the first trigger module is grounded, and the output end of the first trigger module is triggered.
  • the output of the device is provided, comprising the first aspect or the first possible implementation of the first aspect to any one of the possible implementations of the fifth possible implementation of the first aspect
  • the circuit for detecting a timing error and the first trigger module wherein the control end of the first control module in the circuit is an input end of the trigger, and the control end of the first trigger module is connected to the second control module in the circuit
  • the output end
  • the seventh transistor M7 in the circuit for detecting timing error is the P-channel MOS transistor in the fifth possible implementation manner of the foregoing first aspect
  • the circuit provided in the fifth possible implementation manner of the first aspect and the trigger of the first trigger module may be a positive edge trigger.
  • the seventh transistor M7 in the circuit for detecting timing error is the N-channel MOS transistor in the fifth possible implementation manner of the foregoing first aspect
  • the present application provides The circuit including the fifth possible implementation of the first aspect and the trigger of the first trigger module (the control terminal of the first trigger module is connected to the output of the first control module) may be a negative edge trigger.
  • the above trigger since the above trigger includes the circuit for detecting timing error in the present application, the above trigger can be used in addition to the function of the conventional positive edge trigger or the conventional negative edge trigger. Used to detect if the chip where the trigger is located has a timing error. Moreover, compared with the positive edge trigger which can detect the timing error in the prior art, the timing error of the chip where the trigger is located can be detected more accurately and quickly.
  • the trigger can be a single-phase clock trigger
  • the delay of the trigger of the present application is compared to the prior art that the positive edge trigger capable of detecting a timing error is a two-phase clock trigger. And power consumption is small, and the circuit structure is simple.
  • the third aspect provides a trigger, which includes the circuit for detecting timing error and the second trigger module according to the sixth possible implementation manner of the first aspect, where the first control module is The control end is an input end of the trigger, the input end of the second trigger module is connected to the second pole of the eighth transistor in the circuit, and the output end of the second trigger module is the output end of the trigger.
  • the structure of the third control module in the circuit for detecting timing errors in the sixth possible implementation manner of the foregoing first aspect is the sixth aspect of the foregoing first aspect.
  • the circuit of the sixth possible implementation manner of the first aspect and the trigger of the second trigger module provided by the present application may be a positive edge trigger.
  • the structure of the third control module in the circuit for detecting timing errors in the sixth possible implementation manner of the foregoing first aspect is the sixth possible aspect of the foregoing first aspect.
  • the circuit of the sixth possible implementation manner of the first aspect and the trigger of the second trigger module provided by the present application may be a negative edge trigger.
  • a latch comprising the circuit and the latch module for detecting a timing error according to the sixth possible implementation manner of the first aspect, wherein the control terminal of the latch module is latched At the input end of the device, the first input end of the latch module is connected to the power supply voltage, the second input end of the latch module is grounded, and the first output end of the latch module is connected to the control end of the first control module in the above circuit and the second The control end of the control module, the second output end of the latch module is connected to the second electrode of the eighth transistor in the circuit, and the third output end of the latch module is the output end of the latch.
  • FIG. 1 is a schematic diagram of a flip-flop provided by the prior art
  • FIG. 2 is a schematic diagram 1 of a circuit for detecting timing errors according to an embodiment of the present invention
  • FIG. 3 is a second schematic diagram of a circuit for detecting timing errors according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram 3 of a circuit for detecting a timing error according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram 4 of a circuit for detecting timing errors according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram 5 of a circuit for detecting a timing error according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram 6 of a circuit for detecting timing errors according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram 7 of a circuit for detecting timing errors according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram 8 of a circuit for detecting timing errors according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a circuit for detecting timing errors according to an embodiment of the present invention.
  • Figure IX is a schematic diagram of a circuit for detecting timing errors according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram 1 of a trigger according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram 2 of a trigger according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram 3 of a trigger according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram 4 of a trigger according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram 5 of a trigger according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram 6 of a trigger according to an embodiment of the present disclosure.
  • FIG. 17 is a first schematic diagram of a latch according to an embodiment of the present invention.
  • FIG. 18 is a second schematic diagram of a latch according to an embodiment of the present invention.
  • first”, “second”, and “third” and the like in the embodiments of the present invention are used to distinguish different objects, and are not used to describe a specific order.
  • the first transistor, the second transistor, the third transistor, etc. are used to distinguish different transistors, rather than to describe a particular order of transistors.
  • the words “exemplary” or “such as” are used to mean an example, illustration, or illustration. Any embodiment or design described as “exemplary” or “for example” in the embodiments of the invention should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the words “exemplary” or “such as” is intended to present the concepts in a particular manner.
  • the transistor used in the embodiment of the present invention may be a thin film transistor or a field effect transistor or other devices having the same characteristics. Depending on the function of the transistor in the circuit, all of the transistors used in the embodiments of the present invention function mainly as a switching function. That is, all the transistors used in the embodiments of the present invention may also be referred to as switching transistors.
  • the source and drain of the transistor employed in the embodiments of the present invention are symmetrical in the circuit, the source and drain of the transistor are interchangeable in the circuit.
  • the source in order to distinguish two poles of the transistor except the gate, for example, to distinguish the source and the drain of the transistor except the gate, the source may be represented by the first pole, The two poles represent the drain; or the first pole represents the drain and the second pole represents the source.
  • the transistor used in the embodiments of the present invention may include a P-channel metal oxide.
  • the tube is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the power consumption of the chip is usually reduced by reducing the power supply voltage of the chip.
  • the chip may have a timing error, so that the chip cannot work normally.
  • a positive edge trigger for detecting a timing error can be set in the chip, and when the clock signal is at a high level, whether the input signal of the positive edge trigger changes is detected ( For example, the input signal changes from a low level to a high level, or from a high level to a low level, to detect whether the chip has a timing error, and after detecting a timing error, by adjusting the power supply voltage of the chip. To eliminate this timing error.
  • the speed is slow, and the detection result may be wrong.
  • an embodiment of the present invention provides a circuit for detecting a timing error, a flip-flop, and a latch (a circuit including a trigger for detecting a timing error in a flip-flop and a latch), in a circuit for detecting a timing error.
  • the output voltage of the output terminal of the first control module in the circuit can be an ideal high level ( The power supply voltage), the output voltage of the output of the second control module can be an ideal low level (ground), so that the circuit detecting the timing error can detect the timing error of the chip more accurately and quickly.
  • the circuit, the flip-flop and the latch for detecting the timing error provided by the embodiment of the present invention will be separately described in the following embodiments.
  • the circuit, the flip-flop and the latch for detecting timing errors provided by the embodiments of the present invention can be applied to various chips (also referred to as integrated circuits).
  • the circuit, the flip-flop and the latch for detecting timing errors provided by the embodiments of the present invention can be applied to a small scale integration (SSI), a medium scale integration (MSI), Large scale integration (LSI) and very large scale integration (VLSI).
  • SSI small scale integration
  • MSI medium scale integration
  • LSI Large scale integration
  • VLSI very large scale integration
  • the chip for detecting the timing error circuit, the flip-flop and the latch provided by the embodiment of the present invention when the power consumption of the chip is reduced to reduce the power consumption of the chip, the power supply voltage of the chip is lowered. To a certain extent, when the chip has a timing error, the timing error of the chip can be accurately and quickly detected, so that the power supply voltage of the chip can be quickly adjusted to eliminate the timing error, thereby ensuring the normal operation of the chip.
  • the chip may be a digital logic chip such as a central processing unit (CPU).
  • CPU central processing unit
  • an embodiment of the present invention provides a circuit for detecting a timing error, and the circuit may include: a first control module 11, a second control module 12, a third control module 13, and a detection module 14.
  • the input end 111 of the first control module 11 is connected to the power supply voltage (shown as VDD in FIG. 2 ), and the output end 112 of the first control module is connected to the input end 131 of the third control module 13 and the first input of the detection module 14 .
  • the input end 121 of the second control module 12 is grounded (shown as GND in FIG. 2), and the output end 122 of the second control module 12 is connected to the output end 132 of the third control module 13 and the second input of the detection module 14. End 142.
  • the first control module 11 may be configured to control the output end 112 of the first control module 11 according to the voltage input to the control terminal 113 of the first control module 11 (shown as D in FIG. 2).
  • the input 111 of a control module 11 is connected or disconnected.
  • the second control module 12 can be configured to control the input of the output terminal 122 of the second control module 12 and the second control module 12 according to the voltage input to the control terminal 123 of the second control module 12 (denoted as D in FIG. 2). End 121 is disconnected or connected.
  • the third control module 13 can be used to control the third control module 13 when the clock signal (shown as CLK in FIG. 2) of the control terminal 133 of the third control module 13 is at a high level or a low level.
  • the output 132 is disconnected from the input 131 of the third control module 13.
  • the detection module 14 can be used to output the voltage output from the output 112 of the first control module 11 (ie, the voltage input by the first input 141 of the detection module 14) and the output 122 of the second control module 12.
  • the voltage ie, the voltage input by the second input 142 of the detection module 14
  • the detection signal is output through the output 143 of the detection module 14.
  • the detection signal can be used to indicate whether the chip in which the circuit for detecting the timing error is located has a timing error.
  • control end 113 of the first control module 11 and the control end 123 of the second control module 12 may be the input end of the circuit for detecting the timing error, and the input end of the first control module 11 is input.
  • the voltage of 113 and the voltage input to the control terminal 123 of the second control module 12 may each be the voltage input to the input of the circuit (shown as D in Figure 2), i.e., the input voltage of the circuit.
  • the detecting module 14 may output the voltage outputted by the output terminal 112 of the first control module 11 and the output terminal 122 of the second control module 12 The voltage is logically operated, and the detection signal is outputted at the output 143 of the detection module 14 according to the result of the logic operation.
  • the detection signal output of the output terminal 143 of the detection module 14 is error. Can be equal to the product of n0 and n1 (ie, ).
  • the circuit for detecting timing error as shown in FIG. 2, when the output end of the third control module is disconnected from the input end of the third control module, by detecting whether D changes, Detecting whether the chip in which the circuit for detecting the timing error is located has a timing error.
  • the logic value of the high level is set to 1
  • the logic value of the low level is set to 0
  • the output of the output terminal 112 of the first control module 11 is n0
  • the output of the second control module 12 The output voltage of 122 is n1.
  • the circuit for detecting timing error provided by the embodiment of the present invention can control the output end of the third control module and the third control module when the clock signal input to the control end of the third control module is a high level or a low level.
  • the input is disconnected.
  • the circuit for detecting the timing error is applied to the positive edge trigger
  • the output of the third control module and the third control are controlled when the clock signal input to the control terminal of the third control module is at a high level.
  • the input of the module is disconnected.
  • the circuit for detecting the timing error is applied to the negative edge trigger
  • the input of the output of the third control module and the input of the third control module are controlled when the clock signal input to the control terminal of the third control module is low.
  • the end is disconnected.
  • the circuit for detecting the timing error provided by the embodiment of the present invention when the circuit for detecting the timing error provided by the embodiment of the present invention is applied to the positive edge trigger, that is, when the clock signal input to the control terminal of the third control module is high, the output of the third control module is controlled.
  • the working principle of the circuit for detecting the timing error provided by the embodiment of the present invention is described as an example of the disconnection of the input terminal of the third control module.
  • the input voltage D of the circuit for detecting the timing error has the following four possibilities, and the following four possible situations are respectively performed. Detailed description:
  • the first possibility D changes from 0 to 1 (specifically, the logical value of D changes from 0 to 1), the output of the first control module is disconnected from the input of the first control module by the connection, and the second The output of the control module is disconnected from the input of the second control module.
  • D changes from 1 to 0 (the logical value of D changes from 1 to 0)
  • the output of the first control module is disconnected from the input of the first control module
  • the second control module The output of the second control module is disconnected from the input of the second control module.
  • N0 1 (the voltage of n0 is the voltage output from the output of the first control module after D changes from 1 to 0.
  • the output end of the first control module is always connected with the input end of the first control module (ie, the output end of the first control module is connected to the power supply voltage)
  • the second control module The output is always disconnected from the input of the second control module.
  • the voltage outputted by the output of the module and the voltage outputted by the output of the second control module, since the output of the third control module is connected to the input of the third control module in the case of CLK 0, the first control module
  • the chip on which the timing error is measured has no timing error.
  • the output of the third control module is controlled only when the clock signal input to the control terminal of the third control module is at a high level.
  • the working principle of the circuit for detecting the timing error is exemplarily described. In the case where the clock signal input to the control end of the third control module is low, the control is performed.
  • the working principle of the circuit for detecting the timing error and the above-mentioned clock signal input to the control terminal of the third control module are controlled to be high.
  • the operation principle of the circuit for detecting the timing error is similar, and details are not described herein again.
  • the circuit for detecting timing error provided by the embodiment of the present invention can control the output end of the third control module and the third control when the clock signal input to the control end of the third control module is a high level or a low level.
  • the input end of the module is disconnected, and the first control module can control the output end of the first control module and the input end of the first control module according to the voltage input to the control end of the first control module (the input end of the first control module is connected to the power supply)
  • the voltage is connected or disconnected, and the second control module can control the output end of the second control module and the input end of the second control module according to the voltage input to the control terminal of the second control module (the input end of the second control module is grounded) Disconnect or connect.
  • the output end of the first control module is connected to the input end of the first control module.
  • the output end of the second control module and the input end of the second control module are changed from disconnected to connected.
  • the output voltage of the output end of the first control module is the power supply voltage
  • the output end of the second control module Grounding ie the first possibility mentioned above to ensure that the output voltage of the output of the first control module can be an ideal high level (supply voltage), and the output voltage of the output of the second control module can be ideally low.
  • the circuit for detecting timing errors provided by the embodiment of the present invention can detect the timing error of the chip where the circuit is located more accurately and quickly.
  • the first control module 11 in the circuit for detecting timing errors provided by the embodiment of the present invention includes a first transistor M1.
  • the gate of the first transistor M1 is the control terminal 113 of the first control module 11, and the first end of the first transistor M1 is the input terminal 111 of the first control module 11,
  • the second of the first transistor M1 is extremely the output 112 of the first control module 11 described above.
  • the gate of the first transistor is the control end of the first control module
  • the first end of the first transistor is the input end of the first control module
  • the second end of the first transistor is the output end of the first control module. Therefore, the method of controlling the voltage of the control terminal of the first control module according to the voltage of the gate of the first transistor to control the first transistor to be turned on or off may be used to control the output end of the first control module and the foregoing The input of a control module is connected or disconnected.
  • the first transistor may be a P-channel MOS transistor. Specifically, when the voltage input to the gate of the first transistor is a low level, the first transistor can be controlled to be turned on; when the voltage input to the gate of the first crystal is at a high level, the first transistor can be controlled to be turned off.
  • the circuit for detecting timing error when the voltage input to the gate of the first transistor M1 changes from a low level to a high level (ie, D changes from 0 to 1)
  • the first transistor M1 is turned off by conduction.
  • the voltage outputted by the second pole of the first transistor M1 is the voltage outputted by the second pole of the first transistor M1 before D is changed from 0 to 1, since D is 0.
  • the second electrode of the first transistor M1 Before being changed to 1, the second electrode of the first transistor M1 is connected to the power supply voltage (ie, the first transistor M1 is turned on), and therefore, the voltage output by the second electrode of the first transistor M1 is the power supply voltage, that is, the first control module 11 described above.
  • the output voltage of the output terminal 112 is the power supply voltage; when the voltage input to the gate of the first transistor M1 changes from a high level to a low level (D changes from 1 to 0), the first transistor M1 becomes a turn-off In this case, the voltage outputted by the second pole of the first transistor M1 is the voltage outputted by the second pole of the first transistor M1 after D is changed from 1 to 0, since the first transistor M1 is after D changes from 1 to 0.
  • the second pole is connected to the power supply voltage (ie, the first transistor M1 is turned on), and therefore, the voltage outputted by the second pole of the first transistor M1 is Voltage source, i.e., the first control module 11 is output from the output terminal of voltage supply 112 voltage.
  • the second control module 12 in the circuit for detecting timing errors provided by the embodiment of the present invention includes a second transistor M2.
  • the gate of the second transistor M2 is the control terminal 123 of the second control module 12
  • the first terminal of the second transistor M2 is the input terminal 121 of the second control module 12
  • the second end of the body tube M2 is the output 122 of the second control module 12.
  • the gate of the second transistor is the control end of the second control module
  • the first terminal of the second transistor is the input terminal of the second control module
  • the second terminal of the second transistor is the output terminal of the second control module. Therefore, the voltage of the control terminal of the second control module can be controlled according to the voltage of the gate of the second transistor to control whether the second transistor is turned on or off, and the output of the second control module is controlled.
  • the input terminals of the two control modules are connected or disconnected.
  • the second transistor may be an N-channel MOS transistor. Specifically, when the voltage input to the gate of the second transistor is at a high level, the second transistor can be controlled to be turned on; when the voltage input to the gate of the second crystal is at a low level, the second transistor can be controlled to be turned off.
  • the circuit for detecting timing error in the circuit for detecting timing error according to the embodiment of the present invention, when the voltage input to the gate of the second transistor M2 changes from a low level to a high level (ie, D changes from 0 to 1) The second transistor M2 is turned on by the turn-off. At this time, the voltage outputted by the second pole of the second transistor M2 is the voltage outputted by the second pole of the second transistor M2 after D is changed from 0 to 1, since D is 0.
  • the second pole of the second transistor M2 is grounded (ie, the second transistor M2 is turned on), and therefore, the second pole of the second transistor M2 is grounded, that is, the output terminal 122 of the second control module 12 is grounded;
  • the voltage input to the gate of the second transistor M2 changes from a low level to a high level (ie, D changes from 1 to 0)
  • the second transistor M2 is turned off by conduction, and the second transistor M2 is second.
  • the voltage of the pole output is the voltage of the second pole output of the second transistor M2 before D changes from 1 to 0. Since the second pole of the second transistor M2 is grounded before D changes from 1 to 0 (ie, the second transistor M2 leads) Therefore, the second pole of the second transistor M2 is grounded, that is, the output terminal 122 of the second control module 12 is grounded.
  • the detecting module 14 in the circuit for detecting timing errors provided by the embodiment of the present invention includes a first inverter 144 and a NOR gate 145.
  • the input end 1441 of the first inverter 144 is the first input end 141 of the detection module 14, and the output end 1442 of the first inverter 144 is connected to the first input of the NOR gate 145.
  • the second input end 142 of the NOR gate 145 is the second input end 142 of the detection module 14, and the output end 1453 of the NOR gate 145 is the output end 143 of the detection module 14.
  • the voltage outputted by the output end of the first control module (for example, denoted as n0) may be input into the first reverse
  • the input end of the directional device can be input to the first input end of the NOR gate after the operation of the first inverter, and since the output end of the second control module is connected to the second input end of the NOR gate, therefore, the second The voltage output from the output of the control module (for example, denoted as n1) can be input to the second input of the NOR gate, so that the NOR gate can input the voltage of the first input terminal of the NOR gate and the second input of the input NOR gate.
  • the voltage at the terminal is logically operated to generate a detection signal.
  • the logic value of the high level is set to 1
  • the logic value of the low level is set to 0.
  • the detecting module in the circuit for detecting timing errors provided by the embodiment of the present invention may be implemented by using the logic circuit composed of the first inverter and the NOT gate, or may be implemented by using other forms of logic circuits.
  • the embodiment of the present invention does not limit the specific form of the logic circuit used in the detection module, and the logic output of the output end of the logic circuit (for example, the output of the NOR gate) is equal to the first input end of the input logic circuit.
  • the logical value of (e.g., the input of the first inverter described above) is the product of the non-signal of the logical value of the second input of the input logic circuit (e.g., the second input of the NOR gate).
  • the detecting module 14 in the circuit for detecting timing error includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a third Six transistors M6 and a second inverter 146.
  • the gate of the third transistor M3 is connected to the control signal (shown as Ctrl in FIG. 6), the first pole of the third transistor M3 is connected to the power supply voltage, and the second pole of the third transistor M3 is connected to the second pole of the fourth transistor M4. And the input end 1461 of the second inverter 146; fourth The gate of the transistor M4 is the first input end 141 of the detecting module 14, the first pole of the fourth transistor M4 is connected to the first pole of the fifth transistor M5, and the gate of the fifth transistor M5 is the second input end of the detecting module 14.
  • the second pole of the fifth transistor M5 is connected to the second pole of the sixth transistor M6; and the gate of the sixth transistor M6 is connected with a control signal (shown as Ctrl in FIG. 6), and the first pole of the sixth transistor M6 is grounded;
  • the output 1462 of the second inverter 146 is the output 143 of the detection module 14.
  • control signal is used to determine a detection window (ie, for example, a time period for detecting a timing error).
  • a detection window ie, for example, a time period for detecting a timing error.
  • detection is detected when the control signal is high (eg, the logic value of the control signal is 1), and detection is stopped when the control signal is low (eg, a logic value of 0).
  • the third transistor and the fifth transistor may be P-channel MOS transistors
  • the fourth transistor and the sixth transistor may be N-channel MOS transistors.
  • the third transistor is turned off, and the sixth transistor is turned on.
  • the fourth transistor And the fifth transistor is turned on, since the fourth transistor, the fifth transistor, and the sixth transistor are both turned on, and the first electrode of the sixth transistor is grounded, the voltage of the second electrode of the fourth transistor is equal to the first of the sixth transistor
  • the voltage of the pole (ground) is low (ie, the logic value of the voltage of the second pole of the fourth transistor is 0), so the logic value input to the input of the second inverter is 0, and the output of the second inverter
  • the third control module 13 in the circuit for detecting timing errors provided by the embodiment of the present invention includes a seventh transistor M7. .
  • the gate of the seventh transistor M7 is the control terminal 133 of the third control module 13, the first terminal of the seventh transistor M7 is the input terminal 131 of the third control module 13, and the second terminal of the seventh transistor M7 is the third control module 13 Output 132.
  • the gate of the seventh transistor is the control end of the third control module, and the input end of the first transistor of the seventh transistor is the third
  • the second transistor of the seventh transistor is the output terminal of the third control module, so that the clock signal of the gate of the seventh transistor can be input to a high level or a low level, and the method of controlling the seventh transistor to be turned off is implemented at the input.
  • the clock signal of the control terminal of the third control module is a high level or a low level
  • the output end of the third control module is disconnected from the input end of the third control module.
  • the seventh transistor may be a P-channel MOS transistor or an N-channel MOS transistor.
  • the seventh transistor when the seventh transistor is a P-channel MOS transistor, when the clock signal input to the gate of the seventh transistor is at a high level, the seventh transistor can be controlled to be turned off, and the gate of the seventh transistor is input.
  • the clock signal of the pole is low
  • the seventh transistor can be controlled to be turned on; when the seventh transistor is an N-channel MOS transistor, the clock signal input to the gate of the seventh transistor is low.
  • the seventh transistor can be controlled to be turned off, and in the case where the clock signal input to the gate of the seventh transistor is at a high level, the seventh transistor can be controlled to be turned on.
  • the MOS transistor in which the seventh transistor is a P-channel is exemplarily described as an example.
  • the circuit for detecting timing error as shown in FIG. 7 and FIG. 8 provided by the embodiment of the present invention, when the clock signal input to the gate of the seventh transistor M7 is at a high level (ie, CLK is at a high level),
  • the voltage (D) input to the gate of the first transistor M1 and the gate of the second transistor M2 changes from a low level to a high level, the first transistor M1 is turned off by conduction, and the second transistor M2 is turned off.
  • the voltage of the second pole of the first transistor M1 is the power supply voltage (ie, the voltage of the second pole of the first transistor M1 is the second pole of the first transistor M1 before the first transistor is turned on and turned off).
  • the second pole of the second transistor M2 is grounded to ensure that the voltage outputted by the output of the first control module (ie, the voltage of the second pole of the first transistor M1) can be an ideal high level (supply voltage)
  • the voltage outputted from the output of the second control module (the voltage of the second pole of the second transistor M2) may be an ideal low level (ground); when the gate of the first transistor M1 and the gate of the second transistor M2 are input
  • the voltage of the pole (D) changes from a high level to a low level
  • the first transistor M1 is turned off by the turn-on, and the second transistor M2 is turned off by the turn-on, so that the voltage of the second pole of the first transistor M1 is the power supply voltage, and the second pole of the second transistor M2 is grounded (ie, at this time).
  • the voltage of the second pole of the second transistor M2 is the voltage of the second pole of the second transistor M2 before the second transistor M2 is turned off, to ensure the voltage outputted by the output of the first control module (ie, the first transistor)
  • the voltage of the second pole of M1 can be an ideal high level (supply voltage), and the voltage outputted by the output of the second control module (the voltage of the second pole of the second transistor M2) can be an ideal low level ( Ground). Therefore, the circuit for detecting timing errors provided by the embodiment of the present invention can detect the timing error of the chip where the circuit is located more accurately and quickly.
  • the third control module 13 in the circuit for detecting timing errors provided by the embodiment of the present invention includes an eighth transistor M8.
  • the ninth transistor M9 and the third inverter 134 are also included in the third control module 13 in the circuit for detecting timing errors provided by the embodiment of the present invention.
  • the gate of the eighth transistor M8 is the control terminal 133 of the third control module 13, the first terminal of the eighth transistor M8 is the input terminal 131 of the third control module 13, and the second electrode of the eighth transistor M8 is connected to the third transistor M9.
  • the input terminal 1341 of the third inverter 134 is connected to the gate of the eighth transistor M8, the output terminal 1342 of the third inverter 134 is connected to the gate of the ninth transistor M9; the first extreme of the ninth transistor M9
  • the third control module may be the structure of the third control module 13 shown in FIG. 9 or FIG. 10 (hereinafter referred to as the first structure). ).
  • the structure of the third control module 13 shown in FIG. 9 or FIG. 10 may be replaced with the second structure.
  • the second structure may be specifically: the gate of the ninth transistor M9 in FIG. 9 or FIG.
  • the fourth control module 10 is the control terminal 133 of the third control module 13, and the output terminal 132 of the first extremely third control module 13 of the ninth transistor M9,
  • the second pole of the nine transistor M9 is connected to the second pole of the eighth transistor M8;
  • the input terminal 1341 of the third inverter 134 is connected to the gate of the ninth transistor M9, and the output terminal 1342 of the third inverter 134 is connected.
  • Connecting the gate of the eighth transistor M8; the first terminal of the eighth transistor M8 is the input terminal 131 of the third control module 13; wherein, when the clock signal input to the control terminal 133 of the third control module 13 is low
  • the third control module 13 controls the output 132 of the third control module 13 to be disconnected from the input 131 of the third control module 13.
  • the first structure described above may also be implemented by another structure.
  • the third control module includes an eighth transistor and a ninth transistor, and a gate of the eighth transistor is a control end of the third control module, an input end of the first extremely third control module of the eighth transistor, and an eighth transistor
  • the second pole is connected to the second pole of the ninth transistor; the gate of the ninth transistor is connected to the clock signal of the phase opposite to the clock signal period of the control terminal of the third control module; the first extremely third control module of the ninth transistor Output.
  • the foregoing second structure may also be implemented by another structure.
  • the third control module includes an eighth transistor and a ninth transistor, and a gate of the ninth transistor is a control end of the third control module, and an output terminal of the first extremely third control module of the ninth transistor, the ninth transistor
  • the second pole is connected to the second pole of the eighth transistor;
  • the gate of the eighth transistor is connected to the clock signal of the phase opposite to the clock signal period of the control terminal of the third control module;
  • the first transistor of the eighth transistor is the third control module Input.
  • the eighth transistor and the ninth transistor may be controlled according to the case that the clock signal input to the gate of the eighth transistor is at a high level.
  • a method of cutting off in the case that the clock signal input to the control terminal of the third control module is a high level or a low level, the output end of the third control module is disconnected from the input end of the third control module;
  • the method can be implemented by controlling the eighth transistor and the ninth transistor to be turned off according to a case where the clock signal input to the gate of the ninth transistor is at a low level.
  • the clock signal input to the control terminal of the third control module is high level or low level, the output end of the third control module is controlled to be disconnected from the input end of the third control module.
  • the eighth transistor may be a P-channel In the MOS transistor
  • the ninth transistor may be an N-channel MOS transistor.
  • the structure of the third control module is the first structure
  • the clock signal input to the gate of the eighth transistor is at a high level
  • the third inverter is input
  • the input of the ninth transistor is deleted.
  • the pole clock signal is low, so that the eighth transistor and the ninth transistor can be turned off when the clock signal is high.
  • the structure of the third control module is the second structure described above, in the case where the clock signal input to the gate of the ninth transistor is at a low level, after the third inverter is passed, the clock of the gate of the eighth transistor is input.
  • the signal is high, so that the eighth transistor and the ninth transistor can be turned off when the clock signal is low.
  • the clock signal input to the gate of the eighth transistor M8 is at a high level (ie, CLK is a high level).
  • CLK is a high level
  • the voltage (D) input to the gate of the first transistor M1 and the gate of the second transistor M2 changes from a low level to a high level, the first transistor M1 is turned off by conduction, and the second transistor is turned off.
  • the second pole of the second transistor M2 changes from off to on, such that the voltage of the second pole of the first transistor M1 is the power supply voltage, and the second pole of the second transistor M2 is grounded to ensure the voltage outputted by the output of the first control module (ie, the first transistor)
  • the voltage of the second pole of M1 can be an ideal high level (supply voltage)
  • the voltage outputted by the output of the second control module (the voltage of the second pole of the second transistor M2) can be an ideal low level
  • the first transistor M1 is turned off by the turn-on, the second transistor M2 Turning from on to off, so that the voltage of the second pole of the first transistor M1 is the power supply voltage
  • the second pole of the second transistor M2 is grounded to ensure that the voltage outputted from the output of the first control module (ie, the voltage of the second pole of the first transistor M1) can be an ideal high level (supply voltage)
  • the second control module ie, the voltage of the second pole of the first transistor M1
  • Embodiments of the present invention provide a trigger, which may include FIG. 2 to FIG. 8 .
  • a trigger which may include FIG. 2 to FIG. 8 .
  • FIG. 11 and FIG. 12 illustrate that the flip-flop includes the circuit for detecting timing error and the first trigger module 15 shown in FIG. 2 as an example.
  • the control end 113 of the first control module 11 in the circuit for detecting the timing error is the input end of the trigger, and the control end 151 of the first trigger module 15 is connected to the output end 122 of the second control module 12 (eg
  • the control terminal 151 of the first trigger module 15 is connected to the output terminal 112 of the first control module 11 (as shown in FIG. 12), and the first input terminal 152 of the first trigger module 15 is connected to the power supply voltage.
  • a second input 153 of the trigger module 15 is grounded, and an output 154 of the first trigger module 15 is an output of the flip-flop.
  • the MOS transistor in which the seventh transistor M7 is a P-channel is exemplarily described as an example.
  • the trigger provided by the embodiment of the invention includes the circuit for detecting the timing error as shown in FIG. 7 or FIG. 8 and the trigger of the first trigger module (the control end of the first trigger module is connected to the output of the second control module). Edge trigger.
  • the seventh transistor M7 in FIG. 7 and FIG. 8 can also be an N-channel MOS transistor.
  • the seventh transistor M7 in FIGS. 7 and 8 is an N-channel MOS transistor, the present invention is implemented.
  • the trigger provided by the example includes the circuit for detecting the timing error as shown in FIG. 7 or FIG. 8 and the trigger of the first trigger module (the control end of the first trigger module is connected to the output end of the first control module) may be triggered by a negative edge. Device.
  • the first trigger module 15 of the flip-flop may include a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth.
  • the gate of the tenth transistor M10 is connected to the first clock signal (shown as CLK in FIG.
  • the first pole is connected to the first pole of the thirteenth transistor M13
  • the second pole of the tenth transistor M10 is connected to the second pole of the eleventh transistor M11, the gate of the thirteenth transistor M13, and the gate of the fifteenth transistor M15.
  • the gate of the eleventh transistor M11 is the first control terminal 151 of the first trigger module 15, and the first pole of the eleventh transistor M11 is connected to the twelfth transistor.
  • a second pole of M12; a gate of the twelfth transistor M12 is coupled to a first clock signal (denoted as CLK in FIG.
  • the gate of the fourteenth transistor is connected to the first clock signal (denoted as CLK in FIG. 13), the first pole of the fourteenth transistor M14 is connected to the second pole of the fifteenth transistor M15, and the fourth inverter 155 is
  • the output 1552 is the output 154 of the first trigger module 15.
  • the tenth transistor M10 and the thirteenth transistor M13 in FIG. 13 may be a P-channel MOS transistor, and the eleventh transistor M11, the twelfth transistor M12, and the fourteenth transistor.
  • M14 and the fifteenth transistor M15 may be N-channel MOS transistors.
  • the first trigger module 15 of the flip-flop may include a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth.
  • the gate of the tenth transistor M10 is connected to the first clock signal (shown as CLK in FIG.
  • the first pole is connected to the first pole of the thirteenth transistor M13, the second pole of the tenth transistor M10 is connected to the second pole of the eleventh transistor M11; the gate of the eleventh transistor M11 is the first control of the first trigger module 15 Terminal 151, the first pole of the eleventh transistor M11 is connected to the second pole of the twelfth transistor M12, the gate of the thirteenth transistor M13 and the gate of the fifteenth transistor M15; the gate connection of the twelfth transistor M12 a first clock signal (denoted as CLK in FIG.
  • the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13, and the fourteenth transistor M14 in FIG. 14 may be a P-channel MOS transistor, and the twelfth transistor M12 and the fifteenth transistor M15 may be N-channel MOS transistors.
  • the first control module 11, the second control module 12, the third control module 13, and the first trigger module 15 can be used to implement the functions of the conventional positive-edge flip-flop. That is, when the positive edge of the CLK signal (ie, the CLK signal changes from a low level to a high level), the output of the flip-flop (output 155 of the first trigger module 15) outputs a voltage (in FIGS. 11 and 13). Expressed as Q) equal to the voltage input to the input of the flip-flop (denoted as D in Figure 11 and Figure 13). At the non-positive edge of the CLK signal, the output of the flip-flop is equal to the voltage at the CLK signal. The voltage at the output of this flip-flop at the edge.
  • the first control module 11, the second control module 12, the third control module 13, and the first trigger module 15 can be used to implement the functions of the conventional negative edge trigger. That is, when the negative edge of the CLK signal (ie, the CLK signal changes from a high level to a low level), the output of the flip-flop (output 155 of the first flip-flop module 15) outputs a voltage (in FIGS. 12 and 14). Expressed as Q) equal to the voltage input to the input of the flip-flop (denoted as D in Figure 12 and Figure 14). At the non-negative edge of the CLK signal, the output of the flip-flop is equal to the voltage at the CLK signal. The voltage at the output of this flip-flop at the edge.
  • the first control module 11 , the second control module 12 , the third control module 13 , and the detection module 14 can also form a circuit for detecting a timing error. Therefore, the flip-flops shown in FIG. 11 to FIG. 14 can be used to detect the timing of the chip where the flip-flop is located, in addition to the functions of the conventional positive-edge flip-flop or the conventional negative-edge flip-flop. Moreover, compared with the positive edge flip-flop shown in FIG. 1, the timing error of the chip in which the flip-flop is located can be detected more accurately and quickly.
  • the erroneous circuit and the flip-flop of the first trigger module can be a single-phase clock flip-flop. Compared with the two-phase clock flip-flop shown in FIG. 1, the delay and power consumption are small, and the circuit structure is simple.
  • the embodiment of the invention provides a trigger, which may include the circuit for detecting timing error and the second trigger module shown in FIG. 9 or FIG. 10.
  • FIG. 15 illustrates the trigger including the circuit for detecting timing error and the second trigger module 16 shown in FIG. 9 as an example.
  • the control terminal 113 of the first control module 11 in the circuit for detecting the timing error is the input end of the flip-flop, and the input terminal 161 of the second trigger module 16 is connected to the second pole of the eighth transistor M8, and the second The output 162 of the trigger module 16 is the output of the flip flop.
  • the flip-flop provided by the embodiment of the invention including the circuit for detecting timing errors and the second trigger module as shown in FIG. 9 or 10 may be a positive edge flip-flop.
  • the flip-flop provided by the embodiment of the present invention including the circuit for detecting timing error and the second trigger module as shown in FIG. 9 or 10 may be a negative edge trigger.
  • the second trigger module 16 provided by the embodiment of the present invention includes a fifth inverter 163, a sixth inverter 164, a sixteenth transistor M16, and a seventeenth transistor. M17, seventh inverter 165, eighth inverter 166, and ninth inverter 167.
  • the input end 1631 of the fifth inverter 163 is the input end 161 of the second trigger module 16, and the input end 1631 of the fifth inverter 163 is connected to the output end 1644 of the sixth inverter 164.
  • the fifth inverter The output terminal 1632 of the 163 is connected to the input terminal 1641 of the sixth inverter 164, the first pole of the sixteenth transistor M16 and the second pole of the seventeenth transistor M17; and the first control terminal 1642 of the sixth inverter 164 is connected.
  • the second clock signal (shown as The second clock signal is a clock signal having an opposite phase to the first clock signal period, and the second control terminal 1643 of the sixth inverter 164 is connected to the first clock signal (shown as CLK in FIG.
  • the sixteenth transistor M16 The gate is connected to the second clock signal, and the second pole of the sixteenth transistor M16 is connected to the first pole of the seventeenth transistor M17, the input terminal 1651 of the seventh inverter 165, and the output terminal 1664 of the eighth inverter 166.
  • the gate of the seventeenth transistor M17 is connected to the first clock signal; the output end 1662 of the seventh inverter 166 is connected to the input terminal 1661 of the eighth inverter 166 and the input terminal 1671 of the ninth inverter 167;
  • the first control terminal 1662 of the inverter 166 is connected to the first clock signal, the second control terminal 1663 of the eighth inverter 166 is connected to the second clock signal, and the output terminal 1672 of the ninth inverter 167 is the second trigger module 16 Output 162.
  • the sixth inverter 164 and the eighth inverter 166 in FIG. 16 are different from other inverters involved in the embodiment of the present invention, and other reversers involved in the embodiments of the present invention are
  • the voltage at the input of the input inverter is high, the voltage at the output of the inverter is low; when the voltage at the input of the input inverter is low, the voltage at the input of the inverter is high.
  • the sixth inverter 164 in FIG. 16 can make the sixth inverter 164 have the same operating state as the other inverters involved in the embodiment of the present invention when CLK is at a high level, and the CLK is low.
  • the input terminal 1641 of the sixth inverter 164 is disconnected from the output terminal 1644 of the sixth inverter 164, that is, the voltage of the input terminal 1641 of the sixth inverter 164 is high. Still low, the output 1644 of the sixth inverter 164 has no voltage output.
  • the eighth inverter 166 in FIG. 16 can make the eighth inverter 166 have the same working state as the other inverters according to the embodiment of the present invention when CLK is low, and the CLK is high.
  • the input terminal 1661 of the eighth inverter 166 is disconnected from the output terminal 1664 of the eighth inverter 166, that is, the voltage of the input terminal 1641 of the input eighth inverter 164 is high. Still low, the output 1664 of the eighth inverter 166 has no voltage output.
  • the flip-flop shown in FIG. 16 above is a positive edge flip-flop.
  • the third control module 13 shown in FIG. 16 may be replaced with the second structure described above, and the second trigger module 16 may be replaced with the third structure to obtain a negative edge trigger.
  • the third structure may be specifically: the first control end 1642 of the sixth inverter 164 in FIG.
  • 16 is connected to the first clock signal, and the second control end 1643 of the sixth inverter 164 is connected to the second clock signal;
  • the first control end 1662 of the eighth inverter 166 The second clock signal and the second control terminal 1663 of the eighth inverter 166 are connected to the first clock signal;
  • the gate of the sixteenth transistor M16 is connected to the first clock signal, and the gate of the seventeenth transistor M17 is connected to the second clock. signal.
  • the sixteenth transistor may be a P-channel MOS transistor, and the seventeenth transistor may be an N-channel MOS transistor.
  • the first control module 11, the second control module 12, the third control module 13, and the second trigger module 16 can be used to implement the functions of the conventional positive-edge flip-flop. That is, at the positive edge of the CLK signal (ie, the CLK signal changes from low to high), the output of the flip-flop (output 162 of the second flip-flop module 16) outputs the voltage ( Figures 15 and 16). Expressed as Q) equal to the voltage input to the input of the flip-flop (shown as D in Figure 15 and Figure 16). At the non-positive edge of the CLK signal, the output of the flip-flop is equal to the voltage at the CLK signal. The voltage at the output of this flip-flop at the edge.
  • the first control module 11, the second control module 12, the third control module 13, and the first trigger module 15 can be used to implement the function of the conventional negative edge trigger, that is, the negative edge of the CLK signal (ie, the CLK signal is high)
  • the voltage output from the output of the flip-flop (output 162 of the second flip-flop module 16) (denoted as Q in Figures 15 and 16) is equal to the voltage input to the input of the flip-flop. (shown as D in Figures 15 and 16), at the non-negative edge of the CLK signal, the output of the flip-flop outputs a voltage equal to the voltage output at the output of the flip-flop at the last negative edge of the CLK signal.
  • the first control module 11 , the second control module 12 , the third control module 13 , and the detection module 14 can also form a circuit for detecting a timing error. Therefore, the flip-flops shown in FIG. 13 and FIG. 14 can be used to detect whether the chip in which the flip-flop is located has a timing error in addition to the function of the conventional positive-edge flip-flop, and is compared with the figure.
  • the positive edge trigger shown in 1 can detect the timing of the chip where the trigger is located more accurately and quickly. error.
  • the flip-flops shown in FIGS. 15 and 16 are The first control module 11, the second control module 12, the third control module 13, and the detection module 14 may also constitute a circuit for detecting timing errors, so that the flip-flops shown in FIG. 15 and FIG. 16 can be used to implement the conventional In addition to the function of the negative edge trigger, it can also be used to detect whether the chip in which the trigger is located has a timing error, and can detect the current edge trigger more accurately and quickly than the positive edge trigger shown in FIG. The timing of the chip on which the trigger is located is incorrect.
  • the circuit including the circuit for detecting timing errors and the triggering module of the second trigger module shown in FIG. 9 or FIG. 10 may be a bidirectional phase clock trigger.
  • FIG. 17 illustrates a case where the latch includes the circuit for detecting timing error and the latch module 17 shown in FIG.
  • the control terminal 171 of the latch module 17 is the input end of the latch, the first input terminal 172 of the latch module 17 is connected to the power supply voltage, the second input terminal 173 of the latch module 17 is grounded, and the latch module 17 is An output terminal 174 is connected to the control terminal 113 of the first control module 11 and the control terminal 123 of the second control module 12, and the second output terminal 175 of the latch module 17 is connected to the second electrode of the eighth transistor M8, and the latch module 17 is The third output 176 is the output of the latch.
  • the latch module 17 provided by the embodiment of the present invention includes an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21.
  • the gate of the eighteenth transistor M18 is the control terminal 171 of the latch module 17, the gate of the eighteenth transistor M18 is connected to the gate of the twenty-first transistor M21, and the first extreme latching module of the eighteenth transistor M18 a first input terminal 172 of the 17th, and a first pole of the eighteenth transistor M18 is coupled to the first pole of the twenty-second transistor M22, the eighteenth crystal
  • the second pole of the body tube M18 is connected to the first pole of the nineteenth transistor M19; the gate of the nineteenth transistor M19 is connected to the second clock signal, and the second output terminal 177 of the second extreme latching module of the nineteenth transistor M19
  • the second pole of the nineteenth transistor M19 is connected to the second pole of the twentieth transistor M20, the gate of the twenty-second transistor M22, and the gate of the twenty-third transistor M23; the gate of the twentieth transistor M20 Connecting the first clock signal, the first pole of the twentieth transistor M20 is connected to the second pole of the twenty-first transistor M
  • the eighteenth transistor, the nineteenth transistor, and the twenty-second transistor may each be a P-channel MOS transistor, and the twentieth transistor, the twenty-first transistor, and the second The thirteen transistors can each be an N-channel MOS transistor.
  • the first control module 11, the second control module 12, and the third control module 13 and the latch module 17 are used to implement a conventional latch.
  • the voltage output at the output of the latch ie, the output voltage of the latch, denoted as Q in FIGS. 17 and 18
  • Q the output voltage of the latch
  • the latch is latched when CLK is low (ie, the output voltage at the output of the latch is always equal to CLK going low The voltage output from the output of the previous latch).
  • the first control module 11, the second control module 12, the third control module 13, and the detection module 14 may also constitute a circuit for detecting timing errors. Therefore, the latch shown in FIG. 17 and FIG. 18 can be used to detect whether the chip in which the latch is located has a timing error in addition to the function of the conventional latch, and is compared with The positive edge flip-flop shown in Figure 1 can detect the timing error of the chip where the latch is located more accurately and quickly.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

一种侦测时序错误的电路、触发器和锁存器，涉及电子技术领域，能更准确且快速地侦测芯片的时序错误。该电路包括第一控制模块（11）、第二控制模块（12）、第三控制模块（13）和侦测模块（14）。第一控制模块（11）的输入端（111）连接电源电压（VDD），输出端（112）连接第三控制模块（13）的输入端（131）和侦测模块（14）的第一输入端（141）；第二控制模块（12）的输入端（121）接地（GND），输出端（122）连接第三控制模块（13）的输出端（132）和侦测模块（14）的第二输入端（142）。第一控制模块（11）根据输入其控制端（113）的电压，控制其输出端（112）与其输入端（111）连接或断开；第二控制模块（12）根据输入其控制端（123）的电压，控制其输出端（122）与其输入端（121）断开或连接；第三控制模块（13）在输入其控制端（133）的时钟信号（CLK）为高电平或低电平时，控制其输出端（132）与其输入端（131）断开；侦测模块（14）对第一控制模块（11）和第二控制模块（12）的输出端输出的电压运算，生成指示该电路所在的芯片是否出现时序错误的侦测信号。

Description

一种侦测时序错误的电路、触发器和锁存器 技术领域
本发明实施例涉及电子技术领域，尤其涉及一种侦测时序错误的电路、触发器和锁存器。
背景技术
随着半导体技术的发展，芯片的集成度越来越高，且芯片的功耗也越来越大。
通常，可以通过降低芯片的供电电压来降低芯片的功耗，但是当芯片的供电电压降低到一定程度时，芯片可能会出现时序错误，使得芯片无法正常工作。为了保证芯片能够正常工作，可以在芯片中设置侦测时序错误的正边沿触发器(即时钟信号由低电平变为高电平时，输出信号等于输入信号的触发器)，并在时钟信号为高电平的时间段内，通过侦测该正边沿触发器的输入信号是否发生变化(例如该输入信号由低电平变为高电平，或者由高电平变为低电平)，来侦测芯片是否出现时序错误。示例性的，如图1所示，在时钟信号CLK为高电平的时间段内，晶体管T1与晶体管T4截止，并且在该正边沿触发器的输入信号D发生变化的过程中，由于晶体管T2和晶体管T3会出现同时导通的情况，因此VVDD点和VVSS点的电压将趋近于相等(即VVDD点和VVSS点均为低电平或者均为高电平)，此时该正边沿触发器输出的侦测信号(图1中表示为error)为高电平，即表示芯片出现时序错误。
但是，在图1所示的正边沿触发器中，由于在CLK为高电平的时间段内，晶体管T1和晶体管T4截止，因此在晶体管T2和晶体管T3同时导通的情况下，VVDD点和VVSS点的电压不可能为VDD(理想的高电平)或者GND(理想的低电平)，即VVDD点和VVSS点的电压无法达到理想的高电平或者理想的低电平，如此会使得该正边沿触发器侦测时序错误时的速度较慢，且有可能导致侦测结果 出错。
发明内容
本申请提供一种侦测时序错误的电路、触发器和锁存器，能够更加准确且快速地侦测芯片出现的时序错误。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种侦测时序错误的电路，该侦测时序错误的电路可以包括：第一控制模块、第二控制模块、第三控制模块和侦测模块。其中，第一控制模块的输入端连接电源电压，第一控制模块的输出端连接第三控制模块的输入端和侦测模块的第一输入端，第二控制模块的输入端接地，第二控制模块的输出端连接第三控制模块的输出端和侦测模块的第二输入端。上述第一控制模块用于根据输入第一控制模块的控制端的输入电压，控制第一控制模块的输出端与第一控制模块的输入端连接或者断开；第二控制模块用于根据输入第二控制模块的控制端的输入电压，控制第二控制模块的输出端与第二控制模块的输入端断开或者连接；第三控制模块用于在输入所述第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开；侦测模块用于对第一控制模块的输出端输出的电压和第二控制模块的输出端输出的电压进行运算，以生成用于指示上述侦测时序错误的电路是否出现时序错误的侦测信号。
本申请提供的侦测时序错误的电路，由于在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，可以控制第三控制模块的输出端与第三控制模块的输入端断开，并且第一控制模块可以根据输入第一控制模块的控制端的电压，控制第一控制模块的输出端与第一控制模块的输入端(第一控制模块的输入端连接电源电压)连接或者断开，以及第二控制模块可以根据输入第二控制模块的控制端的电压，控制第二控制模块的输出端与第二控制模块的输入端(第二控制模块的输入端接地)断开或者连接。因此能够使得当输入第一控制模块的控制端的电压和输入第二控制模块的控 制端的电压由低电平变为高电平时，第一控制模块的输出端与第一控制模块的输入端由连接变为断开，第二控制模块的输出端与第二控制模块的输入端由断开变为连接，此时第一控制模块的输出端输出的电压为电源电压(即此时第一控制模块的输出端输出的电压为第一控制模块的输出端与第一控制模块的输入端由连接变为断开之前，第一控制模块的输出端输出的电压)，第二控制模块的输出端接地，以保证第一控制模块的输出端输出的电压可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压可以为理想的低电平(接地)；以及能够使得当输入第一控制模块的控制端的电压和输入第二控制模块的控制端的电压由高电平变为低电平时，第一控制模块的输出端与第一控制模块的输入端由断开变为连接，且第二控制模块的输出端与第二控制模块的输入端由连接变为断开，此时第一控制模块的输出端输出的电压为电源电压，第二控制模块的输出端接地(即此时第二控制模块的输出端输出的电压为第二控制模块的输出端与第二控制模块的输入端由连接变为断开之前，第二控制模块的输出端输出的电压)，以保证第一控制模块的输出端输出的电压可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压可以为理想的低电平(接地)。从而本发明实施例提供的侦测时序错误的电路能够更加准确且快速地侦测该电路所在芯片出现的时序错误。
在第一方面的第一种可能的实现方式中，本申请提供的侦测时序错误的电路中的第一控制模块可以包括第一晶体管，第一晶体管的栅极为第一控制模块的控制端，第一晶体管的第一极为第一控制模块的输入端，第一晶体管的第二极为第一控制模块的输出端。
本申请中，由于第一控制模块可以通过第一晶体管实现，因此可以通过根据输入第一晶体管的栅极的电压，控制第一晶体管导通或者截止的方法，来实现根据第一控制模块的控制端的电压，控制上述第一控制模块的输出端与上述第一控制模块的输入端连接或者断开。
可选的，本申请中，上述第一晶体管可以为P沟道的MOS管。具体的，在输入第一晶体管的栅极的电压为低电平时，可以控制第一晶体管导通；在输入第一晶体的栅极的电压为高电平时，可以控制第一晶体管截止。
在第一方面的第二种可能的实现方式中，本申请提供的侦测时序错误的电路中的第二控制模块可以包括第二晶体管，第二晶体管的栅极为第二控制模块的控制端，第二晶体管的第一极为第二控制模块的输入端，第二晶体管的第二极为第二控制模块的输出端。
本申请中，由于第二控制模块可以通过第二晶体管实现，因此可以通过根据输入第二晶体管的栅极的电压，控制第二晶体管导通或者截止的方法，来实现根据第二控制模块的控制端的电压，控制上述第二控制模块的输出端与上述第二控制模块的输入端连接或者断开。
可选的，本申请中，上述第二晶体管可以为N沟道的MOS管。具体的，在输入第二晶体管的栅极的电压为高电平时，可以控制第二晶体管导通；在输入第二晶体的栅极的电压为低电平时，可以控制第二晶体管截止。
在第一方面的第三种可能的实现方式中，本申请提供的侦测时序错误的电路中的侦测模块可以包括第一反向器和或非门，第一反向器的输入端为侦测模块的第一输入端，第一反向器的输出端连接或非门的第一输入端；或非门的第二输入端为侦测模块的第二输入端，或非门的输出端为侦测模块的输出端。
本申请中，由于第一控制模块的输出端连接第一反向器的输入端，因此第一控制模块的输出端输出的电压可以输入第一反向器的输入端，在经过第一反向器运算后可以输入到或非门的第一输入端，并且由于第二控制模块的输出端连接或非门的第二输入端，因此第二控制模块的输出端输出的电压可以输入或非门的第二输入端，从而或非门可以对输入或非门的第一输入端的电压和输入或非门的第二输入端的电压进行逻辑运算，以生成侦测信号，从而可以侦测上 述侦测时序错误的电路所在的芯片出现的时序错误。
在第一方面的第四种可能的实现方式中，本申请提供的侦测时序错误的电路中的侦测模块可以包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和第二反向器，第三晶体管的栅极连接控制信号，第三晶体管的第一极连接电源电压，第三晶体管的第二极连接第四晶体管的第二极和第二反向器的输入端；第四晶体管的栅极为侦测模块的第一输入端，第四晶体管的第一极连接第五晶体管的第一极；第五晶体管的栅极为侦测模块的第二输入端，第五晶体管的第二极连接第六晶体管的第二极；第六晶体管的栅极连接控制信号，第六晶体管的第一极接地；第二反向器的输出端为侦测模块的输出端。
可选的，本发明实施例中，上述第三晶体管和第五晶体管可以为P沟道的MOS管，上述第四晶体管和第六晶体管可以为N沟道的MOS管。
其中，当上述侦测时序错误的电路在侦测窗口内(即上述控制信号为高电平)时，第三晶体管截止，第六晶体管导通，此时若第一控制模块的输出端输出的电压为高电平(即第四晶体管的栅极为高电平)，第二控制模块的输出端输出的电压为低电平(即第五晶体管的栅极为低电平)，则第四晶体管和第五晶体管导通，由于第四晶体管、第五晶体管和第六晶体管均导通，且第六晶体管的第一极接地，因此第四晶体管的第二极的电压等于第六晶体管的第一极的电压(接地)，即为低电平(即第四晶体管的第二极的电压的逻辑值为0)，因此输入第二反向器的输入端的逻辑值为0，第二反向器的输出端输出的逻辑值为1(即输出侦测信号error＝1)，从而表示上述侦测时序错误的电路所在的芯片出现时序错误。
在第一方面的第五种可能的实现方式中，本申请提供的侦测时序错误的电路中的第三控制模块可以包括第七晶体管，第七晶体管的栅极为第三控制模块的控制端，第七晶体管的第一极为第三控制模块的输入端，第七晶体管的第二极为第三控制模块的输出端。
本申请中，由于第三控制模块可以通过第七晶体管实现，因此可以通过根据在输入第七晶体管的栅极的时钟信号为高电平或者低电平的情况下，控制第七晶体管截止的方法，来实现在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开。
可选的，本申请中，上述第七晶体管可以为P沟道的MOS管，也可以为N沟道的MOS管。具体的，当上述第七晶体管为P沟道的MOS管时，在输入第七晶体管的栅极的时钟信号为高电平的情况下，可以控制第七晶体管截止，在输入第七晶体管的栅极的时钟信号为低电平的情况下，可以控制第七晶体管导通。当上述第七晶体管为N沟道的MOS管时，在输入第七晶体管的栅极的时钟信号为低电平的情况下，可以控制第七晶体管截止，在输入第七晶体管的栅极的时钟信号为高电平的情况下，可以控制第七晶体管导通。
在第一方面的第六种可能的实现方式中，本申请提供的侦测时序错误的电路中的第三控制模块可以包括第八晶体管、第九晶体管和第三反向器；第八晶体管的栅极为第三控制模块的控制端，第八晶体管的第一极为第三控制模块的输入端，第八晶体管的第二极连接第九晶体管的第二极；第三反向器的输入端连接第八晶体管的栅极，第三反相器的输出端连接第九晶体管的栅极；第九晶体管的第一极为第三控制模块的输出端，其中，在输入第三控制模块的控制端的时钟信号为高电平的情况下，第三控制模块控制第三控制模块的输出端与第三控制模块的输入端断开；或者，第九晶体管的栅极为第三控制模块的控制端，第九晶体管的第一极为第三控制模块的输出端，第九晶体管的第二极连接第八晶体管的第二极；第三反向器的输入端连接第九晶体管的栅极，第三反相器的输出端连接第八晶体管的栅极；第八晶体管的第一极为第三控制模块的输入端；其中，在输入第三控制模块的控制端的时钟信号为低电平的情况下，第三控制模块控制第三控制模块的输出端与第三控制模块的输入端断开。
可选的，可以将上述第三控制模块的两种不同的结构中的第一种(即第八晶体管的栅极为第三控制模块的控制端，第八晶体管的第一极为第三控制模块的输入端，第八晶体管的第二极连接第九晶体管的第二极；第三反向器的输入端连接第八晶体管的栅极，第三反相器的输出端连接第九晶体管的栅极；第九晶体管的第一极为第三控制模块的输出端)称为第一结构，可以将上述第三控制模块的两种不同的结构中的第二种(即第九晶体管的栅极为第三控制模块的控制端，第九晶体管的第一极为第三控制模块的输出端，第九晶体管的第二极连接第八晶体管的第二极；第三反向器的输入端连接第九晶体管的栅极，第三反相器的输出端连接第八晶体管的栅极；第八晶体管的第一极为第三控制模块的输入端)称为第二结构。
可选的，上述第一结构，还可以通过另一种结构来实现。具体的，该第三控制模块包括第八晶体管和第九晶体管，并且第八晶体管的栅极为第三控制模块的控制端，第八晶体管的第一极为第三控制模块的输入端，第八晶体管的第二极连接第九晶体管的第二极；第九晶体管的栅极连接与第三控制模块的控制端的时钟信号周期相等相位相反的时钟信号；第九晶体管的第一极为第三控制模块的输出端。
可选的，上述第二结构，也可以通过另一种结构来实现。具体的，该第三控制模块包括第八晶体管和第九晶体管，并且第九晶体管的栅极为第三控制模块的控制端，第九晶体管的第一极为第三控制模块的输出端，第九晶体管的第二极连接第八晶体管的第二极；第八晶体管的栅极连接与第三控制模块的控制端的时钟信号周期相等相位相反的时钟信号；第八晶体管的第一极为第三控制模块的输入端。
本申请中，在第三控制模块的结构为上述第一结构时，可以通过根据在输入第八晶体管的栅极的时钟信号为高电平的情况下，控制第八晶体管和第九晶体管均截止的方法，来实现在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制第三 控制模块的输出端与第三控制模块的输入端断开；在第三控制模块的结构为上述第二结构时，可以通过根据在输入第九晶体管的栅极的时钟信号为低电平的情况下，控制第八晶体管和第九晶体管均截止的方法，来实现在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开。
可选的，本发明实施例中，上述第八晶体管可以为P沟道的MOS管，上述第九晶体管可以为N沟道的MOS管。具体的，在第三控制模块的结构为上述第一结构时，在输入第八晶体管的栅极的时钟信号为高电平的情况下，经过第三反向器之后，输入第九晶体管的栅极的时钟信号为低电平，从而可以在时钟信号为高电平的情况下，控制第八晶体管和第九晶体管均截止。在第三控制模块的结构为上述第二结构时，在输入第九晶体管的栅极的时钟信号为低电平的情况下，经过第三反向器之后，输入第八晶体管的栅极的时钟信号为高电平，从而可以在时钟信号为低电平的情况下，控制第八晶体管和第九晶体管均截止。
第二方面，提供一种触发器，该触发器包括上述第一方面或第一方面的第一种可能的实现方式至第一方面的第五种可能的实现方式中的任意一种可能的实现方式所述的侦测时序错误的电路和第一触发模块，上述电路中的第一控制模块的控制端为触发器的输入端，第一触发模块的控制端连接上述电路中的第二控制模块的输出端或者连接上述电路中的第一控制模块的输出端，第一触发模块的第一输入端连接电源电压，第一触发模块的第二输入端接地，第一触发模块的输出端为触发器的输出端。
可选的，一种可能的实现方式中，在上述第一方面的第五种可能的实现方式中所述的侦测时序错误的电路中的第七晶体管M7为P沟道的MOS管时，本申请提供的包括第一方面的第五种可能的实现方式所述的电路和第一触发模块(该第一触发模块的控制端连接第二控制模块的输出端)的触发器可以为正边沿触发器。
另一种可能的实现方式中，在上述第一方面的第五种可能的实现方式中所述的侦测时序错误的电路中的第七晶体管M7为N沟道的MOS管时，本申请提供的包括第一方面的第五种可能的实现方式所述的电路和第一触发模块(该第一触发模块的控制端连接第一控制模块的输出端)的触发器可以为负边沿触发器。
本申请中，由于上述触发器中包括本申请中的侦测时序错误的电路，因此上述触发器除了可以用于实现传统的正边沿触发器或者传统的负边沿触发器的功能之外，还可以用于侦测该触发器所在的芯片是否出现时序错误。并且，相比于现有技术中可以侦测时序错误的正边沿触发器，可以更加准确且快速地侦测出上述触发器所在的芯片出现的时序错误。
可选的，由于上述触发器可以为单相时钟触发器，因此相比于现有技术中可以侦测时序错误的正边沿触发器为双相时钟触发器来说，本申请的触发器的延迟和功耗较小，且电路结构简单。
第三方面，提供一种触发器，该触发器包括上述第一方面的第六种可能的实现方式所述的侦测时序错误的电路和第二触发模块，上述电路中的第一控制模块的控制端为触发器的输入端，第二触发模块的输入端连接上述电路中的第八晶体管的第二极，第二触发模块的输出端为触发器的输出端。
可选的，一种可能的实现方式中，在上述第一方面的第六种可能的实现方式所述的侦测时序错误的电路中的第三控制模块的结构为上述第一方面的第六种可能的实现方式中所述的第一结构时，本申请提供的包括第一方面的第六种可能的实现方式所述的电路和第二触发模块的触发器可以为正边沿触发器。
另一种可能的实现方式中，在上述第一方面的第六种可能的实现方式所述的侦测时序错误的电路中的第三控制模块的结构为上述第一方面的第六种可能的实现方式中所述的第二结构时，本申请提供的包括第一方面的第六种可能的实现方式所述的电路和第二触发模块的触发器可以为负边沿触发器。
第四方面，提供一种锁存器，该锁存器包括上述第一方面的第六种可能的实现方式所述侦测时序错误的电路和锁存模块，锁存模块的控制端为锁存器的输入端，锁存模块的第一输入端连接电源电压，锁存模块的第二输入端接地，锁存模块的第一输出端连接上述电路中的第一控制模块的控制端和第二控制模块的控制端，锁存模块的第二输出端连接上述电路中的第八晶体管的第二极，锁存模块的第三输出端为锁存器的输出端。
本申请中，上述第三方面和第四方面的技术效果，可以参见对于上述第一方面及其各种可能的实现方式和第二方面的技术效果的描述，此处不再赘述。
附图说明
图1为现有技术提供的一种触发器的示意图；
图2为本发明实施例提供的一种侦测时序错误的电路的示意图一；
图3为本发明实施例提供的一种侦测时序错误的电路的示意图二；
图4为本发明实施例提供的一种侦测时序错误的电路的示意图三；
图5为本发明实施例提供的一种侦测时序错误的电路的示意图四；
图6为本发明实施例提供的一种侦测时序错误的电路的示意图五；
图7为本发明实施例提供的一种侦测时序错误的电路的示意图六；
图8为本发明实施例提供的一种侦测时序错误的电路的示意图七；
图9为本发明实施例提供的一种侦测时序错误的电路的示意图八；
图10为本发明实施例提供的一种侦测时序错误的电路的示意 图九；
图11为本发明实施例提供的一种触发器的示意图一；
图12为本发明实施例提供的一种触发器的示意图二；
图13为本发明实施例提供的一种触发器的示意图三；
图14为本发明实施例提供的一种触发器的示意图四；
图15为本发明实施例提供的一种触发器的示意图五；
图16为本发明实施例提供的一种触发器的示意图六；
图17为本发明实施例提供的一种锁存器的示意图一；
图18为本发明实施例提供的一种锁存器的示意图二。
具体实施方式
本发明实施例中的术语“第一”、“第二”和“第三”等是用于区别不同对象，而不是用于描述特定顺序。例如，第一晶体管、第二晶体管和第三晶体管等是用于区别不同晶体管，而不是用于描述晶体管的特定顺序。
在本发明实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本发明实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本发明实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件。并且根据晶体管在电路中的作用，本发明实施例中采用的所有晶体管的作用主要为开关作用，即本发明实施例中采用的所有晶体管也可以称为开关晶体管。
由于本发明实施例中采用的晶体管的源极和漏极在电路中是对称的，因此晶体管的源极和漏极在电路中是可以互换的。示例性的，在本发明实施例中，为了区分晶体管除栅极之外的两个极，例如为了区分晶体管除栅极之外的源极和漏极，可以用第一极表示源极，第二极表示漏极；或者用第一极表示漏极，第二极表示源极。
此外，本发明实施例所采用的晶体管可以包括P沟道的金属氧 化物半导体(metal oxide semiconductor，MOS)管和N沟道的MOS管两种；其中，P沟道的MOS管在栅极为低电平时导通，在栅极为高电平时截止，N沟道的MOS管在栅极为高电平时导通，在栅极为低电平时截止。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行详细地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
目前，通常通过降低芯片的供电电压来降低芯片的功耗，但是当芯片的供电电压降低到一定程度时，芯片可能会出现时序错误，使得芯片无法正常工作。为了保证芯片能够正常工作，可以在芯片中设置侦测时序错误的正边沿触发器，并在时钟信号为高电平的时间段内，通过侦测该正边沿触发器的输入信号是否发生变化(例如该输入信号由低电平变为高电平，或者由高电平变为低电平)，来侦测芯片是否出现时序错误，以及在侦测到时序错误后，通过调整芯片的供电电压以消除该时序错误。但是，现有技术中在采用上述方法侦测芯片出现的时序错误时速度较慢，且有可能导致侦测结果出错。
为了解决上述问题，本发明实施例提供一种侦测时序错误的电路、触发器和锁存器(触发器和锁存器中包括侦测时序错误的电路)，在侦测时序错误的电路中的第三控制模块的输出端与第三控制模块的输入端断开的情况下，当侦测时序错误的电路中输入第一控制模块的控制端的电压和输入第二控制模块的控制端的电压发生变化(例如由低电平变为高电平，或者由高电平变为低电平)时，能够保证该电路中的第一控制模块的输出端输出的电压可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压可以为理想的低电平(接地)，从而该侦测时序错误的电路能够更加准确且快速地侦测芯片出现的时序错误。具体的，本发明实施例提供的侦测时序错误的电路、触发器和锁存器将在下述实施例中分别进行详细地描述。
本发明实施例提供的侦测时序错误的电路、触发器和锁存器可以应用于各种芯片(也称为集成电路)。示例性的，本发明实施例提供的侦测时序错误的电路、触发器和锁存器可以应用于小规模集成电路(small scale integration，SSI)、中规模集成电路(medium scale integration，MSI)、大规模集成电路(large scale integration，LSI)和超大规模集成电路(very large scale integration，VLSI)等。并且在应用了本发明实施例提供的侦测时序错误的电路、触发器和锁存器的芯片中，当采用降低芯片的供电电压的方法降低芯片的功耗时，在将芯片的供电电压降低到一定程度，导致芯片出现时序错误的情况下，可以准确且快速地侦测芯片出现的时序错误，从而能够快速的调整芯片的供电电压消除该时序错误，进而能够保证芯片的正常工作。
示例性的，本发明实施例中，上述芯片可以为中央处理器(Central Processing Unit，CPU)等各类数字逻辑芯片。
如图2所示，本发明实施例提供一种侦测时序错误的电路，该电路可以包括：第一控制模块11、第二控制模块12、第三控制模块13和侦测模块14。
其中，第一控制模块11的输入端111连接电源电压(图2中表示为VDD)，第一控制模块的输出端112连接第三控制模块13的输入端131和侦测模块14的第一输入端141；第二控制模块12的输入端121接地(图2中表示为GND)，第二控制模块12的输出端122连接第三控制模块13的输出端132和侦测模块14的第二输入端142。
本发明实施例中，上述第一控制模块11，可以用于根据输入第一控制模块11的控制端113的电压(图2中表示为D)，控制第一控制模块11的输出端112与第一控制模块11的输入端111连接或者断开。
上述第二控制模块12，可以用于根据输入第二控制模块12的控制端123的电压(图2中表示为D)，控制第二控制模块12的输出端122与第二控制模块12的输入端121断开或者连接。
上述第三控制模块13，可以用于在输入第三控制模块13的控制端133的时钟信号(图2中表示为CLK)为高电平或者低电平的情况下，控制第三控制模块13的输出端132与第三控制模块13的输入端131断开。
上述侦测模块14，可以用于对第一控制模块11的输出端112输出的电压(即侦测模块14的第一输入端141输入的电压)和第二控制模块12的输出端122输出的电压(即侦测模块14的第二输入端142输入的电压)进行运算，以生成侦测信号，并将该侦测信号(图2中表示为error)通过侦测模块14的输出端143输出，该侦测信号可以用于指示上述侦测时序错误的电路所在的芯片是否出现时序错误。
可选的，上述第一控制模块11的控制端113和上述第二控制模块12的控制端123均可以为上述侦测时序错误的电路的输入端，且上述输入第一控制模块11的控制端113的电压和输入第二控制模块12的控制端123的电压均可以为输入该电路的输入端的电压(图2中表示为D)，即该电路的输入电压。
可选的，在如图2所示的侦测时序错误的电路中，上述侦测模块14可以对第一控制模块11的输出端112输出的电压和第二控制模块12的输出端122输出的电压进行逻辑运算，并根据逻辑运算的结果在侦测模块14的输出端143输出侦测信号。示例性的，假设第一控制模块11的输出端112输出的电压为n0，第二控制模块12的输出端122输出的电压为n1，则侦测模块14的输出端143输出的侦测信号error可以等于n0与n1的非的乘积(即
Figure PCTCN2016108226-appb-000001
)。
可选的，在如图2所示的侦测时序错误的电路中，在第三控制模块的输出端与第三控制模块的输入端断开的情况下，通过侦测D是否发生变化，来侦测上述侦测时序错误的电路所在的芯片是否出现时序错误。示例性的，假设将高电平的逻辑值设置为1，将低电平的逻辑值设置为0，第一控制模块11的输出端112输出的电压为n0，第二控制模块12的输出端122输出的电压为n1。
本发明实施例提供的侦测时序错误的电路，可以在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开。具体的，当该侦测时序错误的电路应用于正边沿触发器时，在输入第三控制模块的控制端的时钟信号为高电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开。当该侦测时序错误的电路应用于负边沿触发器时，在输入第三控制模块的控制端的时钟信号为低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开。下面以本发明实施例提供的侦测时序错误的电路应用于正边沿触发器时，即在输入第三控制模块的控制端的时钟信号为高电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开为例，对本发明实施例提供的侦测时序错误的电路的工作原理进行说明。
具体的，在第三控制模块的输出端与第三控制模块的输入端断开时，上述侦测时序错误的电路的输入电压D存在以下四种可能，下面分别对这四种可能的情况进行详细说明：
第一种可能：D由0变为1(具体是D的逻辑值由0变为1)，第一控制模块的输出端与第一控制模块的输入端由连接变为断开，且第二控制模块的输出端与第二控制模块的输入端由断开变为连接，此时，n0＝1(n0的电压为D由0变为1之前，第一控制模块的输出端输出的电压，由于在D由0变为1之前，第一控制模块的输出端连接电源电压，因此n0＝1)，n1＝0(n1的电压为D由0变为1之后，第二控制模块的输出端输出的电压，由于在D由0变为1之后，第二控制模块的输出端接地，因此n1＝0)，侦测模块输出的侦测信号error等于1与0的非的乘积，error＝1，即表示上述侦测时序错误的电路所在的芯片出现时序错误。
第二种可能：D由1变为0(D的逻辑值由1变为0)，第一控制模块的输出端与第一控制模块的输入端由断开变为连接，且第二控制模块的输出端与第二控制模块的输入端由连接变为断开，此时， n0＝1(n0的电压为D由1变为0之后，第一控制模块的输出端输出的电压，由于在D由0变为1之后，第一控制模块的输出端连接电源电压，因此n0＝1)，n1＝0(n1的电压为D由1变为0之前，第二控制模块的输出端输出的电压，由于在D由1变为0之前，第二控制模块的输出端接地，因此n1＝0)，侦测模块输出的侦测信号error等于1与0的非的乘积，error＝1，即表示上述侦测时序错误的电路所在的芯片出现时序错误。
第三种可能：D不变(D＝0)，第一控制模块的输出端与第一控制模块的输入端始终连接(即第一控制模块的输出端连接电源电压)，且第二控制模块的输出端与第二控制模块的输入端始终断开，此时，n0＝n1＝1(n0与n1的电压为在CLK由0变为1之前，即CLK＝0的情况下，第一控制模块的输出端输出的电压和第二控制模块的输出端输出的电压，由于在CLK＝0的情况下，第三控制模块的输出端与第三控制模块的输入端连接，因此第一控制模块的输出端和第二控制模块的输出端均连接电源电压，所以n0＝n1＝1)，侦测模块输出的侦测信号error等于1与1的非的乘积，error＝0，即表示上述侦测时序错误的电路所在的芯片无时序错误。
第四种可能：D不变(D＝1)，第一控制模块的输出端与第一控制模块的输入端始终断开，且第二控制模块的输出端与第二控制模块的输入端始终连接(即第二控制模块的输出端接地)，此时，n0＝n1＝0(n0与n1的电压为在CLK由0变为1之前，即CLK＝0的情况下，第一控制模块的输出端输出的电压和第二控制模块的输出端输出的电压，由于在CLK＝0的情况下，第三控制模块的输出端与第三控制模块的输入端连接，因此第一控制模块的输出端和第二控制模块的输出端均接地，所以n0＝n1＝0)，侦测模块输出的侦测信号error等于1与1的非的乘积，error＝0，即表示上述侦测时序错误的电路所在的芯片无时序错误。
需要说明的是，一方面，由于通常的正边沿触发器，在CLK＝1(即时钟信号为高电平)的情况下接收到的输入信号D不会发生变 化，因此在CLK＝1的情况下，如果侦测到输入信号D发生变化，则说明正边沿触发器所在的芯片出现了时序错误。另一方面，在电路正常工作时，由于通常的正边沿触发器，在CLK＝0(即时钟信号为低电平)的情况下接收到的输入信号D本身就会也可发生变化，因此在CLK＝0的情况下，即使侦测到输入信号D发生变化，也无法说明正边沿触发器所在的芯片出现了时序错误。因此，当上述侦测时序错误的电路应用于正边沿触发器时，在CLK＝0的情况下，采用该侦测时序错误的电路侦测芯片中是否存在时序错误时，输出侦测信号应表示上述侦测时序错误的电路所在的芯片无时序错误(即error＝0)。
示例性的，在CLK＝0(即时钟信号为低电平)的情况下，由于第三控制模块的输出端与第三控制模块的输入端始终连接(即第一控制模块的输出端和第二控制模块的输出端始终连接)，因此无论D的逻辑值如何变化，n0与n1始终相等，即n0＝n1(具体的，n0＝n1＝1，或者n0＝n1＝0)，这种情况下，侦测模块输出的侦测信号error等于
Figure PCTCN2016108226-appb-000002
即在CLK＝0的情况下，侦测信号error始终等于0。也就是说，在CLK＝0的情况下，采用上述侦测时序错误的电路侦测芯片中是否存在时序错误时，输出侦测信号表示上述侦测时序错误的电路所在的芯片无时序错误(即error＝0)。
需要说明的是，本发明实施例提供的侦测时序错误的电路中，上述仅以在输入第三控制模块的控制端的时钟信号为高电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开时，该侦测时序错误的电路的工作原理为例进行示例性的说明，在输入第三控制模块的控制端的时钟信号为低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开时，该侦测时序错误的电路的工作原理与上述在输入第三控制模块的控制端的时钟信号为高电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开时，该侦测时序错误的电路的工作原理类似，此处不再赘述。
本发明实施例提供的侦测时序错误的电路，由于在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，可以控制第三控制模块的输出端与第三控制模块的输入端断开，并且第一控制模块可以根据输入第一控制模块的控制端的电压，控制第一控制模块的输出端与第一控制模块的输入端(第一控制模块的输入端连接电源电压)连接或者断开，以及第二控制模块可以根据输入第二控制模块的控制端的电压，控制第二控制模块的输出端与第二控制模块的输入端(第二控制模块的输入端接地)断开或者连接。如此能够使得当输入第一控制模块的控制端的电压和输入第二控制模块的控制端的电压由低电平变为高电平时，第一控制模块的输出端与第一控制模块的输入端由连接变为断开，第二控制模块的输出端与第二控制模块的输入端由断开变为连接，此时第一控制模块的输出端输出的电压为电源电压，第二控制模块的输出端接地(即上述的第一种可能)，以保证第一控制模块的输出端输出的电压可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压可以为理想的低电平(接地)；以及能够使得当输入第一控制模块的控制端的电压和输入第二控制模块的控制端的电压由高电平变为低电平时，第一控制模块的输出端与第一控制模块的输入端由断开变为连接，且第二控制模块的输出端与第二控制模块的输入端由连接变为断开，此时第一控制模块的输出端输出的电压为电源电压，第二控制模块的输出端接地(即上述的第二种可能)，以保证第一控制模块的输出端输出的电压可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压可以为理想的低电平(接地)。从而本发明实施例提供的侦测时序错误的电路能够更加准确且快速地侦测该电路所在芯片出现的时序错误。
可选的，结合图2，如图3所示，本发明实施例提供的侦测时序错误的电路中的上述第一控制模块11包括第一晶体管M1。
其中，第一晶体管M1的栅极为上述第一控制模块11的控制端113，第一晶体管M1的第一极为上述第一控制模块11的输入端111， 第一晶体管M1的第二极为上述第一控制模块11的输出端112。
本发明实施例中，由于第一晶体管的栅极为第一控制模块的控制端，第一晶体管的第一极为第一控制模块的输入端，第一晶体管的第二极为第一控制模块的输出端，因此可以通过根据输入第一晶体管的栅极的电压，控制第一晶体管导通或者截止的方法，来实现根据第一控制模块的控制端的电压，控制上述第一控制模块的输出端与上述第一控制模块的输入端连接或者断开。
可选的，本发明实施例中，上述第一晶体管可以为P沟道的MOS管。具体的，在输入第一晶体管的栅极的电压为低电平时，可以控制第一晶体管导通；在输入第一晶体的栅极的电压为高电平时，可以控制第一晶体管截止。
如图3所示，本发明实施例提供的侦测时序错误的电路中，当输入第一晶体管M1的栅极的电压由低电平变为高电平(即D由0变为1)时，第一晶体管M1由导通变为截止，此时第一晶体管M1的第二极输出的电压为D由0变为1之前第一晶体管M1的第二极输出的电压，由于在D由0变为1之前，第一晶体管M1的第二极连接电源电压(即第一晶体管M1导通)，因此，第一晶体管M1的第二极输出的电压为电源电压，即上述第一控制模块11的输出端112输出的电压为电源电压；当输入第一晶体管M1的栅极的电压由高电平变为低电平(D由1变为0)时，第一晶体管M1由截止变为导通，此时第一晶体管M1的第二极输出的电压为D由1变为0之后第一晶体管M1的第二极输出的电压，由于在D由1变为0之后，第一晶体管M1的第二极连接电源电压(即第一晶体管M1导通)，因此，第一晶体管M1的第二极输出的电压为电源电压，即上述第一控制模块11的输出端112输出的电压为电源电压。
可选的，结合图3，如图4所示，本发明实施例提供的侦测时序错误的电路中的上述第二控制模块12包括第二晶体管M2。
其中，第二晶体管M2的栅极为第二控制模块12的控制端123，第二晶体管M2的第一极为第二控制模块12的输入端121，第二晶 体管M2的第二极为第二控制模块12的输出端122。
本发明实施例中，由于第二晶体管的栅极为第二控制模块的控制端，第二晶体管的第一极为第二控制模块的输入端，第二晶体管的第二极为第二控制模块的输出端，因此可以通过根据输入第二晶体管的栅极的电压，控制第二晶体管导通或者截止的方法，来实现根据第二控制模块的控制端的电压，控制上述第二控制模块的输出端与上述第二控制模块的输入端连接或者断开。
可选的，本发明实施例中，上述第二晶体管可以为N沟道的MOS管。具体的，在输入第二晶体管的栅极的电压为高电平时，可以控制第二晶体管导通；在输入第二晶体的栅极的电压为低电平时，可以控制第二晶体管截止。
如图4所示，本发明实施例提供的侦测时序错误的电路中，当输入第二晶体管M2的栅极的电压由低电平变为高电平(即D由0变为1)时，第二晶体管M2由截止变为导通，此时第二晶体管M2的第二极输出的电压为D由0变为1之后第二晶体管M2的第二极输出的电压，由于在D由0变为1之后，第二晶体管M2的第二极接地(即第二晶体管M2导通)，因此，第二晶体管M2的第二极接地，即上述第二控制模块12的输出端122接地；当输入第二晶体管M2的栅极的电压由低电平变为高电平(即D由1变为0)时，第二晶体管M2由导通变为截止，此时第二晶体管M2的第二极输出的电压为D由1变为0之前第二晶体管M2的第二极输出的电压，由于在D由1变为0之前，第二晶体管M2的第二极接地(即第二晶体管M2导通)，因此，第二晶体管M2的第二极接地，即上述第二控制模块12的输出端122接地。
可选的，结合图4，如图5所示，本发明实施例提供的侦测时序错误的电路中的上述侦测模块14包括第一反向器144和或非门145。
其中，第一反向器144的输入端1441为侦测模块14的第一输入端141，第一反向器144的输出端1442连接或非门145的第一输 入端1451；或非门145的第二输入端1452为侦测模块14的第二输入端142，或非门145的输出端1453为侦测模块14的输出端143。
可选的，本发明实施例中，由于第一控制模块的输出端连接第一反向器的输入端，因此第一控制模块的输出端输出的电压(例如记为n0)可以输入第一反向器的输入端，在经过第一反向器运算后可以输入到或非门的第一输入端，并且由于第二控制模块的输出端连接或非门的第二输入端，因此，第二控制模块的输出端输出的电压(例如记为n1)可以输入或非门的第二输入端，从而或非门可以对输入或非门的第一输入端的电压和输入或非门的第二输入端的电压进行逻辑运算，以生成侦测信号。示例性的，假设将高电平的逻辑值设置为1，将低电平的逻辑值设置为0，当n0＝1，n1＝0时，n0经过反向器后逻辑值变为0，此时输入或非门的第一输入端的逻辑值和输入或非门的第二输入端的逻辑值均为0，因此或非门输出的逻辑值为1，也即侦测信号error＝1，如此可以表示上述侦测时序错误的电路所在的芯片出现时序错误。
可选的，本发明实施例提供的侦测时序错误的电路中的侦测模块可以采用上述第一反向器和或非门组成的逻辑电路来实现，也可以采用其他形式的逻辑电路来实现，本发明实施例不限定上述侦测模块中采用的逻辑电路的具体形式，以该逻辑电路的输出端(例如上述或非门的输出端)输出的逻辑值等于输入逻辑电路的第一输入端(例如上述第一反向器的输入端)的逻辑值与输入逻辑电路的第二输入端(例如上述或非门的第二输入端)的逻辑值的非的乘积为准。
可选的，结合图4，如图6所示，本发明实施例提供的侦测时序错误的电路中的上述侦测模块14包括第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6和第二反向器146。
其中，第三晶体管M3的栅极连接控制信号(图6中表示为Ctrl)，第三晶体管M3的第一极连接电源电压，第三晶体管M3的第二极连接第四晶体管M4的第二极和第二反向器146的输入端1461；第四 晶体管M4的栅极为侦测模块14的第一输入端141，第四晶体管M4的第一极连接第五晶体管M5的第一极；第五晶体管M5的栅极为侦测模块14的第二输入端142，第五晶体管M5的第二极连接第六晶体管M6的第二极；和第六晶体管M6的栅极连接控制信号(图6中表示为Ctrl)，第六晶体管M6的第一极接地；第二反向器146的输出端1462为侦测模块14的输出端143。
本发明实施例中，上述控制信号用于确定侦测窗口(即例如侦测时序错误的时间段)。示例性的，当控制信号为高电平(例如控制信号的逻辑值为1)时侦测，当控制信号为低电平(例如逻辑值为0)时停止侦测。
可选的，本发明实施例中，上述第三晶体管和第五晶体管可以为P沟道的MOS管，上述第四晶体管和第六晶体管可以为N沟道的MOS管。具体的，当上述侦测时序错误的电路在侦测窗口内(即Ctrl＝1)时，第三晶体管截止，第六晶体管导通，此时若n0＝1，n1＝0，则第四晶体管和第五晶体管导通，由于第四晶体管、第五晶体管和第六晶体管均导通，且第六晶体管的第一极接地，因此第四晶体管的第二极的电压等于第六晶体管的第一极的电压(接地)为低电平(即第四晶体管的第二极的电压的逻辑值为0)，因此输入第二反向器的输入端的逻辑值为0，第二反向器的输出端输出的逻辑值为1(即输出侦测信号error＝1)，即表示上述侦测时序错误的电路所在的芯片出现时序错误。
可选的，结合图5，如图7所示，或者结合图6，如图8所示，本发明实施例提供的侦测时序错误的电路中的上述第三控制模块13包括第七晶体管M7。
其中，第七晶体管M7的栅极为第三控制模块13的控制端133，第七晶体管M7的第一极为第三控制模块13的输入端131，第七晶体管M7的第二极为第三控制模块13的输出端132。
可选的，本发明实施例中，由于第七晶体管的栅极为第三控制模块的控制端，第七晶体管的第一极为第三控制模块的输入端，第 七晶体管的第二极为第三控制模块的输出端，因此可以输入第七晶体管的栅极的时钟信号为高电平或者低电平的情况下，控制第七晶体管截止的方法，来实现在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开。
可选的，本发明实施例中，上述第七晶体管可以为P沟道的MOS管，也可以为N沟道的MOS管。具体的，当上述第七晶体管为P沟道的MOS管时，在输入第七晶体管的栅极的时钟信号为高电平的情况下，可以控制第七晶体管截止，在输入第七晶体管的栅极的时钟信号为低电平的情况下，可以控制第七晶体管导通；当上述第七晶体管为N沟道的MOS管时，在输入第七晶体管的栅极的时钟信号为低电平的情况下，可以控制第七晶体管截止，在输入第七晶体管的栅极的时钟信号为高电平的情况下，可以控制第七晶体管导通。
需要说明的是，本发明实施例中图7和图8所示的侦测时序错误的电路中是以第七晶体管为P沟道的MOS管为例进行示例性的说明的。
本发明实施例提供的如图7和图8所示的侦测时序错误的电路，在输入第七晶体管M7的栅极的时钟信号为高电平(即CLK为高电平)的情况下，当输入第一晶体管M1的栅极和第二晶体管M2的栅极的电压(D)由低电平变为高电平时，第一晶体管M1由导通变为截止，第二晶体管M2由截止变为导通，使得第一晶体管M1的第二极的电压为电源电压(即此时第一晶体管M1第二极的电压为第一晶体管由导通变为截止之前，第一晶体管M1第二极的电压)，第二晶体管M2的第二极接地，以保证第一控制模块的输出端输出的电压(即第一晶体管M1的第二极的电压)可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压(第二晶体管M2的第二极的电压)可以为理想的低电平(接地)；当输入第一晶体管M1的栅极和第二晶体管M2的栅极的电压(D)由高电平变为低电平时， 第一晶体管M1由截止变为导通，第二晶体管M2由导通变为截止，使得第一晶体管M1的第二极的电压为电源电压，第二晶体管M2的第二极接地(即此时第二晶体管M2第二极的电压为第二晶体管M2由导通变为截止之前，第二晶体管M2第二极的电压)，以保证第一控制模块的输出端输出的电压(即第一晶体管M1的第二极的电压)可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压(第二晶体管M2的第二极的电压)可以为理想的低电平(接地)。从而本发明实施例提供的侦测时序错误的电路能够更加准确且快速地侦测该电路所在芯片出现的时序错误。
可选的，结合图5，如图9所示，或者结合图6，如图10所示，本发明实施例提供的侦测时序错误的电路中的上述第三控制模块13包括第八晶体管M8、第九晶体管M9和第三反向器134。
第八晶体管M8的栅极为第三控制模块13的控制端133，第八晶体管M8的第一极为第三控制模块13的输入端131，第八晶体管M8的第二极连接第九晶体管M9的第二极；第三反向器134的输入端1341连接第八晶体管M8的栅极，第三反相器134的输出端1342连接第九晶体管M9的栅极；第九晶体管M9的第一极为第三控制模块13的输出端132，其中，在输入第三控制模块13的控制端133的时钟信号为高电平的情况下，第三控制模块13控制所述第三控制模块13的输出端132与第三控制模块13的输入端131断开。
在本发明实施例提供的侦测时序错误的电路应用于正边沿触发器时，第三控制模块可以为图9或图10中所示的第三控制模块13的结构(以下称为第一结构)。在本发明实施例提供的侦测时序错误的电路应用于负边沿触发器时，图9或图10中所示的第三控制模块13的结构可以被替换为第二结构。第二结构具体可以为：图9或图10中的第九晶体管M9的栅极为第三控制模块13的控制端133，第九晶体管M9的第一极为第三控制模块13的输出端132，第九晶体管M9的第二极连接第八晶体管M8的第二极；第三反向器134的输入端1341连接第九晶体管M9的栅极，第三反相器134的输出端1342 连接第八晶体管M8的栅极；第八晶体管M8的第一极为第三控制模块13的输入端131；其中，在输入第三控制模块13的控制端133的时钟信号为低电平的情况下，第三控制模块13控制第三控制模块13的输出端132与第三控制模块13的输入端131断开。
可选的，上述第一结构，还可以通过另一种结构来实现。具体的，该第三控制模块包括第八晶体管和第九晶体管，并且第八晶体管的栅极为第三控制模块的控制端，第八晶体管的第一极为第三控制模块的输入端，第八晶体管的第二极连接第九晶体管的第二极；第九晶体管的栅极连接与第三控制模块的控制端的时钟信号周期相等相位相反的时钟信号；第九晶体管的第一极为第三控制模块的输出端。
可选的，上述第二结构，也可以通过另一种结构来实现。具体的，该第三控制模块包括第八晶体管和第九晶体管，并且第九晶体管的栅极为第三控制模块的控制端，第九晶体管的第一极为第三控制模块的输出端，第九晶体管的第二极连接第八晶体管的第二极；第八晶体管的栅极连接与第三控制模块的控制端的时钟信号周期相等相位相反的时钟信号；第八晶体管的第一极为第三控制模块的输入端。
本发明实施例中，在第三控制模块的结构为上述第一结构时，可以通过根据在输入第八晶体管的栅极的时钟信号为高电平的情况下，控制第八晶体管和第九晶体管均截止的方法，来实现在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开；在第三控制模块的结构为上述第二结构时，可以通过根据在输入第九晶体管的栅极的时钟信号为低电平的情况下，控制第八晶体管和第九晶体管均截止的方法，来实现在输入第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制第三控制模块的输出端与第三控制模块的输入端断开。
可选的，本发明实施例中，上述第八晶体管可以为P沟道的 MOS管，上述第九晶体管可以为N沟道的MOS管。具体的，在第三控制模块的结构为上述第一结构时，在输入第八晶体管的栅极的时钟信号为高电平的情况下，经过第三反向器之后，输入第九晶体管的删极的时钟信号为低电平，从而可以在时钟信号为高电平的情况下，控制第八晶体管和第九晶体管均截止。在第三控制模块的结构为上述第二结构时，在输入第九晶体管的栅极的时钟信号为低电平的情况下，经过第三反向器之后，输入第八晶体管的栅极的时钟信号为高电平，从而可以在时钟信号为低电平的情况下，控制第八晶体管和第九晶体管均截止。
可选的，本发明实施例提供的如图9和图10所示的侦测时序错误的电路，在输入第八晶体管M8的栅极的时钟信号为高电平(即CLK为高电平)的情况下，当输入第一晶体管M1的栅极和第二晶体管M2的栅极的电压(D)由低电平变为高电平时，第一晶体管M1由导通变为截止，第二晶体管M2由截止变为导通，使得第一晶体管M1的第二极的电压为电源电压，第二晶体管M2的第二极接地，以保证第一控制模块的输出端输出的电压(即第一晶体管M1的第二极的电压)可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压(第二晶体管M2的第二极的电压)可以为理想的低电平(接地)；当输入第一晶体管M1的栅极和第二晶体管M2的栅极的电压(D)由高电平变为低电平时，第一晶体管M1由截止变为导通，第二晶体管M2由导通变为截止，使得第一晶体管M1的第二极的电压为电源电压，第二晶体管M2的第二极接地，以保证第一控制模块的输出端输出的电压(即第一晶体管M1的第二极的电压)可以为理想的高电平(电源电压)，第二控制模块的输出端输出的电压(第二晶体管M2的第二极的电压)可以为理想的低电平(接地)。从而本发明实施例提供的侦测时序错误的电路能够更加准确且快速地侦测该电路所在芯片出现的时序错误。
本发明实施例提供一种触发器，该触发器可以包括图2至图8 所示的任意一种侦测时序错误的电路和第一触发模块。示例性的，图11和图12以该触发器包括图2所示的侦测时序错误的电路和第一触发模块15为例进行说明。其中，上述侦测时序错误的电路中的第一控制模块11的控制端113为所述触发器的输入端，第一触发模块15的控制端151连接第二控制模块12的输出端122(如图11所示)，或者第一触发模块15的控制端151连接第一控制模块11的输出端112(如图12所示)，第一触发模块15的第一输入端152连接电源电压，第一触发模块15的第二输入端153接地，第一触发模块15的输出端154为该触发器的输出端。
需要说明的是，由于本发明实施例中图7和图8所示的侦测时序错误的电路中是以第七晶体管M7为P沟道的MOS管为例进行示例性的说明的，因此本发明实施例提供的包括如图7或图8所示的侦测时序错误的电路和第一触发模块(该第一触发模块的控制端连接第二控制模块的输出端)的触发器可以为正边沿触发器。
可以理解的是，图7和图8中的第七晶体管M7还可以为N沟道的MOS管，当图7和图8中的第七晶体管M7为N沟道的MOS管时，本发明实施例提供的包括如图7或图8所示的侦测时序错误的电路和第一触发模块(该第一触发模块的控制端连接第一控制模块的输出端)的触发器可以为负边沿触发器。
可选的，结合图11，如图13所示，本发明实施例提供的触发器的第一触发模块15可以包括第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15和第四反向器155。其中，第十晶体管M10的栅极连接第一时钟信号(在图13中表示为CLK)，第十晶体管M10的第一极为第一触发模块15的第一输入端152，并且第十晶体管M10的第一极连接第十三晶体管M13的第一极，第十晶体管M10的第二极连接第十一晶体管M11的第二极、第十三晶体管M13的栅极和第十五晶体管M15的栅极；第十一晶体管M11的栅极为第一触发模块15的第一控制端151，第十一晶体管M11的第一极连接第十二晶体管 M12的第二极；第十二晶体管M12的栅极连接第一时钟信号(在图13中表示为CLK)，第十二晶体管M12的第一极为第一触发模块15的第二输入端153，并且第十二晶体管M12的第一极连接第十五晶体管的第一极；第十三晶体管M13的第二极连接第十四晶体管M14的第二极和第四反向器155的输入端1551；第十四晶体管的栅极连接第一时钟信号(在图13中表示为CLK)，第十四晶体管M14的第一极连接第十五晶体管M15的第二极；第四反向器155的输出端1552为第一触发模块15的输出端154。
可选的，本发明实施例中，图13中上述第十晶体管M10和第十三晶体管M13可以为P沟道的MOS管，上述第十一晶体管M11、第十二晶体管M12、第十四晶体管M14和第十五晶体管M15可以为N沟道的MOS管。
可选的，结合图12，如图14所示，本发明实施例提供的触发器的第一触发模块15可以包括第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15和第四反向器155。其中，第十晶体管M10的栅极连接第一时钟信号(在图12中表示为CLK)，第十晶体管M10的第一极为第一触发模块15的第一输入端152，并且第十晶体管M10的第一极连接第十三晶体管M13的第一极，第十晶体管M10的第二极连接第十一晶体管M11的第二极；第十一晶体管M11的栅极为第一触发模块15的第一控制端151，第十一晶体管M11的第一极连接第十二晶体管M12的第二极、第十三晶体管M13的栅极和第十五晶体管M15的栅极；第十二晶体管M12的栅极连接第一时钟信号(在图12中表示为CLK)，第十二晶体管M12的第一极为第一触发模块15的第二输入端153，并且第十二晶体管M12的第一极连接第十五晶体管的第一极；第十三晶体管M13的第二极连接第十四晶体管M14的第二极；第十四晶体管的栅极连接第一时钟信号(在图12中表示为CLK)，第十四晶体管M14的第一极连接第十五晶体管M15的第二极和第四反向器155的输入端1551；第四反向器155的输出端 1552为第一触发模块15的输出端154。
可选的，本发明实施例中，图14中上述第十晶体管M10、第十一晶体管M11、第十三晶体管M13和第十四晶体管M14可以为P沟道的MOS管，上述第十二晶体管M12和第十五晶体管M15可以为N沟道的MOS管。
在图11和图13所示的触发器中，第一控制模块11、第二控制模块12、第三控制模块13和第一触发模块15，可以用于实现传统的正边沿触发器的功能，即在CLK信号的正边沿(即CLK信号由低电平变为高电平)时，该触发器的输出端(第一触发模块15的输出端155)输出的电压(图11和图13中表示为Q)等于输入该触发器的输入端的电压(图11和图13中表示为D)，在CLK信号的非正边沿时，该触发器的输出端输出的电压等于在CLK信号上一次正边沿时该触发器的输出端输出的电压。
在图12和图14所示的触发器中，第一控制模块11、第二控制模块12、第三控制模块13和第一触发模块15，可以用于实现传统的负边沿触发器的功能，即在CLK信号的负边沿(即CLK信号由高电平变为低电平)时，该触发器的输出端(第一触发模块15的输出端155)输出的电压(图12和图14中表示为Q)等于输入该触发器的输入端的电压(图12和图14中表示为D)，在CLK信号的非负边沿时，该触发器的输出端输出的电压等于在CLK信号上一次负边沿时该触发器的输出端输出的电压。
可选的，在图11至图14所示的触发器中，由于第一控制模块11、第二控制模块12、第三控制模块13和侦测模块14还可以组成侦测时序错误的电路，因此图11至图14所示的触发器除了可以用于实现传统的正边沿触发器或者传统的负边沿触发器的功能之外，还可以用于侦测该触发器所在的芯片是否出现时序错误，并且，相比于图1所示的正边沿触发器，可以更加准确且快速地侦测该触发器所在的芯片出现的时序错误。
本发明实施例提供的包括图2至图8所示的任意一种侦测时序 错误的电路和第一触发模块的触发器，可以为单相时钟触发器，相比于图1所示的双相时钟触发器，延迟和功耗较小，且电路结构简单。
本发明实施例提供一种触发器，该触发器可以包括图9或图10所示的侦测时序错误的电路和第二触发模块。示例性的，图15以该触发器包括图9所示的侦测时序错误的电路和第二触发模块16为例进行说明。其中，上述侦测时序错误的电路中的第一控制模块11的控制端113为所述触发器的输入端，第二触发模块16的输入端161连接第八晶体管M8的第二极，第二触发模块16的输出端162为该触发器的输出端。
需要说明的是，发明实施例提供的包括如图9或10所示的侦测时序错误的电路和第二触发模块的触发器可以为正边沿触发器。
当将图9或图10中的第三控制模块13的结构(即上述第一结构)，替换为上述第二结构时。本发明实施例提供的包括如图9或10所示的侦测时序错误的电路和第二触发模块的触发器可以为负边沿触发器。
可选的，结合图15，如图16所示，本发明实施例提供的第二触发模块16包括第五反向器163、第六反向器164、第十六晶体管M16、第十七晶体管M17、第七反向器165、第八反向器166和第九反向器167。
其中，第五反向器163的输入端1631为第二触发模块16的输入端161，第五反向器163的输入端1631连接第六反向器164的输出端1644，第五反向器163的输出端1632连接第六反向器164的输入端1641、第十六晶体管M16的第一极和第十七晶体管M17的第二极；第六反向器164的第一控制端1642连接第二时钟信号(图16中表示为
Figure PCTCN2016108226-appb-000003
第二时钟信号为与第一时钟信号周期相等相位相反的时钟信号)，第六反向器164的第二控制端1643连接第一时钟信号(图16中表示为CLK)；第十六晶体管M16的栅极连接第二时 钟信号，第十六晶体管M16的第二极连接第十七晶体管M17的第一极、第七反向器165的输入端1651和第八反向器166的输出端1664；第十七晶体管M17的栅极连接第一时钟信号；第七反向器166的输出端1662连接第八反向器166的输入端1661和第九反向器167的输入端1671；第八反向器166的第一控制端1662连接第一时钟信号，第八反向器166的第二控制端1663连接第二时钟信号；第九反向器167的输出端1672为第二触发模块16的输出端162。
可选的，图16中的第六反向器164和第八反向器166与本发明实施例中涉及到的其他反向器不同，本发明实施例中涉及到的其他反向器，在输入反向器的输入端的电压为高电平时，反向器的输出端的电压为低电平；在输入反向器的输入端的电压为低电平时，反向器的输入端的电压为高电平。图16中的第六反向器164可以在CLK为高电平的情况下，使第六反向器164与本发明实施例涉及到的其他反向器的工作状态相同，在CLK为低电平的情况下，使第六反向器164的输入端1641与第六反向器164的输出端1644之间断开，即无论输入第六反向器164的输入端1641的电压为高电平还是低电平，第六反向器164的输出端1644均无电压输出。图16中的第八反向器166可以在CLK为低电平的情况下，使第八反向器166与本发明实施例涉及到的其他反向器的工作状态相同，在CLK为高电平的情况下，使第八反向器166的输入端1661与第八反向器166的输出端1664之间断开，即无论输入第八反向器164的输入端1641的电压为高电平还是低电平，第八反向器166的输出端1664均无电压输出。
需要说明的是，上述图16所示触发器为正边沿触发器。可选的，本发明实施例中可以将图16所示的第三控制模块13替换为上述的第二结构，并且将第二触发模块16替换为第三结构，得到负边沿触发器。其中，第三结构具体可以为：图16中的第六反向器164的第一控制端1642连接第一时钟信号，第六反向器164的第二控制端1643连接的第二时钟信号；第八反向器166的第一控制端1662连 接第二时钟信号和第八反向器166的第二控制端1663连接第一时钟信号；第十六晶体管M16的栅极连接第一时钟信号，第十七晶体管M17的栅极连接第二时钟信号。
可选的，本发明实施例中，上述第十六晶体管可以为P沟道的MOS管，上述第十七晶体管可以为N沟道的MOS管。
在图15和图16所示的触发器中，第一控制模块11、第二控制模块12、第三控制模块13和第二触发模块16，可以用于实现传统的正边沿触发器的功能，即在CLK信号的正边沿(即CLK信号由低电平变为高电平)时，该触发器的输出端(第二触发模块16的输出端162)输出的电压(图15和图16中表示为Q)等于输入该触发器的输入端的电压(图15和图16中表示为D)，在CLK信号的非正边沿时，该触发器的输出端输出的电压等于在CLK信号上一次正边沿时该触发器的输出端输出的电压。
当将图15和图16所示的第三控制模块13替换为上述的第二结构，并且将第二触发模块16替换为第三结构时，在图15和图16所示的触发器中，第一控制模块11、第二控制模块12、第三控制模块13和第一触发模块15，可以用于实现传统的负边沿触发器的功能，即在CLK信号的负边沿(即CLK信号由高电平变为低电平)时，该触发器的输出端(第二触发模块16的输出端162)输出的电压(图15和图16中表示为Q)等于输入该触发器的输入端的电压(图15和图16中表示为D)，在CLK信号的非负边沿时，该触发器的输出端输出的电压等于在CLK信号上一次负边沿时该触发器的输出端输出的电压。
可选的，在图15和图16所示的触发器中，由于第一控制模块11、第二控制模块12、第三控制模块13和侦测模块14还可以组成侦测时序错误的电路，因此图13和图14所示的触发器除了可以用于实现传统的正边沿触发器的功能之外，还可以用于侦测该触发器所在的芯片是否出现时序错误，并且，相比于图1所示的正边沿触发器，可以更加准确且快速地侦测该触发器所在的芯片出现的时序 错误。
当将图15和图16所示的第三控制模块13替换为上述的第二结构，并且将第二触发模块16替换为第三结构时，图15和图16所示的触发器中，由于第一控制模块11、第二控制模块12、第三控制模块13和侦测模块14还可以组成侦测时序错误的电路，因此图15和图16所示的触发器除了可以用于实现传统的负边沿触发器的功能之外，还可以用于侦测该触发器所在的芯片是否出现时序错误，并且，相比于图1所示的正边沿触发器，可以更加准确且快速地侦测该触发器所在的芯片出现的时序错误。
本发明实施例提供的包括图9或图10所示的任意一种侦测时序错误的电路和第二触发模块的触发器可以为双向相时钟触发器。
本发明实施例提供一种锁存器，该锁存器可以包括图9或图10所示的侦测时序错误的电路和锁存模块。示例性的，图17以该锁存器包括图9所示的侦测时序错误的电路和锁存模块17为例进行说明。
其中，锁存模块17的控制端171为锁存器的输入端，锁存模块17的第一输入端172连接电源电压，锁存模块17的第二输入端173接地，锁存模块17的第一输出端174连接第一控制模块11的控制端113和第二控制模块12的控制端123，锁存模块17的第二输出端175连接第八晶体管M8的第二极，锁存模块17的第三输出端176为锁存器的输出端。
可选的，结合图17、如图18所示，本发明实施例提供的锁存模块17包括第十八晶体管M18、第十九晶体管M19，第二十晶体管M20、第二十一晶体管M21、第二十二晶体管M22、第二十三晶体管M23、第十反向器177和第十一反向器178。
其中，第十八晶体管M18的栅极为锁存模块17的控制端171，第十八晶体管M18的栅极连接第二十一晶体管M21的栅极，第十八晶体管M18的第一极为锁存模块17的第一输入端172，并且第十八晶体管M18的第一极连接第二十二晶体管M22的第一极，第十八晶 体管M18的第二极连接第十九晶体管M19的第一极；第十九晶体管M19的栅极连接第二时钟信号，第十九晶体管M19的第二极为锁存模块的第二输出端177，第十九晶体管M19的第二极连接第二十晶体管M20的第二极、第二十二晶体管M22的栅极和、第二十三晶体管M23的栅极；第二十晶体管M20的栅极连接第一时钟信号，第二十晶体管M20的第一极连接第二十一晶体管M21的第二极；第二十一晶体管M21的第一极为锁存模块17的第二输入端173，并且第二十一晶体管M21的第一极连接第二十三晶体管M23的第一极接地；第二十二晶体管M22的第二极连接第二十三晶体管M23的第二极和第十反向器177的输入端1771，第十反向器177的输出端1772连接第十一反向器178的输入端1781，第十一反向器178的输出端1782为锁存模块17的第三输出端176。
可选的，本发明实施例中，上述第十八晶体管、第十九晶体管和第二十二晶体管均可以为P沟道的MOS管，上述第二十晶体管、第二十一晶体管和第二十三晶体管均可以为N沟道的MOS管。
可选的，在图17和图18所示的锁存器中，第一控制模块11、第二控制模块12和第三控制模块13和锁存模块17，用于实现传统的锁存器的功能。即在CLK信号为高电平时，该锁存器的输出端输出的电压(即锁存器的输出电压，图17和图18中表示为Q)等于输入该锁存器的输入端的电压(即锁存器的输入电压，图17和图18中标识为D)；在CLK为低电平时，该锁存器锁存(即锁存器的输出端输出的电压始终等于CLK变为低电平之前锁存器的输出端输出的电压)。
可选的，在图17和图18所示的锁存器中，由于第一控制模块11、第二控制模块12、第三控制模块13和侦测模块14还可以组成侦测时序错误的电路，因此图17和图18所示的锁存器除了可以用于实现传统锁存器的功能之外，还可以用于侦测该锁存器所在的芯片是否出现时序错误，并且，相比于图1所示的正边沿触发器，可以更加准确且快速地侦测该锁存器所在的芯片出现的时序错误。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (10)

  1. 一种侦测时序错误的电路，其特征在于，包括：第一控制模块、第二控制模块、第三控制模块和侦测模块；所述第一控制模块的输入端连接电源电压，所述第一控制模块的输出端连接所述第三控制模块的输入端和所述侦测模块的第一输入端；所述第二控制模块的输入端接地，所述第二控制模块的输出端连接所述第三控制模块的输出端和所述侦测模块的第二输入端；
    所述第一控制模块，用于根据输入所述第一控制模块的控制端的电压，控制所述第一控制模块的输出端与所述第一控制模块的输入端连接或者断开；
    所述第二控制模块，用于根据输入所述第二控制模块的控制端的电压，控制所述第二控制模块的输出端与所述第二控制模块的输入端断开或者连接；
    所述第三控制模块，用于在输入所述第三控制模块的控制端的时钟信号为高电平或者低电平的情况下，控制所述第三控制模块的输出端与所述第三控制模块的输入端断开；
    所述侦测模块，用于对所述第一控制模块的输出端输出的电压和所述第二控制模块的输出端输出的电压进行运算，以生成侦测信号，所述侦测信号用于指示所述电路所在的芯片是否出现时序错误。
  2. 根据权利要求1所述的电路，其特征在于，所述第一控制模块包括第一晶体管；其中，
    所述第一晶体管的栅极为所述第一控制模块的控制端，所述第一晶体管的第一极为所述第一控制模块的输入端，所述第一晶体管的第二极为所述第一控制模块的输出端。
  3. 根据权利要求1或2所述的电路，其特征在于，所述第二控制模块包括第二晶体管；其中，
    所述第二晶体管的栅极为所述第二控制模块的控制端，所述第二晶体管的第一极为所述第二控制模块的输入端，所述第二晶体管的第二极为所述第二控制模块的输出端。
  4. 根据权利要求1至3任意一项所述的电路，其特征在于，所述侦测模块包括第一反向器和或非门；其中，
    所述第一反向器的输入端为所述侦测模块的第一输入端，所述第一反向器的输出端连接所述或非门的第一输入端；所述或非门的第二输入端为所述侦测模块的第二输入端，所述或非门的输出端为所述侦测模块的输出端。
  5. 根据权利要求1至3任意一项所述的电路，其特征在于，所述侦测模块包括第三晶体管、第四晶体管、第五晶体管、第六晶体管和第二反向器；其中，
    所述第三晶体管的栅极连接控制信号，所述第三晶体管的第一极连接电源电压，所述第三晶体管的第二极连接所述第四晶体管的第二极和所述第二反向器的输入端；所述第四晶体管的栅极为所述侦测模块的第一输入端，所述第四晶体管的第一极连接所述第五晶体管的第一极；所述第五晶体管的栅极为所述侦测模块的第二输入端，所述第五晶体管的第二极连接所述第六晶体管的第二极；所述第六晶体管的栅极连接所述控制信号，所述第六晶体管的第一极接地；所述第二反向器的输出端为所述侦测模块的输出端。
  6. 根据权利要求1至5任意一项所述的电路，其特征在于，所述第三控制模块包括第七晶体管；其中，
    所述第七晶体管的栅极为所述第三控制模块的控制端，所述第七晶体管的第一极为所述第三控制模块的输入端，所述第七晶体管的第二极为所述第三控制模块的输出端。
  7. 根据权利要求1至5任意一项所述的电路，其特征在于，所述第三控制模块包括第八晶体管、第九晶体管和第三反向器；
    所述第八晶体管的栅极为所述第三控制模块的控制端，所述第八晶体管的第一极为所述第三控制模块的输入端，所述第八晶体管的第二极连接所述第九晶体管的第二极；所述第三反向器的输入端连接所述第八晶体管的栅极，所述第三反相器的输出端连接所述第九晶体管的栅极；所述第九晶体管的第一极为所述第三控制模块的输出端；其 中，在输入所述第三控制模块的控制端的时钟信号为高电平的情况下，所述第三控制模块控制所述第三控制模块的输出端与所述第三控制模块的输入端断开；
    或者；
    所述第九晶体管的栅极为所述第三控制模块的控制端，所述第九晶体管的第一极为所述第三控制模块的输出端，所述第九晶体管的第二极连接所述第八晶体管的第二极；所述第三反向器的输入端连接所述第九晶体管的栅极，所述第三反相器的输出端连接所述第八晶体管的栅极；所述第八晶体管的第一极为所述第三控制模块的输入端；其中，在输入所述第三控制模块的控制端的时钟信号为低电平的情况下，所述第三控制模块控制所述第三控制模块的输出端与所述第三控制模块的输入端断开。
  8. 一种触发器，其特征在于，包括如权利要求1至6任意一项所述的侦测时序错误的电路和第一触发模块；所述电路中的第一控制模块的控制端为所述触发器的输入端，所述第一触发模块的控制端连接所述电路中的第二控制模块的输出端或者连接所述电路中的第一控制模块的输出端，所述第一触发模块的第一输入端连接电源电压，所述第一触发模块的第二输入端接地，所述第一触发模块的输出端为所述触发器的输出端。
  9. 一种触发器，其特征在于，包括如权利要求7所述的侦测时序错误的电路和第二触发模块；所述电路中的第一控制模块的控制端为所述触发器的输入端，所述第二触发模块的输入端连接所述电路中的第八晶体管的第二极，所述第二触发模块的输出端为所述触发器的输出端。
  10. 一种锁存器，其特征在于，包括如权利要求7所述的侦测时序错误的电路和锁存模块；所述锁存模块的控制端为所述锁存器的输入端，所述锁存模块的第一输入端连接电源电压，所述锁存模块的第二输入端接地，所述锁存模块的第一输出端连接所述电路中的第一控制模块的控制端和所述电路中的第二控制模块的控制端，所述锁存模 块的第二输出端连接所述电路中的第八晶体管的第二极，所述锁存模块的第三输出端为所述锁存器的输出端。
PCT/CN2016/108226 2016-12-01 2016-12-01 一种侦测时序错误的电路、触发器和锁存器 WO2018098773A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201680082727.6A CN108702152A (zh) 2016-12-01 2016-12-01 一种侦测时序错误的电路、触发器和锁存器
PCT/CN2016/108226 WO2018098773A1 (zh) 2016-12-01 2016-12-01 一种侦测时序错误的电路、触发器和锁存器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/108226 WO2018098773A1 (zh) 2016-12-01 2016-12-01 一种侦测时序错误的电路、触发器和锁存器

Publications (1)

Publication Number Publication Date
WO2018098773A1 true WO2018098773A1 (zh) 2018-06-07

Family

ID=62242295

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/108226 WO2018098773A1 (zh) 2016-12-01 2016-12-01 一种侦测时序错误的电路、触发器和锁存器

Country Status (2)

Country Link
CN (1) CN108702152A (zh)
WO (1) WO2018098773A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112309880A (zh) * 2020-02-17 2021-02-02 成都华微电子科技有限公司 芯片边缘损坏检测方法和电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070168848A1 (en) * 2005-12-30 2007-07-19 James Tschanz Error-detection flip-flop
US20110302460A1 (en) * 2010-06-07 2011-12-08 Arm Limited Apparatus and method for detecting an approaching error condition
CN102520754A (zh) * 2011-12-28 2012-06-27 东南大学 一种面向动态电压调节系统的片上监测电路
CN103856192A (zh) * 2012-12-04 2014-06-11 邱沥毅 一种嵌入式脉冲时序电路系统
CN106100617A (zh) * 2016-06-27 2016-11-09 东南大学 一种面向超宽电压的在线监测单元及其控制电路
CN106209060A (zh) * 2016-06-27 2016-12-07 东南大学 一种基于电流监测的时序错误监控系统

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102221671B (zh) * 2011-03-30 2013-04-03 中国科学院计算技术研究所 信号稳定性检测器及时延测试装置
US20140115408A1 (en) * 2012-10-24 2014-04-24 Broadcom Corporation Maximum frequency and minimum voltage discovery

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070168848A1 (en) * 2005-12-30 2007-07-19 James Tschanz Error-detection flip-flop
US20110302460A1 (en) * 2010-06-07 2011-12-08 Arm Limited Apparatus and method for detecting an approaching error condition
CN102520754A (zh) * 2011-12-28 2012-06-27 东南大学 一种面向动态电压调节系统的片上监测电路
CN103856192A (zh) * 2012-12-04 2014-06-11 邱沥毅 一种嵌入式脉冲时序电路系统
CN106100617A (zh) * 2016-06-27 2016-11-09 东南大学 一种面向超宽电压的在线监测单元及其控制电路
CN106209060A (zh) * 2016-06-27 2016-12-07 东南大学 一种基于电流监测的时序错误监控系统

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112309880A (zh) * 2020-02-17 2021-02-02 成都华微电子科技有限公司 芯片边缘损坏检测方法和电路
CN112309880B (zh) * 2020-02-17 2023-05-19 成都华微电子科技股份有限公司 芯片边缘损坏检测方法和电路

Also Published As

Publication number Publication date
CN108702152A (zh) 2018-10-23

Similar Documents

Publication Publication Date Title
TWI531163B (zh) 電壓轉換器
Kim et al. 27.8 a static contention-free single-phase-clocked 24t flip-flop in 45nm for low-power applications
US7538581B2 (en) Fast AC coupled level translator
US7362160B2 (en) Fuse trimming circuit
CN110011653B (zh) 觉知温度不稳定性的电路及其操作方法
US20080204124A1 (en) Fine-Grained Power Management of Synchronous and Asynchronous Datapath Circuits
US6285209B1 (en) Interface circuit and input buffer integrated circuit including the same
TWI642275B (zh) 正反器電路和掃描鏈
US9374093B2 (en) Capacitively coupled input buffer
WO2022100756A1 (zh) 一种芯片端口状态检测电路、芯片及通信终端
US8786307B2 (en) Bias temperature instability-resistant circuits
US20090066385A1 (en) Latch device having low-power data retention
TW201541062A (zh) 單晶片溫度感應裝置
US7119579B2 (en) Supply voltage detection circuit
CN212675016U (zh) 电流监测电路和集成电路
US8736304B2 (en) Self-biased high speed level shifter circuit
JP2009232184A (ja) 半導体集積回路
TWI686045B (zh) 零電流偵測系統
WO2018098773A1 (zh) 一种侦测时序错误的电路、触发器和锁存器
TWI425228B (zh) 具有電源閘邏輯之低功率位準敏感掃描設計閂鎖之方法及系統
US8829944B1 (en) Dynamic power supply switching for clocking signals
US20160191041A1 (en) Circuit and Method for Power-On Reset of an Integrated Circuit
US5818264A (en) Dynamic circuit having improved noise immunity and method therefor
US20180219549A1 (en) Digital Forward Body Biasing in CMOS Circuits
JP2009188496A (ja) レベルシフタ回路及び半導体集積回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16923118

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16923118

Country of ref document: EP

Kind code of ref document: A1