WO2018094728A1 - 动态电源电路及芯片 - Google Patents

动态电源电路及芯片 Download PDF

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Publication number
WO2018094728A1
WO2018094728A1 PCT/CN2016/107473 CN2016107473W WO2018094728A1 WO 2018094728 A1 WO2018094728 A1 WO 2018094728A1 CN 2016107473 W CN2016107473 W CN 2016107473W WO 2018094728 A1 WO2018094728 A1 WO 2018094728A1
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Prior art keywords
voltage
signal
power supply
switch
output
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PCT/CN2016/107473
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English (en)
French (fr)
Inventor
唐样洋
张健
王新入
张臣雄
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华为技术有限公司
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Priority to PCT/CN2016/107473 priority Critical patent/WO2018094728A1/zh
Publication of WO2018094728A1 publication Critical patent/WO2018094728A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

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  • the embodiments of the present application relate to the field of power supplies, and in particular, to a dynamic power circuit and a chip.
  • Low-power design is an important indicator of the design capabilities of integrated circuits.
  • the power consumption of integrated circuits is mainly divided into Dynamic Power Dissipation and Leakage Dissipation. Leakage loss is proportional to the supply voltage at the load. For this reason, reducing the supply voltage is an effective means to reduce the leakage loss of the integrated circuit.
  • Dynamic Power Gating is a low-power technology used to reduce the leakage losses of System on Chips (SoCs).
  • SoCs System on Chips
  • the gated power supply When the load on the SoC is in operation, the gated power supply provides a first supply voltage to meet the normal operation requirements of the load; when the load on the SoC is in a low load state or a standby state, the gated power supply provides a second supply voltage The second supply voltage is lower than the first supply voltage to achieve the purpose of reducing leakage power consumption.
  • the present application provides a dynamic power supply circuit and a chip.
  • the technical solution is as follows:
  • an embodiment of the present application provides a dynamic power supply circuit. Since the leakage loss is proportional to the supply voltage of the load terminal, in order to reduce the leakage loss of the dynamic power supply circuit, it is necessary to reduce the supply voltage of the load in some scenarios, so the design of the dynamic power supply circuit is improved.
  • the circuit includes: a power gate control circuit, a first driving circuit, a power control tube circuit, and a second driving circuit;
  • the power gate control circuit includes at least one first switch tube, the source of the first switch tube is connected to the power supply voltage, the drain of the first switch tube is connected to the supply voltage end of the load, and the gate of the first switch tube is first The first output of the driving circuit is connected;
  • the first driving circuit is configured to output a first voltage signal to the first switching tube, where the first voltage signal is used to drive the first switching tube to be in a saturated conducting state;
  • the power control tube circuit includes at least one second switch tube, the source of the second switch tube is connected to the power supply voltage, the drain of the second switch tube is connected to the supply voltage end of the load, and the gate and the second drive of the second switch tube The second output of the circuit is connected;
  • the second driving circuit is configured to output a second voltage signal or a square wave signal to the second switching tube, the second voltage signal is used to drive the second switching tube to be in an incomplete conduction state, and the square wave signal is used to drive the second switching tube Switch between incomplete conduction state and saturated conduction state.
  • the application outputs a first voltage signal to the first switching tube through the first driving circuit, the first voltage signal is used to drive the first switching tube to be in a saturated conduction state; when the dynamic power supply circuit is operated in the non-power regulating mode, the second voltage is used.
  • the driving circuit outputs a second voltage signal to the second switching tube, and when the dynamic power supply circuit operates in the power control mode, the second driving circuit outputs a square wave signal to the second switching tube, and the square wave signal is used to drive the second switching tube Switching between the incomplete conduction state and the saturation conduction state, when the second switching transistor is in the saturated conduction state, the supply voltage VVDD of the load is a normal power supply voltage, and when the second switching tube is in an incomplete conduction state, At this time, the supply voltage VVDD of the load will be smaller than the normal supply voltage, that is, the voltage of the logic output of the load will decrease, thereby reducing the leakage loss of the load.
  • the square wave signal is a signal formed by alternating high and low levels.
  • the second switch tube when the second voltage signal is a high level signal, the second switch tube is driven to be in an incomplete state, and when the square wave signal is switched from a low level signal to a high level signal, the second is driven.
  • the switch tube is switched from the saturated conduction state to the incomplete conduction state, and when the square wave signal is switched from the high level signal to the low level signal, the second switch tube is driven to switch from the incomplete conduction state to the saturated conduction state;
  • the second switching tube can be driven to switch between the incomplete conduction state and the saturated conduction state, thereby facilitating the control of the second switching tube.
  • the second driving circuit includes: a multiplexer and a voltage drop unit;
  • the first input end of the multiplexer is connected to the second control signal, the second input end of the multiplexer is connected to the timing signal, and the control end of the multiplexer is configured to receive the enable signal;
  • the output of the multiplexer is connected to the input of the voltage drop unit, and the output of the voltage drop unit is the second The output end, the voltage drop unit is configured to: when the enable signal enables the second control signal and the second control signal is the power supply voltage, the power supply voltage is voltage-reduced to the second voltage signal, or when the enable signal enables the timing signal, The timing signal is voltage reduced to a square wave signal.
  • the multiplexer determines whether the second control signal or the timing signal is output to the voltage drop unit, and the voltage drop unit drops the power voltage to the second voltage signal according to the enable signal or drops the timing signal.
  • the square wave signal is such that the second driving circuit drives the second switching transistor to switch between the incomplete conduction state and the saturated conduction state according to the signal of the voltage drop of the voltage drop unit, thereby achieving a reduction of the supply voltage of the load.
  • the voltage drop unit is further configured to: when the enable signal enables the second control signal and the second control signal is low, The second switching tube outputs a third voltage signal, and the third voltage signal is used to control the second switching tube to be in a saturated conduction state.
  • the third voltage signal is output to the second switching tube through the voltage drop unit, so that the second switching tube is in a saturated conduction state, and the second switching tube is already in an on state in an incomplete conduction state. Therefore, when the current of the load is switched from a low current to a high current, the time required for the second switch to switch from the incomplete conduction state to the saturated conduction state is short, and the current switching speed is improved.
  • the multiplexer and the voltage drop unit further includes: a second buffer chain;
  • the second buffer chain includes an even number of inverters connected in series at the beginning and the end.
  • the input of the first inverter is connected to the output of the multiplexer, and the output of the last inverter is connected to the input of the voltage drop unit.
  • the voltage drop unit includes an N-channel metal oxide semiconductor transistor NMOS transistor; the drain of the NMOS transistor and the output of the multiplexer The terminals are connected, the source of the NMOS transistor is connected to the gate of the second switching transistor; the gate of the NMOS transistor is connected to the power supply voltage or the supply voltage terminal of the load, and the sum of the threshold voltage of the NMOS transistor and the threshold voltage of the second switching transistor is greater than 0;
  • the voltage drop unit comprises at least two NMOS transistors connected in series, the drain of the first NMOS transistor is connected to the output of the multiplexer, and the source of the last NMOS transistor is connected to the gate of the second switch transistor; each NMOS The gate of the tube is connected to the supply voltage or the supply voltage terminal of the load, and the NMOS tube The sum of the threshold voltage and the threshold voltage of the second switching transistor is greater than zero.
  • the sum of the threshold voltage of each NMOS transistor and the threshold voltage of the second switching transistor is greater than 0, so that the signal output by the voltage drop unit satisfies the conduction condition for driving the second switch to be turned on, so that the second switch The tube is in an incomplete conduction state or a saturated conduction state.
  • the signal output from the first driving circuit to the first switching transistor is enhanced by an even number of inverters connected in series at the end and the tail, and the interference signal is isolated, thereby improving the driving capability of the first driving circuit.
  • the third driving circuit outputs a third voltage signal to the second switching tube, so that the second switching tube is in a saturated conduction state, and the second switching tube is already in conduction due to the incomplete conduction state. State, so when the current of the load is switched from a low current to a high current, the time required for the second switch to switch from the incomplete conduction state to the saturated conduction state is short, and the current switching speed is improved.
  • the first switch transistor and the second switch transistor are P-channel metal oxide semiconductor transistor PMOS transistors;
  • first switch tube is at least two, at least two first switch tubes are connected in parallel with each other;
  • the at least two second switching tubes are connected in parallel with each other.
  • a chip comprising the dynamic power supply circuit provided by any of the first aspect or the first aspect of the first aspect.
  • FIG. 1 is a circuit diagram of a dynamic power supply circuit provided by an exemplary embodiment of the present application.
  • FIG. 2A is a schematic circuit diagram of a dynamic power supply circuit provided by another exemplary embodiment of the present application.
  • 2B is a waveform signal diagram of a dynamic power supply circuit provided by an exemplary embodiment of the present application.
  • 2C is a waveform signal diagram of a dynamic power supply circuit provided by another exemplary embodiment of the present application.
  • 2D is a waveform signal diagram of a dynamic power supply circuit provided by another exemplary embodiment of the present application.
  • FIG. 3 is a circuit diagram of a dynamic power supply circuit provided by another exemplary embodiment of the present application.
  • FIG. 4 is a circuit diagram of a dynamic power supply circuit provided by another exemplary embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a chip according to an exemplary embodiment of the present application.
  • FIG. 1 shows a circuit schematic of a dynamic power supply circuit provided by an exemplary embodiment of the present application.
  • the dynamic power circuit can be implemented as part of an integrated circuit chip.
  • the dynamic power supply circuit includes a power gate control circuit 10, a first drive circuit 20, a power control tube circuit 30, and a second drive circuit 40.
  • the first switch tube 11 may be a power switch or a transistor under a CMOS (Channel Metal Oxide Semiconductor) process.
  • CMOS Channel Metal Oxide Semiconductor
  • the first switching transistor 11 is exemplified as a PMOS (Positive Channel Metal Oxide Semiconductor) tube, but the specific type of the first switching transistor 11 is not limited.
  • the first switch tubes 11 are at least two, and the first switch tubes 11 are connected in parallel with each other, that is, the source of each of the first switch tubes 11 is connected to the power supply voltage VDD, and each of the first switch tubes 11 The drain is connected to the supply voltage terminal VVDD of the load 50, and the gate of each of the first switching transistors 11 is connected to the first output terminal of the first driving circuit 20.
  • the number of the first driving circuits 20 is less than or equal to the number of the first switching tubes 11 . That is, each of the first driving circuits 20 drives the plurality of first switching tubes 11, or each of the first driving circuits 20 drives a corresponding one of the first switching tubes 11.
  • the first driving circuit 20 is configured to output the same first voltage signal to the two first switching tubes 11 at the same time; for example, when the first switching tube 11 is two, the first driving circuit 20 When the first output ends are also two, the first output end of each of the first driving circuits 20 is connected to the gate of the corresponding one of the first switching tubes 11.
  • the power control tube circuit 30 includes at least one second switch tube 31.
  • the source of the second switch tube 31 is connected to the power supply voltage VDD
  • the drain of the second switch tube 31 is connected to the supply voltage terminal VVDD of the load 50
  • the load 50 is further One end is grounded to VSS
  • the gate of the second switching transistor 31 is connected to the second output end of the second driving circuit 40.
  • the second switch tube 31 may be a power switch or a transistor under a CMOS (Channel Metal Oxide Semiconductor) process.
  • CMOS Channel Metal Oxide Semiconductor
  • the second switching transistor 31 is exemplified as a PMOS (Positive Channel Metal Oxide Semiconductor) tube.
  • PMOS Platinum Channel Metal Oxide Semiconductor
  • the specific type of the second switching tube 31 is not limited.
  • the second switch tube 31 is at least two, and each of the second switch tubes 31 is connected in parallel with each other, that is, the source of each second switch tube 31 is connected to the power supply voltage VDD, and the drain of each of the second switch tubes 31 is connected. Connected to the supply voltage terminal VVDD of the load 50, the gate of each of the second switch transistors 31 is connected to the second output terminal of the second drive circuit 40.
  • the second driving circuit 40 is configured to output a second voltage signal or a square wave signal to the second switching transistor 31, the second voltage signal is used to drive the second switching transistor 31 to be in an incomplete state, and the square wave signal is used to drive the second The switching transistor 31 is switched between an incomplete conduction state and a saturated conduction state.
  • the second driving circuit 40 when the dynamic power circuit operates in the non-power regulation mode, the second driving circuit 40 outputs the second voltage signal to all or part of the second switching transistor 31; when the dynamic power circuit operates in the power regulation mode, The two drive circuit 40 outputs a square wave signal to all or part of the switch tube 31.
  • the second voltage signal is a high level, and a voltage difference between the high level and the power supply voltage VDD is smaller than a threshold voltage V thp of the second switching transistor 31, so that the second switching transistor 31 is incompletely guided. Pass state.
  • the square wave signal is a signal formed by the high level and the low level alternately. The voltage difference between the square wave signal and the power supply voltage VDD is smaller than the threshold voltage V thp of the second switching transistor 31, and the low level signal is the ground voltage.
  • the second switch tube 31 is driven to switch from the saturated conduction state to the incomplete conduction state; when the square wave signal is alternately low by the high level signal In the case of the level signal, the second switching transistor 31 is driven to be switched from the incomplete conduction state to the saturated conduction state.
  • the number of the second driving circuits 40 is less than or equal to the number of the second switching tubes 31. That is, each of the second driving circuits 40 drives the plurality of second switching tubes 31, or each of the second driving circuits 40 drives a corresponding one of the second switching tubes 31.
  • the second switch tube 31 is two and the second drive circuit 40 is one
  • the two second switch tubes 31 are connected in parallel with each other, and the gates of the two second switch tubes 31 and the second drive circuit 40 are respectively
  • the second output circuit 40 is configured to output the same second voltage signal or square wave signal to the two second switch tubes 31 at the same time; for example, when the second switch tube 31 is two, the second When the second output end of the driving circuit 40 is also two, the second output end of each second driving circuit 40 is connected to the gate of the corresponding one of the second switching tubes 31.
  • the second switch tube 31 when the second switch tube 31 is in an incomplete conduction state or in a saturated conduction state, it indicates that the second switch tube 31 is in an on state; however, it is incompletely guided compared to the saturated conduction state.
  • the on state indicates that the second switching transistor 31 is in an on state that is about to be turned off, that is, the difference between the high level and the power supply voltage VDD is smaller than the threshold voltage V thp of the second switching transistor 31 is very small, less than a predetermined threshold. .
  • the first driving circuit outputs a first voltage signal to the first switching tube, the first voltage signal is used to drive the first switching tube to be in a saturated conduction state; when the dynamic power supply circuit operates in a non-power control state In the mode, the second driving circuit outputs a second voltage signal to the second switching tube, and when the dynamic power circuit operates in the power control mode, the second driving circuit outputs a square wave signal to the second switching tube, because the square wave signal is used.
  • Driving the second switch between the incomplete conduction state and the saturated conduction state Switching, when the second switching transistor is in a saturated conduction state, the supply voltage VVDD of the load is a normal power supply voltage. When the second switching transistor is in an incomplete conduction state, the supply voltage VVDD of the load is lower than the normal power supply voltage. That is, the voltage of the logic output of the load is lowered, so that the leakage loss of the load is reduced.
  • FIG. 2A shows a circuit schematic diagram of a dynamic power supply circuit provided by another exemplary embodiment of the present application.
  • the dynamic power circuit can be implemented as part of an integrated circuit chip. In this embodiment:
  • the first driving circuit 20 includes a first buffer chain 21, and the first buffer chain 21 includes an even number of inverters connected in series at the beginning and the end.
  • the input end of the first inverter is the input end of the first driving circuit 20, and the last one is reversed.
  • the output of the phase comparator is the first output of the first drive circuit 20.
  • the input end of the first driving circuit 20 is configured to receive the first control signal V pg and output the first voltage signal V pgsw according to the first control signal V pg .
  • the second drive circuit 40 includes a multiplexer 41 and a voltage drop unit 42.
  • the multiplexer 41 includes a first input, a second input, a control, and an output.
  • the first input terminal is configured to receive the timing signal CLK
  • the second input terminal is configured to receive the second control signal V pd .
  • the control terminal is configured to receive the enable signal EN pd , and output the timing signal CLK to the voltage drop unit 42 when the enable signal EN pd is at the first level; and to the voltage drop unit 42 when the enable signal EN pd is at the second level
  • the second control signal V pd is output.
  • the output of the multiplexer 41 is connected to the input of the voltage drop unit 42.
  • the output of the voltage drop unit 42 is the second output.
  • the voltage drop unit 42 is used to enable the second control signal V at the enable signal EN pd.
  • Pd and the second control signal V pd is the power supply voltage VDD, the power supply voltage VDD is voltage-lowered to the second voltage signal, or when the enable signal EN pd is enabled to the timing signal CLK, the timing signal CLK is voltage-reduced to a square wave signal. .
  • the voltage drop unit 42 is an NMOS transistor.
  • the drain of the NMOS transistor is connected to the output of the multiplexer 41, and the source of the NMOS transistor is connected to the gate of the second switch transistor 31.
  • the gate of the NMOS transistor is connected to the power supply voltage VDD.
  • the sum of the threshold voltage V thn of the NMOS transistor and the threshold voltage V thp of the second switching transistor 31 is greater than zero.
  • a second buffer chain 43 is further included between the multiplexer 41 and the voltage drop unit 42.
  • the second buffer chain 43 includes an even number of inverters connected in series at the beginning and the end, and the input of the first inverter is The outputs of the multiplexer 41 are connected, and the output of the last inverter is connected to the input of the voltage drop unit 42.
  • the dynamic power circuit described above has three different operating modes: a non-power regulated mode, a power regulated mode, and a fast upper current mode.
  • V s (VDD - V thn ) V
  • V thn is an NMOS
  • the first switch tube 11 and the second switch tube 31 are multiple, in the non-power control mode, all or part of the first switch tube 11 is in a saturated conduction state by the control unit according to the configuration, and all of the second The switch tube 12 is in an incomplete conduction state, and the incomplete conduction state is close to the off state.
  • the voltage drop unit 42 drops the timing signal CLK into a square wave signal, the high level of the square wave signal is (VDD-V thn )V, and the low level signal of the square wave signal is the ground voltage, the ground voltage 0V; since the gate voltage of the second switching transistor 31 dynamically changes following the square wave signal, the conduction state and the output current of the second switching transistor 31 also dynamically change, so that part of the time in each clock cycle
  • the load supply voltage VVDD is lower than the voltage in the non-voltage regulation mode, thereby reducing the voltage of the logic output of the load. Since the leakage loss is proportional to the supply voltage VVDD, it is approximately cubic, so the load can be effectively reduced. Leakage loss.
  • the first switch tube 11 and the second switch tube 31 are plural, in the power control mode, all or part of the first switch tube 11 is in a saturated conduction state by the control unit according to the configuration, all or part of The two switching tubes 12 are in a controlled state in which the conduction state is constantly changing.
  • a control unit on the chip controls the dynamic power supply circuit to change from a non-power regulated mode to a fast upper current mode.
  • a first voltage signal V pgsw is 0V
  • the first switch 11 is in the state of saturated conduction
  • multiplexer 41 outputs the enable signal EN pd drop unit to the second control signal 42 V pd; since the second switch 31 When the gate voltage V s is at a low level, all the second switching transistors are in a saturated conduction state, and simultaneously output current to the load simultaneously with all the first switching tubes.
  • the first switch tube 11 and the second switch tube 31 are multiple, in the fast current mode, all the first switch tubes 11 are in a saturated conduction state by the control unit according to the configuration, and all the second switch tubes are controlled. 31 is in a saturated conduction state, thereby achieving a fast current. Since the second switching transistor 31 is changed from the incomplete conduction state to the saturated conduction state, instead of changing from the off state to the saturated conduction state, it has been turned on before the fast upper current, so the second switching transistor 31 is switched to The saturation conduction state can be very short, effectively achieving a fast current.
  • the first switch tube 11 and the second switch tube 31 are both PMOS tubes.
  • the first switch tube 11 is at least two, at least two first switch tubes 11 are connected in parallel with each other;
  • the second switch tube 31 is At least two, at least two second switching tubes 31 are connected in parallel with each other.
  • the gate of the NMOS transistor is not connected to the power supply voltage VDD, but is connected to the supply voltage terminal VVDD of the load.
  • the second switching transistor 31 when the threshold voltage V thn NMOS threshold tube 31 and the second switch value is less than the sum of the voltage V thp 0, in order to ensure that the voltage drop unit 42 outputs the signal satisfies
  • the second switching transistor 31 is driven to be in an on-state of incomplete conduction, and the sum of the threshold voltage V thn of each NMOS transistor connected in series and the threshold voltage V thp of the second switching transistor is greater than 0 by at least two NMOS transistors connected in series Therefore, the second switching transistor 31 is in an incomplete conduction state when the second control signal V pd is the power supply voltage VDD.
  • the voltage drop unit 42 includes at least two NMOS transistors in series, the drain of the first NMOS transistor and the output of the multiplexer 41 (or the output of the second buffer chain 43). Connected, the source of the last NMOS transistor is connected to the gate of the second switching transistor.
  • the gate of each NMOS transistor is connected to the power supply voltage or the supply voltage terminal of the load, and the sum of the threshold voltage of each NMOS transistor and the threshold voltage of the second switch transistor is greater than 0; schematically, when there are n NMOS transistors connected in series, threshold the threshold voltage V thn n th NMOS transistor and a second switching threshold voltage V thp of the tube and the sum is greater than 0, i.e.,
  • the second driving circuit includes: a multiplexer 41, a second buffer chain 42 and a voltage drop unit 43;
  • the multiplexer 41 in the present embodiment has three inputs.
  • the first input terminal of the multiplexer 41 is connected to the power supply voltage VDD
  • the second input terminal of the multiplexer 41 is connected to the timing signal CLK
  • the third input terminal of the multiplexer 41 is connected to the ground voltage VSS.
  • the control terminal of the selector 41 is for receiving the enable signal EN pd .
  • the second buffer chain 42 includes an even number of inverters connected in series at the beginning and the end.
  • the input of the first inverter is connected to the output of the multiplexer 41, and the output of the last inverter is input to the voltage drop unit 43.
  • the output of the voltage drop unit 43 is a second output
  • the second buffer chain 42 is for outputting a signal V pdsw to the voltage drop unit 42
  • the voltage drop unit 42 is for outputting a voltage to the gate of the second switch 31 Signal V s .
  • the present embodiment determines by the multiplexer 41 that the power supply voltage VDD or the timing signal CLK or the ground voltage VSS is output to the voltage drop unit 43, and the voltage drop unit drops the power supply voltage VDD according to the enable signal EN pd. Pressing the second voltage signal V s or the timing signal CLK to a square wave signal or directly outputting the ground voltage VSS, so that the second driving circuit drives the second switching transistor to be incompletely conducting according to the voltage drop signal of the voltage drop unit 43 . Switching between the state and the saturated conduction state, thereby achieving a reduction in the supply voltage of the load.
  • the second driving circuit includes: a multiplexer 41;
  • the first input of the multiplexer 41 is coupled to the signal source of the first signal VDD1
  • the second input of the multiplexer 41 is coupled to the signal source of the second signal CLK1
  • the third input of the multiplexer 41 Connected to the signal source of the third signal VSS
  • the control terminal of the multiplexer 41 is for receiving the enable signal EN pd
  • the output of the multiplexer 41 is the second output terminal.
  • the above three signal sources belong to independent voltage domains, so the voltage drop unit is not required in the implementation.
  • the first signal VDD1 (VDD ⁇ V thn )V
  • the high voltage of the second signal CLK1 is equal to (VDD ⁇ V thn )V
  • the third signal VSS is a low level signal.
  • FIG. 6 is a schematic structural diagram of a chip provided by an exemplary embodiment of the present application.
  • the chip includes a control unit 60 and a dynamic power supply circuit 70; the control unit 60 is connected to an input end of the first drive circuit 20 and an input end of the second drive circuit 40, respectively;
  • the control unit 60 is configured to output a first control signal V pg to the first driving circuit 20, and the control unit 60 is further configured to output the second control signal V pd , the timing signal CLK and the enable signal EN pg to the second driving circuit 40 .
  • the timing signal CLK, and the enable signal EN pd the first level (such as 1), the on-chip control unit 60 controls the dynamic power supply circuit to be in the power regulation mode.
  • the control unit 60 goes to the second drive.
  • the dynamic power supply circuit 70 is the dynamic power supply circuit provided in the above FIG. 1 or FIG. 2A.
  • first, second, third, etc. are objects for distinguishing types, and are not necessarily used to describe a specific order or order, which should be understood.
  • the objects used may be interchanged where appropriate, so that embodiments of the invention can be implemented in other sequences in other embodiments than those illustrated or described herein.

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Abstract

本申请实施例提供了一种动态电源电路及芯片，涉及电源领域，所述电路包括：电源门控管电路、第一驱动电路、电源管制管电路和第二驱动电路；第一驱动电路用于向第一开关管输出第一电压信号，第一电压信号用于驱动第一开关管处于饱和导通状态；第二驱动电路用于向第二开关管输出第二电压信号或方波信号，第二电压信号用于驱动第二开关管处于不完全导通状态，方波信号用于驱动第二开关管在不完全导通状态和饱和导通状态之间切换。本申请通过当第二开关管处于饱和导通状态时，负载的供电电压为正常供电电压，当第二开关管处于不完全导通状态时，此时负载的供电电压会小于正常供电电压，即负载的逻辑输出的电压会降低，从而使得负载的漏电损耗降低。

Description

动态电源电路及芯片 技术领域
本申请实施例涉及电源领域，特别涉及一种动态电源电路及芯片。
背景技术
低功耗设计成为衡量集成电路的设计能力的一个重要指标。集成电路的功耗主要分为动态损耗(Dynamic Power Dissipation)和漏电损耗(Leakage Dissipation)。漏电损耗与负载端的供电电压成正比。为此，降低供电电压是减少集成电路的漏电损耗的有效手段。
动态电源门控(Dynamic Power Gating)是用于降低片上系统(System on Chip，SoC)的漏电损耗的一种低功耗技术。当SoC上的负载处于工作状态时，门控电源提供第一供电电压，以满足负载的正常工作的要求；当SoC上的负载处于低负载状态或待机状态时，门控电源提供第二供电电压，该第二供电电压低于第一供电电压，以达到降低漏电功耗的目的。
现有技术中，通常需要非常复杂的电路设计才能实现动态电源门控，比如对动态电源电路进行大幅度修改，或者增加较多的导通管等。如何提供一种设计相对简单且实用性较高的动态电源电路是急需解决的技术问题。
发明内容
为了解决现有技术的问题，本申请提供了一种动态电源电路及芯片。所述技术方案如下：
第一方面，本申请实施例提供了一种动态电源电路。由于漏电损耗与负载端的供电电压成正比，为了减少动态电源电路的漏电损耗，需要在一些场景下降低负载的供电电压，因此对动态电源电路的设计进行了改进。
作为本申请的一种可能的实现方式，该电路包括：电源门控管电路、第一驱动电路、电源管制管电路和第二驱动电路；
电源门控管电路包括至少一个第一开关管，第一开关管的源极与电源电压相连，第一开关管的漏极与负载的供电电压端相连，第一开关管的栅极与第一 驱动电路的第一输出端相连；
第一驱动电路用于向第一开关管输出第一电压信号，第一电压信号用于驱动第一开关管处于饱和导通状态；
电源管制管电路包括至少一个第二开关管，第二开关管的源极与电源电压相连，第二开关管的漏极与负载的供电电压端相连，第二开关管的栅极与第二驱动电路的第二输出端相连；
第二驱动电路用于向第二开关管输出第二电压信号或方波信号，第二电压信号用于驱动第二开关管处于不完全导通状态，方波信号用于驱动第二开关管在不完全导通状态和饱和导通状态之间切换。
本申请通过第一驱动电路向第一开关管输出第一电压信号，第一电压信号用于驱动第一开关管处于饱和导通状态；当动态电源电路工作在非电源管制模式下时由第二驱动电路向第二开关管输出第二电压信号，当动态电源电路工作在电源管制模式下时由第二驱动电路向第二开关管输出方波信号，由于方波信号用于驱动第二开关管在不完全导通状态和饱和导通状态之间切换，当第二开关管处于饱和导通状态时，负载的供电电压VVDD为正常供电电压，当第二开关管处于不完全导通状态时，此时负载的供电电压VVDD会小于正常供电电压，即负载的逻辑输出的电压会降低，从而使得负载的漏电损耗降低。
在第一方面的第一种可能的实施方式中，第二电压信号为高电平信号，高电平与电源电压的压差小于第二开关管的阈值电压；
方波信号为高电平和低电平交替形成的信号。
在本实施方式中，通过当第二电压信号为高电平信号时，驱动第二开关管处于不完全导通状态，当方波信号由低电平信号切换为高电平信号时，驱动第二开关管由饱和导通状态切换为不完全导通状态，当方波信号由高电平信号切换为低电平信号时，驱动第二开关管由不完全导通状态切换为饱和导通状态；使得通过控制方波信号能够驱动第二开关管在不完全导通状态和饱和导通状态之间切换，方便对第二开关管的控制。
在第一方面的第二种可能的实施方式中，第二驱动电路包括：多路选择器和压降单元；
多路选择器的第一输入端与第二控制信号相连，多路选择器的第二输入端与时序信号相连，多路选择器的控制端用于接收使能信号；
多路选择器的输出端与压降单元的输入端相连，压降单元的输出端是第二 输出端，压降单元用于在使能信号使能第二控制信号且第二控制信号为电源电压时，将电源电压压降为第二电压信号，或者在使能信号使能时序信号时，将时序信号压降为方波信号。
在本实施方式中，通过多路选择器确定向压降单元输出的是第二控制信号还是时序信号，压降单元根据使能信号将电源电压压降为第二电压信号或将时序信号压降为方波信号，使得第二驱动电路根据压降单元压降的信号，驱动第二开关管在不完全导通状态和饱和导通状态之间切换，从而实现负载的供电电压的降低。
结合第一方面的第二种可能的实施方式，在第三种可能的实施方式中，压降单元还用于在使能信号使能第二控制信号且第二控制信号为低电平时，向第二开关管输出第三电压信号，第三电压信号用于控制第二开关管处于饱和导通状态。
在本实施方式中，通过压降单元向第二开关管输出第三电压信号，使得第二开关管处于饱和导通状态，由于第二开关管在不完全导通状态下已经处于导通的状态，因此当负载的电流从低电流切换到高电流时，第二开关管由不完全导通状态切换为饱和导通状态所需要的时间很短，提高了电流的切换速度。
结合第一方面的第二种可能的实施方式，在第四种可能的实施方式中，多路选择器和压降单元之间还包括：第二缓冲链；
第二缓冲链包括偶数个首尾串联的反相器，第一个反相器的输入端与多路选择器的输出端相连，最后一个反相器的输出端与压降单元的输入端相连。
在本实施方式中，通过偶数个首尾串联的反相器增强多路选择器向压降单元输出的信号，隔离了干扰信号，提高了第二驱动电路的驱动能力。
结合第一方面的第二种可能的实施方式，在第五种可能的实施方式中，压降单元包括一个N沟道金属氧化半导体晶体管NMOS管；NMOS管的漏极与多路选择器的输出端相连，NMOS管的源极与第二开关管的栅极相连；NMOS管的栅极与电源电压或负载的供电电压端相连，NMOS管的阈值电压与第二开关管的阈值电压之和大于0；
或，
压降单元包括串联的至少两个NMOS管，第一个NMOS管的漏极与多路选择器的输出端相连，最后一个NMOS管的源极与第二开关管的栅极相连；每个NMOS管的栅极与电源电压或负载的供电电压端相连，各个NMOS管的 阈值电压与第二开关管的阈值电压之和大于0。
在本实施方式中，通过各个NMOS管的阈值电压与第二开关管的阈值电压之和大于0，保证压降单元输出的信号满足驱动第二开关管导通的导通条件，使得第二开关管处于不完全导通状态或者饱和导通状态。
在第一方面的第六种可能的实施方式中，第一驱动电路包括第一缓冲链，第一缓冲链包括偶数个首尾串联的反相器，第一个反相器的输入端是第一驱动电路的输入端，最后一个反相器的输出端是第一输出端。
在本实施方式中，通过偶数个首尾串联的反相器增强第一驱动电路向第一开关管输出的信号，隔离了干扰信号，提高了第一驱动电路的驱动能力。
结合第一方面、第一方面的第一种可能的实施方式、第一方面的第二种可能的实施方式、第一方面的第三种可能的实施方式、第一方面的第四种可能的实施方式、第一方面的第五种可能的实施方式、第一方面的第六种可能的实施方式中的任一种可能的实现方式，在第一方面的第七种可能的实施方式，第二驱动电路还用于向第二开关管输出第三电压信号，第三电压信号用于控制第二开关管处于饱和导通状态。
在本实施方式中，通过第二驱动电路向第二开关管输出第三电压信号，使得第二开关管处于饱和导通状态，由于第二开关管在不完全导通状态下已经处于导通的状态，因此当负载的电流从低电流切换到高电流时，第二开关管由不完全导通状态切换为饱和导通状态所需要的时间很短，提高了电流的切换速度。
结合第一方面、第一方面的第一种可能的实施方式、第一方面的第二种可能的实施方式、第一方面的第三种可能的实施方式、第一方面的第四种可能的实施方式、第一方面的第五种可能的实施方式、第一方面的第六种可能的实施方式、第一方面的第七种可能的实施方式中的任一种可能的实现方式，在第一方面的第八种可能的实施方式，第一开关管和第二开关管均为P沟道金属氧化半导体晶体管PMOS管；
当第一开关管为至少两个时，至少两个第一开关管互相并联；
当第二开关管为至少两个时，至少两个第二开关管互相并联。
第二方面，提供了一种芯片，芯片包括上述第一方面或第一方面中任意一种可能的实施方式所提供的动态电源电路。
附图说明
图1是本申请一个示意性实施例提供的动态电源电路的电路示意图；
图2A是本申请另一个示意性实施例提供的动态电源电路的电路示意图；
图2B是本申请一个示意性实施例提供的动态电源电路所涉及的一个波形信号图；
图2C是本申请另一个示意性实施例提供的动态电源电路所涉及的一个波形信号图；
图2D是本申请另一个示意性实施例提供的动态电源电路所涉及的一个波形信号图；
图3是本申请另一个示意性实施例提供的动态电源电路的电路示意图；
图4是本申请另一个示意性实施例提供的动态电源电路的电路示意图；
图5是本申请另一个示意性实施例提供的动态电源电路所涉及的一个波形信号图；
图6是本申请一个示意性实施例提供的一种芯片的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
请参考图1，其示出了本申请一个示意性实施例提供的动态电源电路的电路示意图。该动态电源电路能够实现成为集成电路芯片中的一部分。该动态电源电路包括：电源门控管电路10、第一驱动电路20、电源管制管电路30和第二驱动电路40。
电源门控管电路10包括至少一个第一开关管11，第一开关管11的源极与电源电压VDD相连，第一开关管11的漏极与负载50的供电电压端VVDD相连，第一开关管11的栅极与第一驱动电路20的第一输出端相连，负载50的另一端接地VSS。
第一开关管11可以是功率开关管(power switches)，也可以是CMOS(Channel Metal Oxide Semiconductor，金属氧化半导体)工艺下的晶体管。示意性的，本实施例中以第一开关管11为PMOS(Positive Channel Metal Oxide Semiconductor，P沟道金属氧化半导体)管来举例说明，但对第一开关管11的具体类型不加以限定。
可选的，第一开关管11为至少两个，各个第一开关管11之间互相并联，即每个第一开关管11的源极与电源电压VDD相连，每个第一开关管11的漏极与负载50的供电电压端VVDD相连，每个第一开关管11的栅极与第一驱动电路20的第一输出端相连。
第一驱动电路20用于向全部或部分第一开关管11输出第一电压信号，第一电压信号用于驱动第一开关管11处于饱和导通状态或截止状态。可选地，第一电压信号是低电平(接地电压VSS)时，第一开关管11处于饱和导通状态；第一电压信号是电源电压VDD时，第一开关管11处于截止状态。可选地，当第一驱动电路20向第一开关管11输出等于电源电压VDD的高电平时，第一开关管11处于截止状态。
可选的，第一驱动电路20的数量小于或等于第一开关管11的数量。也即，每个第一驱动电路20驱动多个第一开关管11，或者，每个第一驱动电路20驱动各自对应的一个第一开关管11。比如，当第一开关管11为两个，第一驱动电路20为一个时，两个第一开关管11互相并联，两个第一开关管11的栅极分别与第一驱动电路20的第一输出端相连；第一驱动电路20用于向同时向两个第一开关管11输出相同的第一电压信号；又比如，当第一开关管11为两个时，第一驱动电路20的第一输出端也为两个时，每个第一驱动电路20的第一输出端与对应的一个第一开关管11的栅极相连。
电源管制管电路30包括至少一个第二开关管31，第二开关管31的源极与电源电压VDD相连，第二开关管31的漏极与负载50的供电电压端VVDD相连，负载50的另一端接地VSS，第二开关管31的栅极与第二驱动电路40的第二输出端相连。
第二开关管31可以是功率开关管(power switches)，也可以是CMOS(Channel Metal Oxide Semiconductor，金属氧化半导体)工艺下的晶体管。示意性的，本实施例中以第二开关管31为PMOS(Positive Channel Metal Oxide Semiconductor，P沟道金属氧化半导体)管来举例。但对第二开关管31的具体类型不加以限定。
可选的，第二开关管31为至少两个，各个第二开关管31互相并联，即每个第二开关管31的源极与电源电压VDD相连，每个第二开关管31的漏极与负载50的供电电压端VVDD相连，每个第二开关管31的栅极与第二驱动电路40的第二输出端相连。
第二驱动电路40用于向第二开关管31输出第二电压信号或方波信号，第二电压信号用于驱动第二开关管31处于不完全导通状态，方波信号用于驱动第二开关管31在不完全导通状态和饱和导通状态之间切换。
可选地，当动态电源电路工作在非电源管制模式下时，第二驱动电路40向全部或部分第二开关管31输出第二电压信号；当动态电源电路工作在电源管制模式下时，第二驱动电路40向全部或部分1开关管31输出方波信号。
可选地，第二电压信号是高电平，且该高电平与电源电压VDD之间的压差小于第二开关管31的阈值电压Vthp，以使得第二开关管31处于不完全导通状态。而方波信号为该高电平与低电平交替形成的信号，方波信号与电源电压VDD之间的压差小于第二开关管31的阈值电压Vthp，低电平信号为接地电压。可选的，当方波信号由低电平信号交替为高电平信号时，驱动第二开关管31由饱和导通状态切换为不完全导通状态；当方波信号由高电平信号交替为低电平信号时，驱动第二开关管31由不完全导通状态切换为饱和导通状态。
可选的，第二驱动电路40的数量小于或等于第二开关管31的数量。也即，每个第二驱动电路40驱动多个第二开关管31，或者，每个第二驱动电路40驱动各自对应的一个第二开关管31。比如，当第二开关管31为两个，第二驱动电路40为一个时，两个第二开关管31互相并联，两个第二开关管31的栅极分别与第二驱动电路40的第二输出端相连；第二驱动电路40用于向同时向两个第二开关管31输出相同的第二电压信号或方波信号；又比如，当第二开关管31为两个时，第二驱动电路40的第二输出端也为两个时，每个第二驱动电路40的第二输出端与对应的一个第二开关管31的栅极相连。
需要说明的是，当第二开关管31处于不完全导通状态或者处于饱和导通状态时，表示第二开关管31均处于导通的状态；但与饱和导通状态相比，不完全导通状态表示第二开关管31处于即将截止的导通状态，即该高电平与电源电压VDD之间的压差小于第二开关管31的阈值电压Vthp的差值非常小，小于预定阈值。
综上所述，本实施例通过第一驱动电路向第一开关管输出第一电压信号，第一电压信号用于驱动第一开关管处于饱和导通状态；当动态电源电路工作在非电源管制模式下时由第二驱动电路向第二开关管输出第二电压信号，当动态电源电路工作在电源管制模式下时由第二驱动电路向第二开关管输出方波信号，由于方波信号用于驱动第二开关管在不完全导通状态和饱和导通状态之间 切换，当第二开关管处于饱和导通状态时，负载的供电电压VVDD为正常供电电压，当第二开关管处于不完全导通状态时，此时负载的供电电压VVDD会小于正常供电电压，即负载的逻辑输出的电压会降低，从而使得负载的漏电损耗降低。
由于第一驱动电路20和第二驱动电路40存在不同的实现方式，请参考图2A，其示出了本申请另一个示意性实施例提供的动态电源电路的电路示意图。该动态电源电路能够实现成为集成电路芯片中的一部分。在本实施例中：
第一驱动电路20包括：第一缓冲链21，第一缓冲链21包括偶数个首尾串联的反相器，第一个反相器的输入端是第一驱动电路20的输入端，最后一个反相器的输出端是第一驱动电路20的第一输出端。其中，第一驱动电路20的输入端用于接收第一控制信号Vpg，并根据第一控制信号Vpg输出第一电压信号Vpgsw。
第二驱动电路40包括：多路选择器41和压降单元42。
多路选择器41包括第一输入端、第二输入端、控制端和输出端。其中，第一输入端用于接收时序信号CLK，第二输入端用于接收第二控制信号Vpd。
控制端用于接收使能信号ENpd，当使能信号ENpd为第一电平时，向压降单元42输出时序信号CLK；当使能信号ENpd为第二电平时，向压降单元42输出第二控制信号Vpd。
多路选择器41的输出端与压降单元42的输入端相连，压降单元42的输出端是第二输出端，压降单元42用于在使能信号ENpd使能第二控制信号Vpd且第二控制信号Vpd为电源电压VDD时，将电源电压VDD压降为第二电压信号，或者在使能信号ENpd使能时序信号CLK时，将时序信号CLK压降为方波信号。
可选地，压降单元42是一个NMOS管。该NMOS管的漏极与多路选择器41的输出端相连，NMOS管的源极与第二开关管31的栅极相连。NMOS管的栅极与电源电压VDD相连。为了在第二控制信号Vpd为电源电压VDD时，第二开关管31仍然能够处于导通状态，NMOS管的阈值电压Vthn与第二开关管31的阈值电压Vthp之和大于0。
可选地，多路选择器41和压降单元42之间还包括：第二缓冲链43。
第二缓冲链43包括偶数个首尾串联的反相器，第一个反相器的输入端与 多路选择器41的输出端相连，最后一个反相器的输出端与压降单元42的输入端相连。
上述动态电源电路具有在三种不同的工作模式：非电源管制模式、电源管制模式和快速上电流模式。
第一，非电源管制模式；
控制单元会向第一驱动电路的输入端输出第一控制信号Vpg＝接地电压VSS，向全部第二驱动电路的输入端输出第二控制信号Vpd＝电源电压VDD，以及使能信号ENpd＝第二电平(比如0)，如图2B所示，此时第一电压信号Vpgsw为0V，第一开关管11处于饱和导通状态，多路选择器41根据使能信号ENpd向压降单元42输出第二控制信号Vpd且Vpd＝VDD，压降单元42将电源电压VDD压降为第二电压信号，此时Vs＝(VDD-Vthn)V，Vthn是NMOS管的阈值电压，此时第二开关管31处于不完全导通状态。
可选地，由于第一开关管11和第二开关管31为多个，在非电源管制模式下，由控制单元根据配置控制全部或部分第一开关管11处于饱和导通状态，全部第二开关管12处于不完全导通状态，该不完全导通状态接近于截止状态。
第二，电源管制模式；
控制单元会向第一驱动电路的输入端输出第一控制信号Vpg＝接地电压VSS，向全部或部分第二驱动电路的输入端输出时序信号CLK，以及使能信号ENpd＝第一电平(比如1)，如图2C所示，第一电压信号Vpgsw为0V，第一开关管11处于饱和导通状态，多路选择器41根据使能信号ENpd向压降单元42输出时序信号CLK，压降单元42将时序信号CLK压降为方波信号，该方波信号中的高电平为(VDD-Vthn)V，该方波信号的低电平信号为接地电压，接地电压为0V；由于第二开关管31的栅极电压跟随方波信号发生动态变化，此时第二开关管31的导通状态和输出电流也会发生动态变化，使得每个时钟周期内的部分时间内，负载的供电电压VVDD小于非电压管制模式时的电压，从而降低负载的逻辑输出的电压，由于漏电损耗与供电电压VVDD呈正比关系，大约为三次方关系，所以能够有效降低负载的漏电损耗。
可选地，由于第一开关管11和第二开关管31为多个，在电源管制模式下，由控制单元根据配置控制全部或部分第一开关管11处于饱和导通状态，全部或部分第二开关管12处于导通状态不断变化的管制状态。
第三，快速上电流模式；
当负载工作在非电源管制模式下时，有时存在快速上电流的需求。芯片上的控制单元控制该动态电源电路从非电源管制模式改变为快速上电流模式。在切换时，控制单元将向全部第二驱动电路的输入端输出第二控制信号Vpd＝接地电压VSS，以及使能信号ENpd＝第二电平(比如0)，如图2D所示，第一电压信号Vpgsw为0V，第一开关管11处于饱和导通状态，多路选择器41根据使能信号ENpd向压降单元42输出第二控制信号Vpd；由于第二开关管31的栅极电压Vs为低电平，则全部第二开关管处于饱和导通状态，与全部第一开关管同时向负载输出电流。
可选地，由于第一开关管11和第二开关管31为多个，在快速上电流模式下，由控制单元根据配置控制全部第一开关管11处于饱和导通状态，全部第二开关管31处于饱和导通状态，从而实现快速上电流。由于第二开关管31是从不完全导通状态变为饱和导通状态，而不是从截止状态变为饱和导通状态，在快速上电流之前已经被导通，所以第二开关管31切换至饱和导通状态的时间会非常短，从而有效地实现快速上电流。
可选的，第一开关管11和第二开关管31均为PMOS管，当第一开关管11为至少两个时，至少两个第一开关管11互相并联；当第二开关管31为至少两个时，至少两个第二开关管31互相并联。
作为图2A实施例的一种可替代的实现方式，如图3所示，NMOS管的栅极不与电源电压VDD相连，而是与负载的供电电压端VVDD相连。
作为图2A实施例的另一种可替代的实现方式，当NMOS管的阈值电压Vthn与第二开关管31的阈值电压Vthp之和小于0时，为了保证压降单元42输出的信号满足驱动第二开关管31处于不完全导通的导通条件，通过串联的至少两个NMOS管，使得串联的各个NMOS管的阈值电压Vthn与第二开关管的阈值电压Vthp之和大于0，从而使得第二开关管31在第二控制信号Vpd为电源电压VDD时，处于不完全导通状态。换句话说，在本实现方式中，压降单元42包括串联的至少两个NMOS管，第一个NMOS管的漏极与多路选择器41的输出端(或第二缓冲链43的输出端)相连，最后一个NMOS管的源极与第二开关管的栅极相连。每个NMOS管的栅极与电源电压或负载的供电电压端相连，各个NMOS管的阈值电压与第二开关管的阈值电压之和大于0；示意性的，当存在n个NMOS管串联时，n个NMOS管的阈值电压Vthn与第二开关 管的阈值电压Vthp之和大于0，即
Figure PCTCN2016107473-appb-000001
作为图2A实施例的另一种可替代的实现方式中，结合参考图4，第二驱动电路包括：多路选择器41、第二缓冲链42和压降单元43；
与图2A实施例不同的是，本实现方式中的多路选择器41具有三个输入端。多路选择器41的第一输入端与电源电压VDD相连，多路选择器41的第二输入端与时序信号CLK相连，多路选择器41的第三输入端与接地电压VSS相连，多路选择器41的控制端用于接收使能信号ENpd。
第二缓冲链42包括偶数个首尾串联的反相器，第一个反相器的输入端与多路选择器41的输出端相连，最后一个反相器的输出端与压降单元43的输入端相连，压降单元43的输出端是第二输出端，第二缓冲链42用于向压降单元42输出信号Vpdsw，压降单元42用于向第二开关管31的栅极输出电压信号Vs。
压降单元43用于在使能信号ENpd使能电源电压VDD时，将电源电压VDD压降为第二电压信号，或者在使能信号ENpd使能时序信号CLK时，将时序信号压降为方波信号，或者在使能信号ENpd使能接地电压VSS时，输出接地电压VSS，即0V；其中，第二电压信号小于电源电压VDD与第二开关管的阈值电压Vthp之和，此时Vs＝(VDD-Vthn)V；时序信号CLK的高电平信号小于电源电压VDD与第二开关管的阈值电压Vthp之和，时序信号CLK的高电平信号也为(VDD-Vthn)V。
综上所述，本实施例通过多路选择器41确定向压降单元43输出的是电源电压VDD或时序信号CLK或接地电压VSS，压降单元根据使能信号ENpd将电源电压VDD压降为第二电压信号Vs或将时序信号CLK压降为方波信号或直接输出接地电压VSS，使得第二驱动电路根据压降单元43压降的信号，驱动第二开关管在不完全导通状态和饱和导通状态之间切换，从而实现负载的供电电压的降低。
作为图2A实施例的另一种可替代的实现方式中，结合参考图5，第二驱动电路包括：多路选择器41；
多路选择器41的第一输入端与第一信号VDD1的信号源相连，多路选择器41的第二输入端与第二信号CLK1的信号源相连，多路选择器41的第三输入端与第三信号VSS的信号源相连，多路选择器41的控制端用于接收使能信号ENpd，多路选择器41的输出端是第二输出端。
与上述实现方式不同的是，上述三个信号源属于独立的电压域，所以本实现方式中不需要压降单元。
其中，第一信号VDD1＝(VDD-Vthn)V，第二信号CLK1的高电压等于(VDD-Vthn)V，第三信号VSS为低电平信号。
请参考图6，其示出了本申请一个示意性实施例提供的一种芯片的结构示意图。
该芯片包括控制单元60和动态电源电路70；控制单元60分别与第一驱动电路20的输入端和第二驱动电路40的输入端相连；
控制单元60用于向第一驱动电路20输出第一控制信号Vpg，控制单元60还用于向第二驱动电路40输出第二控制信号Vpd、时序信号CLK和使能信号ENpg。
当需要动态电源电路工作在非电源管制模式下时，控制单元60向第一驱动电路20的输入端输出第一控制信号Vpg＝接地电压VSS，向全部第二驱动电路40的输入端输出第二控制信号Vpd＝电源电压VDD，以及使能信号ENpd＝第二电平(比如0)，芯片上的控制单元60控制该动态电源电路处于非电源管制模式。
当需要动态电源电路工作在电源管制模式下时，控制单元60向第一驱动电路20的输入端输出第一控制信号Vpg＝接地电压VSS，向全部或部分第二驱动电路40的输入端输出时序信号CLK，以及使能信号ENpd＝第一电平(比如1)，芯片上的控制单元60控制该动态电源电路处于电源管制模式。
当动态电源电路工作在非电源管制模式下时，有时存在快速上电流的需求，当需要动态电源电路的工作模式从非电源管制模式改变为快速上电流模式时，控制单元60向全部第二驱动电路40的输入端输出第二控制信号Vpd＝接地电压VSS，以及使能信号ENpd＝第二电平(比如0)，芯片上的控制单元60控制该动态电源电路从非电源管制模式改变为快速上电流模式。
动态电源电路70为上述图1或图2A提供的动态电源电路。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘 或光盘等。
在本发明实施例中，术语“第一”、“第二”、“第三”等(如果存在)是用于区别类型的对象，而不必用于描述特定的顺序或先后次序，应该理解这样使用的对象在适当情况下可以互换，以便本发明实施例能够在除了本文图示或描述的实施例之外的其它实施例中以其它顺序实施。
以上所述仅为本申请的较佳实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种动态电源电路，其特征在于，所述电路包括：电源门控管电路、第一驱动电路、电源管制管电路和第二驱动电路；
    所述电源门控管电路包括至少一个第一开关管，所述第一开关管的源极与电源电压相连，所述第一开关管的漏极与负载的供电电压端相连，所述第一开关管的栅极与所述第一驱动电路的第一输出端相连；
    所述第一驱动电路用于向所述第一开关管输出第一电压信号，所述第一电压信号用于驱动所述第一开关管处于饱和导通状态；
    所述电源管制管电路包括至少一个第二开关管，所述第二开关管的源极与所述电源电压相连，所述第二开关管的漏极与所述负载的供电电压端相连，所述第二开关管的栅极与所述第二驱动电路的第二输出端相连；
    所述第二驱动电路用于向所述第二开关管输出第二电压信号或方波信号，所述第二电压信号用于驱动所述第二开关管处于不完全导通状态，所述方波信号用于驱动所述第二开关管在所述不完全导通状态和饱和导通状态之间切换。
  2. 根据权利要求1所述的动态电源电路，其特征在于，
    所述第二电压信号为高电平，所述高电平与所述电源电压的压差小于所述第二开关管的阈值电压；
    所述方波信号为所述高电平和低电平交替形成的信号。
  3. 根据权利要求1所述的动态电源电路，其特征在于，所述第二驱动电路包括：多路选择器和压降单元；
    所述多路选择器的第一输入端与第二控制信号相连，所述多路选择器的第二输入端与时序信号相连，所述多路选择器的控制端用于接收使能信号；
    所述多路选择器的输出端与所述压降单元的输入端相连，所述压降单元的输出端是所述第二输出端，所述压降单元用于在所述使能信号使能所述第二控制信号且所述第二控制信号为所述电源电压时，将所述电源电压压降为所述第二电压信号，或者在所述使能信号使能所述时序信号时，将所述时序信号压降为所述方波信号。
  4. 根据权利要求3所述的动态电源电路，其特征在于，所述压降单元还用于在所述使能信号使能所述第二控制信号且所述第二控制信号为低电平时，向所述第二开关管输出第三电压信号，所述第三电压信号用于控制所述第二开关管处于所述饱和导通状态。
  5. 根据权利要求3所述的动态电源电路，其特征在于，所述多路选择器和所述压降单元之间还包括：第二缓冲链；
    所述第二缓冲链包括偶数个首尾串联的反相器，第一个所述反相器的输入端与所述多路选择器的输出端相连，最后一个所述反相器的输出端与所述压降单元的输入端相连。
  6. 根据权利要求3所述的动态电源电路，其特征在于，
    所述压降单元包括一个N沟道金属氧化半导体晶体管NMOS管；所述NMOS管的漏极与所述多路选择器的输出端相连，所述NMOS管的源极与所述第二开关管的栅极相连；所述NMOS管的栅极与所述电源电压或所述负载的供电电压端相连，所述NMOS管的阈值电压与所述第二开关管的阈值电压之和大于0；
    或，
    所述压降单元包括串联的至少两个NMOS管，第一个所述NMOS管的漏极与所述多路选择器的输出端相连，最后一个所述NMOS管的源极与所述第二开关管的栅极相连；每个所述NMOS管的栅极与所述电源电压或所述负载的供电电压端相连，各个所述NMOS管的阈值电压与所述第二开关管的阈值电压之和大于0。
  7. 根据权利要求1所述的动态电源电路，其特征在于，所述第一驱动电路包括第一缓冲链，所述第一缓冲链包括偶数个首尾串联的反相器，第一个所述反相器的输入端是所述第一驱动电路的输入端，最后一个所述反相器的输出端是所述第一输出端。
  8. 根据权利要求1至7任一所述的动态电源电路，其特征在于，所述第二驱动电路还用于向所述第二开关管输出第三电压信号，所述第三电压信号用于 控制所述第二开关管处于所述饱和导通状态。
  9. 根据权利要求1至7任一所述的动态电源电路，其特征在于，所述第一开关管和所述第二开关管均为P沟道金属氧化半导体晶体管PMOS管；
    当所述第一开关管为至少两个时，至少两个所述第一开关管互相并联；
    当所述第二开关管为至少两个时，至少两个所述第二开关管互相并联。
  10. 一种芯片，其特征在于，所述芯片包括如权利要求1至9任一所述的动态电源电路。
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CN113437762B (zh) * 2021-07-30 2023-11-03 易事特集团股份有限公司 一种光伏逆变电源系统
CN116225197A (zh) * 2023-05-08 2023-06-06 核芯互联科技(青岛)有限公司 电压模式驱动方法及电路
CN116225197B (zh) * 2023-05-08 2023-08-29 核芯互联科技(青岛)有限公司 电压模式驱动方法及电路

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