WO2018086395A1 - 半导体存储器、半导体存储模块及其制作方法 - Google Patents

半导体存储器、半导体存储模块及其制作方法 Download PDF

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WO2018086395A1
WO2018086395A1 PCT/CN2017/096756 CN2017096756W WO2018086395A1 WO 2018086395 A1 WO2018086395 A1 WO 2018086395A1 CN 2017096756 W CN2017096756 W CN 2017096756W WO 2018086395 A1 WO2018086395 A1 WO 2018086395A1
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layer
insulating layer
memory
chipset
electrically connected
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PCT/CN2017/096756
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English (en)
French (fr)
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陆原
陈�峰
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华进半导体封装先导技术研发中心有限公司
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Priority claimed from CN201610981072.8A external-priority patent/CN106449590B/zh
Priority claimed from CN201610980670.3A external-priority patent/CN106653628B/zh
Application filed by 华进半导体封装先导技术研发中心有限公司 filed Critical 华进半导体封装先导技术研发中心有限公司
Publication of WO2018086395A1 publication Critical patent/WO2018086395A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Definitions

  • Embodiments of the present invention relate to the field of semiconductor technologies, and in particular, to a semiconductor memory, a semiconductor memory module, and a method of fabricating the same.
  • a method of stacking the memory chips may be employed.
  • the memory chips are stacked one by one in a staggered manner, and then the respective chips are electrically connected together by metal wire bonding in one step and one step.
  • the purpose of the misaligned structure is to implement metal wire bonding.
  • the other is to vertically stack the memory chips together, and use through silicon vias (TSVs) to realize electrical signal connections between the stacked memory chips.
  • TSVs through silicon vias
  • Fan-out wafer level technology enables the stacking of memory chips as a solution for mass storage manufacturing.
  • the FOWLP technology is currently two-dimensional, and it is difficult to apply it in the manufacture of high-end memory devices having multiple memory cells.
  • US Patent US 2005/0124093 A1 introduces a two-dimensional fan-out wafer level packaging technology.
  • 100 is a carrier; 110 is a chip; 130 and 130a are a redistribution layer (RDL); 148 is an inter-chip electrical interconnection; 120, 122, 132, 120a and 132a are dielectric; For external connection terminals (tin balls).
  • RDL redistribution layer
  • U.S. Patent No. 2009/0014876A1 (Cheul-Joong Youn et al.) proposes a method for realizing three-dimensional integration of a memory device based on a chip-stacked fan-out wafer level technology.
  • 104, 110, 132 and 142 are chips; 112, 134 and 144 are insulating dielectrics; 108, 118, 136 and 146 are inter-chip electrical interconnections; 116 is the outermost RDL; 120 is the external connection terminal (tin ball).
  • the method proposed in this patent is an idealized, difficult concept to achieve in engineering.
  • the metal redistribution layer (RDL) cannot be directly deposited on the molding material; 2) using the spin-on dielectric material, it is difficult to be flush with the surface of the chip; 3) the chip is active The problem of preventing organic contamination of the metal pad. Moreover, according to the basic method described in the patent, stacking more than 4 layers of chips is difficult to achieve.
  • U.S. Patent No. 8,872,350 B2 (Shigenorl Sawachi et al.) describes two methods of filling the gaps between memory chips and forming an inter-chip electrical connection path.
  • 1 is a heat sink (also a carrier); 2 is a chip; 6 is RDL; 9 is an electrical interconnection between the chips; 4 is an insulating dielectric; 13 is an external connection terminal (tin ball) .
  • the first method is laser drilling after plastic sealing. This method can be implemented for ordinary semiconductor chip packages, but cannot be used for high-end memory chips fabricated by 16nm (or less) process. Because such high-end memory chips have a pitch of about 50 ⁇ m, laser drilling cannot be applied to such a small pitch.
  • the second method will be a very difficult (deep blind hole filling), and expensive (due to the use of very thick photosensitive dielectric (about 100 ⁇ m) as an inter-chip filling material) manufacturing technology.
  • the method provided by this patent is costly to manufacture and difficult to achieve mass production.
  • the current drawbacks in the large-capacity memory stacking technology are: low stacking efficiency, difficulty in realizing multi-layer stacking technology, and difficulty in mass production.
  • the embodiments of the present invention provide a semiconductor memory, a semiconductor memory module, and a manufacturing method thereof, to solve the technical problem that the semiconductor memory device in the prior art has low stacking efficiency, is difficult to implement in a multi-layer stacking technology, and is difficult to mass-produce.
  • an embodiment of the present invention provides a semiconductor memory, including at least two memory chipsets stacked in order from bottom to top, and a first redistribution layer of two adjacent memory chipsets adjacent to each other
  • the interlayer conductive pillars are electrically connected, and the first redistribution layer of the lowermost memory chip set is electrically connected to the external connection bumps;
  • the memory chip set includes at least two memory chips stacked in sequence, and a first composite insulating layer under the at least two memory chips, the at least two memory chips being encapsulated into a unitary structure, the first weight
  • the wiring layer is disposed in the first composite insulating layer, and the conductive pillars in the first layer of the at least two memory chips are staggered by a predetermined angle to be electrically connected to the first redistribution layer, respectively.
  • the embodiment of the present invention provides a semiconductor memory module, including the semiconductor memory device of the first aspect, further comprising a control chipset, wherein the control chipset and the memory chipset are sequentially stacked from bottom to top.
  • the second redistribution layer of the control chip set and the adjacent ones of the memory chip sets are electrically connected by an inter-region conductive pillar, and the lowermost first redistribution layer or the second redistribution layer Electrically connecting with the external connecting bump;
  • the control chipset includes a control chip, and a second composite insulating layer under the control chip, the second redistribution layer is disposed in the second composite insulating layer, and the second layer of the control chip A conductive post is electrically connected to the second redistribution layer.
  • an embodiment of the present invention further provides a method for fabricating a semiconductor memory, comprising: sequentially manufacturing at least two memory chip sets on a carrier from bottom to top, and fabricating interlayer conductive pillars, wherein the interlayer conductive pillars are respectively The first redistribution layer of the two memory chip sets adjacent to each other is electrically connected, and the first redistribution layer of the lowermost memory chip set is electrically connected to the external connection bumps;
  • Stacking the at least two memory chips in sequence, and the conductive pillars in the first layer of the at least two memory chips are staggered by a preset angle;
  • a first redistribution layer is formed in the first composite insulating layer, and the first redistribution layer is electrically connected to the first layer inner conductive pillar.
  • an embodiment of the present invention further provides a method for fabricating a semiconductor memory module, including The method for fabricating a semiconductor memory according to the third aspect, further comprising: forming a control chip set and an inter-area conductive pillar on the carrier, wherein the control chip set and the memory chip set are sequentially stacked from bottom to top, the control chip And connecting the second redistribution layer of the group to the adjacent one of the memory chip sets through the inter-region conductive pillars, and the lowermost first redistribution layer or the second redistribution layer and the external Connection bump electrical connection;
  • control chipset The steps of making a control chipset include:
  • a second composite insulating layer is formed under the control chip, a second redistribution layer is formed in the second composite insulating layer, and the second redistribution layer is electrically connected to the inner conductive pillars in the second layer.
  • the semiconductor memory, the semiconductor memory module and the manufacturing method thereof are provided by sequentially stacking at least two memory chips to form a memory chip set, wherein the conductive pillars of the at least two memory chips are staggered by a preset angle, respectively
  • the wiring layer is electrically connected; and at least two memory chip sets are sequentially stacked to form a memory, wherein the redistribution layers of the two adjacent memory chips groups are electrically connected through the interlayer conductive pillars, thereby realizing large capacity and high integration of the memory. , effectively improve the stacking efficiency of the memory, and reduce the difficulty of stacking.
  • FIG. 1 is a schematic structural diagram of a memory of a two-dimensional fan-out wafer level packaging technology provided by the prior art
  • FIG. 2 is a schematic structural diagram of a memory based on a chip stack fan-out wafer level technology provided by the prior art
  • FIG. 3 is a schematic structural diagram of a third memory provided by the prior art.
  • FIG. 4 is a schematic cross-sectional structural view of a semiconductor memory device according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional structural diagram of a semiconductor memory module according to an embodiment of the present invention.
  • FIG. 6 is a schematic top plan view of a carrier of a semiconductor memory according to an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional structural view of a temporary bonding adhesive coated on a carrier board according to an embodiment of the present invention.
  • FIG. 8a is a schematic top view showing a first memory chip formed on a memory wafer according to an embodiment of the present invention.
  • FIG. 8b is a schematic cross-sectional view showing a first memory chip formed on a memory wafer according to an embodiment of the present invention
  • 9a is a top plan view of forming a second memory chip on a memory wafer according to an embodiment of the present invention.
  • 9b is a schematic cross-sectional view showing a second memory chip formed on a memory wafer according to an embodiment of the present invention.
  • 10a is a cross-sectional structural view showing a plurality of first memory chips formed by cutting a memory wafer according to an embodiment of the present invention
  • FIG. 10b is a cross-sectional structural diagram of forming a plurality of second memory chips by cutting a memory wafer according to an embodiment of the present invention
  • FIG. 11a, FIG. 11b and FIG. 11c are schematic diagrams showing the structure of fabricating a first memory chip and a second memory chip on a carrier board according to an embodiment of the present invention
  • FIG. 12 is a schematic cross-sectional view showing a structure in which a carrier plate on which a first memory chip and a second memory chip are formed is solid-sealed to form a solid sealing layer according to an embodiment of the present invention
  • FIG. 13 is a schematic cross-sectional structural view showing a thinning of a solid sealing layer according to an embodiment of the present invention.
  • FIG. 14 is a schematic cross-sectional view showing a first lower insulating layer formed on a solid sealing layer according to an embodiment of the present invention
  • FIG. 15 is a schematic cross-sectional view showing a first rewiring layer formed on a first lower insulating layer according to an embodiment of the present invention
  • 16 is a schematic cross-sectional view showing a first upper insulating layer formed on a first redistribution layer according to an embodiment of the present invention
  • 17 is a schematic cross-sectional structural view showing formation of an interlayer conductive pillar according to an embodiment of the present invention.
  • FIG. 18 is a schematic cross-sectional structural view showing an integrated structure between interlayer conductive pillars according to an embodiment of the present invention.
  • FIG. 19 is a cross-sectional structural view showing a solid sealing of an integrated structure according to an embodiment of the present invention.
  • FIG. 20 is a cross-sectional structural diagram of thinning a solid sealing layer in a second layer memory chip set according to an embodiment of the present invention
  • FIG. 21 is a cross-sectional structural diagram of a first lower insulating layer forming a second layer memory chip set according to an embodiment of the present invention.
  • FIG. 22 is a cross-sectional structural view showing a first redistribution layer and a first upper insulating layer forming a second layer memory chip set according to an embodiment of the present invention
  • FIG. 23 is a schematic cross-sectional structural view showing formation of a second interlayer conductive pillar according to an embodiment of the present invention.
  • 24 is a schematic cross-sectional view showing the formation of four memory chipsets according to an embodiment of the present invention.
  • 25 is a schematic cross-sectional view showing the structure of forming an external connection bump on the first composite insulating layer according to an embodiment of the present invention.
  • FIG. 26 is a schematic structural diagram of the inverted and removed carrier board and the bonding adhesive of FIG. 25 according to an embodiment of the present invention.
  • FIG. 27 is a schematic structural diagram of a memory deposition protective film according to an embodiment of the present invention.
  • FIG. 29 is a schematic structural diagram of a single memory according to an embodiment of the present invention.
  • FIG. 30 is a cross-sectional structural diagram of forming an inter-area conductive pillar according to an embodiment of the present invention.
  • FIG. 31 is a top plan view showing a control chip formed on a logic wafer according to an embodiment of the present invention.
  • FIG. 31b is a cross-sectional structural diagram of forming a control chip on a logic wafer according to an embodiment of the present invention.
  • 32 is a schematic cross-sectional structural view showing a plurality of control chips formed by cutting a logic wafer according to an embodiment of the present invention
  • FIG. 33 is a schematic cross-sectional structural view of a control chip fabricated in a storage area according to an embodiment of the present invention.
  • FIG. 34 is a schematic cross-sectional structural view showing a solidification of a control chip according to an embodiment of the present invention.
  • FIG. 35 is a schematic cross-sectional structural view showing a thinning of a solid sealing layer of a control chip according to an embodiment of the present invention.
  • 36 is a schematic cross-sectional view showing a second composite insulating layer according to an embodiment of the present invention.
  • FIG. 37 is a schematic cross-sectional view showing the structure of forming an external connection bump on a second composite insulating layer according to an embodiment of the present invention.
  • FIG. 38 is a schematic structural view showing the structure of the cross-sectional structure of FIG. 37 inverted and depositing a protective film according to an embodiment of the present invention
  • 39 is a schematic structural diagram of cutting a plurality of storage modules formed according to an embodiment of the present invention.
  • FIG. 40 is a schematic structural diagram of a single storage module according to an embodiment of the present invention.
  • the semiconductor memory provided by the embodiment of the present invention can be used as a cache memory, a main memory, a stack memory, and the like. As shown in FIG. 4, the semiconductor memory provided by the embodiment of the present invention may include:
  • the first redistribution layers of the two upper and lower adjacent memory chip sets are electrically connected through the interlayer conductive pillars, and the first first redistribution layer and the outer connection convexity are located at the bottom Block electrical connection
  • the memory chip set includes at least two memory chips stacked in sequence, and a first composite insulating layer under the at least two memory chips, the at least two memory chips being encapsulated into a unitary structure, and the first redistribution layer is disposed at the first In the composite insulating layer, the conductive pillars in the first layer of the at least two memory chips are staggered by a predetermined angle to be electrically connected to the first redistribution layer, respectively.
  • the memory shown in FIG. 4 includes four memory chipsets, here four memory chips
  • the memory includes a first memory chipset 310, a second memory chipset 510, a third memory chipset 610, and a fourth memory chipset 710, wherein the fourth memory chipset 710,
  • the three memory chipset 610, the second memory chipset 510, and the first memory chipset 310 are sequentially stacked from bottom to top.
  • the first memory chipset 310, the second memory chipset 510, the third memory chipset 610, and the fourth memory chipset 710 may respectively include two, three, or four memory chips, and only two are stored in FIG.
  • the chip, the first memory chip 110 and the second memory chip 210 are described.
  • the first memory chip 110 includes a first active surface and a first pad disposed on the first active surface, and a first layer of conductive pillars 122 of the first memory chip 110 is disposed in the first pad, and a second
  • the memory chip 210 includes a first active surface and a first pad disposed on the first active surface, and a first layer of conductive pillars 222 of the second memory chip 210 is disposed in the first pad.
  • the spatial orientations of the first memory chip 110 and the second memory chip 210 are the same, that is, the orientations of the first active surfaces of the two memory chips are the same, and thus the orientations of the conductive pillars 122 and 222 in the first layer are also the same.
  • the first memory chip 110, the second memory chip 210, and the first-layer inner conductive pillars 122 and 222 can be understood as a single structure.
  • the first memory chipset 310 further includes a first composite insulating layer under the integrated structure in the first memory chip set 310, the first composite insulating layer includes a first upper insulating layer 405, and a first lower insulating layer. a layer 401 and a first redistribution layer 403 between the first upper insulating layer 405 and the first lower insulating layer 401; the second memory chip set 510 may further include a second under the integrated structure of the second memory chip set 510 a composite insulating layer including a first upper insulating layer 505, a first lower insulating layer 501, and a first redistribution layer between the first upper insulating layer 505 and the first lower insulating layer 501 503.
  • the third memory chipset 610 may further include a first composite insulating layer under the integrated structure in the third memory chipset 610, the first composite insulating layer including a first upper insulating layer 605 and a first lower insulating layer 601. And a first redistribution layer 603 between the first upper insulating layer 605 and the first lower insulating layer 601; the fourth memory chipset 710 may further include a first composite under the integrated structure of the fourth memory chipset 710 Edge layer, the first composite insulating layer includes a first upper insulating layer 705, a first redistribution layer 703 between the first insulating layer 701 and a lower portion 705 and a lower portion of the first insulating layer located between the first upper insulating layer 701.
  • the first inner conductive pillars 122 and 222 in the first memory chip set 310 may be electrically connected to the first redistribution layer 403 through the first via holes in the first lower insulating layer 401.
  • the first redistribution layer 403 is electrically connected to the interlayer conductive pillars 407 through the second via holes in the first upper insulating layer 405; the first conductive pillars 122 and 222 in the first layer of the second memory chipset 510 may pass through the first
  • the first via hole in the portion insulating layer 501 is electrically connected to the first redistribution layer 503, and the redistribution layer 503 is electrically connected to the interlayer conductive pillar 507 through the second via hole in the upper insulating layer 505; the third memory chip group 610
  • the first inner conductive pillars 122 and 222 of the first layer may be electrically connected to the first redistribution layer 603 through a first via hole in the first lower insulating layer 601, and the redistribution
  • the first inner conductive pillars 122 and 222 in the memory chip set may be staggered by a predetermined angle to be electrically connected to the corresponding first redistribution layer, for example, the first inner conductive pillar 122 in the first memory chipset 310.
  • the first and second rewiring layers 403 in the first memory chip 310 can be electrically connected to the first re-wiring layer 403 in the first memory chip 310.
  • the first inner conductive pillars 122 and 222 in the second memory chip set 510 can also be offset by a predetermined angle.
  • the preset angle may be 180°, 90° or 45°.
  • the conductive pillars in the layer in the memory chipset may be staggered at any angle other than 0°, as long as the conductive pillars in the layer are not overlapped, and may be offset by 180°, 90° or 45°.
  • an interlayer conductive pillar may be further included in the memory chipset to implement electrical connection between different memory chipsets.
  • the second memory chipset 510 may include an interlayer conductive pillar 407, the first memory chip.
  • the first redistribution layer 403 of the group 310 and the first redistribution layer 503 of the second memory chipset 510 may be electrically connected through the interlayer conductive pillars to realize the electricity of the first memory chipset 310 and the second memory chipset 510. connection.
  • the memory may further include an external connection bump 908.
  • the fourth memory chip set 710 When the fourth memory chip set 710 is located at the bottom, the first redistribution layer 703 of the fourth memory chip set 710 is electrically connected to the external connection bump 908.
  • the memory may further include an under bump metal layer 906 , and the first redistribution layer 703 of the fourth memory chip set 710 is electrically connected to the outer connecting bump 908 through the under bump metal layer 906 .
  • the memory shown in FIG. 4 is only an example of the memory provided by the embodiment of the present invention.
  • the memory chipset may also be two or three. One or more to achieve high capacity and high integration of the memory.
  • the first upper insulating layer and the first lower insulating layer are made of an organic photosensitive material.
  • At least two memory chips in the memory chipset are encapsulated into a unitary structure, and 302, 502, 602, and 702 are solid sealing layers.
  • a bottom of the uppermost memory chipset may be provided with a protection layer.
  • a protection layer 909 is disposed above the memory chipset 310.
  • the memory provided by the embodiment of the present invention superimposes the memory chipsets having the conductive pillars in the layer two or two, so that when performing the three-dimensional wafer level memory stacking, the reliability risk caused by multiple cycles of the manufacturing process can be reduced; Layer, the actual stacking of two chips, so that when the number of stacked chip layers is the same, the number of stacked chips will double, so the stacking efficiency is doubled, the production cost is reduced; the filling and coating of the chip gap is low-cost.
  • Thermosetting materials and eliminating the use of lithography and other processes, the production cost is reduced; when stacking the second memory chipset, first make the interlayer conductive pillars to achieve electrical interconnection, then perform memory chip placement and storage inter-chip dielectric filling
  • the method of coating and coating solves the difficulty of laser drilling to limit the pitch, so as to meet the requirement of super-fine pitch for mass storage manufacturing.
  • the semiconductor memory module according to the embodiment of the present invention includes the semiconductor memory device of the above embodiment, and may further include:
  • Controlling a chipset the control chipset and the memory chipset are sequentially stacked from bottom to top, and the second redistribution layer of the control chipset and the adjacent ones of the memory chipsets pass through the inter-area conductive pillars Connected, and the first rewiring layer or the second redistribution layer located at the bottom is electrically connected to the external connection bump;
  • the control chipset includes a control chip, and a second composite insulating layer under the control chip, the second redistribution layer is disposed in the second composite insulating layer, and the second layer of the control chip A conductive post is electrically connected to the second redistribution layer.
  • the memory module shown in FIG. 5 includes a control chipset and four memory chipsets.
  • a control chipset and four memory chipsets are illustrated.
  • the memory module includes a control chip.
  • the third memory chipset 610, the second memory chipset 510, and the first memory chipset 310 are sequentially stacked from bottom to top.
  • control chipset 810 can include a control chip 806 and a second composite insulating layer under the control chip 806, and the second composite insulating layer can include a second upper insulating layer 805, a second lower insulating layer 801, and The second redistribution layer 803 is located between the second upper insulating layer 805 and the second lower insulating layer 801.
  • the control chip 806 includes a second active surface and a second pad disposed on the second active surface, and a second layer of conductive pillars 808 of the control chip 806 is disposed in the second pad.
  • the two-layer inner conductive post 808 is electrically connected to the second pad.
  • the second inner conductive pillar 808 in the control chip 806 can be electrically connected to the second redistribution layer 803 through the third via hole in the second lower insulating layer 801.
  • the second active surface of the control chip 806 and the first active surface orientation of the memory chip may be the same.
  • the storage module may also include an external connection bump 908.
  • the second redistribution layer 803 of the control chipset 810 is electrically connected to the external connection bump 908.
  • the memory module may further include an under bump metal layer 906, and the second redistribution layer 803 of the control chipset 810 is electrically connected to the outer connection bump 908 through the under bump metal layer 906.
  • the storage module shown in FIG. 5 is only an example of the storage module provided by the embodiment of the present invention.
  • the control chipset may also be located between the storage chipsets. Used to implement control of the memory chipset.
  • the second upper insulating layer and the second lower insulating layer are made of an organic photosensitive material.
  • control chip in the control chipset is encapsulated by a thermosetting material.
  • the bottom of the uppermost storage chipset or the control chipset may be provided with a protection layer.
  • a protection layer 909 is disposed above the memory chipset 310.
  • the storage module provided by the embodiment of the present invention, by sequentially stacking the control chipset and the at least two memory chip sets, the first redistribution layer of the two upper and lower adjacent memory chip sets are electrically connected through the interlayer conductive pillars, and the chipset is controlled.
  • the second redistribution layer is electrically connected to the adjacent memory chipset through the inter-region conductive pillars.
  • the memory chipset includes at least two memory chips stacked in sequence, and the conductive pillars in the first layer of the two memory chips are staggered by default. The angle is electrically connected to the first redistribution layer, respectively.
  • the memory chipset includes at least two memory chips, and the memory chip sets are electrically connected through the interlayer conductive pillars and the first redistribution layer, and the memory chipset and the control chipset are electrically connected by the inter-region conductive pillars to predict the second heavy wiring group. Ensure that the memory module has higher storage capacity and smaller size, while ensuring that the memory chipset and the control chipset are placed in the same wafer, achieving wafer level manufacturing and wafer level functional testing of the memory module, improving storage. Module production efficiency.
  • the embodiment of the invention further provides a method for fabricating a semiconductor memory, comprising: fabricating at least two memory chip sets sequentially from bottom to top of the carrier, and fabricating interlayer conductive pillars, wherein the interlayer conductive pillars are respectively adjacent to the upper and lower sides
  • the first redistribution layers of the two memory chipsets are electrically connected, and the first redistribution layer located at the bottom is electrically connected to the external connection bumps.
  • the following describes the sequence of the memory chip set, the interlayer conductive pillars, and the first composite insulating layer in the process.
  • the embodiment of the present invention uses four memory chipsets as an example for description.
  • a carrier 300 is provided.
  • the material of the carrier 300 may be metal, silicon, glass, an organic substrate or the like.
  • the geometry of the carrier 300 can be circular or square.
  • An alignment mark for the chip placement position is formed on the edge of the cleaned carrier 300, as shown in FIG.
  • Alignment marks are typically fabricated by thin film deposition techniques such as ion sputtering, photolithography, development, and etching, as well as by laser etching, screen printing, pattern plating, and mechanical finishing.
  • the manufacturing method of the semiconductor memory provided by the embodiment of the present invention can form a plurality of memories at a time, and cut a plurality of memories to obtain a single memory.
  • the temporary bonding adhesive 301 is coated on the carrier 300, as shown in FIG.
  • the coating of the temporary bonding glue 301 can be performed by spin coating, spray coating, rolling, printing, non-rotation coating, hot pressing, vacuum pressing, and pressure bonding.
  • the temporary bonding glue 301 may be an organic material or a
  • the storage chipset is formed on the carrier 300. Specifically, the memory chip in the memory chipset is first formed. In the embodiment of the present invention, two memory chips are taken as an example for introduction.
  • first composite insulating layer under the integrated structure, wherein the first composite insulating layer is formed a first redistribution layer, the first redistribution layer being electrically connected to the conductive pillars in the first layer;
  • the memory wafer 100 has an array of first memory chips 110.
  • the first memory chip 110 has an active surface 110a and a non-active surface 110b.
  • a first memory chip 110 is externally connected to the conductive first pad 121, and on the pad 121, a pre-deposited first layer is disposed.
  • the deposition of the conductive pillars 122 in the first layer can be achieved by different methods, such as vacuum deposition and electroplating.
  • the first pad 121 may be a single layer or a plurality of layers of metal, such as Ti, W, Al, Cu, Ni, Pt, Ag, Au or alloys thereof, and the material of the conductive pillars 122 in the first layer is a metal such as Cu. Ni, Ag, Au or an alloy thereof.
  • the height of the conductive pillars 122 in the first layer is about 70 to 90 ⁇ m.
  • the thickness of the first memory chip 110 is 40 to 50 ⁇ m.
  • a DAF film 101 is deposited on the back side of the wafer 100 (corresponding to the inactive surface of the first memory chip 110). Its deposition can be achieved in a variety of ways: spin coating, spray coating, printing, rolling, and hot pressing.
  • the thickness of the effective bonding layer of the DAF film 101 is about 10 to 30 ⁇ m.
  • the DAF film 101 is an organic material.
  • the memory wafer 200 has an array of second memory chips 210.
  • the second memory chip 210 and the first memory chip 110 may be the same type of memory, or may be different types of memories.
  • the second memory chip 210 has an active surface 210a and a non-active surface 210b.
  • On the active surface 210a a second memory chip 210 is externally connected to the conductive first pad 221.
  • the deposition of the conductive pillars 122 in the first layer can be achieved by different methods, such as vacuum deposition and electroplating.
  • the first pad 121 may be a single layer or a plurality of layers of metal, such as Ti, W, Al, Cu, Ni, Pt, Ag, Au or alloys thereof, and the material of the first conductive pillar 122 is a metal such as Cu, Ni. , Ag, Au or its alloys, and the like.
  • the height of the first conductive pillar is about 20 to 40 ⁇ m.
  • the thickness of the second memory chip 210 is 40 to 5 ⁇ m.
  • a DAF film 201 is deposited on the back side of the wafer 200 (corresponding to the inactive surface of the second memory chip 210). Its deposition can be achieved in a variety of ways: for example, spin coating, spray coating, printing, rolling, and hot pressing.
  • the thickness of the effective bonding layer of the DAF film 201 is about 10 to 30 ⁇ m, the DAF film 201 is an organic material, and the DAF film 201 and the DAF film 101 may be the same DAF film or different DAF films.
  • the two semiconductor memory wafers are respectively cut to obtain a first memory chip 110 and a second memory chip 210.
  • the cutting can be performed using standard semiconductor wafer cutting methods such as mechanical cutting or laser cutting.
  • the active surface 110a of the first memory chip 110 is directed upward by a semiconductor chip device, and is attached in a so-called "Chip-to-Wafer” manner. Relocation of the first memory chip 110 on the carrier is achieved by the upper surface of the temporary bonding glue 301 on the carrier 300.
  • the active surface 220a of the second memory chip 210 is directed upward by a semiconductor chip device, and placed on the active surface 110a of the first memory chip 110 in a so-called "Chip-to-Chip” manner to form an integrated body.
  • the integrated structure can be visually understood as a "super chip.”
  • the second memory chip 210 When the second memory chip 210 is placed, the second memory chip 210 and the first memory chip 110 are offset in a position to expose the first layer of the conductive pillars 122 on the active surface of the first memory chip 110. By such placement, re-reset of the second memory chip 210 on the carrier 300 is also achieved.
  • the carrier plate with the integrated structure is placed in an oven with a certain high pressure. Pressurization to discharge the bubbles trapped at the interface of each patch confirms the integrity of the interface of the patch and pre-cures the DAF material.
  • the deposition medium material is used to seal the carrier sheet including the unitary structure to form a solid sealing layer 302, that is, to fill the voids and surfaces of the integrated structure.
  • the height of the solid seal layer 302 should be higher than the conductive pillars in the first layer in the unitary structure.
  • the deposition method may be spin coating, printing, organic lamination or plastic sealing.
  • the dielectric material is generally an organic thermoset material, but is not excluded as an insulating non-organic material.
  • the solid sealing layer 302 is thinned and thinned until the surface of the conductive pillars in all the first layers on the integrated structure is exposed.
  • the thinning method uses a standard grinding and polishing technique manufactured by a semiconductor. At this time, the distance of the surface of the solid dielectric material from the uppermost surface of the integrated structure, that is, the active surface 210a of the second memory chip 210 is about 20 ⁇ m.
  • Forming the first composite insulating layer over the integrated structure may include:
  • first redistribution layer Forming a first redistribution layer over the first lower insulating layer, the first redistribution layer being electrically connected to the first layer inner conductive pillar through the first via hole;
  • a first upper insulating layer is formed over the first redistribution layer.
  • a specific engineering method is as follows: As shown in FIG. 14, a photolithographic first lower insulating layer 401 is deposited on the upper surface of the solid sealing layer 302.
  • the material of the first lower insulating layer 401 includes a photosensitive resin and a resin which can be patterned by a process such as dry etching, such as polyimide, photosensitive epoxy resin, and diphenylcyclobutene.
  • a process such as dry etching, such as polyimide, photosensitive epoxy resin, and diphenylcyclobutene.
  • One or more of the olefin resin and the phenyl bisoxazole resin, the first lower insulating layer 401 has a thickness of 5 to 7 ⁇ m.
  • the first lower insulating layer 401 is patterned to form a first via hole, and the first via hole is up to the surface of the conductive pillars in each of the first layers in the integrated structure to expose each A conductive pillar in the first layer (not shown).
  • a first redistribution layer 403 is formed on the first lower insulating layer 401 by a standard semiconductor fabrication process.
  • the process consists of a series of processes such as thin film deposition, electroplating, photolithography, development, and etching.
  • the terminal on one side of the first redistribution layer 403 is connected to the first-layer inner conductive pillars 122 and 222 in the integrated structure via the first via hole on the first lower insulating layer 401 to lead out the first memory chip 110 and the second memory. Electrical connection of the chip 210.
  • the material of the first redistribution layer 403 may be a metal material such as Al, Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W, or the like and alloys thereof.
  • a photolithographic first upper insulating layer 405 is formed on the first redistribution layer 403 and the first lower insulating layer 401.
  • the material of the first upper insulating layer 405 includes a photosensitive resin and a resin which can be patterned by a dry etching process, such as polyimide, photosensitive epoxy resin, bisphenylcyclobutene resin, phenyl bisoxazole One or more of the resins.
  • the thickness of the first upper insulating layer 405 is 5 to 7 ⁇ m.
  • the first upper insulating layer 405 is patterned by a standard process of semiconductor device wafer fabrication to form openings, and the openings are exposed to respective end faces of the first redistribution layer 403.
  • the first upper insulating layer 405 is patterned to form a front or middle pass of a standard semiconductor, such as by exposure, development, wet or dry etching.
  • the interlayer conductive pillars may be formed on the first upper insulating layer.
  • the inter-layer conductive pillars may be:
  • interlayer conductive pillars are formed on the first upper insulating layer, and the interlayer conductive pillars are used to connect adjacent two memory chip sets.
  • an integrated structure of interlayer conductive pillars 407 is fabricated by a standard process of semiconductor wafer fabrication.
  • One end of the interlayer conductive pillar 407 is connected to the respective end faces of the first redistribution layer 403 through the opening of the first upper insulating layer 405.
  • the height of the other end of the interlayer conductive pillar 407 should be higher than the surface of the first upper insulating layer 405 by about 100 to 120 ⁇ m.
  • Interlayer conduction The fabrication of the pillars 407 can be accomplished using standard techniques for semiconductor fabrication, such as vacuum deposition, electroplating, and electroless plating.
  • the interlayer conductive pillars 407 are metal materials such as Cu, Ni, Pd, Ag, Au, or alloys thereof.
  • the method for fabricating the interlayer conductive pillar provided by the embodiment of the invention is directly fabricated on the formed first composite insulating layer, and the interlayer conductive pillar is first formed, and then the integrated structure and the dielectric filling of the integral structure are fabricated, so that the low-cost can be adopted.
  • the thermosetting material acts as a filled dielectric instead of an expensive thick photosensitive dielectric material, and eliminates the need for photolithography and the like in the solid sealing layer, which reduces the production cost and does not require laser drilling of the sealing material. It also solves the difficulty of laser drilling to limit the pitch, so as to meet the requirements of the ultra-fine pitch for the production of large-capacity sensors.
  • the above-mentioned integral structure has an active surface facing upward by a semiconductor chip device, and continues to be attached to the first upper portion of the carrier 300 in a so-called "Chip-to-Wafer” manner according to the design position.
  • the integrated structure in each memory chip group may be the same, that is, the first memory chip 110, the second memory chip 120, and the intra-layer conductive pillars on the active surface of the first memory chip 110. 122 and an in-layer conductive post 222 on the active surface of the second memory chip 120.
  • the entire carrier plate is solid-sealed by depositing a dielectric material to form a solid sealing layer 502, that is, filling the voids and surfaces of the integrated structure.
  • the height of the solid sealing layer 502 should be higher than all of the first inner conductive pillars and the interlayer conductive pillars 407 in the integrated structure.
  • the deposition method may be spin coating, printing, organic lamination, plastic molding, or the like.
  • the dielectric material is generally an organic thermoset material, but is not excluded as an insulating non-organic material.
  • the solid sealing layer 502 is thinned and thinned until all the first inner conductive pillars and the interlayer conductive pillars 407 on the integrated structure are exposed.
  • the thinning method uses a standard grinding and polishing technique manufactured by a semiconductor. After grinding and polishing, the distance between the upper surface of the solid sealing layer 502 and the uppermost surface of the integrated structure is about 20 ⁇ m.
  • a photolithographic first lower insulating layer 501 is coated on the front surface of the solid sealing layer 502.
  • the material of the first lower insulating layer 501 includes a photosensitive resin and a resin which can be patterned by a dry etching process, such as polyimide, photosensitive epoxy resin, bisphenylcyclobutene resin, phenyl dioxime
  • a dry etching process such as polyimide, photosensitive epoxy resin, bisphenylcyclobutene resin, phenyl dioxime
  • the first lower insulating layer 501 has a thickness of 5 to 7 ⁇ m.
  • the first through holes are formed, and the first through holes are up to the surface of the conductive pillars in each of the first layers in the integrated structure to expose the conductive pillars (not shown) in the first layers.
  • a first redistribution layer 503 is formed on the first lower insulating layer 501 by a standard semiconductor fabrication process.
  • the process consists of a series of processes such as thin film deposition, electroplating, photolithography, development, and etching.
  • the terminal on one side of the first redistribution layer 503 is connected to the first-layer inner conductive pillars 122 and 222 in the integrated structure via the first via hole on the first lower insulating layer 501 to lead out the first memory chip 110 and the second memory. Electrical connection of the chip 210.
  • the material of the first redistribution layer 503 may be a metal material such as Al, Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W, or the like and alloys thereof.
  • a photolithographic first upper insulating layer 505 is formed on the first redistribution layer 503 and the first lower insulating layer 501.
  • the material of the first upper insulating layer 505 includes a photosensitive resin and a resin which can be patterned by a dry etching process, such as polyimide, photosensitive epoxy resin, bisbenzocyclobutene resin, phenyl bisoxazole One or more of the resins.
  • the first upper insulating layer 505 has a thickness of 5 to 7 ⁇ m.
  • the first upper insulating layer 505 is patterned by a standard process of semiconductor device wafer fabrication to form openings, and the openings are exposed to respective end faces of the first redistribution layer 503.
  • the first upper insulating layer 505 can be patterned using a front or intermediate process of a standard semiconductor, such as by exposure, development, wet or dry etching.
  • an integrated interlayer conductive pillar 507 is fabricated by a standard process of semiconductor wafer fabrication.
  • One end of the interlayer conductive pillar 507 is connected to the respective end faces of the first redistribution layer 503 through the opening of the first upper insulating layer 505.
  • the height of the other end of the interlayer conductive pillar 507 should be higher than the surface of the first upper insulating layer 505 by about 100 to 120 ⁇ m.
  • the fabrication of the interlayer conductive pillars 507 can be accomplished using standard techniques for semiconductor fabrication, such as vacuum deposition, electroplating, and electroless plating.
  • each memory chip in the integrated structure passes through the first redistribution layer 403 and the layer conductive pillar 407 of the integral structure, and the memory chips in the integrated structure pass through the first redistribution layer 503 and the interlayer conductive pillar 507 of the integral structure.
  • the electrical connection with the outside world is realized.
  • the interlayer conductive pillar 507 is a metal material such as Cu, Ni, Pd, Ag, Au, or an alloy thereof, like the interlayer conductive pillar 407.
  • the memory chipset with large-capacity storage capability described in the embodiment of the present invention forms a two-layer "super chip” structure after two large rounds of process cycles, and realizes four-layer memory chip stacking.
  • the following steps basically repeat the above cycle and continue until the completion of the four-layer "super chip” structure (ie, the implementation of an eight-layer memory chip stack), which will not be described in detail herein.
  • 310, 510, 610, and 710 are memory chipsets; 602 and 702 are dielectric sealing layers; 601 and 701 are first lower insulating layers, and 701 and 705 are first upper insulating layers; 603 and 703 first rewiring layers; 507 and 607 are interlayer conductive pillars of the memory chipset.
  • the gap between the "super chip” and the deposition method of the dielectric can be spin coating, printing, organic lamination or plastic sealing.
  • the material properties are generally organic thermoset materials, but are not excluded as insulating non-organic materials.
  • the deposition of insulating dielectric can be performed by a front or middle pass of a standard semiconductor, such as by exposure, development, wet or dry etching.
  • the insulating dielectric material includes a photosensitive resin and a resin which can be patterned by a dry etching process, such as polyimide, photosensitive epoxy resin, BCB (bisphenylcyclobutene resin), PBO (phenyl phenyl) One or more of oxazole resins).
  • the fabrication of the RDL layer involves a series of processes such as thin film deposition, electroplating, photolithography, development, etching, and the like.
  • the RDL material is a metal material such as Al, Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W, or the like and alloys thereof.
  • the fabrication of "super chip” interlayer conductive pillars can be achieved by standard techniques for semiconductor fabrication, such as vacuum deposition, electroplating, electroless plating, and the like.
  • the "super chip” interlayer conductive pillar is a metal material such as Cu, Ni, Pd, Ag, Au or an alloy thereof.
  • the insulating passivation layer is fabricated using a standard semiconductor front or intermediate process, such as by exposure, development, wet or dry etching.
  • the passivation layer material is generally an organic material, but is not excluded as an inorganic material.
  • Organic materials include photosensitive resin, such as polyimide, photosensitive epoxy resin, solder resist ink, green paint, dry film, photosensitive build-up material, BCB (bis-phenylcyclobutene resin), PBO (benzene) One or more of the benzobisoxazole resins).
  • the external connection bumps are fabricated below.
  • the first upper insulating layer 705 is patterned by a standard process of semiconductor device wafer fabrication to form a second via hole, and the second via hole is exposed to the respective end faces of the redistribution layer 703.
  • the first upper insulating layer 705 can be patterned using a front or intermediate process of a standard semiconductor, such as by exposure, development, wet or dry etching.
  • an under bump metal 906 is formed at the second via hole of the first upper insulating layer 705, and the under bump metal 906 is connected to the end pads of the first redistribution layer 703.
  • the fabrication of the under bump metal 906 is achieved by processes such as sputtering, electroplating, vacuum evaporation deposition, and the like by photolithography, development, etching, and the like.
  • the material of the under bump metal 906 is a metal or alloy that is Wetting with the solder, such as Ni, Cu, Pt, Ag, and alloys thereof.
  • the outer connecting bumps 908 are formed on the under bump metal 906. Its production can be through electroplating, printing, ball planting, ball placement and other processes.
  • the reflow process is carried out.
  • the reflow can be achieved by heat conduction, convection, radiation, and the like.
  • the material of the outer connecting bumps 908 is mainly solder metal.
  • the carrier and temporary bonding glue are removed.
  • Carrier plates and temporary bonding adhesives can be removed by mechanical, heating, chemical, laser, and the like. Then, the entire mass storage memory "wafer" is flipped (Flip Over) so that the inactive surface 110b of the first memory chip 110 and the lower surface of the solid sealing layer 302 in the first memory chip set 310 are at the top level. surface.
  • a protective film 909 is deposited on the inactive surface 110b of the first memory chip 110 and the lower surface of the solid sealing layer 302.
  • the deposition of the protective film 909 can be carried out in various ways such as spin coating, spray coating, printing, rolling, hot pressing, or vacuum pressing.
  • the protective film material is an organic material.
  • the formed large-capacity memory structure is subjected to separation and cutting.
  • the interlayer conductive pillars are respectively electrically connected to the redistribution layers of the two memory chip sets adjacent to each other.
  • the redistribution layer of the uppermost storage chipset is electrically connected to the external connection bumps; any one of the memory chipsets is sequentially stacked with at least two memory chips, and the conductive pillars of the at least two memory chips are staggered by a preset angle And packaging at least two memory chips into a unitary structure, and forming a composite insulating layer over the integrated structure, a redistribution layer is formed in the composite insulating layer, and the redistribution layer is electrically connected to the conductive pillars in the layer.
  • the embodiment of the present invention further provides a method for fabricating a semiconductor memory module, where the semiconductor memory module includes the semiconductor memory and the control chip set described in the foregoing embodiments, and the method for fabricating the semiconductor memory may adopt the above embodiment.
  • the method for fabricating the semiconductor memory device may further include: fabricating a control chipset on the basis of the semiconductor memory.
  • the method for fabricating the semiconductor memory module provided by the embodiment of the present invention may include:
  • control chip combination region inter-conductive pillar on the carrier board, the control chip group and the memory core
  • the chip groups are stacked in order from bottom to top, and the second redistribution layer of the control chip group is electrically connected to the adjacent memory chip group through the inter-region conductive pillars, and the first redistribution layer located at the bottom
  • the layer or the second redistribution layer is electrically connected to the external connection bump;
  • control chipset The steps of making a control chipset include:
  • a second composite insulating layer is formed under the control chip, a second redistribution layer is formed in the second composite insulating layer, and the second redistribution layer is electrically connected to the inner conductive pillars in the second layer.
  • the following also describes the sequence of the memory chipset, the control chipset, the interlayer conductive pillars, the regional conductive pillars, the first composite insulating layer, and the second composite insulating layer in the process.
  • the embodiment of the present invention uses four memory chipsets as For the description of the example, and the method for preparing the semiconductor memory, reference may be made to the description of the above embodiments, and details are not described herein again.
  • a first upper insulating layer 705 of the first composite insulating layer of the fourth layer is patterned by a standard process of semiconductor device wafer fabrication to form an opening, and the opening is up to the first redistribution layer 703 respective end faces are exposed (not shown).
  • the first upper insulating passivation layer 705 can be patterned using a front or middle pass of a standard semiconductor, such as by exposure, development, wet or dry etching.
  • an inter-region conductive pillar 707 for storing a chipset and a control chipset is fabricated.
  • the making inter-area conductive pillars may include:
  • inter-region conductive pillars are formed on the first upper insulating layer, and the inter-region conductive pillars are used to connect the control chipset and the memory chipset.
  • one end of the inter-region conductive pillar 707 passes through the opening of the first upper insulating layer 705, and is connected to each corresponding end surface of the first redistribution layer 703, and the height of the other end of the inter-region conductive pillar 707 should be about 100 ⁇ m.
  • the inter-region conductive pillars 707 can be fabricated using standard semiconductor fabrication techniques such as vacuum deposition, electroplating, and electroless plating.
  • the method for fabricating the inter-region conductive pillars is similar to the method for fabricating the inter-layer conductive pillars, and is directly fabricated on the formed composite insulating layer, and the inter-region conductive pillars are first prepared, and then the control chip and the control chip are fabricated. Electrically filled, so that low-temperature thermosetting materials can be used as the filling medium. Electrical quality, rather than expensive thick layer of photosensitive dielectric material, and eliminating the need for lithography in the solid sealing layer, the production cost is reduced, and the laser drilling is also solved because laser drilling is not required for the sealing material. Pitch restrictions are difficult to meet the requirements of large-capacity sensor fabrication for ultra-fine pitch.
  • control chipset 810 can be formed between the inter-region conductive pillars 707.
  • steps of fabricating the control chipset can include:
  • a second composite insulating layer is formed over the control chip, and a second redistribution layer is formed in the second composite insulating layer, and the second redistribution layer is electrically connected to the conductive pillars in the second layer.
  • the logic wafer 800 has an array arrangement of control chips (logic chips) 806.
  • the control chip 806 has an active surface 806a and a non-active surface 806b.
  • a control chip 806 is externally connected to the conductive second pad 821.
  • a pre-deposited second layer is electrically conductive.
  • Column 808 The deposition of the conductive pillars 808 in the second layer can be achieved by different methods, such as vacuum deposition and electroplating.
  • the second pad 821 may be a single layer or a plurality of layers of metal such as Ti, W, Al, Cu, Ni, Pt, Ag, Au or alloys thereof and the like.
  • the material of the conductive pillars 808 in the second layer is a metal such as Cu, Ni, Ag, Au or an alloy thereof, and the height of the conductive pillars in the second layer is about 20 to 40 ⁇ m.
  • the thickness of the control chip 806 is 40 to 50 ⁇ m.
  • a DAF film 801 is deposited on the back side of the wafer 800 (corresponding to the inactive surface of the control chip 806 chip). Its deposition can be achieved in a variety of ways: spin coating, spray coating, printing, rolling, and hot pressing.
  • the thickness of the effective bonding layer of the DAF film 801 is about 10 to 30 ⁇ m.
  • the DAF film 801 and the DAF film 101 and the DAF film 201 may be the same DAF film or different DAF films.
  • the DAF film is an organic material.
  • the semiconductor logic wafer is diced to obtain a control chip 806.
  • Cutting uses standard semiconductor wafer cutting methods such as mechanical cutting, laser cutting and the like.
  • the active surface 806a of the control chip 806 is directed upward by a semiconductor chip device, and is attached to the first upper insulating layer of the fourth first composite insulating layer in a so-called "Chip-to-Wafer" manner.
  • the surface of layer 705 implements the configuration of chip 806 on the functional area of the carrier.
  • the deposition medium material solidifies the entire carrier to form a solid sealing layer 802, that is, to fill the voids of the cladding logic chip 806 and the gaps between the surface and the inter-region conductive pillars 707.
  • the height of the solid sealing layer 802 should be higher than all the second inner conductive pillars 808 and the inter-region conductive pillars 707 in the control chip 806. high.
  • the deposition method may be spin coating, printing, organic lamination, and plastic sealing.
  • the dielectric material is generally an organic thermoset material, but is not excluded as an insulating non-organic material.
  • the sealing layer 802 is thinned and thinned until all of the conductive pillar surfaces on the control chip 806 and the surface of the inter-region conductive pillars 707 are completely exposed.
  • the thinning method adopts a standard grinding and polishing technique of semiconductor manufacturing. After grinding and polishing, the distance between the upper surface of the solid sealing layer 802 and the uppermost surface of the control chip 806 is about 20 ⁇ m.
  • a second composite insulating layer is formed over the solidified control chip 806, and forming the second composite insulating layer under the control chip 806 may include:
  • a second upper insulating layer is formed under the second redistribution layer.
  • a lithographic second lower insulating layer 801 is coated on the front surface of the solid sealing layer 802.
  • the material of the second lower insulating layer 801 includes a photosensitive resin and a resin which can be patterned by a dry etching process, such as poly.
  • a photosensitive resin such as poly
  • a resin which can be patterned by a dry etching process such as poly.
  • the second lower insulating layer 801 has a thickness of 5 to 7 ⁇ m.
  • the second lower insulating layer 801 is patterned by a standard process of semiconductor device wafer fabrication to form a third via hole, and the third via hole is up to the surface and region of the conductive pillar 808 in each second layer of the control chip 806.
  • the surface of the conductive column 707 is exposed to be exposed (not shown).
  • a second redistribution layer 803 is formed on the second lower insulating layer 801 by a standard semiconductor fabrication process.
  • the process consists of a series of processes such as thin film deposition, electroplating, photolithography, development, and etching.
  • the terminal on one side of the second redistribution layer 803 is connected to the surface of the second interlayer conductive pillar 808 and the inter-region conductive pillar 707 on the second pad of the active surface of the control chip 806 via the second via hole on the second lower insulating layer 801.
  • each memory chip in the memory chipset 710 (through the first redistribution layer 703 and the inter-region conductive pillar 707), and each memory chip in the memory chipset 610 (through the first redistribution layer 603, the memory chip) Inter-layer conductive pillars 607, and inter-region conductive pillars 707), memory chips in the memory chipset 510 (through the first redistribution layer 503, storage chipset interlayer conductive pillars 507, 607 and inter-region conductive pillars) 707), and an electrical connection (not shown) of each of the memory chips in the memory chipset 310 (through the first redistribution layer 403, the memory chipset interlayer electrical interconnections 407, 507, 607 and the inter-region conductive pillars 707).
  • the material of the second redistribution layer 803 is a metal material such as Al, Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W, or the like and alloys thereof
  • a photolithographic second upper insulating layer (passivation layer) 805 is formed on the second redistribution structure 803 and the second lower insulating layer 801.
  • the second upper insulating layer (passivation layer) 805 is fabricated using a standard semiconductor front or intermediate process, such as by exposure, development, wet or dry etching.
  • the material of the second upper insulating layer 805 is generally an organic material, but is not excluded as an inorganic material.
  • Organic materials include photosensitive resin-forming patterns such as polyimide, photosensitive epoxy resin, solder resist ink, green paint, dry film, photosensitive build-up material, bisphenylcyclobutene resin, phenylbenzodioxin One or more of the azole resins.
  • the under bump metal and the external connection terminal are fabricated below.
  • the second upper insulating layer 805 is patterned by a standard process of semiconductor device wafer fabrication to form an opening, and the opening is exposed to the respective end faces of the second redistribution layer 803 layer (not shown).
  • the second upper insulating layer 805 can be patterned using a front or intermediate process of a standard semiconductor, such as by exposure, development, wet or dry etching.
  • the under bump metal 906 is formed on the opening of the second upper insulating layer 805, and is connected to the end pads of the second redistribution layer 803.
  • the fabrication of the under bump metal 906 is achieved by processes such as sputtering, electroplating, vacuum evaporation deposition, and the like by photolithography, development, etching, and the like.
  • the material of the under bump metal 906 is a metal or alloy that is compatible with the solder, such as Ni, Cu, Pt, Ag, and alloys thereof.
  • the outer connecting bumps 908 are formed on the under bump metal 906.
  • the production can be carried out by electroplating, printing, ball-planting, ball-laying, etc., followed by a reflow process.
  • the reflow can be achieved by heat conduction, convection, radiation, and the like.
  • the material of the outer connecting bumps 908 is mainly solder metal.
  • solder metal For example, Sn, Ag, Cu, Pb, Au, Ni, Zn, Mo, Ta, Bi, In, etc., and alloys thereof.
  • the carrier 300 and the temporary bonding glue 301 are removed.
  • the carrier 300 and the temporary bonding paste 301 can be removed by mechanical, heating, chemical, laser, or the like. Then, the entire high-end memory module is reconfigured to "wafer", so that the inactive surface 110b of the first memory chip 110 and the lower surface of the solid sealing layer 302 in the memory chipset 310 are on the topmost surface of the memory module (not drawn) Out).
  • a protective film 909 is deposited on the inactive surface 110b of the first memory chip 110 and the lower surface of the solid sealing layer 302.
  • the protective film can be deposited in various ways, such as spin coating, spray coating, printing, rolling, hot pressing, or vacuum pressing, etc., and the protective film material is an organic material.
  • the formed high-end semiconductor memory module is separated and cut along the broken line in the figure to obtain a memory module.
  • the semiconductor memory module is composed of two functional areas: a large-capacity storage area and a control area.
  • the mass storage area itself is composed of four memory chipsets and one control chipset.
  • Each memory chipset is composed of a first memory chip and a second memory chip stack, and the control chipset is one control chip.
  • the first memory chip and the second memory chip may be the same or different.
  • the memory chip integrated in the storage area will be twice as large as the “super chip”.
  • the control chipset is located below the slice between the storages.
  • the external connection bump is disposed on a side of the control chipset away from the storage chipset.
  • the control chipset may also be disposed between the two memory chipsets.
  • the external connection bumps are disposed on the side of the lowermost memory chipset, such as the external connection bumps in the semiconductor memory of the above embodiment.
  • the embodiment of the present invention does not describe the case where the external connection bumps are disposed on one side of the memory chipset in the semiconductor memory module.
  • the manufacturing method of the semiconductor memory module sequentially forms a control chipset and at least two memory chip sets on the carrier board, each memory chipset includes at least two memory chips, and the memory chipset and the memory chipset pass The first layer of the inner conductive pillar, the interlayer conductive pillar, and the first redistribution layer between the memory chip sets are electrically connected, and the plurality of memory chip sets and the control chipset pass the first interlayer conductive pillar and the second interlayer conductive
  • the pillars, the interlayer conductive pillars, the inter-region conductive pillars, the first redistribution layer between the memory chipsets, and the second redistribution layer between the memory chipset and the control chipset are electrically connected, thus not only providing
  • the large-capacity storage area ensures the small size of the storage area, and the storage chip and the control chip (logic chip) can be disposed on the same wafer, thereby realizing the three-dimensional wafer level integration of the control chip and the

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Abstract

提供了一种半导体存储器、半导体存储模块及其制作方法，该半导体存储模块包括自下而上依次堆叠的至少两个存储芯片组（310,510,610,710），上下相邻的两个存储芯片组的重布线层（403,503,603,703）通过层间导电柱（407,507,607）电连接，且位于最下方的存储芯片组的重布线层（703）与对外连接凸块（908）电连接；存储芯片组包括依次堆叠的至少两个存储芯片（110,210），以及位于至少两个存储芯片下方的复合绝缘层，至少两个存储芯片包封为一体结构，重布线层设置在复合绝缘层中，至少两个存储芯片的层内导电柱（122,222）错开预设角度，以分别与重布线层电连接。这种半导体存储模块实现了半导体存储器的大容量和高集成度，并且有效提高了存储器的堆叠效率，降低了堆叠难度。

Description

半导体存储器、半导体存储模块及其制作方法 技术领域
本发明实施例涉及半导体技术领域，尤其涉及半导体存储器、半导体存储模块及其制作方法。
背景技术
为了实现存储器的大容量、高集成度和高性能，可以采用存储芯片堆叠的方式。目前芯片堆叠的方式主要有两种：一种是存储芯片以错位式的方式一个接一个地堆叠上去，再用金属引线键合一阶一阶地把各个芯片电连接在一起。采用错位式结构的目的是为了实施金属引线键合。另一种是把存储芯片垂直地叠在一起，用硅通孔(Through Silicon Via，TSV)来实现各堆叠存储芯片间电信号连接。这两种方法，都有较显著的缺陷：芯片错位式堆叠加引线键合，随着堆叠的芯片数增加，不仅造成封装体尺寸较大，而且电信号延迟增长；而基于硅通孔技术的堆叠，不仅工艺复杂昂贵，而且用于大规模制造硅通孔芯片的供应链仍未完全形成。
这两种堆叠技术还有两个共同的低效率特征：1)堆叠封装体的制作，都是以单颗形式完成的；2)电性能和功能测试，亦是以单颗形式来进行。这些缺陷，使得现有大容量存储器制造技术越来越难于满足半导体技术的发展和微电子器件制造的趋势——更高性能，更小的形状系数(form factor)，更低的成本。
扇出型晶圆级技术(FOWLP)可以实现存储芯片的堆叠，从而作为大容量存储器制造的解决方案。但目前FOWLP技术是二维的，难以在具有多存储单元的高端存储器装置的制造上得到应用。
美国专利US2005/0124093A1(Wen-KunYang等)介绍了二维的扇出型晶圆级封装技术。如图1所示，100为载板；110为芯片；130和130a为重布线层(RDL)；148为芯片层间电互连；120，122，132，120a和132a为介电质；136为对外连接终端(锡球)。
美国专利US2009/0014876A1(Cheul-Joong Youn等)提出了基于芯片堆叠扇出型晶圆级技术实现存储装置三维集成的方法，如图2所示，104，110，132和142为芯片；106，112，134和144为绝缘介电质；108，118，136和146为芯片层间电互连；116为最外层RDL；120为对外连接终端(锡球)。该专利提出的方法是一理想化，在工程上难以实现的概念。因为：1)若用塑封材料填充芯片间空隙，金属重布线层(RDL)无法直接沉积在塑封材料上；2)采用旋涂介电材料，难以做到与芯片表面齐平；3)芯片主动面金属焊盘的防止有机物污染问题等。而且，根据该专利介绍的基本方法，堆叠4层以上芯片是难以实现的。
美国专利US8872350B2(Shigenorl Sawachi等)介绍了两种填充存储芯片间空隙并形成芯片层间电连接通道方法。如图3所示，1为散热片(亦是载板)；2为芯片；6为RDL；9为芯片层间电互连；4为绝缘介电质；13为对外连接终端(锡球)。第一种方法是塑封后激光钻孔。该方法对普通半导体芯片封装可以实施，但不能用于用16nm(或以下)工艺制造的高端存储芯片，因为这类高端存储芯片的节距在50μm左右，激光钻孔不能施用于具有这么小节距的芯片；第二种方法将是一很困难的(深度盲孔填充)，且昂贵的(因采用很厚的光敏介电质(100μm左右)作为芯片间填充材料)制造技术。该专利提供的方法制造成本高，且难以实现大规模量产。
因此，目前在大容量存储器堆叠技术上存在的缺陷是：堆叠效率低、多层堆叠技术难以实现，以及难以大规模量产。
发明内容
有鉴于此，本发明实施例提供半导体存储器、半导体存储模块及其制作方法，以解决现有技术中半导体存储器件堆叠效率低、多层堆叠技术难以实现，以及难以大规模量产的技术问题。
第一方面，本发明实施例提供了一种半导体存储器，包括自下而上依次堆叠的至少两个存储芯片组，上下相邻的两个所述存储芯片组的第一重布线层通 过层间导电柱电连接，且位于最下方的存储芯片组的第一重布线层与对外连接凸块电连接；
所述存储芯片组包括依次堆叠的至少两个存储芯片，以及位于所述至少两个存储芯片下方的第一复合绝缘层，所述至少两个存储芯片包封为一体结构，所述第一重布线层设置在所述第一复合绝缘层中，所述至少两个存储芯片的第一层内导电柱错开预设角度，以分别与所述第一重布线层电连接。
第二方面，本发明实施例提供了一种半导体存储模块，包括第一方面所述的半导体存储器，还包括控制芯片组，所述控制芯片组与所述存储芯片组自下而上依次堆叠，所述控制芯片组的第二重布线层与相邻的所述存储芯片组之间通过区域间导电柱电连接，且位于最下方的所述第一重布线层或所述第二重布线层与所述对外连接凸块电连接；
所述控制芯片组包括控制芯片，以及位于所述控制芯片下方的第二复合绝缘层，所述第二重布线层设置在所述第二复合绝缘层中，所述控制芯片的第二层内导电柱与所述第二重布线层电连接。
第三方面，本发明实施例还提供了一种半导体存储器的制作方法，包括在载板自下而上依次制作至少两个存储芯片组，以及制作层间导电柱，所述层间导电柱分别与上下相邻的两个所述存储芯片组的第一重布线层电连接，且位于最下方的存储芯片组的第一重布线层与对外连接凸块电连接；
其中在制作任一存储芯片组时，包括如下步骤：
将所述至少两个存储芯片依次堆叠，所述至少两个存储芯片的第一层内导电柱错开预设角度；
将所述至少两个存储芯片包封为一体结构，且将所述第一层内导电柱露出；
在所述一体结构下方形成第一复合绝缘层，所述第一复合绝缘层中形成有第一重布线层，所述第一重布线层与所述第一层内导电柱电连接。
第四方面，本发明实施例还提供了一种半导体存储模块的制作方法，包括 第三方面所述的半导体存储器的制作方法，还包括在载板上制作控制芯片组和区域间导电柱，所述控制芯片组与所述存储芯片组自下而上依次堆叠，所述控制芯片组的第二重布线层与相邻的所述存储芯片组之间通过区域间导电柱电连接，且位于最下方的所述第一重布线层或所述第二重布线层与所述对外连接凸块电连接；
所述制作控制芯片组的步骤包括：
将控制芯片的第二层内导电柱露出；
在所述控制芯片下方形成第二复合绝缘层，所述第二复合绝缘层中形成有第二重布线层，所述第二重布线层与所述第二层内导电柱电连接。
本发明实施例提供的半导体存储器、半导体存储模块及其制作方法，通过将至少两个存储芯片依次堆叠组成存储芯片组，其中至少两个存储芯片的层内导电柱错开预设角度，分别与重布线层电连接；并将至少两个存储芯片组依次堆叠组成存储器，其中上下相邻的两个存储芯片组的重布线层通过层间导电柱电连接，实现了存储器的大容量和高集成度，有效提高了存储器的堆叠效率，并且降低了堆叠难度。
附图说明
图1为现有技术提供的二维扇出型晶圆级封装技术的存储器的结构示意图；
图2为现有技术提供的基于芯片堆叠扇出型晶圆级技术的存储器的结构示意图；
图3为现有技术提供的第三种存储器的结构示意图；
图4为本发明实施例提供的一种半导体存储器的剖面结构示意图；
图5为本发明实施例提供的一种半导体存储模块的剖面结构示意图；
图6为本发明实施例提供的一种半导体存储器的载板的俯视示意图；
图7为本发明实施例提供的一种在载板上涂覆临时键合胶的剖面结构示意图；
图8a为本发明实施例提供的一种在存储器晶圆上形成第一存储芯片的俯视示意图；
图8b为本发明实施例提供的一种在存储器晶圆上形成第一存储芯片的剖面结构示意图；
图9a为本发明实施例提供的一种在存储器晶圆上形成第二存储芯片的俯视示意图；
图9b为本发明实施例提供的一种在存储器晶圆上形成第二存储芯片的剖面结构示意图；
图10a为本发明实施例提供的切割存储器晶圆形成多个第一存储芯片的剖面结构示意图；
图10b为本发明实施例提供的切割存储器晶圆形成多个第二存储芯片的剖面结构示意图；
图11a、图11b和图11c为本发明实施例提供的在载板上制作第一存储芯片和第二存储芯片的结构示意图；
图12为本发明实施例提供的对形成有第一存储芯片和第二存储芯片的载板进行固封，形成固封层的剖面结构示意图；
图13为本发明实施例提供的对固封层进行减薄的剖面结构示意图；
图14为本发明实施例提供的在固封层上形成第一下部绝缘层的剖面结构示意图；
图15为本发明实施例提供的在第一下部绝缘层形成第一重布线层的剖面结构示意图；
图16为本发明实施例提供的在第一重布线层上形成第一上部绝缘层的剖面结构示意图；
图17为本发明实施例提供的形成层间导电柱的剖面结构示意图；
图18为本发明实施例提供的在层间导电柱之间制作一体结构的剖面结构示意图；
图19为本发明实施例提供的对一体结构进行固封，形成固封层的剖面结构示意图；
图20为本发明实施例提供的对第二层存储芯片组中的固封层进行减薄的剖面结构示意图；
图21为本发明实施例提供的形成第二层存储芯片组的第一下部绝缘层的剖面结构示意图；
图22为本发明实施例提供的形成第二层存储芯片组的第一重布线层和第一上部绝缘层的剖面结构示意图；
图23为本发明实施例提供的形成第二个层间导电柱的剖面结构示意图；
图24为本发明实施例提供的形成四个存储芯片组的剖面结构示意图；
图25为本发明实施例提供的在第一复合绝缘层上制作对外连接凸块的剖面结构示意图；
图26为本发明实施例提供的图25的倒置并去除载板和键合胶的结构示意图；
图27为本发明实施例提供的对存储器沉积保护膜的结构示意图；
图28为本发明实施例提供的对形成的多个存储器进行切割的结构示意图；
图29为本发明实施例提供的单个存储器的结构示意图。
图30为本发明实施例提供的形成区域间导电柱的剖面结构示意图；
图31a为本发明实施例提供的一种在逻辑晶圆上形成控制芯片的俯视示意图；
图31b为本发明实施例提供的一种在逻辑晶圆上形成控制芯片的剖面结构示意图；
图32为本发明实施例提供的切割逻辑晶圆形成多个控制芯片的剖面结构示意图；
图33为本发明实施例提供的在存储区域制作控制芯片的剖面结构示意图；
图34为本发明实施例提供的对控制芯片进行固封的剖面结构示意图；
图35为本发明实施例提供的对控制芯片的固封层进行减薄的剖面结构示意图；
图36为本发明实施例提供的制作第二复合绝缘层的剖面结构示意图；
图37为本发明实施例提供的在第二复合绝缘层上制作对外连接凸块的剖面结构示意图；
图38为本发明实施例提供的将图37的剖面结构示意图倒置并沉积保护膜的结构示意图；
图39为本发明实施例提供的对形成的多个存储模块进行切割的结构示意图；
图40为本发明实施例提供的单个存储模块的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下将结合本发明实施例中的附图，通过具体实施方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例，基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动的前提下获得的所有其他实施例，均落入本发明的保护范围之内。
实施例
图4为本发明实施例提供的一种半导体存储器的结构示意图，本发明实施例提供的半导体存储器可以用作高速缓冲存储器、主存储器或堆栈存储器等。如图4所示，本发明实施例提供的半导体存储器可以包括：
自下而上依次堆叠至少两个存储芯片组，上下相邻的两个存储芯片组的第一重布线层通过层间导电柱电连接，且位于最下方的第一重布线层与对外连接凸块电连接；
存储芯片组包括依次堆叠的至少两个存储芯片，以及位于至少两个存储芯片下方的第一复合绝缘层，所述至少两个存储芯片包封为一体结构，第一重布线层设置在第一复合绝缘层中，至少两个存储芯片的第一层内导电柱错开预设角度，以分别与第一重布线层电连接。
示例性的，图4所示的存储器包括四个存储芯片组，这里以四个存储芯片 组进行说明，如图4所示，存储器包括第一存储芯片组310、第二存储芯片组510、第三存储芯片组610以及第四存储芯片组710，其中，第四存储芯片组710、第三存储芯片组610、第二存储芯片组510以及第一存储芯片组310自下而上依次堆叠。
第一存储芯片组310、第二存储芯片组510、第三存储芯片组610和第四存储芯片组710可以分别包括两个、三个或者四个存储芯片，图4中仅是以两个存储芯片，第一存储芯片110和第二存储芯片210进行说明。第一存储芯片110包括第一主动面以及设置在第一主动面上的第一焊盘，在所述第一焊盘内设置有第一存储芯片110的第一层内导电柱122，第二存储芯片210包括第一主动面以及设置在第一主动面上的第一焊盘，在所述第一焊盘内设置有第二存储芯片210的第一层内导电柱222。具体的，第一存储芯片110和第二存储芯片210的空间取向一致，即两个存储芯片的第一主动面的朝向相同，因此第一层内导电柱122和222的朝向也相同。可选的，第一存储芯片110、第二存储芯片210、第一层内导电柱122和222可以理解为一个一体结构。
可选的，第一存储芯片组310还可以包括位于第一存储芯片组310中一体结构下方的第一复合绝缘层，该第一复合绝缘层包括第一上部绝缘层405、第一下部绝缘层401以及位于第一上部绝缘层405和第一下部绝缘层401之间的第一重布线层403；第二存储芯片组510还可以包括位于第二存储芯片组510中一体结构下方的第一复合绝缘层，该第一复合绝缘层包括第一上部绝缘层505、第一下部绝缘层501以及位于第一上部绝缘层505和第一下部绝缘层501之间的第一重布线层503；第三存储芯片组610还可以包括位于第三存储芯片组610中一体结构下方的第一复合绝缘层，该第一复合绝缘层包括第一上部绝缘层605、第一下部绝缘层601以及位于第一上部绝缘层605和第一下部绝缘层601之间的第一重布线层603；第四存储芯片组710还可以包括位于第四存储芯片组710中一体结构下方的第一复合绝缘层，该第一复合绝缘层包括第一上部绝缘层705、第一下部绝缘层701以及位于第一上部绝缘层705和第一下部绝缘层701之间的第一重布线层703。可选的，第一存储芯片组310中的第一层内导电柱122和222可以通过第一下部绝缘层401中的第一通孔与第一重布线层403电连接， 第一重布线层403通过第一上部绝缘层405中的第二通孔与层间导电柱407电连接；第二存储芯片组510中的第一层内导电柱122和222可以通过第一下部绝缘层501中的第一通孔与第一重布线层503电连接，重布线层503通过上部绝缘层505中的第二通孔与层间导电柱507电连接；第三存储芯片组610中的第一层内导电柱122和222可以通过第一下部绝缘层601中的第一通孔与第一重布线层603电连接，重布线层603通过上部绝缘层605中的第二通孔与层间导电柱607电连接；第四存储芯片组710中的第一层内导电柱122和222可以通过第一下部绝缘层701中的通孔与第一重布线层703电连接，重布线层703通过上部绝缘层705中的第二通孔对外连接凸块908电连接。
存储芯片组中的第一层内导电柱122和222可以错开预设角度，以分别与对应的第一重布线层电连接，例如，第一存储芯片组310中的第一层内导电柱122和222可以错开预设角度，以分别与第一存储芯片310中的第一重布线层403电连接，第二存储芯片组510中的第一层内导电柱122和222同样可以错开预设角度，以分别与第二存储芯片510中的第一重布线层503电连接。可选的，所述预设角度可以为180°、90°或者45°。需要说明的是，存储芯片组中的层内导电柱可以错开0°以外的任意角度，只要保证层内导电柱不重合叠加即可，可选的是错开180°、90°或者45°。
可选的，在存储芯片组中还可以包括层间导电柱，实现不同的存储芯片组之间的电连接，例如，在第二存储芯片组510可以包括层间导电柱407，第一存储芯片组310的第一重布线层403和第二存储芯片组510的第一重布线层503可以通过层间导电柱实现电连接，以实现第一存储芯片组310和第二存储芯片组510的电连接。
可选的，所述存储器还可以包括对外连接凸块908，当第四存储芯片组710位于最下方时，第四存储芯片组710的第一重布线层703与对外连接凸块908电连接。可选的，所述存储器还可以包括凸块下金属层906，第四存储芯片组710的第一重布线层703通过凸块下金属层906与外连接凸块908电连接。
需要说明的是，图4所示的存储器只是作为本发明实施例提供的存储器的一种示例说明，本发明实施例提供的存储器中，存储芯片组还可以是两个、三 个或者多个，以实现存储器的大容量、高集成度。
可选的，所述第一上部绝缘层、第一所述下部绝缘层为有机光敏材料制成。
可选的，所述存储芯片组内的至少两个存储芯片包封为一体结构，302、502、602和702为固封层。
可选的，最上方的存储芯片组的底部可以设置有保护层，如图4所示，在存储芯片组310上方设置有保护层909。
本发明实施例提供的存储器，将拥有层内导电柱的存储芯片组两两叠加，这样在进行三维晶圆级存储器堆叠时，可以降低由于制作工艺多次循环造成的可靠性风险；每堆叠一层，将实际堆叠两个芯片，这样在堆叠芯片层数不变时，堆叠芯片数将翻倍，因此堆叠效率提高一倍，减低生产成本；对芯片间隙的填充和包覆，采用成本低廉的热固材料，并免去使用光刻等工艺，生产成本下降；在堆叠第二存储芯片组时，首先制作层间导电柱实现电互连，后进行存储芯片放置和存储芯片间介电质填充和包覆的方法，解决了激光钻孔对节距限制的困难，从而满足大容量存储器制造对超细节距的要求。
图5为本发明实施例提供的一种半导体存储模块的剖面结构示意图，如图5所示，本发明实施例提供的半导体存储模块包括上述实施例所述的半导体存储器，还可以包括：
控制芯片组，所述控制芯片组与所述存储芯片组自下而上依次堆叠，所述控制芯片组的第二重布线层与相邻的所述存储芯片组之间通过区域间导电柱电连接，且位于最下方的所述第一重布线层或所述第二重布线层与所述对外连接凸块电连接；
所述控制芯片组包括控制芯片，以及位于所述控制芯片下方的第二复合绝缘层，所述第二重布线层设置在所述第二复合绝缘层中，所述控制芯片的第二层内导电柱与所述第二重布线层电连接。
示例性的，图5所示的存储模块包括一个控制芯片组和四个存储芯片组，这里以一个控制芯片组和四个存储芯片组进行说明，如图5所示，存储模块包括一个控制芯片组810、第一存储芯片组310、第二存储芯片组510、第三存储芯片组610以及第四存储芯片组710，其中，控制芯片组810、第四存储芯片组 710、第三存储芯片组610、第二存储芯片组510以及第一存储芯片组310自下而上依次堆叠。
可选的，控制芯片组810可以包括控制芯片806以及位于控制芯片806下方的第二复合绝缘层，所述第二复合绝缘层可以包括第二上部绝缘层805、第二下部绝缘层801，以及位于第二上部绝缘层805和第二下部绝缘层801之间的第二重布线层803。具体的，控制芯片806包括第二主动面以及设置在所述第二主动面上的第二焊盘，在所述第二焊盘中设置有控制芯片806的第二层内导电柱808，第二层内导电柱808与第二焊盘电连接。可选的，控制芯片806中的第二层内导电柱808可以通过第二下部绝缘层801中的第三通孔与第二重布线层803电连接。
可选的，控制芯片806的第二主动面与存储芯片的第一主动面朝向可以相同。
可选的，所述存储模块同样可以包括对外连接凸块908，当控制芯片组810位于最下方时，控制芯片组810的第二重布线层803与对外连接凸块908电连接。进一步的，所述存储模块还可以包括凸块下金属层906，控制芯片组810的第二重布线层803通过凸块下金属层906与外连接凸块908电连接。
需要说明的是，图5所示的存储模块只是作为本发明实施例提供的存储模块的一种示例说明，本发明实施例提供的存储模块中，控制芯片组还可以位于存储芯片组之间，用于实现对存储芯片组的控制。
可选的，第二上部绝缘层以及第二下部绝缘层为有机光敏材料制成。
可选的，所述控制芯片组内的控制芯片由热固材料包封。
可选的，最上方的存储芯片组或控制芯片组的底部可以设置有保护层，如图5所示，在存储芯片组310上方设置有保护层909。
本发明实施例提供的存储模块，通过依次堆叠控制芯片组和至少两个存储芯片组，上下相邻的两个存储芯片组的第一重布线层通过层间导电柱电连接，控制芯片组的第二重布线层与相邻的存储芯片组之间通过区域间导电柱电连接，存储芯片组包括依次堆叠的至少两个存储芯片，并且两个存储芯片的第一层内导电柱错开预设角度，以分别与第一重布线层电连接。采用上述技术方法，存 储芯片组包括至少两个存储芯片，存储芯片组之间通过层间导电柱以及第一重布线层电连接，存储芯片组与控制芯片组通过区域间导电柱预计第二重布线组电连接，保证存储模块具有较高的存储能力以及较小的尺寸，同时保证存储芯片组与控制芯片组置于同一个晶圆中，实现了存储模块的晶圆级制造和晶圆级功能测试，提高存储模块的生产效率。
本发明实施例还提供一种半导体存储器的制作方法，包括在载板自下而上依次制作至少两个存储芯片组，以及制作层间导电柱，所述层间导电柱分别与上下相邻的两个所述存储芯片组的第一重布线层电连接，且位于最下方的所述第一重布线层与对外连接凸块电连接。
下面按照工程中制作存储芯片组、层间导电柱、以及第一复合绝缘层的顺序进行说明，本发明实施例以四个存储芯片组为例进行说明。
首先，提供一载板300，载板300的材料可为金属、硅、玻璃以及有机基板等。载板300的几何形状可以为圆形或者方形。在清洗后的载板300边缘上制作用于芯片贴片位置的对准标记，如图6所示。对准标记的制作一般通过薄膜沉积技术实现，例如：离子溅射、光刻、显影以及蚀刻，也可通过激光蚀刻、丝网印刷、图形电镀以及机械精加工等实现。本发明实施例提供的半导体存储器的制作方法一次可以形成多个存储器，将多个存储器切割即得到单个存储器。再次对载板300进行清洗后在载板300上涂覆临时键合胶301，如图7所示。临时键合胶301的涂覆可使用旋涂、喷涂、滚压、印刷、非旋转涂覆、热压、真空压合以及压力贴合等方式。临时键合胶301可以为有机材料或复合材料。
在载板300上制作存储芯片组，具体可以为：首先制作存储芯片组中的存储芯片，本发明实施例以两个存储芯片为例进行介绍。
制作任一存储芯片组时，包括如下步骤：
将至少两个存储芯片依次堆叠，所述至少两个存储芯片的第一层内导电柱错开预设角度；
将所述至少两个存储芯片包封为一体结构，且将所述存储芯片的第一层内导电柱露出；
在所述一体结构下方形成第一复合绝缘层，所述第一复合绝缘层中形成有 第一重布线层，所述第一重布线层与所述第一层内导电柱电连接；
如图8a和图8b所示，存储器晶圆100有第一存储芯片110的阵列排布。第一存储芯片110具有主动面110a和非主动面110b，在主动面110a上，有第一存储芯片110对外连接导电的第一焊盘121，在焊盘121上，有预先沉积的第一层内导电柱122。第一层内导电柱122的沉积可采用不同方法实现，例如真空沉积和电镀等。第一焊盘121可为单层或多层金属，如Ti，W，Al，Cu，Ni，Pt，Ag，Au或其合金等，第一层内导电柱122的材料为金属，如Cu，Ni，Ag，Au或其合金等。第一层内导电柱122的高度在70～90μm左右。第一存储芯片110的厚度为40～50μm。在晶圆100的背面(对应第一存储芯片110的非主动面)上，沉积DAF膜101。它的沉积可以多种方式实现：如旋涂、喷涂、印刷、滚压以及热压等。DAF膜101的有效粘接层的厚度在10～30μm左右。DAF膜101为有机材料。
如图9a和图9b所示，存储器晶圆200有第二存储芯片210的阵列排布。第二存储芯片210与第一存储芯片110可为同一类型存储器，也可为不同类型存储器。第二存储芯片210具有主动面210a和非主动面210b，在主动面210a上，有第二存储芯片210对外连接导电的第一焊盘221。在第一焊盘221上，有预先沉积的第一层内导电连接柱222。第一层内导电柱122的沉积可采用不同方法实现，例如真空沉积和电镀等。第一焊盘121可为单层或多层金属，如Ti，W，Al，Cu，Ni，Pt，Ag，Au或其合金等，第一导电柱122的材料为金属，如，Cu，Ni，Ag，Au或其合金等。第一导电柱的高度在20～40μm左右。第二存储芯片210的厚度为40～5μm。在晶圆200的背面(对应第二存储芯片210的非主动面)上，沉积DAF膜201。它的沉积可以多种方式实现：如，旋涂、喷涂、印刷、滚压以及热压等。DAF膜201的有效粘接层的厚度在10～30μm左右，DAF膜201为有机材料，DAF膜201与DAF膜101可为同一种DAF膜，也可为不同的DAF膜。
如图10a和图10b所示，对上述两个半导体存储器晶圆分别进行切割，得到第一存储芯片110和第二存储芯片210。可选的，切割采取标准半导体晶圆切割方法，如机械切割或者激光切割等方式。
如图11a，图11b和图11c所示，在载板300上，用半导体贴片设备将第一存储芯片110的主动面110a朝上，以所谓的“Chip-to-Wafer”的方式，贴到载板300上临时键合胶301的上表面，实现第一存储芯片110在载板上的再配置。类似地，用半导体贴片设备将第二存储芯片210的主动面220a朝上，以所谓“Chip-to-Chip”的方式，分别置放到第一存储芯片110的主动面110a上，形成一体结构，所述一体结构可以形象地理解为一个“超级芯片”。置放第二存储芯片210时，第二存储芯片210与第一存储芯片110有一个位置上的错开以露出第一存储芯片110主动面上的第一层内导电柱122。通过这样的置放，也实现了第二存储芯片210在载板300上的再重置。将贴完一体结构的载板置于一个具有一定高压的烘箱里。加压以排挤出滞留于各贴片界面的气泡，确报贴片界面的完整性，同时对DAF材料进行预固化处理。
如图12所示，沉积介质材料对包含一体结构的载板进行固封，形成固封层302，即填充包覆一体结构的空隙和表面。固封层302的高度应比一体结构中的第一层内导电柱高。沉积方法可为旋涂，印刷，有机叠层或者塑封等。介质材料一般为有机热固材料，但并不排除为绝缘非有机材料。
如图13所示，对固封层302进行减薄处理，减薄直到一体结构上所有的第一层内导电柱表面露出。减薄方法采用半导体制造的标准磨抛技术。此时，固封介质材料表面离一体结构最上端表面，即第二存储芯片210的主动面210a的距离为20μm左右。
所述在所述一体结构上方形成第一复合绝缘层可以包括：
在所述一体结构上方形成第一下部绝缘层，以及在所述第一下部绝缘层上形成第一通孔；
在所述第一下部绝缘层上方形成第一重布线层，所述第一重布线层通过第一通孔与所述第一层内导电柱电连接；
在所述第一重布线层上方形成第一上部绝缘层。
具体的工程上的方法如下：如图14所示，在固封层302的上表面沉积可光刻的第一下部绝缘层401。第一下部绝缘层401的材料包括感光树脂和可以通过干法刻蚀等工艺形成图形的树脂，例如聚酰亚胺、感光型环氧树脂、双苯环丁 烯树脂以及苯基并二恶唑树脂中的一种或者多种，第一下部绝缘层401的厚度为5～7μm。
采用半导体器件晶圆制作的标准工艺，对第一下部绝缘层401进行图形制作，形成第一通孔，且第一通孔直至一体结构中各第一层内导电柱的表面，以露出各第一层内导电柱(图中未示出)。
如图15所示，采用标准半导体制作工艺，在第一下部绝缘层401上制作第一重布线层403。该过程包含一系列的薄膜沉积、电镀、光刻、显影以及蚀刻等工艺制作。第一重布线层403一边的终端经第一下部绝缘层401上的第一通孔与一体结构中的第一层内导电柱122和222相连，以引出第一存储芯片110和第二存储芯片210的电连接。第一重布线层403的材料可以为金属材料，如Al、Au、Cr、Ni、Cu、Mo、Ti、Ta、Ni-Cr、W等及其合金。
如图16所示，在第一重布线层403及第一下部绝缘层401上制作可光刻的第一上部绝缘层405。第一上部绝缘层405的材料包括感光树脂和可以通过干法刻蚀等工艺形成图形的树脂，例如聚酰亚胺、感光型环氧树脂、双苯环丁烯树脂、苯基并二恶唑树脂中的一种或者多种。第一上部绝缘层405的厚度为5～7μm。
采用半导体器件晶圆制作的标准工艺，对第一上部绝缘层405进行图形制作，形成开口，且该开口直至第一重布线层403各相应端面，使其露出。第一上部绝缘层405图形制作可采用标准半导体的前道或中道工艺，如通过曝光、显影、湿法或干法刻蚀等工艺。
形成第一上部绝缘层之后，可以在第一上部绝缘层上制作层间导电柱，具体的，制作层间导电柱可以包括：
形成第一上部绝缘层之后，在所述第一上部绝缘层上形成层间导电柱，所述层间导电柱用于连接相邻的两个存储芯片组。
具体的，如图17所示，在第一上部绝缘层405上，采用半导体晶圆制作的标准工艺，制作一体结构的层间导电柱407。层间导电柱407的一端通过第一上部绝缘层405的开口，与第一重布线层403各相应端面连接。层间导电柱407另一端的高度应比第一上部绝缘层405的表面高出100～120μm左右。层间导电 柱407的制作可采用半导体制作标准技术实现，如真空沉积、电镀以及化学镀等。层间导电柱407为金属材料，如Cu、Ni、Pd、Ag、Au或其合金等。本发明实施例提供的层间导电柱的制作方法，直接在形成的第一复合绝缘层上方制作，先制作层间导电柱，后制作一体结构和一体结构的介电质填充，这样可以采用低廉的热固材料作为填充的介电质，而不是昂贵的厚层光敏介电材料，并且免去在固封层使用光刻等工艺，生产成本下降，同时由于不要对固封材料进行激光钻孔，也解决了激光钻孔对节距限制的困难，从而满足大容量传感器制作对超细节距的要求。
至此，完成一个存储芯片组的制作。
下面，对另一个存储芯片组的制作进行说明：
如图18所示，用半导体贴片设备将上述的一体结构的主动面朝上，根据设计位置，以所谓的“Chip-to-Wafer”的方式，继续贴到载板300上的第一上部绝缘层405上，需要说明的是，每个存储芯片组中的一体结构可以相同，即包括第一存储芯片110、第二存储芯片120以及位于第一存储芯片110主动面上的层内导电柱122和位于第二存储芯片120主动面上的层内导电柱222。
如图19所示，再次沉积介质材料对整个载板进行固封，形成固封层502，即填充包覆一体结构的空隙和表面。固封层502的高度应比一体结构中的所有第一层内导电柱及层间导电柱407要高。沉积方法可为旋涂，印刷，有机叠层和塑封等。介质材料一般为有机热固材料，但不排除为绝缘非有机材料。
如图20所示，对固封层502进行减薄处理，减薄直到一体结构上所有的第一层内导电柱和层间导电柱407表面露出。减薄方法采用半导体制造的标准磨抛技术。磨抛后，固封层502上表面离一体结构上最上端表面的距离为20μm左右。
如图21所示，在固封层502的正面涂覆可光刻的第一下部绝缘层501。第一下部绝缘层501的材料包括感光树脂和可以通过干法刻蚀等工艺形成图形的树脂，例如聚酰亚胺、感光型环氧树脂、双苯环丁烯树脂、苯基并二恶唑树脂中的一种或者多种，第一下部绝缘层501的厚度为5～7μm。
采用半导体器件晶圆制作的标准工艺，对第一下部绝缘层501进行图形制 作，形成第一通孔，且第一通孔直至一体结构中各第一层内导电柱的表面，以露出各第一层内导电柱(图中未示出)。
如图22所示，采用标准半导体制作工艺，在第一下部绝缘层501上制作第一重布线层503。该过程包含一系列的薄膜沉积、电镀、光刻、显影以及蚀刻等工艺制作。第一重布线层503一边的终端经第一下部绝缘层501上的第一通孔与一体结构中的第一层内导电柱122和222相连，以引出第一存储芯片110和第二存储芯片210的电连接。第一重布线层503的材料可以为金属材料，如Al、Au、Cr、Ni、Cu、Mo、Ti、Ta、Ni-Cr、W等及其合金。
在第一重布线层503及第一下部绝缘层501上制作可光刻的第一上部绝缘层505。第一上部绝缘层505的材料包括感光树脂和可以通过干法刻蚀等工艺形成图形的树脂，例如聚酰亚胺、感光型环氧树脂、双苯环丁烯树脂、苯基并二恶唑树脂中的一种或者多种。第一上部绝缘层505的厚度为5～7μm。
采用半导体器件晶圆制作的标准工艺，对第一上部绝缘层505进行图形制作，形成开口，且该开口直至第一重布线层503各相应端面，使其露出。第一上部绝缘层505图形制作可采用标准半导体的前道或中道工艺，如通过曝光、显影、湿法或干法刻蚀等工艺。
如图23所示，在第一上部绝缘层505上，采用半导体晶圆制作的标准工艺，制作一体结构的层间导电柱507。层间导电柱507的一端通过第一上部绝缘层505的开口，与第一重布线层503各相应端面连接。层间导电柱507另一端的高度应比第一上部绝缘层505的表面高出100～120μm左右。层间导电柱507的制作可采用半导体制作标准技术实现，如真空沉积、电镀以及化学镀等。这样，一体结构中的各存储芯片通过第一重布线层403和一体结构的层导电柱407，与一体结构中各存储芯片通过第一重布线层503和一体结构的层间导电柱507，一起实现了与外界的电连接。层间导电柱507与层间导电柱407一样，为金属材料，如，Cu、Ni、Pd、Ag、Au或其合金等。
至此，完成第二个存储芯片组的制作。
综上，本发明实施例描述的具有大容量存储能力的存储芯片组，在经历了两大轮工艺循环后，形成了两层“超级芯片”结构，实现了四层存储芯片堆叠。 下面的步骤基本上是重复以上的循环，继续，直至完成四层“超级芯片”结构(即实现八层存储芯片堆叠)，在这不予以详述。
如图24所示，310、510、610和710为存储芯片组；602和702为介电质固封层；601和701为第一下部绝缘层，701和705为第一上部绝缘层；603和703第一重布线层；507和607为存储芯片组的层间导电柱。
“超级芯片”间空隙填充，包覆介电质的沉积方法可为旋涂，印刷，有机叠层(laminate)或塑封等。其材料性质一般为有机热固材料，但并不排除为绝缘非有机材料。绝缘介电质的沉积可采用标准半导体的前道或中道工艺，如通过曝光、显影、湿法或干法刻蚀等工艺。绝缘介电质材料包括感光树脂和可以通过干法刻蚀等工艺形成图形的树脂，例如聚酰亚胺、感光型环氧树脂、BCB(双苯环丁烯树脂)、PBO(苯基并二恶唑树脂)中的一种或者多种。RDL层的制作包含一系列的薄膜沉积、电镀、光刻、显影、蚀刻等工艺。RDL材料为金属材料，如Al、Au、Cr、Ni、Cu、Mo、Ti、Ta、Ni-Cr、W等及其合金。“超级芯片”层间导电柱的制作可采用半导体制作标准技术实现，如，真空沉积，电镀，化学镀等。“超级芯片”层间导电柱为金属材料，如Cu、Ni、Pd、Ag、Au或其合金等。绝缘钝化层的制作采用标准半导体的前道或中道工艺，如通过曝光、显影、湿法或干法刻蚀等工艺。钝化层材料一般为有机材料，但不排除为无机材料。有机材料包括感光形成图形的树脂，例如聚酰亚胺、感光型环氧树脂、阻焊油墨、绿漆、干膜、感光型增层材料、BCB(双苯环丁烯树脂)、PBO(苯基苯并二恶唑树脂)中的一种或者多种。
为完成大容量存储器件的制作，下面制作对外连接凸块。
采用半导体器件晶圆制作的标准工艺，对第一上部绝缘层705进行图形制作，形成第二通孔，且该第二通孔直至重布线层703各相应端面，使其露出。第一上部绝缘层705图形制作可采用标准半导体的前道或中道工艺，如通过曝光、显影、湿法或干法刻蚀等工艺。
如图25所示，在第一上部绝缘层705的第二通孔处制作凸块下金属906，该凸块下金属906与第一重布线层703各端面焊盘相连。凸块下金属906的制作通过溅射、电镀、真空蒸发沉积等工艺并辅以光刻、显影、刻蚀等工艺实现。 凸块下金属906的材料为与焊料Wetting(相亲和)的金属或合金，如Ni、Cu、Pt、Ag及其合金。随后，在凸块下金属906上制作对外连接凸块908。其制作可以通过电镀、印刷、植球、放球等工艺。然后再进行回流工艺。回流可以通过热传导、对流、辐射等实现。对外连接凸块908的材料主要为焊料金属。如，Sn、Ag、Cu、Pb、Au、Ni、Zn、Mo、Ta、Bi、In、等及其合金。
如图26所示，去除载板和临时键合胶。载板和临时键合胶可以通过机械、加热、化学、激光等方式去除。然后，对整个大容量存储器再购“晶圆”进行翻转(Flip Over)，使第一存储芯片组310中的第一存储芯片110的非主动面110b和固封层302的下表面处于最顶层表面。
如图27所示，在第一存储芯片110的非主动面110b及固封层302的下表面上沉积一层保护膜909。保护膜909的沉积可以有多种方式，如：旋涂、喷涂、印刷、滚压、热压，或真空压合等。保护膜材料为有机材料。
如图28所示，最后对所形成的大容量存储器结构，进行分离切割。
如图29所示，经过以上工艺流程后得到单颗大容量半导体存储器。
本发明实施例提供的半导体存储器的制作方法，通过依次制作至少两个存储芯片组，以及制作层间导电柱，层间导电柱分别与上下相邻的两个存储芯片组的重布线层电连接，且位于最上方的存储芯片组的重布线层与对外连接凸块电连接；其中任一存储芯片组为至少两个存储芯片依次堆叠，至少两个存储芯片的层内导电柱错开预设角度，并将至少两个存储芯片包封为一体结构，以及在一体结构上方形成复合绝缘层，复合绝缘层中形成有重布线层，重布线层与层内导电柱电连接。采用上述技术方法，可以有效提高存储器的堆叠效率，并且降低堆叠难度。
可选的，本发明实施例还提供一种半导体存储模块的制作方法，所述半导体存储模块包括上述实施例所述的半导体存储器以及控制芯片组，所述半导体存储器的制备方法可以采用上述实施例所述的半导体存储器的制作方法，还可以包括在所述半导体存储器的基础上制作控制芯片组，具体的，本发明实施例提供的半导体存储模块的制作方法可以包括：
在载板上制作控制芯片组合区域间导电柱，所述控制芯片组与所述存储芯 片组自下而上依次堆叠，所述控制芯片组的第二重布线层与相邻的所述存储芯片组之间通过区域间导电柱电连接，且位于最下方的所述第一重布线层或所述第二重布线层与所述对外连接凸块电连接；
所述制作控制芯片组的步骤包括：
将控制芯片的第二层内导电柱露出；
在所述控制芯片下方形成第二复合绝缘层，所述第二复合绝缘层中形成有第二重布线层，所述第二重布线层与所述第二层内导电柱电连接。
下面同样按照工程中制作存储芯片组、控制芯片组、层间导电柱、区域导电柱、第一复合绝缘层以及第二复合绝缘层的顺序进行说明，本发明实施例以四个存储芯片组为例进行说明，并且半导体存储器的制备方法可以参照上述实施例的说明，这里不再赘述。
为构建高端的存储模块，采用半导体器件晶圆制作的标准工艺，对第四层的第一复合绝缘层的第一上部绝缘层705进行图形制作，形成开口，且该开口直至第一重布线层703各相应端面，使其露出(未画出)。第一上部绝缘钝化层705图形制作可采用标准半导体的前道或中道工艺，如通过曝光、显影、湿法或干法刻蚀等工艺。
如图30所示，在第一上述绝缘层705上，制作存储芯片组与控制芯片组的区域间导电柱707。
所述制作区域间导电柱，可以包括：
形成第一上部绝缘层之后，在所述第一上部绝缘层上形成区域间导电柱，所述区域间导电柱用于连接控制芯片组与存储芯片组。
具体的，区域间导电柱707的一端通过第一上部绝缘层705的开口，与第一重布线层703层各相应端面连接，区域间导电柱707另一端的高度应在100μm左右。区域间导电柱707的制作可采用半导体制作标准技术实现，如真空沉积、电镀以及化学镀等。
本发明实施例提供的区域间导电柱的制作方法，与层间导电柱的制作方法类似，直接在形成的复合绝缘层上方制作，先制作区域间导电柱，后制作控制芯片以及控制芯片的介电质填充，这样可以采用低廉的热固材料作为填充的介 电质，而不是昂贵的厚层光敏介电材料，并且免去在固封层使用光刻等工艺，生产成本下降，同时由于不要对固封材料进行激光钻孔，也解决了激光钻孔对节距限制的困难，从而满足大容量传感器制作对超细节距的要求。
制作好区域间导电柱707之后，可以在区域间导电柱707之间制作控制芯片组810，具体的，制作控制芯片组的步骤可以包括：
将控制芯片的第二层内导电柱露出；
在控制芯片上方形成第二复合绝缘层，所述第二复合绝缘层中形成有第二重布线层，所述第二重布线层与所述第二层内导电柱电连接。
具体的工程上的方法如下：如图31a和31b所示，逻辑晶圆800上有控制芯片(逻辑芯片)806的阵列排布。控制芯片806具有主动面806a和非主动面806b，在主动面806a上，有控制芯片806对外连接导电的第二焊盘821，在第二焊盘821上，有预先沉积的第二层内导电柱808。第二层内导电柱808的沉积可采用不同方法实现，例如真空沉积和电镀等。第二焊盘821可为单层或多层金属，如Ti，W，Al，Cu，Ni，Pt，Ag，Au或其合金等。第二层内导电柱808的材料为金属，如Cu，Ni，Ag，Au或其合金等，第二层间导电柱的高度在20～40μm左右。控制芯片806的厚度为40～50μm。在晶圆800的背面(对应控制芯片806芯片的非主动面)上，沉积DAF膜801。它的沉积可以多种方式实现：如旋涂、喷涂、印刷、滚压以及热压等。DAF膜801的有效粘接层的厚度在10～30μm左右。DAF膜801与DAF膜101、DAF膜201可为同一种DAF膜，也可为不同的DAF膜。DAF膜为有机材料。
如图32所示，对半导体逻辑晶圆进行切割，得到控制芯片806。切割采取标准半导体晶圆切割方法，如机械切割、激光切割等方式。
如图33所示，用半导体贴片设备将控制芯片806的主动面806a朝上，以所谓的“Chip-to-Wafer”的方式，贴到第四层第一复合绝缘层的第一上部绝缘层705表面，实现芯片806在载板上存储功能区域上的配置。
如图34所示，沉积介质材料对整个载板进行固封，形成固封层802，即，填充包覆逻辑芯片806的空隙和表面及区域间导电柱707的空隙。固封层802的高度应比控制芯片806中所有的第二层内导电柱808及区域间导电柱707要 高。沉积方法可为旋涂，印刷，有机叠层以及塑封等。介质材料一般为有机热固材料，但不排除为绝缘非有机材料。
如图35所示，对固封层802进行减薄处理，减薄直到控制芯片806上所有的导电柱表面和区域间导电柱707表面全部露出。减薄方法采用半导体制造的标准磨抛技术，磨抛后，固封层802上表面离控制芯片806最上端表面的距离为20μm左右。
完成控制芯片806的固封之后，在固封好的控制芯片806上方形成第二复合绝缘层，在控制芯片806下方形成第二复合绝缘层可以包括：
在所述控制芯片下方形成第二下部绝缘层，以及在所述第二下部绝缘层上形成第三通孔；
在所述第二下部绝缘层下方形成第二重布线层，所述第二重布线层通过第三通孔与所述第二层内导电柱电连接；
在所述第二重布线层下方形成第二上部绝缘层。
具体的，在固封层802的正面涂覆可光刻的第二下部绝缘层801，第二下部绝缘层801的材料包括感光树脂和可以通过干法刻蚀等工艺形成图形的树脂，例如聚酰亚胺、感光型环氧树脂、双苯环丁烯树脂、苯基并二恶唑树脂中的一种或者多种。第二下部绝缘层801的厚度为5～7μm。然后采用半导体器件晶圆制作的标准工艺，对第二下部绝缘层801进行图形制作，形成第三通孔，且第三通孔直至控制芯片806中各第二层内导电柱808的表面和区域间导电柱707表面，使其露出(图中未画出)。
采用标准半导体制作工艺，在第二下部绝缘层801上制作第二重布线层803。该过程包含一系列的薄膜沉积、电镀、光刻、显影以及蚀刻等工艺制作。第二重布线层803一边的终端经第二下部绝缘层801上的第二通孔与控制芯片806主动面第二焊盘上的第二层间导电柱808和区域间导电柱707表面相连，以引出控制芯片806、存储芯片组710中的各存储芯片(通过第一重布线层703和区域间导电柱707)、存储芯片组610中各存储芯片(通过第一重布线层603，存储芯片组层间导电柱607，和区域间导电柱707)、存储芯片组510中各存储芯片(通过第一重布线层503，存储芯片组层间导电柱507、607和区域间导电柱 707)、和存储芯片组310中各存储芯片(通过第一重布线层403，存储芯片组层间电互连407、507、607和区域间导电柱707)的电连接(未画出)。第二重布线层803的材料为金属材料，如Al、Au、Cr、Ni、Cu、Mo、Ti、Ta、Ni-Cr、W等及其合金。
如图36所示，在第二重布线结构803及第二下部绝缘层801上制作可光刻的第二上部绝缘层(钝化层)805。第二上部绝缘层(钝化层)805的制作采用标准半导体的前道或中道工艺，如通过曝光、显影、湿法或干法刻蚀等工艺。第二上部绝缘层805的材料一般为有机材料，但不排除为无机材料。有机材料包括感光形成图形的树脂，例如聚酰亚胺、感光型环氧树脂、阻焊油墨、绿漆、干膜、感光型增层材料、双苯环丁烯树脂、苯基苯并二恶唑树脂中的一种或者多种。
为完成高端的存储模块的制作，下面制作凸块下金属和对外连接终端。
采用半导体器件晶圆制作的标准工艺，对第二上部绝缘层805进行图形制作，形成开口，且该开口直至第二重布线层803层各相应端面，使其露出(图中未画出)。第二上部绝缘层805图形制作可采用标准半导体的前道或中道工艺，如通过曝光、显影、湿法或干法刻蚀等工艺。
如图37所示，制作凸块下金属906于第二上部绝缘层805的开口上，并与第二重布线层803各端面焊盘相连。凸块下金属906的制作通过溅射、电镀、真空蒸发沉积等工艺并辅以光刻、显影、刻蚀等工艺实现。凸块下金属906的材料为与焊料相亲和的金属或合金，如Ni、Cu、Pt、Ag及其合金。随后，在凸块下金属906上制作对外连接凸块908。其制作可以通过电镀、印刷、植球、放球等工艺，然后进行回流工艺。回流可以通过热传导、对流、辐射等实现。对外连接凸块908的材料主要为焊料金属。如，Sn、Ag、Cu、Pb、Au、Ni、Zn、Mo、Ta、Bi、In、等及其合金。
去除载板300和临时键合胶301。载板300和临时键合胶301可以通过机械、加热、化学、激光等方式去除。然后，对整个高端存储模块再构“晶圆”进行翻转，使存储芯片组310中的第一存储芯片110的非主动面110b和固封层302的下表面处于存储模块最顶层表面(未画出)。
如图38所示，在第一存储芯片110的非主动面110b及固封层302的下表面上沉积一层保护膜909。保护膜的沉积可以多种方式，如：旋涂、喷涂、印刷、滚压、热压，或真空压合等，保护膜材料为有机材料。
如图39，沿图中的虚线对所形成的高端半导体存储模块，进行分离切割，得到存储模块。
如图40，经过以上工艺流程后得到单颗半导体存储模块。该半导体存储模块由两个功能区域组成：大容量存储区域和控制区域。大容量存储区域本身又由4个存储芯片组和一个控制芯片组组成，每个存储芯片组由一个第一存储芯片和一个第二存储芯片堆叠构成，控制芯片组为1个控制芯片。可选的，第一存储芯片和第二存储芯片可以相同也可以不同，当第一存储芯片和第二存储芯片相同时，存储区域中集成的存储芯片将是“超级芯片”的2倍。
需要说明的是，本发明实施例以控制芯片组位于存储之间片下方为例进行说明，此时，对外连接凸块设置于控制芯片组远离存储芯片组的一侧。可选的，控制芯片组也可以设置在两个存储芯片组之间，如此，对外连接凸块设置在位于最下方的存储芯片组一侧，如上述实施例半导体存储器中对外连接凸块的设置方式，本发明实施例对半导体存储模块中对外连接凸块设置在存储芯片组一侧的情况不再进行说明。
本发明实施例提供的半导体存储模块的制作方法，在载板上依次制作控制芯片组和至少两个存储芯片组，每个存储芯片组包括至少两个存储芯片，存储芯片组与存储芯片组通过第一层内导电柱、层间导电柱以及位于存储芯片组之间的第一重布线层实现电连接，多个存储芯片组和控制芯片组通过第一层间导电柱、第二层间导电柱、层间导电柱、区域间导电柱、位于存储芯片组之间的第一重布线层以及位于存储芯片组与控制芯片组之间的第二重布线层实现电连接，如此，不仅提供了大容量的存储区域，保证存储区域小尺寸的特点，还可以实现存储芯片与控制芯片(逻辑芯片)在同一个晶圆上设置，实现了控制芯片与存储芯片的三维晶圆级集成，减少了存储模块在封装结构上的电路损耗，存储模块的整体功能得到改善，进一步还可以实现存储模块的晶圆级制造和晶圆级功能测试，提高生产效率，降低生产成本。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。

Claims (21)

  1. 一种半导体存储器，其特征在于，包括自下而上依次堆叠的至少两个存储芯片组，上下相邻的两个所述存储芯片组的第一重布线层通过层间导电柱电连接，且位于最下方的存储芯片组的第一重布线层与对外连接凸块电连接；
    所述存储芯片组包括依次堆叠的至少两个存储芯片，以及位于所述至少两个存储芯片下方的第一复合绝缘层，所述至少两个存储芯片包封为一体结构，所述第一重布线层设置在所述第一复合绝缘层中，所述至少两个存储芯片的第一层内导电柱错开预设角度，以分别与所述第一重布线层电连接。
  2. 根据权利要求1所述的半导体存储器，其特征在于，所述至少两个存储芯片的第一主动面的朝向相同，且所述第一主动面上设置有第一焊盘，所述第一焊盘与所述第一层内导电柱电连接。
  3. 根据权利要求1所述的半导体存储器，其特征在于，每个所述存储芯片组包括二个、三个或四个存储芯片。
  4. 根据权利要求3所述的半导体存储器，其特征在于，所述存储芯片组内的至少两个存储芯片的第一层内导电柱错开90°或180°。
  5. 根据权利要求1所述的半导体存储器，其特征在于，所述第一复合绝缘层包括第一上部绝缘层和第一下部绝缘层，以及位于所述第一上部绝缘层和第一下部绝缘层之间的第一重布线层，所述第一层内导电柱通过第一下部绝缘层中的第一通孔与所述第一重布线层电连接，所述第一重布线层通过第一上部绝缘层中的第二通孔与所述层间导电柱电连接。
  6. 根据权利要求5所述的半导体存储器，其特征在于，所述第一上部绝缘层和所述第一下部绝缘层为有机光敏材料制成。
  7. 根据权利要求1所述的半导体存储器，其特征在于，所述存储芯片组内的至少两个存储芯片由热固材料包封。
  8. 根据权利要求1所述的半导体存储器，其特征在于，最上方的存储芯片组的底部设置有保护层。
  9. 一种半导体存储模块，其特征在于，包括权利要求1-8任一项所述的半导体存储器，还包括控制芯片组，所述控制芯片组与所述存储芯片组自下而上依次堆叠，所述控制芯片组的第二重布线层与相邻的所述存储芯片组之间通过区域间导电柱电连接，且位于最下方的所述第一重布线层或所述第二重布线层与所述对外连接凸块电连接；
    所述控制芯片组包括控制芯片，以及位于所述控制芯片下方的第二复合绝缘层，所述第二重布线层设置在所述第二复合绝缘层中，所述控制芯片的第二层内导电柱与所述第二重布线层电连接。
  10. 根据权利要求9所述的半导体存储模块，其特征在于，所述控制芯片组位于最下方，所述控制芯片组的第二重布线层与对所述外连接凸块电连接。
  11. 根据权利要求9所述的半导体存储模块，其特征在于，所述控制芯片的第二主动面与所述存储芯片的第一主动面朝向相同，且所述第二主动面上设置有第二焊盘，所述第二焊盘与所述第二层内导电柱电连接。
  12. 根据权利要求9所述的半导体存储模块，其特征在于，所述第二复合绝缘层包括第二上部绝缘层和第二下部绝缘层，以及位于所述第二上部绝缘层和第二下部绝缘层之间的第二重布线层，所述第二层内导电柱通过第二下部绝缘层中的第三通孔与所述第二重布线层电连接。
  13. 根据权利要求12所述的半导体存储模块，其特征在于，所述第二上部绝缘层以及第二下部绝缘层为有机光敏材料制成。
  14. 根据权利要求9所述的半导体存储模块，其特征在于，所述控制芯片组内的控制芯片由热固材料包封。
  15. 根据权利要求9所述的半导体存储模块，其特征在于，最上方的存储芯片组或控制芯片组的底部设置有保护层。
  16. 一种半导体存储器的制作方法，其特征在于，包括在载板自下而上依次制作至少两个存储芯片组，以及制作层间导电柱，所述层间导电柱分别与上下相邻的两个所述存储芯片组的第一重布线层电连接，且位于最下方的存储芯 片组的第一重布线层与对外连接凸块电连接；
    其中在制作任一存储芯片组时，包括如下步骤：
    将所述至少两个存储芯片依次堆叠，所述至少两个存储芯片的第一层内导电柱错开预设角度；
    将所述至少两个存储芯片包封为一体结构，且将所述第一层内导电柱露出；
    在所述一体结构下方形成第一复合绝缘层，所述第一复合绝缘层中形成有第一重布线层，所述第一重布线层与所述第一层内导电柱电连接。
  17. 根据权利要求16所述的制作方法，其特征在于，所述在所述一体结构下方形成第一复合绝缘层包括：
    在所述一体结构下方形成第一下部绝缘层，以及在所述第一下部绝缘层上形成第一通孔；
    在所述第一下部绝缘层下方形成第一重布线层，所述第一重布线层通过第一通孔与所述第一层内导电柱电连接；
    在所述第一重布线层下方形成第一上部绝缘层。
  18. 根据权利要求17所述的制作方法，其特征在于，所述制作层间导电柱，包括：
    形成第一上部绝缘层之后，在所述第一上部绝缘层上形成层间导电柱，所述层间导电柱用于连接相邻的两个存储芯片组。
  19. 一种半导体存储模块的制作方法，其特征在于，包括权利要求16-18任一项所述的半导体器件的制作方法，还包括在载板上制作控制芯片组和区域间导电柱，所述控制芯片组与所述存储芯片组自下而上依次堆叠，所述控制芯片组的第二重布线层与相邻的所述存储芯片组之间通过区域间导电柱电连接，且位于最下方的所述第一重布线层或所述第二重布线层与所述对外连接凸块电连接；
    所述制作控制芯片组的步骤包括：
    将控制芯片的第二层内导电柱露出；
    在所述控制芯片下方形成第二复合绝缘层，所述第二复合绝缘层中形成有第二重布线层，所述第二重布线层与所述第二层内导电柱电连接。
  20. 根据权利要求19所述的制作方法，其特征在于，
    所述在所述控制芯片下方形成第二复合绝缘层包括：
    在所述控制芯片下方形成第二下部绝缘层，以及在所述第二下部绝缘层上形成第三通孔；
    在所述第二下部绝缘层下方形成第二重布线层，所述第二重布线层通过第三通孔与所述第二层内导电柱电连接；
    在所述第二重布线层下方形成第二上部绝缘层。
  21. 根据权利要求20所述的制作方法，其特征在于，
    所述制作区域间导电柱，包括：
    形成第一上部绝缘层之后，在所述第一上部绝缘层上形成区域间导电柱，所述区域间导电柱用于连接控制芯片组与存储芯片组。
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