WO2018082228A1 - 显示器阵列基板画素结构及其应用的显示设备 - Google Patents

显示器阵列基板画素结构及其应用的显示设备 Download PDF

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WO2018082228A1
WO2018082228A1 PCT/CN2017/074905 CN2017074905W WO2018082228A1 WO 2018082228 A1 WO2018082228 A1 WO 2018082228A1 CN 2017074905 W CN2017074905 W CN 2017074905W WO 2018082228 A1 WO2018082228 A1 WO 2018082228A1
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Prior art keywords
pixel electrode
pixel
sub
electrode
inner layer
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PCT/CN2017/074905
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English (en)
French (fr)
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陈猷仁
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/555,344 priority Critical patent/US10379402B2/en
Publication of WO2018082228A1 publication Critical patent/WO2018082228A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133528—Polarisers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to an electrode design method, and in particular to a display device for a display array substrate pixel structure and application thereof.
  • Mura is caused by uneven brightness distribution on the display screen, and is a vertical Alignment (VA) type/In-Plane Switching (IPS) type/Fringe Field Switching (FFS) type pixel.
  • VA vertical Alignment
  • IPS In-Plane Switching
  • FFS Frute Field Switching
  • the pixel electrodes are generally designed in the shape of a slit, and the control of the line width affects the efficiency of the liquid crystal.
  • a step difference may occur between sub-pixels of different colors.
  • the sub-pixels are more difficult to grasp the line width control of the ITO slit (indium tin oxide slit) due to the severe step difference (due to the width difference of the flat layer), so it is easy to cause the transmittance to be unstable. problem.
  • the purpose of the present application is to provide a pixel structure for a display array substrate, which can not only effectively solve the Mura problem, but also improve the variation of the fourth sub-pixel ITO slit (indium tin oxide slit). Brightness difference.
  • a display array substrate pixel structure includes a plurality of arrayed pixel units, each of the pixel units including a first sub-pixel, a second sub-pixel, and a fourth sub-pixel, each of the pixels
  • the unit further includes: a fourth sub-pixel electrode, wherein the fourth sub-pixel electrode comprises a first pixel electrode, a second pixel electrode, a third pixel electrode and a fourth pixel electrode, respectively located in the fourth sub-pixel And the first pixel electrode, the second pixel electrode, the third pixel electrode and the fourth pixel electrode are respectively divided into at least two compensation regions for feeding back the electrode line widths of the at least two compensation regions to improve a difference in brightness caused by a slit variation of the fourth sub-pixel electrode; and a first sub-pixel electrode and a second sub-pixel electrode respectively located at the first sub-pixel and the second sub-pixel.
  • a liquid crystal display panel comprising: a first substrate; a second substrate disposed opposite to the first substrate; a liquid crystal layer disposed between the first substrate and the second substrate; further comprising the display
  • the array substrate pixel structure is disposed between the first substrate and the second substrate. And further comprising a first polarizer disposed on an outer surface of the first substrate; and a second polarizer disposed on an outer surface of the second substrate, wherein the first polarizer and the second The polarization directions of the polarizers are parallel to each other.
  • a display device includes a backlight module, and further includes the above liquid crystal display panel.
  • the first pixel electrode is divided into three compensation regions, a first inner layer pixel electrode, a first middle layer pixel electrode and a first outer layer pixel electrode, and the first inner layer pixel Electrode, first middle layer pixel electrode and first outer layer pixel electrode
  • the electrode line width is 80% to 120% of the line width of the first sub-pixel electrode and the second sub-pixel electrode, respectively.
  • the second pixel electrode is divided into three compensation regions: a second inner layer pixel electrode, a second middle layer pixel electrode and a second outer layer pixel electrode, and the second inner layer pixel
  • the electrode line widths of the electrode, the second middle layer pixel electrode and the second outer layer pixel electrode are respectively 80% to 120% of the line width of the first sub-pixel electrode and the second sub-pixel electrode.
  • the third pixel electrode is divided into three compensation regions: a third inner layer pixel electrode, a third middle layer pixel electrode, and a third outer layer pixel electrode, and the third inner layer pixel
  • the electrode line widths of the electrode, the third middle layer pixel electrode and the third outer layer pixel electrode are respectively 80% to 120% of the line width of the first sub-pixel electrode and the second sub-pixel electrode.
  • the fourth pixel electrode is divided into three compensation regions: a fourth inner layer pixel electrode, a fourth middle layer pixel electrode, and a fourth outer layer pixel electrode, and the fourth inner layer pixel
  • the electrode line widths of the electrode, the fourth middle layer pixel electrode and the fourth outer layer pixel electrode are respectively 80% to 120% of the line width of the first sub-pixel electrode and the second sub-pixel electrode.
  • the electrode widths of the second pixel electrode, the third pixel electrode, and the fourth pixel electrode are designed as the first pixel electrode.
  • the fourth sub-pixel electrode pixel segmentation form is a rectangle, a circle, or a diamond.
  • the line width of the compensation region electrode is further formed as an outer edge rectangular symmetrical radiographic electrode.
  • the line width of the compensation region electrode is further included as an embedded strip rectangular symmetric radiographic electrode.
  • the line width of the compensation region electrode is further formed as an outer circular circular radiant radioactive electrode or an inlaid circular symmetrical radioactive pixel electrode.
  • the beneficial effects of the present application are to improve the pixels for the display array substrate pixel array display and are therefore less sensitive to process variations.
  • This design provides a method for feedback correction compensation line width for the problem extended in a novel process for display array substrate pixel array, which improves the improvement of the fourth sub-pixel ITO slit (indium tin oxide slit) variation. Brightness difference.
  • FIG. 1a is a schematic diagram of a white pixel step difference for a display array substrate pixel according to an embodiment of the present application.
  • FIG. 1b is a schematic diagram of a pixel type for a display array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a fourth sub-pixel electrode, a first sub-pixel electrode, a second sub-pixel electrode, and a third sub-pixel electrode for a display array substrate pixel structure according to an embodiment of the present application.
  • FIG. 3a is a schematic diagram of a rectangular pixel division of a fourth sub-pixel electrode according to an embodiment of the present application.
  • FIG. 3b is a schematic diagram of circular pixel partitioning of a fourth sub-pixel electrode according to an embodiment of the present application.
  • FIG. 3c is a schematic diagram of a fourth sub-pixel electrode diamond segmentation according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a compensation electrode line width of an electrode structure of an RGB pixel according to an embodiment of the present application.
  • 4a is a schematic diagram of a compensation electrode line width of an electrode structure of a white pixel according to an embodiment of the present application.
  • 4b is a schematic diagram of a compensation electrode line width of an electrode structure of a white pixel according to another embodiment of the present application.
  • 4c is a schematic diagram of a compensation electrode line width of an electrode structure of a white pixel according to still another embodiment of the present application.
  • 4d is a schematic diagram of the compensation electrode line width of the electrode structure of the white pixel of still another embodiment of the present application.
  • FIG. 5a is a schematic diagram of a compensation region electrode line width for a display array substrate pixel structure according to an embodiment of the present application.
  • FIG. 5b is a schematic diagram of a compensation region electrode line width for a display array substrate pixel structure according to another embodiment of the present application.
  • FIG. 5c is a schematic diagram of a compensation region electrode line width for a display array substrate pixel structure according to still another embodiment of the present application.
  • FIG. 5d is a schematic diagram of a compensation region electrode line width for a display array substrate pixel structure according to still another embodiment of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • the liquid crystal display device of the present application may include a backlight module and a liquid crystal display panel.
  • the liquid crystal display panel may include a thin film transistor (TFT) substrate, a color filter (CF) substrate, and a liquid crystal layer formed between the two substrates.
  • TFT thin film transistor
  • CF color filter
  • the liquid crystal display panel of the present application may be a curved display panel, and the liquid crystal display device of the present application may also be a curved display device.
  • the thin film transistor and the color filter of the present application may be formed on the same substrate.
  • VA Vertical Alignment
  • PVA Pattern Vertical Alignment
  • MVA Multi-domain Vertical Alignment
  • the vertical alignment type uses the fringe field effect and the compensation plate to achieve a wide viewing angle.
  • the multi-region vertical alignment type divides one pixel into a plurality of regions, and uses a protrusion or a specific pattern structure to tilt liquid crystal molecules located in different regions toward different directions to achieve a wide viewing angle and improve transmittance.
  • FIG. 1a is a schematic diagram of a white pixel step difference for a display array substrate pixel according to an embodiment of the present application.
  • the difference between the ideal process case 102 and the actual process case 103 is that the severe segment difference of the white sub-pixel (due to the width difference Dh of the flat layer 130) causes the exposure development etching process to the ITO slit (indium tin oxide).
  • the slit 110 has a problem that it is more difficult to grasp because of the line width (which becomes a non-uniform slit line width of 120), and thus the transmittance is unstable.
  • FIG. 1b is a schematic diagram of a pixel type for a display array substrate according to an embodiment of the present application.
  • the display panel substrate pixel type may include a strip 1 type of display array substrate pixel and a rectangle 2 for a display array substrate pixel format type.
  • FIG. 2 is a schematic diagram of a fourth sub-pixel element 300, a first sub-pixel electrode 210, a second sub-pixel electrode 210, and a third sub-pixel electrode 210 for a display array substrate pixel structure according to an embodiment of the present application;
  • a schematic diagram of a rectangular 301 pixel division of the fourth sub-pixel electrode 300 of an embodiment is applied. Referring to FIG. 2 and FIG.
  • the present application is a pixel structure for a display array substrate, comprising a plurality of arrayed pixel units, each of the pixel units may include a first sub-pixel (eg, a red sub-pixel), a second sub-pixel (for example, a green sub-pixel), a third sub-pixel (for example, a blue sub-pixel), and a fourth sub-pixel (for example, a white sub-pixel), each of the pixel units further includes: a fourth sub-pixel electrode 300
  • the fourth sub-pixel electrode 300 includes a first pixel electrode 310, a second pixel electrode 320, a third pixel electrode 330, and a fourth pixel electrode 340, respectively located in four regions of the fourth sub-pixel, and the The first pixel electrode 310, the second pixel electrode 320, the third pixel electrode 330 and the fourth pixel electrode 340 are respectively divided into at least two compensation regions for feeding back the electrode line widths of the at least two compensation regions to improve the The difference in brightness caused by the slit variation
  • FIG. 3b is a schematic diagram of a circular 302 pixel division of a fourth sub-pixel electrode 300 for a display array substrate pixel structure according to an embodiment of the present application
  • FIG. 3c is a fourth sub-structure of a display array substrate pixel structure according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of a compensation electrode line width of an electrode structure of an RGB pixel according to an embodiment of the present application
  • FIG. 4 is a compensation electrode line width of an electrode structure of a fourth pixel according to an embodiment of the present application
  • FIG. FIG. 4b is a schematic diagram of a compensation electrode line width of an electrode structure of a fourth pixel according to another embodiment of the present application
  • FIG. 4c is a schematic diagram of a compensation electrode line width of an electrode structure of a fourth pixel according to still another embodiment of the present application.
  • FIG. 4d It is a schematic diagram of the compensation electrode line width of the electrode structure of the fourth pixel of the embodiment of the present application. Please refer to FIGS. 3a, 3b, 3c, 4, 4a, 4b, 4c and 4d.
  • the The one pixel electrode 310 is divided into three compensation regions: a first inner layer pixel electrode 312, a first middle layer pixel electrode 314 and a first outer layer pixel electrode 316, and the first inner layer pixel electrode 312, the first middle layer pixel electrode
  • the second pixel electrode 320 is divided into three compensation regions: a second inner layer pixel electrode 322, a second middle layer pixel electrode 324, and a second outer layer pixel electrode 326, and the
  • the third pixel electrode 330 is divided into three compensation regions: a third inner layer pixel electrode 332, a third middle layer pixel electrode 334 and a third outer layer pixel electrode 336, and the
  • the fourth pixel electrode 340 is divided into three compensation regions: a fourth inner layer pixel electrode 342, a fourth middle layer pixel electrode 344, and a fourth outer layer pixel electrode 346, and the
  • the electrode line widths of the second pixel electrode 320, the third pixel electrode 330, and the fourth pixel electrode 340 may be designed as the first pixel electrode 310.
  • the pixel division form of the fourth sub-pixel electrode 300 can be, for example, a rectangle 301, a circle 302, a diamond 303, or other patterns.
  • FIG. 5a is a schematic diagram of a compensation region electrode line width for a display array substrate pixel structure according to an embodiment of the present application
  • FIG. 5b is a schematic diagram of a compensation region electrode line width for a display array substrate pixel structure according to another embodiment of the present application
  • 5c is a schematic diagram of a compensation region electrode line width for a display array substrate pixel structure according to still another embodiment of the present application
  • FIG. 5d is a schematic diagram of a compensation region electrode line width for a display array substrate pixel structure according to still another embodiment of the present application.
  • the pixel structure for the display array substrate may further include four kinds of compensation region electrode line width forms as outer edge rectangular symmetric radiation.
  • the pixel electrode 510 is embedded with a long rectangular symmetric radiant pixel electrode 520, a circular circular symmetrical radiation pixel electrode 530 or a circular symmetric radiant pixel electrode 540.
  • the present invention is not limited thereto.
  • the display array substrate pixel structure of the present application may include other patterns of symmetric radiographic electrodes.
  • the liquid crystal display panel of the present application includes: a first substrate; a second substrate disposed opposite to the first substrate; and a liquid crystal layer disposed on the first substrate and the second substrate Between the plurality of array elements (such as FIG. 2 and FIG. 3a), each of the pixel units includes the first sub-pixel, the second sub-pixel, and the fourth sub-pixel.
  • Each of the pixel units includes: a fourth sub-pixel electrode, wherein the fourth sub-pixel electrode comprises a first pixel electrode, a second pixel electrode, a third pixel electrode and a fourth pixel electrode, respectively located in the fourth sub-pixel Four regions of the pixel, and the first pixel electrode, the second pixel electrode, the third pixel electrode and the fourth pixel electrode are respectively divided into at least two compensation regions for feeding back electrode line widths for correcting at least two compensation regions a difference in brightness caused by the slit variation of the fourth sub-pixel electrode; and a first sub-pixel electrode and a second sub-pixel electrode are respectively located in the first sub-pixel and the second sub-pixel, and Each of the pixel units is disposed between the first substrate and the second substrate.
  • the first polarizer is disposed on an outer surface of the first substrate
  • the second polarizer is disposed on an outer surface of the second substrate, wherein the first polarizer and the second The polarization directions of the polarizers are parallel to each other.
  • the display device of the present application includes a backlight module, and further includes a liquid crystal display panel including: a first substrate; a second substrate disposed opposite to the first substrate; and a liquid crystal layer disposed on Between the first substrate and the second substrate; further comprising a plurality of pixel units arranged in an array (as shown in FIG. 2 and FIG.
  • each of the pixel units including the first sub-pixel, the first The second sub-pixel and the fourth sub-pixel, each of the pixel units includes: a fourth sub-pixel electrode, the fourth sub-pixel electrode comprises a first pixel electrode, a second pixel electrode, a third pixel electrode and The fourth pixel electrodes are respectively located in four regions of the fourth sub-pixel, and the first pixel electrode, the second pixel electrode, the third pixel electrode and the fourth pixel electrode are respectively divided into at least two compensation regions, Correcting the electrode line width of the at least two compensation regions by feedback to improve the brightness difference caused by the slit variation of the fourth sub-pixel electrode; and a first sub-pixel electrode and a second sub-pixel electrode respectively located at the Narrative Sub-pixel and the second sub-pixel, and each of the pixel units, disposed between the first substrate and the second substrate.
  • the first polarizer is disposed on an outer surface of the first substrate
  • the second polarizer is disposed on an outer surface of the second substrate, wherein the first polar
  • the beneficial effects of the present application are to improve the pixels for the display array substrate pixel array display and are therefore less sensitive to process variations.
  • the design provides a feedback correction compensation line width mode for improving the brightness caused by the variation of the fourth sub-pixel ITO slit (indium tin oxide slit) for the problem extended in a novel process for the display array substrate pixel array. Difference, so the difference in electrode line width caused by the exposure process caused by the large step difference can be compensated by the adjustment of the control electrode line width, which can effectively reduce the unevenness of the light transmission of the pixel and reduce the risk of electrode disconnection. .

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Abstract

一种显示器阵列基板画素结构及其应用的显示设备，包括多个阵列排列的画素单元，每个画素单元均包括第一子画素、第二子画素和第四子画素，每个画素单元均更包括：一第四子画素电极（300），第四子画素电极（300）包括第一画素电极（310），第二画素电极（320），第三画素电极（330）及第四画素电极（340），分别位于第四子画素的四个区域，且第一画素电极（310），第二画素电极（320），第三画素电极（330）及第四画素电极（340）分别分割成至少二个补偿区；以及一第一子画素电极（210）及一第二子画素电极（210），分别位于第一子画素及第二子画素。

Description

显示器阵列基板画素结构及其应用的显示设备 技术领域
本申请涉及一种电极设计方式，特别是涉及一种显示器阵列基板画素结构及其应用的显示设备。
背景技术
一般Mura是因显示屏上亮度分布不均所造成，在垂直配向(Vertical Alignment，VA)型/平面转换(In-Plane Switching，IPS)型/边缘场开关(Fringe Field Switching，FFS)型的画素设计上，画素电极一般都设计成狭缝状，其线宽的控制影响液晶效率甚钜。在一种用于显示器阵列基板画素设计的工艺中，不同颜色的子画素之间可能会产生段差。在此工艺中，子画素因为严重段差(由于平坦层的宽度落差)而导致曝光显影蚀刻工艺对ITO slit(氧化铟锡狭缝)线宽控制更难掌握，因此容易造成穿透率不稳定的问题。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种用于显示器阵列基板画素结构，不仅可以有效解决Mura问题，同时提升改善第四子画素ITO slit(氧化铟锡狭缝)变异所造成的亮度差异。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种显示器阵列基板画素结构，包括多个阵列排列的画素单元，每个所述画素单元均包括第一子画素、第二子画素和第四子画素，每个所述画素单元均更包括：一第四子画素电极，所述第四子画素电极包括第一画素电极，第二画素电极，第三画素电极及第四画素电极，分别位于所述第四子画素的四个区域，且所述第一画素电极，第二画素电极，第三画素电极及第四画素电极分别分割成至少二个补偿区，用以回馈修正至少二个补偿区的电极线宽，以改善因所述第四子画素电极的狭缝变异而造成的亮度差异；以及一第一子画素电极及一第二子画素电极，分别位于所述第一子画素及第二子画素。
一种液晶显示面板，包括：第一基板；第二基板，与所述第一基板相对设置；液晶层，设置于所述第一基板与所述第二基板之间；还包括所述的显示器阵列基板画素结构，设置于所述第一基板与所述第二基板之间。且更包括第一偏光片设置于所述第一基板的一外表面上；以及第二偏光片设置于所述第二基板的一外表面上，其中所述第一偏光片与所述第二偏光片的偏振方向为互相平行。
一种显示装置，包括背光模块，还包括上述的液晶显示面板。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述第一画素电极分割成三个补偿区为第一内层画素电极，第一中层画素电极及第一外层画素电极，且所述第一内层画素电极，第一中层画素电极及第一外层画素电极 的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
在本申请的一实施例中，所述第二画素电极分割成三个补偿区为第二内层画素电极，第二中层画素电极及第二外层画素电极，且所述第二内层画素电极，第二中层画素电极及第二外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
在本申请的一实施例中，所述第三画素电极分割成三个补偿区为第三内层画素电极，第三中层画素电极及第三外层画素电极，且所述第三内层画素电极，第三中层画素电极及第三外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
在本申请的一实施例中，所述第四画素电极分割成三个补偿区为第四内层画素电极，第四中层画素电极及第四外层画素电极，且所述第四内层画素电极，第四中层画素电极及第四外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
在本申请的一实施例中，所述第二画素电极、第三画素电极及第四画素电极的电极线宽设计如同所述第一画素电极。
在本申请的一实施例中，所述第四子画素电极画素分割形式为矩形、圆形或菱形。
在本申请的一实施例中，更包括补偿区电极线宽形式为外缘矩形对称放射画素电极。
在本申请的一实施例中，更包括补偿区电极线宽形式为内嵌长条矩形对称放射画素电极。
在本申请的一实施例中，更包括补偿区电极线宽形式为外缘圆形对称放射画素电极或内嵌圆形对称放射画素电极。
有益效果
本申请的有益效果是，使针对用于显示器阵列基板画素阵列显示屏的画素改善，因此对于工艺变异较不敏感。本设计针对用于显示器阵列基板画素阵列一种新型工艺中所延伸的问题，提供一种回馈修正补偿线宽的方式，提升改善第四子画素ITO slit(氧化铟锡狭缝)变异所造成的亮度差异。
附图说明
图1a是本申请一实施例的用于显示器阵列基板画素的白色画素段差示意图。
图1b是本申请一实施例的用于显示器阵列基板画素类型示意图。
图2是本申请一实施例的用于显示器阵列基板画素结构具有第四子画素电极及第一子画素电极、第二子画素电极、第三子画素电极示意图。
图3a是本申请一实施例的第四子画素电极矩形画素分割示意图。
图3b是本申请一实施例的第四子画素电极圆形画素分割示意图。
图3c是本申请一实施例的第四子画素电极菱形画素分割示意图。
图4是本申请一实施例的RGB画素的电极结构的补偿电极线宽示意图。
图4a是本申请一实施例的白色画素的电极结构的补偿电极线宽示意图。
图4b是本申请另一实施例的白色画素的电极结构的补偿电极线宽示意图。
图4c是本申请又一实施例的白色画素的电极结构的补偿电极线宽示意图。
图4d是本申请再一实施例的白色画素的电极结构的补偿电极线宽示意图。
图5a是本申请一实施例的用于显示器阵列基板画素结构的补偿区电极线宽示意图。
图5b是本申请另一实施例的用于显示器阵列基板画素结构的补偿区电极线宽示意图。
图5c是本申请又一实施例的用于显示器阵列基板画素结构的补偿区电极线宽示意图。
图5d是本申请再一实施例的用于显示器阵列基板画素结构的补偿区电极线宽示意图。
本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种显示器阵列基板画素结构及其应用的显示设备其具体实施方式、结构、特征及其功效，详细说明如后。
本申请的液晶显示设备可包括背光模块及液晶显示面板。液晶显示面板可包括薄膜晶体管(Thin Film Transistor，TFT)基板、彩色滤光片(Color Filter，CF)基板与形成于两基板之间的液晶层。
在本申请的一实施例中，本申请的液晶显示面板可为曲面型显示面板，且本申请的液晶显示设备亦可为曲面型显示裝置。
在本申请的一实施例中，本申请的薄膜晶体管及彩色滤光片可形成于同一基板上。
垂直配向型(Vertical Alignment，VA)模式的液晶显示设备，例如图形垂直配向型(Patterned Vertical Alignment，PVA)液晶显示器或多区域垂直配向型(Multi-domain Vertical Alignment，MVA)液晶显示设备，其中图形垂直配向型利用边缘场效应与补偿板达到广视角的效果。多区域垂直配向型将一个画素分成多个区域，并使用突起物(Protrusion)或特定图案结构，使位于不同区域的液晶分子朝向不同方向倾倒，以达到广视角且提升穿透率的目的。
图1a为本申请一实施例的用于显示器阵列基板画素的白色画素段差示意图。请参照图1a，在理想工艺情况102与实际工艺情况103中的不同差异，在于白色子画素的严重段差(由于平坦层130的宽度落差Dh)而导致曝光显影蚀刻工艺对ITO slit(氧化铟锡狭缝)110，有著因为线宽(变成非均匀狭缝线宽120)控制上更难掌握，因此容易造成穿透率不稳定的问题。
请参照图1b，其为本申请一实施例的用于显示器阵列基板画素类型示意图。所述用于显示器阵列基板画素类型可包括条状1的用于显示器阵列基板画素及矩形2的用于显示器阵列基板画素格式类型。
图2为本申请一实施例的用于显示器阵列基板画素结构具有第四子画素电极300及第一子画素电极210、第二子画素电极210、第三子画素电极210示意图及图3a为本申请一实施例的第四子画素电极300矩形301画素分割示意图。请参照图2及图3a，本申请是一种用于显示器阵列基板画素结构，包括多个阵列排列的画素单元，每个所述画素单元可包括第一子画素(例如红色子画素)、第二子画素(例如绿色子画素)、第三子画素(例如蓝色子画素)和第四子画素(例如白色子画素)，每个所述画素单元均更包括：一第四子画素电极300，所述第四子画素电极300包括第一画素电极310，第二画素电极320，第三画素电极330及第四画素电极340，分别位于所述第四子画素的四个区域，且所述第一画素电极310，第二画素电极320，第三画素电极330及第四画素电极340分别分割成至少二个补偿区，用以回馈修正至少二个补偿区的电极线宽，以改善所述第四子画素电极300的狭缝变异所造成的亮度差异；以及一第一子画素电极210及一第二子画素电极210，分别位于所述第一子画素及第二子画素。
图3b是本申请一实施例的用于显示器阵列基板画素结构的第四子画素电极300圆形302画素分割示意图、图3c是本申请一实施例的用于显示器阵列基板画素结构的第四子画素电极300菱形303画素分割示意图、图4是本申请一实施例的RGB画素的电极结构的补偿电极线宽示意图、图4a是本申请一实施例的第四画素的电极结构的补偿电极线宽示意图、图4b是本申请另一实施例的第四画素的电极结构的补偿电极线宽示意图、图4c是本申请又一实施例的第四画素的电极结构的补偿电极线宽示意图及图4d是本申请再一实施例的第四画素的电极结构的补偿电极线宽示意图。请参照图3a、图3b、图3c、图4、图4a、图4b、图4c及图4d。在本申请的一实施例中，所述第 一画素电极310分割成三个补偿区为第一内层画素电极312，第一中层画素电极314及第一外层画素电极316，且所述第一内层画素电极312，第一中层画素电极314及第一外层画素电极316的电极线宽可例如分别为所述第一子画素电极210及第二子画素电极210线宽D的80％～120％如D11，D12，D13(D11＝D12＝D13＝0.8～1.2D)。
在本申请的一实施例中，所述第二画素电极320分割成三个补偿区为第二内层画素电极322，第二中层画素电极324及第二外层画素电极326，且所述第二内层画素电极322，第二中层画素电极324及第二外层画素电极326的电极线宽可例如分别为所述第一子画素电极210及第二子画素电极210线宽D的80％～120％如D21，D22，D23(D21＝D22＝D23＝0.8～1.2D)。
在本申请的一实施例中，所述第三画素电极330分割成三个补偿区为第三内层画素电极332，第三中层画素电极334及第三外层画素电极336，且所述第三内层画素电极332，第三中层画素电极334及第三外层画素电极336的电极线宽可例如分别为所述第一子画素电极210、第二子画素电极210线宽D的80％～120％如D31，D32，D33(D31＝D32＝D33＝0.8～1.2D)。
在本申请的一实施例中，所述第四画素电极340分割成三个补偿区为第四内层画素电极342，第四中层画素电极344及第四外层画素电极346，且所述第四内层画素电极342，第四中层画素电极344及第四外层画素电极346的电极线宽可例如分别为所述第一子画素电极210及第二子画素电极210线宽D的80％～120％如D41，D42，D43(D41＝D42＝D43＝0.8～1.2D)。
所述第二画素电极320、第三画素电极330及第四画素电极340的电极线宽设计可如同所述第一画素电极310。
所述第四子画素电极300画素分割形式可例为矩形301、圆形302、菱形303或其他图形。
图5a是本申请一实施例的用于显示器阵列基板画素结构的补偿区电极线宽示意图、图5b是本申请另一实施例的用于显示器阵列基板画素结构的补偿区电极线宽示意图、图5c是本申请又一实施例的用于显示器阵列基板画素结构的补偿区电极线宽示意图及图5d是本申请再一实施例的用于显示器阵列基板画素结构的补偿区电极线宽示意图。请参阅图5a、图5b、图5c及图5d，在本申请的一些实施例中，所述用于显示器阵列基板画素结构，更可包括四种补偿区电极线宽形式为外缘矩形对称放射画素电极510，内嵌长条矩形对称放射画素电极520，外缘圆形对称放射画素电极530或内嵌圆形对称放射画素电极540。但是不限于此，在其他实施例中，本申请的显示器阵列基板画素结构可包括其他图形的对称放射画素电极。
在本申请一实施例中，本申请的液晶显示面板，包括：第一基板；第二基板，与所述第一基板相对设置；液晶层，设置于所述第一基板与所述第二基板之间；还包括多个阵列排列的画素单元(如图2及图3a)，每个所述画素单元均包括所述第一子画素、所述第二子画素和所述第四子画素，每 个所述画素单元均包括：一第四子画素电极，所述第四子画素电极包括第一画素电极，第二画素电极，第三画素电极及第四画素电极，分别位于所述第四子画素的四个区域，且所述第一画素电极，第二画素电极，第三画素电极及第四画素电极分别分割成至少二个补偿区，用以回馈修正至少二个补偿区的电极线宽，以改善所述第四子画素电极的狭缝变异所造成的亮度差异；及一第一子画素电极及一第二子画素电极，分别位于所述第一子画素及第二子画素，且每个所述画素单元，设置于所述第一基板与所述第二基板之间。且还包括第一偏光片设置于所述第一基板的一外表面上，及第二偏光片设置于所述第二基板的一外表面上，其中所述第一偏光片与所述第二偏光片的偏振方向为互相平行。
在本申请一实施例中，本申请的显示装置，包括背光模块，还包括一种液晶显示面板，包括：第一基板；第二基板，与所述第一基板相对设置；液晶层，设置于所述第一基板与所述第二基板之间；还包括多个阵列排列的画素单元(如图2及图3a)，每个所述画素单元均包括所述第一子画素、所述第二子画素和所述第四子画素，每个所述画素单元均包括：一第四子画素电极，所述第四子画素电极包括第一画素电极，第二画素电极，第三画素电极及第四画素电极，分别位于所述第四子画素的四个区域，且所述第一画素电极，第二画素电极，第三画素电极及第四画素电极分别分割成至少二个补偿区，用以回馈修正至少二个补偿区的电极线宽，以改善所述第四子画素电极的狭缝变异所造成的亮度差异；及一第一子画素电极及一第二子画素电极，分别位于所述第一子画素及第二子画素，且每个所述画素单元，设置于所述第一基板与所述第二基板之间。且还包括第一偏光片设置于所述第一基板的一外表面上，及第二偏光片设置于所述第二基板的一外表面上，其中所述第一偏光片与所述第二偏光片的偏振方向为互相平行。
本申请的有益效果是，使针对用于显示器阵列基板画素阵列显示屏的画素改善，因此对于工艺变异较不敏感。本设计针对用于显示器阵列基板画素阵列一种新型工艺中所延伸的问题，提供一种回馈修正补偿线宽方式，提升改善第四子画素ITO slit(氧化铟锡狭缝)变异所造成的亮度差异，因此对于大段差导致曝光工艺造成的电极线宽差异，借着控制电极线宽的调整因而能做作预先性的补偿，可有效减缓画素透光的不均匀，还可以降低电极断线的风险。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的较佳实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以较佳实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但 凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (18)

  1. 一种显示器阵列基板画素结构，包括多个阵列排列的画素单元，每个所述画素单元均包括第一子画素、第二子画素和第四子画素，每个所述画素单元均更包括：
    一第四子画素电极，所述第四子画素电极包括第一画素电极，第二画素电极，第三画素电极及第四画素电极，分别位于所述第四子画素的四个区域，且所述第一画素电极，第二画素电极，第三画素电极及第四画素电极分别分割成至少二个补偿区，用以回馈修正至少二个补偿区的电极线宽，以改善所述第四子画素电极的狭缝变异所造成的亮度差异；以及
    一第一子画素电极及一第二子画素电极，分别位于所述第一子画素及第二子画素。
  2. 如权利要求1所述的显示器阵列基板画素结构，其中所述第一画素电极分割成三个补偿区为第一内层画素电极，第一中层画素电极及第一外层画素电极，且所述第一内层画素电极，第一中层画素电极及第一外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
  3. 如权利要求1所述的显示器阵列基板画素结构，其中所述第二画素电极分割成三个补偿区为第二内层画素电极，第二中层画素电极及第二外层画素电极，且所述第二内层画素电极，第二中层画素电极及第二外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
  4. 如权利要求1所述的显示器阵列基板画素结构，其中所述第三画素电极分割成三个补偿区为第三内层画素电极，第三中层画素电极及第三外层画素电极，且所述第三内层画素电极，第三中层画素电极及第三外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
  5. 如权利要求1所述的显示器阵列基板画素结构，其中所述第四画素电极分割成三个补偿区为第四内层画素电极，第四中层画素电极及第四外层画素电极，且所述第四内层画素电极，第四中层画素电极及第四外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
  6. 如权利要求1所述的显示器阵列基板画素结构，其中所述第二画素电极、第三画素电极及第四画素电极的电极线宽设计如同所述第一画素电极。
  7. 如权利要求1所述的显示器阵列基板画素结构，其中所述第四子画素电极画素分割形式为矩形、圆形或菱形。
  8. 如权利要求1所述的显示器阵列基板画素结构，更包括补偿区电极线宽形式为外缘矩形对称放射画素电极、内嵌长条矩形对称放射画素电极、外缘圆形对称放射画素电极或内嵌圆形对称放射画 素电极。
  9. 一种液晶显示面板，包括：
    第一基板；
    第二基板，与所述第一基板相对设置；以及
    液晶层，设置于所述第一基板与所述第二基板之间。
    其中，更包括一种显示器阵列基板画素结构，设置于所述第一基板与所述第二基板之间，包括多个阵列排列的画素单元，每个所述画素单元均包括第一子画素、第二子画素和第四子画素，每个所述画素单元均更包括：一第四子画素电极，所述第四子画素电极包括第一画素电极，第二画素电极，第三画素电极及第四画素电极，分别位于所述第四子画素的四个区域，且所述第一画素电极，第二画素电极，第三画素电极及第四画素电极分别分割成至少二个补偿区，用以回馈修正至少二个补偿区的电极线宽，以改善所述第四子画素电极的狭缝变异所造成的亮度差异；以及
    一第一子画素电极及一第二子画素电极，分别位于所述第一子画素及第二子画素。
  10. 如权利要求9所述的液晶显示面板，其中所述第一画素电极分割成三个补偿区为第一内层画素电极，第一中层画素电极及第一外层画素电极，且所述第一内层画素电极，第一中层画素电极及第一外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
  11. 如权利要求9所述的液晶显示面板，其中所述第二画素电极分割成三个补偿区为第二内层画素电极，第二中层画素电极及第二外层画素电极，且所述第二内层画素电极，第二中层画素电极及第二外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
  12. 如权利要求9所述的液晶显示面板，其中所述第三画素电极分割成三个补偿区为第三内层画素电极，第三中层画素电极及第三外层画素电极，且所述第三内层画素电极，第三中层画素电极及第三外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
  13. 如权利要求9所述的液晶显示面板，其中所述第四画素电极分割成三个补偿区为第四内层画素电极，第四中层画素电极及第四外层画素电极，且所述第四内层画素电极，第四中层画素电极及第四外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
  14. 如权利要求9所述的液晶显示面板，其中所述第二画素电极、第三画素电极及第四画素电极的电极线宽设计如同所述第一画素电极。
  15. 如权利要求9所述的液晶显示面板，其中所述第四子画素电极画素分割形式为矩形、圆形及菱形。
  16. 如权利要求9所述的液晶显示面板，更包括补偿区电极线宽形式为外缘矩形对称放射画素电极、内嵌长条矩形对称放射画素电极、外缘圆形对称放射画素电极及内嵌圆形对称放射画素电极。
  17. 如权利要求9所述的液晶显示面板，更包括：第一偏光片设置于所述第一基板的一外表面上；以及第二偏光片设置于所述第二基板的一外表面上，其中所述第一偏光片与所述第二偏光片的偏振方向为互相平行。
  18. 一种显示器阵列基板画素结构，包括多个阵列排列的画素单元，每个所述画素单元均包括第一子画素、第二子画素和第四子画素，每个所述画素单元均更包括：
    一第四子画素电极，所述第四子画素电极包括第一画素电极，第二画素电极，第三画素电极及第四画素电极，分别位于所述第四子画素的四个区域，且所述第一画素电极，第二画素电极，第三画素电极及第四画素电极分别分割成至少二个补偿区，用以回馈修正至少二个补偿区的电极线宽，以改善所述第四子画素电极的狭缝变异所造成的亮度差异；以及
    一第一子画素电极及一第二子画素电极，分别位于所述第一子画素及第二子画素；
    所述第一画素电极分割成三个补偿区为第一内层画素电极，第一中层画素电极及第一外层画素电极，且所述第一内层画素电极，第一中层画素电极及第一外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％；
    所述第二画素电极分割成三个补偿区为第二内层画素电极，第二中层画素电极及第二外层画素电极，且所述第二内层画素电极，第二中层画素电极及第二外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％；
    所述第三画素电极分割成三个补偿区为第三内层画素电极，第三中层画素电极及第三外层画素电极，且所述第三内层画素电极，第三中层画素电极及第三外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％；
    所述第四画素电极分割成三个补偿区为第四内层画素电极，第四中层画素电极及第四外层画素电极，且所述第四内层画素电极，第四中层画素电极及第四外层画素电极的电极线宽分别为所述第一子画素电极、第二子画素电极线宽的80％～120％。
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