WO2018061636A1 - Circuit de mesure de capacité et système de mesure de capacité - Google Patents

Circuit de mesure de capacité et système de mesure de capacité Download PDF

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Publication number
WO2018061636A1
WO2018061636A1 PCT/JP2017/031762 JP2017031762W WO2018061636A1 WO 2018061636 A1 WO2018061636 A1 WO 2018061636A1 JP 2017031762 W JP2017031762 W JP 2017031762W WO 2018061636 A1 WO2018061636 A1 WO 2018061636A1
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capacitance
terminal
voltage
circuit
sense
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PCT/JP2017/031762
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English (en)
Japanese (ja)
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英明 杉林
中尾　元保
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株式会社村田製作所
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Publication of WO2018061636A1 publication Critical patent/WO2018061636A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G13/00—Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00

Definitions

  • the present invention relates to a capacitance measurement circuit that measures the capacitance of a capacitance sensor formed by, for example, a micro electro mechanical system (MEMS), and a capacitance measurement system including the capacitance sensor and the capacitance measurement circuit.
  • MEMS micro electro mechanical system
  • FIG. 5 is a circuit diagram showing a configuration of a capacitance measuring circuit according to Conventional Example 1 disclosed in Patent Document 1, for example.
  • the capacitance measuring circuit measures a minute measured capacitance Cx of the measured circuit 101, and the measured circuit 101 includes a stray capacitance Csf.
  • the capacitance measuring circuit impedance-converts the constant voltage source Vs1 for charging the circuit under test 101 to the voltage V0, the constant current source Is of the discharge current I1, and the voltage of the circuit under test 101 with a low impedance.
  • An output buffer amplifier BA and an inverting amplifier OPA are provided.
  • R101 and R103 are voltage dividing circuits that divide the output voltage of the buffer amplifier BA into a ratio of R103 / (R101 + R103) in an AC and DC manner.
  • the AC amplitude of the output of the buffer amplifier BA is attenuated so as to be within the input range of the next-stage inverting amplifier OPA, the DC offset voltage is adjusted by the applied voltage Vb1 of the voltage source VoF, and the output voltage of the inverting amplifier OPA Shift to the proper range.
  • the capacitance measurement circuit further includes a data processing unit 102 including an AD conversion circuit and an arithmetic circuit for converting the output voltage of the inverting amplifier OPA into a digital value, a limiter circuit 104 including a diode D and a DC power supply VLMP, and a device under test.
  • the control circuit 103 outputs signals CC1, CC2, and CC3 for controlling on / off of the switches SW11, SW12, and SW13.
  • the following procedure is proposed as a method of measuring the measured capacitance Cx of the measured circuit 101 with the stray capacitance Csf.
  • (1) After the stray capacitance Csf is charged to a predetermined voltage Vpre1, it is discharged with a current I1 for a predetermined time to obtain an output voltage V1.
  • (2) After the combined capacitance of the stray capacitance Csf and the measured capacitance Cx is charged to the predetermined voltage Vpre2, the output voltage V2 is obtained by discharging with the current I1 for a predetermined time.
  • the voltages V1 and V2 at the time of each discharge are amplified, AD converted, and then subjected to numerical calculation to obtain the measured capacitance Cx of the measured object.
  • FIG. 6A is a plan view showing a configuration of the MEMS capacitive sensor 1 disclosed in Patent Document 2 and used in the capacitance measuring system according to Conventional Example 2, and FIG. 6B is a longitudinal section taken along line BB ′ of FIG. 6A.
  • FIG. 6A is a plan view showing a configuration of the MEMS capacitive sensor 1 disclosed in Patent Document 2 and used in the capacitance measuring system according to Conventional Example 2, and FIG. 6B is a longitudinal section taken along line BB ′ of FIG. 6A.
  • the MEMS capacitive sensor 201 is formed through an insulating layer 228, a conductive layer 227, and an insulating layer 229 so as to form a hermetic gap 222 in the central portion thereof on, for example, a parallel plate conductive substrate 221.
  • a diaphragm plate 220 which is a membrane covering the whole is formed.
  • the sidewall layer 223 is formed by the insulating layer 228, the conductive layer 227, and the insulating layer 229.
  • the conductive layer 227 has a central rectangular opening 222h having a size of W1 ⁇ W1
  • the insulating layer 229 has a central rectangular opening 229h having a size of W2 ⁇ W2.
  • the insulating layers 228 and 229 are made of, for example, silicon dioxide, and the conductive substrate 221, the conductive layer 227, and the diaphragm plate 220 are made of, for example, polysilicon.
  • the diaphragm plate 220 changes up and down, so that the sense terminal TS and the base terminal TB The sense capacitance Cs during the period changes.
  • a change in atmospheric pressure can be measured.
  • FIG. 7 is a circuit diagram showing an equivalent circuit of the MEMS capacitive sensor 201 of FIGS. 6A and 6B.
  • the MEMS capacitive sensor 201 includes the sense capacitor 210 and the stray capacitors 211 and 212 as described above.
  • the stray capacitance 211 is connected in series with the sense capacitance 210
  • the stray capacitance 212 is connected in parallel with the series circuit of the sense capacitance 210 and the stray capacitance 211
  • the stray capacitances 211 and 212 have capacitance values Cbg and Csg, respectively.
  • the sense capacitor 210 is connected between the sense terminal TS and the base terminal TB, the stray capacitor 211 is connected between the base terminal TB and the guard terminal TG, and the stray capacitor 212 is connected to the sense terminal between the TS and the guard terminal TG. Connected between. That is, in the MEMS capacitance sensor 201 according to the conventional example 2, the stray capacitances 211 and 212 exist for the sense capacitance 210 having the sense capacitance Cs to be measured.
  • 8A to 8C are circuit diagrams showing an operation when the capacitance of the MEMS capacitance sensor 201 according to Conventional Example 2 is measured using the capacitance measurement circuit of FIG.
  • the output voltage after connecting and discharging only to the stray capacitance, the stray capacitance When the output voltage after being connected to the combined capacitance with the measured capacitance is discharged and subjected to circuit processing and arithmetic processing, the measured capacitance is obtained.
  • FIG. 8C a method is assumed in which the switches are switched so that the wiring patterns of the phases P11 to P13 are obtained, and the sense capacitance Cs is calculated from the output voltage obtained in each state.
  • the sense capacitor 210 is connected between the sense terminal TS and the base terminal TB, the stray capacitance 211 is connected between the base terminal TB and the guard terminal TG, and the stray capacitance 212 is sensed.
  • a terminal is connected between TS and guard terminal TG.
  • Vp is a measurement voltage.
  • the specific capacity measurement procedure is as follows: (1) In phase P11 of FIG. 8A, the charge (Cs + Cbg) ⁇ (Vp ⁇ Vcom) at the capacity (Cs + Cbg) is discharged, and the voltage V1 after discharge is measured. To do. (2) In phase P12 of FIG. 8B, the charge (Cs + Csg) ⁇ (Vp ⁇ Vcom) at the capacity (Cs + Csg) is discharged, and the voltage V2 after the discharge is measured. (3) In phase P13 of FIG. 8C, the charge (Csg + Cbg) ⁇ (Vp ⁇ Vcom) at the capacity (Csg + Cbg) is discharged, and the voltage V3 after the discharge is measured. (4) Based on the voltages V1, V2, and V3 obtained after discharging, the sense capacitance Cs is calculated using the following equation.
  • An object of the present invention includes a capacitance measurement circuit that can measure capacitance with higher accuracy than the prior art without being affected by stray capacitance of the capacitance sensor, and a capacitance sensor and a capacitance measurement circuit. Another object is to provide a capacity measurement system.
  • the capacitance measuring circuit according to the first invention is: A sense capacitance between the first terminal and the second terminal; A first stray capacitance between the second terminal and the third terminal; A capacitance measuring circuit comprising measuring means for measuring a sense capacitance of a capacitance sensor having a second stray capacitance between the first terminal and the third terminal from the first terminal; A control circuit is provided in which the first terminal and the third terminal have the same potential in a predetermined period.
  • the control circuit includes: In the first period, the first terminal and the third terminal are set to the same potential, a first voltage is applied to the second terminal, In a second period following the first period, a second voltage is applied to the second terminal, the third terminal is set to the potential, and the voltage of the first terminal is measured by the measuring unit. Thus, the sense capacitance is measured.
  • the first voltage is higher than the same potential
  • the second voltage is lower than the same potential
  • the first voltage is lower than the same potential, and the second voltage is higher than the same potential.
  • the control circuit includes: A timing signal generator that outputs a first control signal in the first period and outputs a second control signal in the second period; A first switch connected between the first terminal and the potential and turned on based on the first control signal; A second switch connected between the first terminal and the measuring means and turned on based on the second control signal; A third switch connected between the second terminal and the first voltage and turned on based on the first control signal; And a fourth switch connected between the second terminal and the second voltage and turned on based on the second control signal.
  • the timing signal generator repeatedly generates the first control signal and the second control signal.
  • the measuring means further includes an integrator that integrates the voltage of the first terminal and outputs an output voltage.
  • the measuring means further includes a low-pass filter that passes a low-frequency component of the output voltage from the integrator.
  • the measuring means corrects the output voltage from the integrator or the low-pass filter according to an ambient temperature, and based on the corrected output voltage, A correction circuit for calculating a capacitance value is further provided.
  • the measurement unit corrects the output voltage from the integrator or the low-pass filter according to an ambient temperature, and based on the corrected output voltage, A correction circuit for calculating an atmospheric pressure value corresponding to the capacitance value is further provided.
  • the capacitance sensor includes a diaphragm plate through a first insulating layer, a conductive layer, and a second insulating layer so as to form a sealed space on the substrate. Formed and configured, The diaphragm plate is connected to the first terminal, the conductive layer is connected to the third terminal, and the substrate is connected to the second terminal.
  • the capacity measuring system is: The capacitive sensor; And a capacitance measuring circuit.
  • the capacitance measuring circuit and the capacitance measuring system it is possible to measure the capacitance with higher accuracy than the conventional technology without being affected by the stray capacitance of the capacitance sensor.
  • FIG. 1B is a longitudinal sectional view taken along line A-A ′ of FIG. 1A.
  • FIG. 3 is a timing chart showing an operation of the capacitance measuring circuit in FIG. 2.
  • FIG. 3 is a circuit diagram of the MEMS capacitance sensor 1 showing an operation in a phase P1 of the capacitance measuring circuit in FIG. 2.
  • FIG. 3 is a circuit diagram of the MEMS capacitance sensor 1 showing an operation in a phase P2 of the capacitance measuring circuit of FIG. It is a circuit diagram which shows the structure of the capacity
  • FIG. It is a top view which shows the structure of the MEMS capacitive sensor 1 used with the capacity
  • FIG. 6B is a longitudinal sectional view taken along line B-B ′ of FIG. 6A. It is a circuit diagram which shows the equivalent circuit of the MEMS capacitive sensor 1 of FIG. 6A and 6B.
  • FIG. 6 is a circuit diagram showing the operation of phase P11 when the capacitance of the MEMS capacitance sensor 1 according to the conventional example 2 is measured using the capacitance measurement circuit of FIG.
  • FIG. 6 is a circuit diagram showing the operation of phase P12 when the capacitance of the MEMS capacitance sensor 1 according to the conventional example 2 is measured using the capacitance measurement circuit of FIG.
  • FIG. 6 is a circuit diagram showing an operation of a phase P13 when the capacitance of the MEMS capacitance sensor 1 according to Conventional Example 2 is measured using the capacitance measurement circuit of FIG.
  • FIG. 1A is a plan view showing a configuration of a MEMS capacitive sensor 1 used in a capacitance measuring system according to an embodiment of the present invention
  • FIG. 1B is a longitudinal sectional view taken along line A-A ′ of FIG. 1A.
  • the MEMS capacitive sensor 1 includes an insulating layer 28, a conductive layer 27, and an insulating layer 29 so that a hermetic gap 22 is formed at the center of a parallel flat conductive substrate 21, for example.
  • a diaphragm plate 20 which is a membrane covering the whole is formed.
  • the sidewall layer 23 is constituted by the insulating layer 28, the conductive layer 27, and the insulating layer 29.
  • the conductive layer 27 has a central rectangular opening 27h having a size of W1 ⁇ W1
  • the insulating layer 29 has a central rectangular opening 29h having a size of W2 ⁇ W2.
  • the insulating layers 28 and 29 are made of, for example, silicon dioxide
  • the conductive substrate 21, the conductive layer 27, and the diaphragm plate 20 are made of, for example, polysilicon.
  • the diaphragm plate 20 changes up and down, so that the sense terminal TS and the base terminal TB The sense capacitance Cs during the period changes.
  • the change in the atmospheric pressure can be measured.
  • FIG. 2 is a circuit diagram showing a capacitance measuring circuit for measuring the sense capacitance Cs of the MEMS capacitive sensor 1 of FIGS. 1A and 1B.
  • the capacity measurement system includes a MEMS capacity sensor 1, a front end circuit 2, and a signal processing circuit 3.
  • the capacity measurement circuit includes a front end circuit 2 and a signal processing circuit 3.
  • the MEMS capacitance sensor 1 includes the sense capacitance 10 and the stray capacitances 11 and 12 as described above.
  • the stray capacitance 11 is connected in series with the sense capacitance 10
  • the stray capacitance 12 is connected in parallel with the series circuit of the sense capacitance 10 and the stray capacitance 11, and the stray capacitances 11 and 12 have capacitance values Cbg and Csg, respectively.
  • the sense capacitor 10 is connected between the sense terminal TS and the base terminal TB
  • the stray capacitor 11 is connected between the base terminal TB and the guard terminal TG
  • the stray capacitor 12 is connected to the sense terminal TS and the guard terminal TG. Connected between.
  • the front end circuit 2 includes switches SW1 to SW4, an integrator 15, a timing signal generator 16, and DC voltage sources 17 and 18.
  • the integrator 15 includes a differential amplifier 13 that is an operational amplifier, an integration capacitor 14, and a reset switch SW5.
  • the operational amplifier is preferably a high input impedance operational amplifier such as CMOS in order to avoid errors due to leakage current.
  • the timing signal generator 16 constitutes a control circuit that controls the operation of the MEMS capacitance sensor 1 and the front end circuit 2 by generating control signals ⁇ 1 and ⁇ 2.
  • the timing signal generator 16 outputs the control signal ⁇ 1 to the switches SW1, SW3, SW5 to turn on / off the switches SW1, SW3, SW5.
  • the timing signal generator 16 outputs the control signal ⁇ 2 to the switches SW2 and SW4, thereby turning on and off the switches SW2 and SW4.
  • the control signal ⁇ 1 is turned on in phase P1 and turned off in phase P2.
  • control signal ⁇ 2 is turned off in phase P1 and turned on in phase P2. Therefore, the control signals ⁇ 1 and ⁇ 2 are cyclic signals having opposite phases to each other, which are repeated at a predetermined cycle, and each has, for example, a duty ratio of 50%.
  • the duty ratio is not limited to 50%.
  • the sense terminal TS is connected to the non-inverting output terminal of the differential amplifier 13 via the switch SW1, and is connected to the inverting input terminal of the differential amplifier 13 via the switch SW2.
  • the non-inverting output terminal is connected to a predetermined potential Vcom (Vrefn ⁇ Vcom ⁇ Vrefp).
  • the potential Vcom may be a ground potential, for example.
  • the output terminal of the differential amplifier 13 is connected to the inverting input terminal of the differential amplifier 13 via a feedback circuit which is a parallel circuit of the integration capacitor 14 having the capacitance value Cfb and the reset switch SW5.
  • the differential amplifier 13 having the period circuit constitutes an integrator 15 for sample-holding by amplifying and integrating the output voltage due to the electric charge of the sense terminal TS of the MEMS capacitive sensor 1.
  • the base terminal TB is connected to the potential Vcom via the switch SW1 via the DC voltage source 17 having the voltage Vrefp, and connected to the potential Vcom via the DC voltage source 18 having the voltage Vrefn via the switch SW2. Is done.
  • the guard terminal TG is connected to the potential Vcom.
  • the integrator 15 and the signal processing circuit 3 of the front end circuit 2 constitute a measuring means for measuring the sense capacitance Cs, and the output voltage Vo from the integrator 15 is supplied to the AD converter 31 of the signal processing circuit 3. Entered.
  • the signal processing circuit 3 includes an AD converter 31, a low-pass filter 32 (denoted as LPF in FIG. 2), a digital correction circuit 33, a temperature sensor 34, a nonvolatile memory 35, and a FIFO (First-In First). -Out)
  • a memory 36 and an interface circuit 37 are provided.
  • the AD converter 31 converts the input output voltage Vo into a binary digital voltage, for example, and then outputs it to the low-pass filter 32.
  • the low-pass filter 32 passes only a predetermined low-frequency component of the input digital voltage and outputs the signal after passing to the digital correction circuit 33.
  • the AD converter 31 includes, for example, a ⁇ AD converter including a subtractor, a delay unit, a comparator, and a DA converter, and the differential amplifier 13 and the AD converter 31 are interlocked. Works with format. In each phase, the charge is transferred to the final stage of the AD converter 31, and when the charge is converted into a voltage, it is input to the comparator to obtain a digital value.
  • the low-pass filter 32 is provided to remove high-frequency components such as the sampling frequency, and a similar effect can be obtained even with a sinc filter that simply combines downsampling, an integrator, and a differentiator.
  • the temperature sensor 34, the non-volatile memory 35, and the FIFO memory 36 are connected to the digital correction circuit 33.
  • the temperature sensor 34 measures the ambient temperature of the MEMS capacitance sensor 1 and outputs a digital value of the measured temperature to the digital correction circuit 33.
  • the nonvolatile memory 35 stores a correction coefficient for converting the output voltage Vo (corresponding to the sense capacitor Cs) from the front end circuit 2 into a pressure value and performing correction in consideration of the ambient temperature.
  • the digital correction circuit 33 calculates a digital pressure value (atmospheric pressure value) by multiplying the digital value from the low-pass filter 32 by, for example, a correction coefficient, temporarily stores it in the FIFO memory 36, and then stores the interface circuit 37. Output to.
  • the interface circuit 37 converts the input digital pressure value into an output signal of digital data in a predetermined format and outputs it to an external circuit.
  • the significance of providing the digital correction circuit 33 is as follows. With the capacitance output value as it is from the MEMS capacitance sensor 1, the linearity of the capacitance value with respect to the atmospheric pressure cannot be obtained. Further, the temperature characteristics vary according to the ambient temperature. Therefore, an internal calculation is performed using the digital value of the capacitance and the digital value of the temperature to obtain a temperature characteristic having a desired linearity. Specifically, after assembling the sensor module, the pressure characteristics and temperature characteristics of each module are measured at the factory to obtain initial characteristics. Coefficients obtained by calculating digital correction coefficients based on the initial characteristics are written in the nonvolatile memory 35.
  • the capacitance digital value and the temperature digital value measured in accordance with the ambient temperature and the ambient pressure, and the above-described correction coefficient are called from the nonvolatile memory 35 and calculated.
  • an accurate digital pressure value can be calculated.
  • the digital correction circuit 33 calculates a digital pressure value (atmospheric pressure value), but the present invention is not limited to this, and the sense capacitance Cs may be calculated and output.
  • FIG. 3 is a timing chart showing the operation of the capacitance measuring circuit of FIG.
  • the control signal ⁇ 1 becomes high level, while the control signal ⁇ 2 becomes low level.
  • the switches SW1, SW3 and SW5 are turned on, while the switches SW2 and SW4 are turned off.
  • the base terminal voltage Vb becomes the voltage Vrefp
  • the output voltage Vo becomes the potential Vcom.
  • the control signal ⁇ 1 is at a low level, while the control signal ⁇ 2 is at a high level.
  • the switches SW1, SW3 and SW5 are turned off, while the switches SW2 and SW4 are turned on.
  • the base terminal voltage Vb becomes the voltage Vrefn
  • the output voltage Vo becomes the measured value Vmeas.
  • the capacitance measuring circuit having the configuration of FIG. 2 has the following characteristics. (1) As a method of measuring the sense capacitance Cs, electric charges generated by inputting a rectangular wave from the front end circuit 2 to the base terminal TB are taken out to the front end circuit 2 via the sense terminal TS. (2) The sense capacitor Cs is measured by controlling the sense terminal TS and the guard terminal TG to have the same potential Vcom. (3) A rectangular wave having a voltage Vrefp at phase P1 and having a voltage Vrefn at phase P2 is input to the base terminal TB. (4) The sense terminal TS is configured to be connected to the integrator 15 of the front end circuit 2 in the phase P2. (5) The output voltage Vo of the integrator 15 is sampled and held every period to obtain a discrete voltage signal sequence.
  • FIG. 4A is a circuit diagram of the MEMS capacitance sensor 1 showing an operation in the phase P1 of the capacitance measurement circuit of FIG. 2
  • FIG. 4B is a circuit diagram of the MEMS capacitance sensor 1 showing an operation in the phase P2 of the capacitance measurement circuit of FIG. is there.
  • the feedback capacitance of the integrator 15 of the front end circuit 2 is Cfb
  • the output voltage is dV0
  • dV0 dQs / Cfb
  • the output voltage can be output as a voltage value.
  • the electric potential at both ends of the stray capacitance 12 is always equal to the potential Vcom regardless of the phase, so that no charge is generated in the stray capacitance 12.
  • the stray capacitance 11 accumulates charges in each phase, the extracted charge is only from the sense terminal TS, and the charge accumulated in the stray capacitance 11 does not move to the sense terminal TS. Does not affect. Therefore, the sense capacitor Cs of the sense capacitor 10 can be measured with higher accuracy than the conventional example without being affected by the stray capacitances 11 and 12, and can be measured in two steps of the phases P1 and P2. Compared with this, the capacity can be detected at high speed.
  • the sense terminal TS and the guard terminal TG are set to the same potential in a predetermined period, so that the capacitance value of the sense capacitor 10 is compared with the conventional example without being affected by the stray capacitances 11 and 12. Can be measured with high accuracy.
  • the sense terminal TS and the guard terminal TG are set to the same potential, the first voltage Vrefp higher than the potential is applied to the base terminal TB, and in the phase P2 following the phase P1, the base terminal TB is applied.
  • the sense capacitor 10 is measured by applying a second voltage Vrefn lower than the potential to the guard terminal TG to the potential and measuring the voltage at the sense terminal TS by the measuring means.
  • the sense terminal TS and the guard terminal TG are set to the same potential in the phase P1, and the capacitance value of the sense capacitor 10 is set in the phase P2.
  • a circuit to be measured can be realized.
  • the timing signal generator 16 can repeatedly generate the control signal ⁇ 1 and the control signal ⁇ 2 with a predetermined period, thereby realizing a circuit that repeatedly measures the capacitance value of the sense capacitor 10 with a predetermined period.
  • the capacitance value can be measured with high accuracy.
  • the low-pass filter 32 it is possible to remove spurious components generated before the AD converter 31, and to measure the capacitance value with high accuracy. Further, it is possible to remove the clock frequency component for which SW switching is performed by the timing generator.
  • the digital correction circuit 33 the correction is made according to the ambient temperature, and the capacitance value of the sense capacitor is calculated based on the corrected output voltage. Capacitance value can be measured with accuracy.
  • the digital correction circuit 33 can also be configured as an atmospheric pressure sensor by calculating the atmospheric pressure value.
  • the MEMS capacitive sensor 1 can be formed as shown in FIGS. 1A and 1B, for example, and the capacitance value of the sense capacitor 10 can be measured with high accuracy without the influence of the stray capacitances 11 and 12 using the MEMS capacitive sensor 1.
  • a capacity measuring system can be configured by including the MEMS capacity sensor 1 and a capacity measuring circuit including the front end circuit 2 and the signal processing circuit 3.
  • the capacitance measuring circuit of FIG. 2 is used as the atmospheric pressure sensor circuit.
  • the present invention is not limited to this, and the sense capacitance Cs itself of the sense capacitance 10 may be measured.
  • the phase P1 and the phase P2 are periodically repeated.
  • the present invention is not limited to this, and the sense capacitor 10 has at least a time period of the phase P1 and a time period of the phase P2. Cs can be measured.
  • the potential Vcom may be a ground potential, for example.
  • the voltage Vrefp is a positive voltage and the voltage Vrefn is a negative voltage.
  • the AD converter 31 is provided.
  • the present invention is not limited to this, and when the digital correction circuit 33 is configured by an analog circuit, the AD converter 31 is omitted, and the integrator 15 An operational amplifier for a buffer may be separately provided in the subsequent stage.
  • the low-pass filter 32 is provided.
  • the present invention is not limited to this, and when the spurious of the output voltage signal from the AD converter 31 is lower than a predetermined value, the low-pass filter 32 is provided. 32 may be omitted.
  • the base terminal TB and the guard terminal TG are set to the same potential Vcom, the voltage Vrefp higher than the same potential Vcom is applied to the base terminal TB, and the phase P1 period.
  • a voltage Vrefn lower than the same potential Vcom is applied to the base terminal TB, the guard terminal TG is set to the same potential Vcom, and the voltage at the sense terminal TS is measured to thereby sense the capacitance Cs. Is measuring.
  • the present invention is not limited to this, and during the period of phase P1, the base terminal TB and the guard terminal TG are set to the same potential Vcom, and a voltage Vrefn lower than the same potential Vcom is applied to the base terminal TB.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Measuring Fluid Pressure (AREA)

Abstract

La présente invention concerne un circuit de mesure de capacité, comprenant : un circuit d'extrémité avant (2) qui mesure, à partir d'une borne de détection (TS), une capacité de détection (Cs) d'un capteur de capacité MEMS (1) qui comporte un condensateur de détection (10) entre la borne de détection (TS) et une borne de base (TB), un condensateur parasite (11) entre la borne de base (TB) et une borne de protection (TG) et un condensateur parasite (12) entre la borne de détection (TS) et la borne de protection (TG); un circuit de traitement de signal (3); et un circuit de commande destiné à régler la borne de détection (TS) et la borne de protection (TG) au même potentiel pendant une période prescrite. Ainsi, la présente invention permet de mesurer la capacité électrostatique avec une précision plus importante que celle de la technologie classique sans être influencée par la capacité parasite du capteur de capacité.
PCT/JP2017/031762 2016-09-29 2017-09-04 Circuit de mesure de capacité et système de mesure de capacité WO2018061636A1 (fr)

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