WO2018039236A1 - Semiconductor heterostructure with reduced unintentional calcium impurity incorporation - Google Patents

Semiconductor heterostructure with reduced unintentional calcium impurity incorporation Download PDF

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WO2018039236A1
WO2018039236A1 PCT/US2017/048026 US2017048026W WO2018039236A1 WO 2018039236 A1 WO2018039236 A1 WO 2018039236A1 US 2017048026 W US2017048026 W US 2017048026W WO 2018039236 A1 WO2018039236 A1 WO 2018039236A1
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iii
nitride
deposited
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Erin C. Young
James S. Speck
Nicolas Grandjean
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University of California Berkeley
University of California San Diego UCSD
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/10—Heating of the reaction chamber or the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/22—Sandwich processes
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/8215—Bodies characterised by crystalline imperfections, e.g. dislocations; characterised by the distribution of dopants, e.g. delta-doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2921—Materials being crystalline insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3216—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3251—Layer structure consisting of three or more layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides

Definitions

  • the present invention is related to a semiconductor heterostructure with reduced calcium impurity incorporation. 2. Description of the Related Art.
  • III-nitride materials has been well established for the fabrication of high-efficiency visible light-emitting devices, where the term“III-nitrides” refers to any alloy composition of the (Ga,Al,In,B)N semiconductors having the formula
  • GaN and InGaN alloy based thin films and light emitting diode (LED) heterostructures grown by the technique of molecular beam epitaxy (MBE) have high (10 15 -10 18 /cm 3 ) concentrations of unintentional Calcium (Ca) impurities that come from the growth environment or the surface of the starting substrate.
  • Ca impurities have previously been reported for growth of Silicon (Si) based
  • GaAs Gallium Arsenide
  • the high concentration of Ca impurity atoms is likely the source of a mechanism for non-radiative recombination known as Shockley-Read-Hall (SRH) recombination.
  • Shockley-Read-Hall (SRH) recombination Dreyer et al. have predicted that defect concentrations of the order of 10 16 /cm 3 are already sufficient to cause extremely high non-radiative recombination rates and result in low device efficiency [4].
  • the present invention discloses a device and a method for fabrication of the device.
  • the device comprises a III-nitride semiconductor heterostructure with at least one Calcium impurity reduction structure, deposited on or above a substrate, that reduces unintentional Calcium impurity incorporation in subsequent layers of the III-nitride semiconductor heterostructure to a concentration of about 1 x 10 14 /cm 3 or less.
  • the Calcium impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature, and is sandwiched between a plurality of high temperature III-nitride layers deposited at a higher temperature, to reduce the Calcium at a surface of the low temperature III-nitride layer by forcing the Calcium’s incorporation into the low temperature III-nitride layer.
  • the substrate comprises a sapphire substrate with a III-nitride template layer deposited thereon.
  • a first one of the plurality of high temperature III-nitride layers is deposited on the sapphire substrate with the III-nitride template layer and the Calcium impurity reduction structure is deposited on the first one of the plurality of high temperature III- nitride layers.
  • a second one of the plurality of high temperature III-nitride layers is deposited on the Calcium impurity reduction structure and the subsequent layers of the III-nitride semiconductor heterostructure are deposited on the second one of the plurality of high temperature III-nitride layers.
  • the Calcium impurity reduction structure may be a multilayer superlattice with alternating ones of the low temperature and high temperature III-nitride layers deposited at the lower and higher temperatures, respectively.
  • the low temperature III-nitride layer comprises a low temperature Gallium Nitride (GaN) layer grown at the lower temperature of about 550oC to 700oC.
  • GaN Gallium Nitride
  • the high temperature III-nitride layer comprises a high temperature GaN layer grown at the higher temperature of greater than about 700oC.
  • the subsequent layers of the semiconductor heterostructure form an
  • FIG.1 is a graph of SIMS (Secondary Ion Mass Spectrometry) data showing the Ca concentration in a heterostructure of a LED grown by MBE.
  • FIG.2 is a graph of SIMS data showing the Ca concentration in a GaN superlattice (SL) with layers grown alternating at high and low growth temperature.
  • FIG.3 is a schematic of an LED structure with a 15 period Ca impurity reduction superlattice grown prior to the LED device structure.
  • FIG.4 is a graph of electroluminescence (EL) data for two LED devices, with and without the Ca impurity reduction structure as shown in FIG.3.
  • FIG.5 is a flowchart that illustrates the process for fabricating a III-nitride semiconductor heterostructure with a Ca impurity reduction structure, according to one embodiment.
  • the Ca incorporation in a heterostructure of interest can be reduced by introducing a Ca impurity reduction structure into the heterostructure that includes at least one III-nitride layer grown at a lower temperature of about 550oC to 700oC to trap the Ca, wherein the III-nitride layer grown at the lower temperature is sandwiched by a plurality of III-nitride layers grown at a higher temperature of greater than about 700oC.
  • the Ca impurity reduction structure reduces the unintentional Ca concentration in subsequent layers of the heterostructure.
  • the invention described herein improves III-nitride semiconductor device performance by reducing non-radiative losses associated with unintentional Ca defects.
  • the invention disclosed is a III-nitride semiconductor heterostructure with an underlying Ca impurity reduction structure comprised of a single III-nitride layer or multiple III- nitride layers that reduce the unintentional Ca concentration to concentrations to about 1 x 10 14 /cm 3 or less in subsequent layers of the heterostructure.
  • the single III-nitride layer is grown at the lower temperature, and the multiple III-nitride layers are a superlattice with the III-nitride layers grown alternating at the higher and lower temperatures.
  • the Ca impurity reduction structure is sandwiched by a plurality of III-nitride layers grown at the higher temperature.
  • Subsequent layers of the heterostructure could be an optoelectronic device based on a p-n junction, such as a light emitting diode, a laser diode, a solar cell, or a photodetector, or another electronic device such as a transistor.
  • FIG.1 is a graph of SIMS data showing the Ca, In and Si concentrations in an InGaN-based LED heterostructure grown by MBE, wherein the x-axis is time (minutes, mn), the left-hand y-axis is intensity (counts/second, c/s), the right-hand y-axis is concentration (atom/cm 3 ), and the lines are labeled as Ca, In and Si.
  • the Ca concentration peaks at about 1 x 10 18 /cm 3 in the InGaN quantum well layers which are grown at a low temperature of about 600oC.
  • the background Ca concentration is about 1 x 10 16 /cm 3 for layers grown at a high temperature of about 820oC.
  • the Ca impurity can be reduced by depositing a Ca impurity reduction structure, comprised of at least one low temperature (LT) GaN layer grown at a lower temperature, and sandwiched between a plurality of high temperature (HT) GaN layers grown at a higher temperature, to trap the Ca impurity in the LT GaN layer at a growth condition where it incorporates more readily.
  • a Ca impurity reduction structure comprised of at least one low temperature (LT) GaN layer grown at a lower temperature, and sandwiched between a plurality of high temperature (HT) GaN layers grown at a higher temperature, to trap the Ca impurity in the LT GaN layer at a growth condition where it incorporates more readily.
  • FIG.2 is a graph of SIMS data showing the Ca, Ga and In concentrations for a heterostructure including the multilayer superlattice, wherein the x-axis is depth (nanometers, nm), the left-hand y-axis is intensity (counts/second, c/s), the right-hand y-axis is concentration (atom/cm 3 ), and the lines are labeled as Ca, Ga and In. From right-to-left in the graph, the Ca
  • concentrations are shown at a regrowth interface, in a 100 nm GaN buffer layer grown at a temperature of about 820oC, in a 10x HT/LT GaN SL with an Indium (In) surfactant, and a 120 nm GaN cap layer grown at a temperature of about 820oC. It can be seen that, after the 10x HT/LT GaN SL with layers grown alternating at the higher and lower temperatures, the Ca concentration in the top layer is reduced to about 1 x 10 14 /cm 3 or less.
  • FIG.3 is a schematic of an LED structure fabricated with a Ca impurity reduction structure comprised of a 15 period multilayer superlattice grown prior to the LED device layers.
  • the LED structure 300 is fabricated on a sapphire substrate 302 having an n-GaN template deposited thereon, and includes a 100 nm HT GaN buffer layer 304 grown at a higher temperature of about 820o, a Ca impurity reduction structure 306 that is a superlattice comprised of 15 periods of a 5 nm LT n-type GaN:Si layer 308 grown at a lower temperature of about 600°C, followed by a 20 nm HT n-type GaN:Si layer 310 grown at a higher temperature of about 820°C (with the layers 308, 310 repeated 15 times within the superlattice), a 100 nm HT n-type GaN:Si layer 312 grown at a higher temperature of about 820°C, a multiple quantum well (MQW)
  • FIG.4 is a graph of EL data for two LED devices, with and without the Ca impurity reduction structure 306 shown in FIG.3, wherein the x-axis is wavelength (nanometers, nm), the y-axis is intensity (arbitrary units, au), and the lines are labeled as LED with Ca reduction and Reference LED.
  • the LED with Ca reduction shows higher EL efficiency than the Reference LED with no Ca reduction.
  • the output power of the LED with Ca reduction was 10 times higher at low (20 mA) current density than the Reference LED with no Ca reduction.
  • the Ca impurity reduction structure 306 comprises a single low temperature III-nitride layer deposited at a lower temperature, i.e., a thicker version of layer 308, but not layer 310.
  • the single low temperature III-nitride layer comprises at least 50 nm of an LT n-type GaN:Si layer 308 grown at a lower temperature of about 600°C.
  • FIG.5 is a flowchart that illustrates the process for fabricating a III-nitride semiconductor heterostructure with a Ca impurity reduction structure using MBE, according to one embodiment.
  • Block 500 represents the step of providing a substrate, wherein the substrate is a sapphire substrate having a III-nitride template layer deposited thereon in one embodiment.
  • Block 502 represents the step of depositing a high temperature III-nitride layer on or above the substrate, wherein the high temperature III-nitride layer is a high temperature GaN buffer layer that is grown at a higher temperature of greater than about 700o.
  • Block 504 represents the step of creating a Ca impurity reduction structure on or above the high temperature III-nitride layer of step 502, wherein the Ca impurity reduction structure reduces unintentional Ca impurity incorporation in subsequent layers of the III-nitride semiconductor heterostructure to a concentration of about 1 x 10 14 /cm 3 or less.
  • Block 506 represents the step of depositing a high temperature III-nitride layer on or above the Ca impurity reduction structure, wherein the high temperature III-nitride layer is an n-type GaN layer that is grown at a higher temperature of greater than about 700o.
  • the Ca impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature of about 550oC to 700oC, and is sandwiched between a plurality of high temperature III-nitride layers deposited at a higher temperature of greater than about 700oC (i.e., the III-nitride layers deposited in Blocks 502 and 506), to reduce the Ca at a surface of the low temperature III-nitride layer by forcing the Ca’s incorporation into the low temperature III-nitride layer.
  • the Ca impurity reduction structure comprises a single low temperature III-nitride layer deposited at a lower temperature, wherein the single low temperature III-nitride layer comprises at least 50 nm of an LT n-type GaN:Si layer grown at a lower temperature of about 550oC to 700oC.
  • the Ca impurity reduction structure is a superlattice with alternating ones of the low temperature and high temperature III-nitride layers deposited at the lower and higher temperatures, respectively, wherein the low temperature III- nitride layer comprises an LT n-type GaN:Si layer grown at a lower temperature of about 550oC to 700oC, and the high temperature III-nitride layer comprises an HT n-type GaN:Si layer grown at a higher temperature of greater than about 700oC.
  • Block 506 represents the step of depositing subsequent III-nitride layers of the semiconductor heterostructure on or above the Ca impurity reduction structure to form an optoelectronic device based on a p-n junction or a transistor.
  • This invention could potentially improve the performance (for example, efficiency and output power) of semiconductor devices such as LEDs, lasers, and transistors. It could also enable the use of the MBE growth technique for prototype and commercial production of GaN based light emitting devices. References

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Abstract

A semiconductor heterostructure with reduced unintentional Calcium (Ca) impurity concentration of about 1 x 1014/cm3 or less. A Calcium impurity reduction structure may comprise a single low temperature layer or a multilayer superlattice with alternating low temperature and high temperature layers, wherein the Calcium impurity reduction structure is sandwiched between high temperature layers. The semiconductor heterostructure is comprised of a III-nitride alloy.

Description

SEMICONDUCTOR HETEROSTRUCTURE WITH REDUCED
UNINTENTIONAL CALCIUM IMPURITY INCORPORATION CROSS REFERENCE TO RELATED APPLICATION
This application claims the benefit under 35 U.S.C Section 119(e) of the following co-pending and commonly-assigned application:
U.S. Provisional Application Serial No.62/378,073, filed on August 22, 2016, by Erin Young, James S. Speck and Nicolas Grandjean, entitled“SEMICONDUCTOR HETEROSTRUCTURE WITH BUFFER LAYERS TO REDUCE UNINTENTIONAL CALCIUM IMPURITY INCORPORATION,” attorneys’ docket number 30794.624-US- P1 (2017-041-1);
which application is incorporated by reference herein. BACKGROUND OF THE INVENTION
1. Field of the Invention.
The present invention is related to a semiconductor heterostructure with reduced calcium impurity incorporation. 2. Description of the Related Art.
(Note: This application references a number of different publications as indicated throughout the specification by one or more reference numbers in brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled“References.” Each of these publications is incorporated by reference herein.).
The usefulness of III-nitride materials has been well established for the fabrication of high-efficiency visible light-emitting devices, where the term“III-nitrides” refers to any alloy composition of the (Ga,Al,In,B)N semiconductors having the formula
Figure imgf000004_0001
It has recently been discovered that GaN and InGaN alloy based thin films and light emitting diode (LED) heterostructures grown by the technique of molecular beam epitaxy (MBE) have high (1015-1018/cm3) concentrations of unintentional Calcium (Ca) impurities that come from the growth environment or the surface of the starting substrate. Ca impurities have previously been reported for growth of Silicon (Si) based
semiconductor devices [1,2] and Gallium Arsenide (GaAs) based heterostructures [3].
The high concentration of Ca impurity atoms is likely the source of a mechanism for non-radiative recombination known as Shockley-Read-Hall (SRH) recombination. Dreyer et al. have predicted that defect concentrations of the order of 1016/cm3 are already sufficient to cause extremely high non-radiative recombination rates and result in low device efficiency [4].
There is a need in the art, then, for improved methods of reducing for
concentrations of unintentional Ca impurities in III-nitride materials. The present invention satisfies this need. SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding this specification, the present invention discloses a device and a method for fabrication of the device.
The device comprises a III-nitride semiconductor heterostructure with at least one Calcium impurity reduction structure, deposited on or above a substrate, that reduces unintentional Calcium impurity incorporation in subsequent layers of the III-nitride semiconductor heterostructure to a concentration of about 1 x 1014/cm3 or less. The Calcium impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature, and is sandwiched between a plurality of high temperature III-nitride layers deposited at a higher temperature, to reduce the Calcium at a surface of the low temperature III-nitride layer by forcing the Calcium’s incorporation into the low temperature III-nitride layer.
The substrate comprises a sapphire substrate with a III-nitride template layer deposited thereon.
A first one of the plurality of high temperature III-nitride layers is deposited on the sapphire substrate with the III-nitride template layer and the Calcium impurity reduction structure is deposited on the first one of the plurality of high temperature III- nitride layers.
A second one of the plurality of high temperature III-nitride layers is deposited on the Calcium impurity reduction structure and the subsequent layers of the III-nitride semiconductor heterostructure are deposited on the second one of the plurality of high temperature III-nitride layers.
The Calcium impurity reduction structure may be a multilayer superlattice with alternating ones of the low temperature and high temperature III-nitride layers deposited at the lower and higher temperatures, respectively.
The low temperature III-nitride layer comprises a low temperature Gallium Nitride (GaN) layer grown at the lower temperature of about 550ºC to 700ºC.
The high temperature III-nitride layer comprises a high temperature GaN layer grown at the higher temperature of greater than about 700ºC.
The subsequent layers of the semiconductor heterostructure form an
optoelectronic device based on a p-n junction or a transistor. BRIEF DESCRIPTION OF THE DRAWINGS Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
FIG.1 is a graph of SIMS (Secondary Ion Mass Spectrometry) data showing the Ca concentration in a heterostructure of a LED grown by MBE.
FIG.2 is a graph of SIMS data showing the Ca concentration in a GaN superlattice (SL) with layers grown alternating at high and low growth temperature.
FIG.3 is a schematic of an LED structure with a 15 period Ca impurity reduction superlattice grown prior to the LED device structure.
FIG.4 is a graph of electroluminescence (EL) data for two LED devices, with and without the Ca impurity reduction structure as shown in FIG.3.
FIG.5 is a flowchart that illustrates the process for fabricating a III-nitride semiconductor heterostructure with a Ca impurity reduction structure, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION
In the following description of the preferred embodiment, reference is made to a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. Overview
It has recently been discovered that semiconductor heterostructures and devices based on the compounds GaN and InGaN grown by MBE contain relatively high (1e15 - 1e18 /cm3) levels of Ca as an unintentional impurity. There is evidence that the Ca reduces the light emission efficiency of the material. The Ca incorporation in a heterostructure of interest can be reduced by introducing a Ca impurity reduction structure into the heterostructure that includes at least one III-nitride layer grown at a lower temperature of about 550ºC to 700ºC to trap the Ca, wherein the III-nitride layer grown at the lower temperature is sandwiched by a plurality of III-nitride layers grown at a higher temperature of greater than about 700ºC. The Ca impurity reduction structure reduces the unintentional Ca concentration in subsequent layers of the heterostructure. Technical Description
The invention described herein improves III-nitride semiconductor device performance by reducing non-radiative losses associated with unintentional Ca defects. The invention disclosed is a III-nitride semiconductor heterostructure with an underlying Ca impurity reduction structure comprised of a single III-nitride layer or multiple III- nitride layers that reduce the unintentional Ca concentration to concentrations to about 1 x 1014/cm3 or less in subsequent layers of the heterostructure. The single III-nitride layer is grown at the lower temperature, and the multiple III-nitride layers are a superlattice with the III-nitride layers grown alternating at the higher and lower temperatures. The Ca impurity reduction structure is sandwiched by a plurality of III-nitride layers grown at the higher temperature. Subsequent layers of the heterostructure could be an optoelectronic device based on a p-n junction, such as a light emitting diode, a laser diode, a solar cell, or a photodetector, or another electronic device such as a transistor.
As noted above, it has recently been discovered that GaN and InGaN alloy based thin films and LED heterostructures grown by MBE have high (1015-1018/cm3) concentrations of unintentional Ca impurities. FIG.1 is a graph of SIMS data showing the Ca, In and Si concentrations in an InGaN-based LED heterostructure grown by MBE, wherein the x-axis is time (minutes, mn), the left-hand y-axis is intensity (counts/second, c/s), the right-hand y-axis is concentration (atom/cm3), and the lines are labeled as Ca, In and Si. The Ca concentration peaks at about 1 x 1018/cm3 in the InGaN quantum well layers which are grown at a low temperature of about 600ºC. The background Ca concentration is about 1 x 10 16 /cm 3 for layers grown at a high temperature of about 820ºC.
Subsequent experiments showed that the Ca impurity can be reduced by depositing a Ca impurity reduction structure, comprised of at least one low temperature (LT) GaN layer grown at a lower temperature, and sandwiched between a plurality of high temperature (HT) GaN layers grown at a higher temperature, to trap the Ca impurity in the LT GaN layer at a growth condition where it incorporates more readily.
Subsequent layers grown on top of the LT GaN layer showed a significantly lower Ca concentration.
A Ca impurity reduction structure comprised of a multilayer superlattice (SL) with LT and HT GaN layer pairs, grown at alternating low temperatures of about 600°C and high temperatures of about 820°C, respectively, had a similar effect and the final surface was smooth enough for subsequent device growth. FIG.2 is a graph of SIMS data showing the Ca, Ga and In concentrations for a heterostructure including the multilayer superlattice, wherein the x-axis is depth (nanometers, nm), the left-hand y-axis is intensity (counts/second, c/s), the right-hand y-axis is concentration (atom/cm3), and the lines are labeled as Ca, Ga and In. From right-to-left in the graph, the Ca
concentrations are shown at a regrowth interface, in a 100 nm GaN buffer layer grown at a temperature of about 820ºC, in a 10x HT/LT GaN SL with an Indium (In) surfactant, and a 120 nm GaN cap layer grown at a temperature of about 820ºC. It can be seen that, after the 10x HT/LT GaN SL with layers grown alternating at the higher and lower temperatures, the Ca concentration in the top layer is reduced to about 1 x 1014/cm3 or less.
FIG.3 is a schematic of an LED structure fabricated with a Ca impurity reduction structure comprised of a 15 period multilayer superlattice grown prior to the LED device layers. Specifically, the LED structure 300 is fabricated on a sapphire substrate 302 having an n-GaN template deposited thereon, and includes a 100 nm HT GaN buffer layer 304 grown at a higher temperature of about 820º, a Ca impurity reduction structure 306 that is a superlattice comprised of 15 periods of a 5 nm LT n-type GaN:Si layer 308 grown at a lower temperature of about 600°C, followed by a 20 nm HT n-type GaN:Si layer 310 grown at a higher temperature of about 820°C (with the layers 308, 310 repeated 15 times within the superlattice), a 100 nm HT n-type GaN:Si layer 312 grown at a higher temperature of about 820°C, a multiple quantum well (MQW) 314 comprised of 3 periods of 2.5 nm InGaN quantum wells (QWs) grown at a temperature of about 600°C and 5 nm GaN barriers grown at a temperature of about 820°C (with the quantum wells and barriers repeated 3 times within the MQW), a 100 nm p-type GaN:Mg layer 316 grown at a temperature of about 740°C, and a 5 nm p++-type GaN:Mg++ layer 318 grown at a temperature of about 740°C. Substrate temperatures (Tsub) during the MBE growth are also indicated to the right of the layers of the structure 300, as well as the use of an In surfactant for controlling morphology of the Ca impurity reduction structure 306.
The electroluminescence of the device of FIG.3 was brighter than that of a reference sample grown without the Ca impurity reduction structure 306, as shown in FIG.4. FIG.4 is a graph of EL data for two LED devices, with and without the Ca impurity reduction structure 306 shown in FIG.3, wherein the x-axis is wavelength (nanometers, nm), the y-axis is intensity (arbitrary units, au), and the lines are labeled as LED with Ca reduction and Reference LED. The LED with Ca reduction shows higher EL efficiency than the Reference LED with no Ca reduction. In addition, the output power of the LED with Ca reduction was 10 times higher at low (20 mA) current density than the Reference LED with no Ca reduction.
In an alternative embodiment, the Ca impurity reduction structure 306 comprises a single low temperature III-nitride layer deposited at a lower temperature, i.e., a thicker version of layer 308, but not layer 310. Preferably, the single low temperature III-nitride layer comprises at least 50 nm of an LT n-type GaN:Si layer 308 grown at a lower temperature of about 600°C. Process Flowchart
FIG.5 is a flowchart that illustrates the process for fabricating a III-nitride semiconductor heterostructure with a Ca impurity reduction structure using MBE, according to one embodiment.
Block 500 represents the step of providing a substrate, wherein the substrate is a sapphire substrate having a III-nitride template layer deposited thereon in one embodiment.
Block 502 represents the step of depositing a high temperature III-nitride layer on or above the substrate, wherein the high temperature III-nitride layer is a high temperature GaN buffer layer that is grown at a higher temperature of greater than about 700º.
Block 504 represents the step of creating a Ca impurity reduction structure on or above the high temperature III-nitride layer of step 502, wherein the Ca impurity reduction structure reduces unintentional Ca impurity incorporation in subsequent layers of the III-nitride semiconductor heterostructure to a concentration of about 1 x 1014/cm3 or less.
Block 506 represents the step of depositing a high temperature III-nitride layer on or above the Ca impurity reduction structure, wherein the high temperature III-nitride layer is an n-type GaN layer that is grown at a higher temperature of greater than about 700º.
The Ca impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature of about 550ºC to 700ºC, and is sandwiched between a plurality of high temperature III-nitride layers deposited at a higher temperature of greater than about 700ºC (i.e., the III-nitride layers deposited in Blocks 502 and 506), to reduce the Ca at a surface of the low temperature III-nitride layer by forcing the Ca’s incorporation into the low temperature III-nitride layer.
In one embodiment, the Ca impurity reduction structure comprises a single low temperature III-nitride layer deposited at a lower temperature, wherein the single low temperature III-nitride layer comprises at least 50 nm of an LT n-type GaN:Si layer grown at a lower temperature of about 550ºC to 700ºC.
In another embodiment, the Ca impurity reduction structure is a superlattice with alternating ones of the low temperature and high temperature III-nitride layers deposited at the lower and higher temperatures, respectively, wherein the low temperature III- nitride layer comprises an LT n-type GaN:Si layer grown at a lower temperature of about 550ºC to 700ºC, and the high temperature III-nitride layer comprises an HT n-type GaN:Si layer grown at a higher temperature of greater than about 700ºC.
Block 506 represents the step of depositing subsequent III-nitride layers of the semiconductor heterostructure on or above the Ca impurity reduction structure to form an optoelectronic device based on a p-n junction or a transistor. Advantages and Benefits
This invention could potentially improve the performance (for example, efficiency and output power) of semiconductor devices such as LEDs, lasers, and transistors. It could also enable the use of the MBE growth technique for prototype and commercial production of GaN based light emitting devices. References
The following publications are incorporated by reference herein:
[1] S. G. dos Santos Filho, C.M. Hasenack, L.C. Salay, and P. Mertens, J.
Electrochem. Soc.142, 902 (1995).
[2] L. Mouche, F. Tardif and J. Derrien, J. Electrochem. Soc.142, 2395 (1995). [3] A. J. Ptak, D. J. Friedman, S. Kurtz, R. C. Reedy, M. Young, D. B. Jackrel, H. B. Yuen, S. R. Bank, M. A. Wistey, and J. S. Harris, J. Vac. Sci. Tech.24, 1540 (2006).
[4] C. E. Dreyer, A. Alkauskas, J. L. Lyons, J. S. Speck, and C. G. Van de Walle, Appl. Phys. Lett.108, 141101 (2016). Conclusion
This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS: 1. A device, comprising:
a III-nitride semiconductor heterostructure with at least one Calcium impurity reduction structure, deposited on or above a substrate, that reduces unintentional Calcium impurity incorporation in subsequent layers of the III-nitride semiconductor
heterostructure to a concentration of about 1 x 1014/cm3 or less, wherein the Calcium impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature, and is sandwiched between a plurality of high temperature III-nitride layers deposited at a higher temperature, to reduce the Calcium at a surface of the low temperature III-nitride layer by forcing the Calcium’s incorporation into the low temperature III-nitride layer.
2. The device of claim 1, wherein the substrate comprises a sapphire substrate with a III-nitride template layer deposited thereon.
3. The device of claim 2, wherein a first one of the plurality of high temperature III-nitride layers is deposited on the sapphire substrate with the III-nitride template layer, and the Calcium impurity reduction structure is deposited on the first one of the plurality of high temperature III-nitride layers.
4. The device of claim 3, wherein a second one of the plurality of high temperature III-nitride layers is deposited on the Calcium impurity reduction structure, and the subsequent layers of the III-nitride semiconductor heterostructure are deposited on the second one of the plurality of high temperature III-nitride layers.
5. The device of claim 1, wherein the Calcium impurity reduction structure is a multilayer superlattice with alternating ones of the low temperature and high temperature III-nitride layers deposited at the lower and higher temperatures,
respectively.
6. The device of claim 1, wherein the low temperature III-nitride layer comprises a low temperature Gallium Nitride (GaN) layer grown at the lower temperature of about 550ºC to 700ºC.
7. The device of claim 1, wherein each of the plurality of high temperature III-nitride layers comprise a high temperature Gallium Nitride (GaN) layer grown at the higher temperature of greater than about 700ºC.
8. The device of claim 1, wherein the subsequent layers of the semiconductor heterostructure form an optoelectronic device based on a p-n junction or a transistor.
9. A method, comprising:
fabricating a III-nitride semiconductor heterostructure with at least one Calcium impurity reduction structure, deposited on or above a substrate, that reduces unintentional Calcium impurity incorporation in subsequent layers of the III-nitride semiconductor heterostructure to a concentration of about 1 x 1014/cm3 or less, wherein the Calcium impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature, and is sandwiched between a plurality of high temperature III-nitride layers deposited at a higher temperature, to reduce the Calcium at a surface of the low temperature III-nitride layer by forcing the Calcium’s incorporation into the low temperature III-nitride layer.
10. The method of claim 9, wherein the substrate comprises a sapphire substrate with a III-nitride template layer deposited thereon.
11. The method of claim 10, wherein a first one of the plurality of high temperature III-nitride layers is deposited on the sapphire substrate with the III-nitride template layer, and the Calcium impurity reduction structure is deposited on the first one of the plurality of high temperature III-nitride layers.
12. The method of claim 11, wherein a second one of the plurality of high temperature III-nitride layers is deposited on the Calcium impurity reduction structure, and the subsequent layers of the III-nitride semiconductor heterostructure are deposited on the second one of the plurality of high temperature III-nitride layers.
13. The method of claim 9, wherein the Calcium impurity reduction structure is a multilayer superlattice with alternating ones of the low temperature and high temperature III-nitride layers deposited at the lower and higher temperatures,
respectively.
14. The method of claim 9, wherein the low temperature III-nitride layer comprises a low temperature Gallium Nitride (GaN) layer grown at the lower temperature of about 550ºC to 700ºC.
15. The method of claim 9, wherein each of the plurality of high temperature III-nitride layers comprise a high temperature Gallium Nitride (GaN) layer grown at the higher temperature of greater than about 700ºC.
16. The method of claim 9, wherein the subsequent layers of the
semiconductor heterostructure form an optoelectronic device based on a p-n junction or a transistor.
17. A device, comprising:
a III-nitride semiconductor heterostructure with at least one Calcium impurity reduction structure, deposited on or above a substrate, that reduces unintentional Calcium impurity incorporation in subsequent layers of the III-nitride semiconductor
heterostructure to a concentration of about 1 x 1014/cm3 or less, wherein:
the Calcium impurity reduction structure is comprised of at least one low temperature III-nitride layer deposited at a lower temperature of about 550ºC to 700ºC; or the Calcium impurity reduction structure is comprised of multilayer superlattice with alternating low temperature and high temperature III-nitride layers deposited at the lower temperature and a higher temperature of greater than about 700ºC, respectively; and
the Calcium impurity reduction structure is sandwiched between a plurality of high temperature III-nitride layers deposited at the higher temperature.
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