WO2018035994A1 - 像素电路的驱动方法 - Google Patents

像素电路的驱动方法 Download PDF

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Publication number
WO2018035994A1
WO2018035994A1 PCT/CN2016/106035 CN2016106035W WO2018035994A1 WO 2018035994 A1 WO2018035994 A1 WO 2018035994A1 CN 2016106035 W CN2016106035 W CN 2016106035W WO 2018035994 A1 WO2018035994 A1 WO 2018035994A1
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WIPO (PCT)
Prior art keywords
mos transistor
data line
control signal
sub
pixel
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Ceased
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PCT/CN2016/106035
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English (en)
French (fr)
Inventor
易士娟
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/317,498 priority Critical patent/US10354588B2/en
Publication of WO2018035994A1 publication Critical patent/WO2018035994A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a method for driving a pixel circuit.
  • AMOLED Active-matrix organic light emitting diode
  • AMOLED has self-luminous properties, using a very thin coating of organic materials and a glass substrate. When an electric current passes, these organic materials emit light. . Since the AMOLED panel is driven by current, it is very sensitive to voltage changes, especially the threshold voltage Vth drift is likely to cause uneven display of the panel, so the AMOLED pixel compensation circuit is particularly important. The AMOLED pixel circuit can compensate for the drift of the threshold voltage and improve the uniformity of the display of the OLED panel.
  • LTPS low temperature poly-silicon
  • COF chip on film
  • the data signal of the AA area is not reset before the input of the Data signal, and the data signal of the AA area is maintained at the floating potential before the demux data is supplied, the scan signal When turned on, the floating potential is easily mischarged into the sub pixel pixel circuit, causing a risk of abnormal display.
  • Embodiments of the present invention provide a gate driving circuit capable of effectively preventing potential mischarging and generating a screen display abnormality.
  • the present invention provides a driving method of a pixel circuit, comprising: receiving a data line control signal input by a driving chip, and resetting a data line of the pixel unit according to the data line control signal, wherein the pixel unit includes three sub-ports of R, G, and B.
  • the pixel circuit comprises a first MOS transistor, the gate of the first MOS transistor is connected to the data line selection signal, and the drain receiving the input of the driving chip a data line control signal, the source is connected to the data line; receiving the data line control signal input by the driving chip, and resetting the data line of the pixel unit according to the data line control signal includes: the data line selection signal controls the first MOS tube to be turned on The data line control signal input by the driving chip is input to the data line through the first MOS transistor, and the data line is reset.
  • the step of charging the pixel unit to the target potential includes: sequentially charging three sub-pixels of R, G, and B to corresponding target potentials.
  • the pixel circuit includes three sub-pixel circuits of R, G, and B. Each sub-pixel circuit further includes a second MOS transistor, a third MOS transistor, and a first MOS transistor unit. The gate of the second MOS transistor is connected to the first scan signal.
  • the drain is connected to the drain of the third MOS transistor, the gate and the source of the third MOS transistor are connected to the first MOS transistor unit, and the first MOS transistor unit is further connected to the first scan signal, wherein the gate of the third MOS transistor
  • the potential is the potential of the sub-pixel; the step of charging the pixel unit to the target potential according to the data line control signal includes: sequentially controlling the second MOS transistor and the first MOS transistor unit for the R, G, and B sub-pixels
  • the data line selection signal controls the first MOS transistor to be turned on; the data line control signal input by the driving chip charges the sub-pixel to the target potential through the first MOS transistor and the second MOS transistor.
  • the first MOS transistor unit includes a fourth MOS transistor and a fifth MOS transistor, and the gates of the fourth MOS transistor and the fifth MOS transistor are connected to the first scan signal, and the drain of the fourth MOS transistor and the gate of the third MOS transistor a pole connection, a source is connected to a drain of the fifth MOS transistor, a source of the fifth MOS transistor is connected to a source of the third MOS transistor; and the step of controlling the first MOS transistor unit to be turned on by the first scan signal comprises: first The scan signal controls the fourth MOS transistor and the fifth MOS transistor to be simultaneously turned on.
  • the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are PMOS transistors.
  • the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are NMOS transistors.
  • Each sub-pixel circuit further includes a sixth MOS transistor and a seventh MOS transistor.
  • the gates of the sixth MOS transistor and the seventh MOS transistor are connected to the control signal, and the drain of the sixth MOS transistor is connected to the first reference voltage, and the source is The drain of the third MOS transistor is connected, the drain of the seventh MOS transistor is connected to the source of the third MOS transistor, the source is connected to the anode of the LED, the cathode of the LED is connected to the second reference voltage, and the control signal is controlled to receive the pixel.
  • the step of displaying the corresponding gray scale according to the target potential includes: the control signal controls the sixth MOS transistor and the seventh MOS transistor to be turned on, and the light emitting diode emits light according to the current formed by the target potential, and displays the corresponding gray scale.
  • each sub-pixel circuit further includes an eighth MOS transistor and a ninth MOS transistor, and the eighth MOS
  • the gate of the tube and the ninth MOS transistor are connected to the second scan signal
  • the drain of the eighth MOS transistor is connected to the gate of the third MOS transistor
  • the source of the eighth MOS is connected to the drain of the ninth MOS transistor
  • the ninth The source of the MOS transistor is connected to the reset signal; before the step of receiving the data line control signal input by the driving chip, the second scan signal controls the eighth MOS transistor and the ninth MOS transistor to be turned on, and the reset signal is transmitted to the gate of the third MOS transistor And reset.
  • the present invention also provides a driving method of a pixel circuit, comprising: receiving a data line control signal input by a driving chip, and resetting a data line of the pixel unit according to the data line control signal; charging the pixel unit to the target according to the data line control signal
  • the potential control unit controls the pixel unit to display the corresponding gray level according to the target potential.
  • the pixel unit includes three sub-pixels of R, G, and B.
  • the step of resetting the data line of the pixel unit includes: resetting three sub-pixels of R, G, and B according to the received data line control signal.
  • the step of charging the pixel unit to the target potential includes: sequentially charging three sub-pixels of R, G, and B to corresponding target potentials.
  • the pixel circuit includes a first MOS transistor, the gate of the first MOS transistor is connected to the data line selection signal, the drain receives the data line control signal input by the driving chip, the source is connected to the data line, and the data line control signal input by the driving chip is received. And resetting the data line of the pixel unit according to the data line control signal, the data line selection signal controls the first MOS transistor to be turned on, and the data line control signal input by the driving chip is input to the data line through the first MOS tube, and Reset the data line.
  • the pixel circuit includes three sub-pixel circuits of R, G, and B. Each sub-pixel circuit further includes a second MOS transistor, a third MOS transistor, and a first MOS transistor unit. The gate of the second MOS transistor is connected to the first scan signal.
  • the drain is connected to the drain of the third MOS transistor, the gate and the source of the third MOS transistor are connected to the first MOS transistor unit, and the first MOS transistor unit is further connected to the first scan signal, wherein the gate of the third MOS transistor
  • the potential is the potential of the sub-pixel; the step of charging the pixel unit to the target potential according to the data line control signal includes: sequentially controlling the second MOS transistor and the first MOS transistor unit for the R, G, and B sub-pixels
  • the data line selection signal controls the first MOS transistor to be turned on; the data line control signal input by the driving chip charges the sub-pixel to the target potential through the first MOS transistor and the second MOS transistor.
  • the first MOS transistor unit includes a fourth MOS transistor and a fifth MOS transistor, and the gates of the fourth MOS transistor and the fifth MOS transistor are connected to the first scan signal, and the drain of the fourth MOS transistor and the gate of the third MOS transistor a pole connection, a source is connected to a drain of the fifth MOS transistor, a source of the fifth MOS transistor is connected to a source of the third MOS transistor; and the step of controlling the first MOS transistor unit to be turned on by the first scan signal comprises: first The scan signal controls the fourth MOS transistor and the fifth MOS transistor to be simultaneously turned on.
  • the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are PMOS transistors.
  • the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are NMOS transistors.
  • Each sub-pixel circuit further includes a sixth MOS transistor and a seventh MOS transistor.
  • the gates of the sixth MOS transistor and the seventh MOS transistor are connected to the control signal, and the drain of the sixth MOS transistor is connected to the first reference voltage, and the source is The drain of the third MOS transistor is connected, the drain of the seventh MOS transistor is connected to the source of the third MOS transistor, the source is connected to the anode of the LED, the cathode of the LED is connected to the second reference voltage, and the control signal is controlled to receive the pixel.
  • the step of displaying the corresponding gray scale according to the target potential includes: the control signal controls the sixth MOS transistor and the seventh MOS transistor to be turned on, and the light emitting diode emits light according to the current formed by the target potential, and displays the corresponding gray scale.
  • Each sub-pixel circuit further includes an eighth MOS transistor and a ninth MOS transistor.
  • the gates of the eighth MOS transistor and the ninth MOS transistor are connected to the second scan signal, and the drain of the eighth MOS transistor and the gate of the third MOS transistor a pole connection, a source of the eighth MOS is connected to a drain of the ninth MOS transistor, and a source of the ninth MOS transistor is connected to the reset signal; before the step of receiving the data line control signal input by the driving chip, the second scan signal controls the eighth The MOS transistor and the ninth MOS transistor are turned on, and the reset signal is transmitted to the gate of the third MOS transistor and reset.
  • the present invention has the beneficial effects that the present invention receives the data line control signal input by the driving chip, and resets the data line of the pixel unit according to the data line control signal; and charges the pixel unit to the target according to the data line control signal.
  • the potential control unit controls the pixel unit to display the corresponding gray scale according to the target potential, thereby effectively preventing potential mischarge and generating a screen display abnormality.
  • FIG. 1 is a schematic flow chart of a pixel circuit driving method according to an embodiment of the present invention.
  • FIG. 2 is a structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 3 is a structural diagram of a sub-pixel circuit according to an embodiment of the present invention.
  • FIG. 4 is a timing chart of a pixel circuit of an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart of a pixel circuit driving method according to an embodiment of the present invention
  • FIG. 2 is a structural diagram of a pixel circuit according to an embodiment of the present invention
  • FIG. 3 is a structural diagram of a sub-pixel circuit according to an embodiment of the present invention.
  • the pixel circuit driving method includes:
  • Step S10 receiving a data line control signal input by the driving chip, and resetting the data line of the pixel unit according to the data line control signal.
  • the pixel unit includes three sub-pixels of R, G, and B.
  • step S10 three sub-pixels of R, G, and B are simultaneously reset according to the received data line control signal. Specifically, before the data line is charged to the pixel unit, the data line control signal input by the driving chip is received to reset the data line, thereby ensuring that the pixel unit can prevent the potential mis-charging at the next moment and generate a screen display abnormality.
  • Step S11 charging the pixel unit to the target potential according to the data line control signal.
  • step S11 three sub-pixels of R, G, and B are sequentially charged to corresponding target potentials.
  • the pixel units are arranged in a matrix and connected to the scan lines and the data lines.
  • the pixel circuit of each pixel unit includes three sub-pixel circuits of R, G, and B. Each sub-pixel circuit shares one scan line, and different sub-pixels correspond to different data lines.
  • the pixel circuit includes a first MOS transistor T1.
  • the gate of the first MOS transistor T1 is connected to the data line selection signal, the drain receives the data line control signal input from the driving chip, and the source is connected to the data line.
  • the data line selection signal controls the first MOS transistor T1 to be turned on
  • the data line control signal Data from IC input from the driving chip is input to the data line through the first MOS transistor T1, and the data line is reset.
  • the pixel circuit includes three sub-pixel circuits of R, G, and B. Taking the R sub-pixel circuit in one pixel unit as an example, each sub-pixel circuit 10 further includes a second MOS transistor T2 and a third MOS transistor T3.
  • the first MOS transistor unit 101 has a gate of the second MOS transistor connected to the first scan signal Scan(n), a drain connected to the drain of the third MOS transistor T3, and a gate and a source of the third MOS transistor T3.
  • a MOS transistor unit 101 is connected, and the first MOS transistor unit 101 is further connected to the first scan signal Scan(n), wherein the potential of the gate of the third MOS transistor T3 is the potential of the sub-pixel.
  • step S11 for the R, G, and B sub-pixels, the first scan signal Scan(n) controls the second MOS transistor T2 and the first MOS transistor unit 101 to be turned on, and the data line selection signal controls the first MOS transistor T1.
  • the data line control signal Data from IC of the driving chip inputs the sub-pixels to the target potential through the first MOS transistor T1 and the second MOS transistor T2.
  • the data line selection signal Mux R controls the first MOS transistor T1 corresponding to the R sub-pixel.
  • the data line control signal Data from IC that drives the chip input charges the R sub-pixel to the target potential through the first MOS transistor T1 and the second MOS transistor T2 in the R sub-pixel. Then, the data line selection signal Mux G controls the first MOS transistor T1 corresponding to the G sub-pixel to be turned on, and the data line control signal Data from IC input by the driving chip passes through the first MOS transistor T1 and the second MOS transistor T2 in the G sub-pixel. The G sub-pixel is charged to the target potential.
  • the last data line selection signal Mux B controls the first MOS transistor T1 corresponding to the B sub-pixel to be turned on, and the data line control signal Data from IC input by the driving chip passes through the first MOS transistor T1 and the second MOS transistor T2 in the B sub-pixel.
  • the B sub-pixel is charged to the target potential.
  • the target potential is the sum of the potential of the data line control signal Data from IC and the threshold voltage Vth of the third MOS transistor.
  • the first MOS transistor unit 101 includes a fourth MOS transistor T4 and a fifth MOS transistor T5, and the gates of the fourth MOS transistor T4 and the fifth MOS transistor T5 are connected to the first scan signal Scan(n).
  • the drain of the fourth MOS transistor T4 is connected to the gate of the third MOS transistor T3, the source is connected to the drain of the fifth MOS transistor T5, and the source of the fifth MOS transistor T5 is connected to the source of the third MOS transistor T3.
  • the first scan signal Scan(n) controls the first MOS transistor unit 101 to be turned on
  • the first scan signal Scan(n) needs to control the fourth MOS transistor T4 and the fifth MOS transistor T5 to be simultaneously turned on.
  • the first MOS transistor unit 101 may also include only one MOS transistor.
  • the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, the fourth MOS transistor T4, and the fifth MOS transistor T5 may be PMOS transistors.
  • the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, the fourth MOS transistor T4, and the fifth MOS transistor T5 may be NMOS transistors.
  • Step S12 The receiving control signal controls the pixel unit to display the corresponding gray scale according to the target potential.
  • each sub-pixel circuit further includes a sixth MOS transistor T6 and a seventh MOS transistor T7.
  • the gates of the sixth MOS transistor T6 and the seventh MOS transistor T7 are connected to the control signal EM, and the sixth MOS transistor T6
  • the drain is connected to the first reference voltage VDD
  • the source is connected to the drain of the third MOS transistor T3
  • the drain of the seventh MOS transistor T7 is connected to the source of the third MOS transistor T3
  • the source is connected to the anode of the LED OLED.
  • the cathode of the LED OLED is connected to the second reference voltage.
  • step S12 the control signal EM controls the sixth MOS transistor T6 and the seventh MOS transistor T7 to be turned on, and the light emitting diode OLED emits light according to the current formed by the target potential, and displays the corresponding gray scale.
  • each sub-pixel circuit 10 further includes an eighth MOS transistor T8 and a ninth MOS transistor T9.
  • the gates of the eighth MOS transistor T8 and the ninth MOS transistor T9 are connected to the second scan signal Scan(n+1).
  • the drain of the eighth MOS transistor T8 is connected to the gate of the third MOS transistor T3, the source of the eighth MOS transistor T8 is connected to the drain of the ninth MOS transistor T9, and the source of the ninth MOS transistor T9 is reset.
  • Signal VI Correspondingly, before step S10, the second scan signal Scan(n+1) controls the eighth MOS transistor T8 and the ninth MOS transistor T9 to be turned on, and the reset signal VI is transmitted to the gate of the third MOS transistor T3 and reset.
  • FIG. 4 is a timing chart of a pixel circuit of an embodiment of the present invention.
  • the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor T8, and the seventh MOS transistor T9 may be PMOS transistors.
  • the data line control signal data from IC When the data line selection signals Mux R, Mux G, and Mux B are simultaneously turned on, the data line control signal data from IC resets the data lines Data-R, Data-G, and Data-B corresponding to the three sub-pixels R, G, and B. Is the reset signal VI. Then, the first scan signal scan(n) signal becomes a low level, and when the data line selection signal Mux R is at a low level, the data line control signal Data from IC performs a data line Data-R corresponding to the R sub-pixel of the nth row.
  • the potential of the gate Red(n)G of the third MOS transistor T3 in the R sub-pixel becomes V Data-R + Vth; then, the data line selection signal Mux G becomes a low level, and the data line control signal Data from The IC charges the data line Data-G corresponding to the G sub-pixel of the nth row, and the potential of the gate Green(n)G of the third MOS transistor T3 in the G sub-pixel becomes V Data-G +Vth; then, the data The line selection signal Mux B becomes a low level, the data line control signal Data from IC charges the data line Data-B corresponding to the B sub-pixel of the nth row, and the gate blue of the third MOS transistor T3 in the B sub-pixel ( n) The potential of G becomes V Data-B + Vth, thus completing the charging of the R, G, and B sub-pixels in the nth row, and charging the R, G, and B sub-pixels to the target potential.
  • the data line selection signals Mux R, Mux G, and Mux B are simultaneously turned on, and the data line control signal data from IC sets the data lines corresponding to the three sub-pixels R, G, and B. R, Data-G, and Data-B are reset to the reset signal VI. Thereafter, the control signal EM controls the sixth MOS transistor T6 and the seventh MOS transistor T7 to be turned on, and the light emitting diode OLED emits light according to the current formed by the target potential, and displays the corresponding gray scale.
  • the data lines Data-R, Data-G, and Data-B corresponding to the three sub-pixels of R, G, and B have a high floating-point potential V floating , and if the next period directly pairs, three sub-pixels of R, G, and B are directly performed.
  • the corresponding data lines Data-R, Data-G, and Data-B are charged. If the potential V Data-G of the data line Data-G needs to be charged is less than V floating , the charging will not be possible, and the data line Data-G remains.
  • the floating point potential V floating so that the period G sub-pixel does not reach the target potential V Data-G + Vth, is maintained at the charging potential V floating + Vth.
  • the smaller the V Data-G the higher the gray scale, and the more obvious the phenomenon.
  • the data line selection signal Mux R also becomes a low level, and the data line control signal Data from IC is given to the n+1th.
  • the data line Data-R corresponding to the R sub-pixel of the row is charged, and the potential of the gate Red(n)G of the third MOS transistor T3 in the R sub-pixel of the n+1th row becomes V Data-R + Vth.
  • the data line Data-G corresponding to the G sub-pixel and the data line Data-B corresponding to the B sub-pixel are reset signal VI, which is a very low level, and there will be no third MOS transistor T3 in the G sub-pixel.
  • the gate Green(n+1)G or the B sub-pixel has a case where the gate Blue(n+1)G of the third MOS transistor T3 is mischarged to the potential V floating +Vth.
  • each sub-pixel can be normally charged to the target potential, and it is possible to effectively prevent potential mischarge and cause a screen display abnormality, and the screen display quality is greatly improved.
  • the dotted line portion in FIG. 4 is the floating point potential V floating , and the specific value thereof is uncertain, and is related to the gray scale displayed by the corresponding sub-pixel in the previous period.
  • the present invention receives the data line control signal input by the driving chip, and resets the data line of the pixel unit according to the data line control signal; charges the pixel unit to the target potential according to the data line control signal; and receives the control signal control
  • the pixel unit displays the corresponding gray scale according to the target potential, and can effectively prevent the potential mischarge and cause a screen display abnormality.

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Abstract

一种像素电路的驱动方法，包括：接收驱动芯片输入的数据线控制信号，并根据数据线控制信号对像素单元的数据线进行复位（S10）；根据数据线控制信号向像素单元充电至目标电位（S11）；接收控制信号（EM）控制像素单元根据目标电位显示对应的灰阶（S12）。通过以上方式能够有效的防止电位错充而产生画面显示异常。

Description

像素电路的驱动方法 【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种像素电路的驱动方法。
【背景技术】
有源矩阵有机发光二极体面板(Active-matrix organic light emitting diode，AMOLED)具有自发光的特性，采用非常薄的有机材料涂层和玻璃基板，当有电流通过时，这些有机材料就会发光。由于AMOLED面板是电流驱动，对电压的变化非常敏感，特别是阈值电压Vth漂移容易造成面板显示不均，因此AMOLED像素补偿电路显得尤为重要。AMOLED像素电路可以补偿阈值电压的漂移，提高OLED面板显示的均匀性。
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，而且由于LTPS半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到系统面板(System on Panel，SOP)的相关技术研究，并逐步成为现实。。在面板设计中，为降低驱动芯片(IC)与覆晶薄膜(Chip On Film，COF)成本，通常采用的demux电路设计。
在一般的OLED中，数据线Data通过demux电路进行信号输入的时序图设计中，在Data信号输入前不对AA区data信号进行复位，AA区data信号在demux data给电前保持floating电位，scan信号打开时，该floating电位容易错充入sub pixel像素电路中，产生画面显示异常的风险。
【发明内容】
本发明实施例提供了一种栅极驱动电路，能够有效的防止电位错充而产生画面显示异常。
本发明提供一种像素电路的驱动方法，包括：接收驱动芯片输入的数据线控制信号，并根据数据线控制信号对像素单元的数据线进行复位，其中，像素单元包括R、G、B三个子像素，根据接收的数据线控制信号同时对R、G、B三个子像素进行复位；根据数据线控制信号向像素单元充电至目标电位；接收控制信号控制像素单元根据目标电位显示对应的灰阶；其中，像素电路包括第一MOS管，第一MOS管的栅极接数据线选择信号，漏极接收驱动芯片输入的 数据线控制信号，源极接数据线；接收驱动芯片输入的数据线控制信号，并根据数据线控制信号对像素单元的数据线进行复位的步骤包括：数据线选择信号控制第一MOS管导通，驱动芯片输入的数据线控制信号通过第一MOS管输入至数据线，并对数据线进行复位。
其中，向像素单元充电至目标电位的步骤包括：依次分别向R、G、B三个子像素充电至对应的目标电位。
其中，像素电路包括R、G、B三个子像素电路，每个子像素电路还包括第二MOS管、第三MOS管以及第一MOS管单元，第二MOS管的栅极接第一扫描信号，漏极与第三MOS管的漏极连接，第三MOS管的栅极和源极与第一MOS管单元连接，第一MOS管单元还接第一扫描信号，其中第三MOS管的栅极的电位为子像素的电位；根据数据线控制信号向像素单元充电至目标电位的步骤包括：依次针对R、G、B子像素，第一扫描信号控制第二MOS管和第一MOS管单元导通，数据线选择信号控制第一MOS管导通；驱动芯片输入的数据线控制信号通过第一MOS管和第二MOS管对子像素进行充电至目标电位。
其中，第一MOS管单元包括第四MOS管和第五MOS管，第四MOS管和第五MOS管的栅极接第一扫描信号，第四MOS管的漏极与第三MOS管的栅极连接，源极与第五MOS管的漏极连接，第五MOS管的源极与第三MOS管的源极连接；第一扫描信号控制第一MOS管单元导通的步骤包括：第一扫描信号控制第四MOS管和第五MOS管同时导通。
其中，第一MOS管、第二MOS管、第三MOS管、第四MOS管以及第五MOS管为PMOS管。
其中，第一MOS管、第二MOS管、第三MOS管、第四MOS管以及第五MOS管为NMOS管。
其中，每个子像素电路还包括第六MOS管以及第七MOS管，第六MOS管和第七MOS管的栅极接控制信号，第六MOS管的漏极接第一参考电压，源极与第三MOS管的漏极连接，第七MOS管的漏极与第三MOS管的源极连接，源极与发光二极管的正极连接，发光二极管的负极接第二参考电压；接收控制信号控制像素单元根据目标电位显示对应的灰阶的步骤包括：控制信号控制第六MOS管和第七MOS管导通，发光二极管根据目标电位形成的电流发光，显示对应的灰阶。
其中，每个子像素电路还包括第八MOS管以及第九MOS管，第八MOS 管和第九MOS管的栅极接第二扫描信号，第八MOS管的漏极与第三MOS管的栅极连接，第八MOS的源极与第九MOS管的漏极连接，第九MOS管的源极接复位信号；接收驱动芯片输入的数据线控制信号的步骤之前，第二扫描信号控制第八MOS管和第九MOS管导通，复位信号传输至第三MOS管的栅极并进行复位。
本发明还提供一种像素电路的驱动方法，包括：接收驱动芯片输入的数据线控制信号，并根据数据线控制信号对像素单元的数据线进行复位；根据数据线控制信号向像素单元充电至目标电位；接收控制信号控制像素单元根据目标电位显示对应的灰阶。
其中，像素单元包括R、G、B三个子像素，对像素单元的数据线进行复位的步骤包括：根据接收的数据线控制信号同时对R、G、B三个子像素进行复位。
其中，向像素单元充电至目标电位的步骤包括：依次分别向R、G、B三个子像素充电至对应的目标电位。
其中，像素电路包括第一MOS管，第一MOS管的栅极接数据线选择信号，漏极接收驱动芯片输入的数据线控制信号，源极接数据线；接收驱动芯片输入的数据线控制信号，并根据数据线控制信号对像素单元的数据线进行复位的步骤包括：数据线选择信号控制第一MOS管导通，驱动芯片输入的数据线控制信号通过第一MOS管输入至数据线，并对数据线进行复位。
其中，像素电路包括R、G、B三个子像素电路，每个子像素电路还包括第二MOS管、第三MOS管以及第一MOS管单元，第二MOS管的栅极接第一扫描信号，漏极与第三MOS管的漏极连接，第三MOS管的栅极和源极与第一MOS管单元连接，第一MOS管单元还接第一扫描信号，其中第三MOS管的栅极的电位为子像素的电位；根据数据线控制信号向像素单元充电至目标电位的步骤包括：依次针对R、G、B子像素，第一扫描信号控制第二MOS管和第一MOS管单元导通，数据线选择信号控制第一MOS管导通；驱动芯片输入的数据线控制信号通过第一MOS管和第二MOS管对子像素进行充电至目标电位。
其中，第一MOS管单元包括第四MOS管和第五MOS管，第四MOS管和第五MOS管的栅极接第一扫描信号，第四MOS管的漏极与第三MOS管的栅极连接，源极与第五MOS管的漏极连接，第五MOS管的源极与第三MOS管的源极连接；第一扫描信号控制第一MOS管单元导通的步骤包括：第一扫描信号控制第四MOS管和第五MOS管同时导通。
其中，第一MOS管、第二MOS管、第三MOS管、第四MOS管以及第五MOS管为PMOS管。
其中，第一MOS管、第二MOS管、第三MOS管、第四MOS管以及第五MOS管为NMOS管。
其中，每个子像素电路还包括第六MOS管以及第七MOS管，第六MOS管和第七MOS管的栅极接控制信号，第六MOS管的漏极接第一参考电压，源极与第三MOS管的漏极连接，第七MOS管的漏极与第三MOS管的源极连接，源极与发光二极管的正极连接，发光二极管的负极接第二参考电压；接收控制信号控制像素单元根据目标电位显示对应的灰阶的步骤包括：控制信号控制第六MOS管和第七MOS管导通，发光二极管根据目标电位形成的电流发光，显示对应的灰阶。
其中，每个子像素电路还包括第八MOS管以及第九MOS管，第八MOS管和第九MOS管的栅极接第二扫描信号，第八MOS管的漏极与第三MOS管的栅极连接，第八MOS的源极与第九MOS管的漏极连接，第九MOS管的源极接复位信号；接收驱动芯片输入的数据线控制信号的步骤之前，第二扫描信号控制第八MOS管和第九MOS管导通，复位信号传输至第三MOS管的栅极并进行复位。
通过上述方案，本发明的有益效果是：本发明通过接收驱动芯片输入的数据线控制信号，并根据数据线控制信号对像素单元的数据线进行复位；根据数据线控制信号向像素单元充电至目标电位；接收控制信号控制像素单元根据目标电位显示对应的灰阶，能够有效的防止电位错充而产生画面显示异常。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明实施例的像素电路驱动方法的流程示意图；
图2是本发明实施例的像素电路的结构图；
图3是本发明实施例的子像素电路的结构图；
图4是本发明实施例的像素电路的时序图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图1-3，图1是本发明实施例的像素电路驱动方法的流程示意图，图2是本发明实施例的像素电路的结构图，图3是本发明实施例的子像素电路的结构图。像素电路驱动方法包括：
步骤S10：接收驱动芯片输入的数据线控制信号，并根据数据线控制信号对像素单元的数据线进行复位。
在本发明实施例中，像素单元包括R、G、B三个子像素。对应地，在步骤S10中，根据接收的数据线控制信号同时对R、G、B三个子像素进行复位。具体地，数据线在向像素单元充电之前，接收驱动芯片输入的数据线控制信号，使数据线复位，从而保证了在像素单元在下一时刻能够防止电位错充而产生画面显示异常。
步骤S11：根据数据线控制信号向像素单元充电至目标电位。
在步骤S11中，依次分别向R、G、B三个子像素充电至对应的目标电位。参见图2，在本发明实施例中，像素单元成矩阵排列，与扫描线和数据线连接。每个像素单元的像素电路包括R、G、B三个子像素电路，每个子像素电路共用一条扫描线，不同的子像素对应不同的数据线。像素电路包括第一MOS管T1，第一MOS管T1的栅极接数据线选择信号，漏极接收驱动芯片输入的数据线控制信号Data from IC，源极接数据线。数据线选择信号控制第一MOS管T1导通时，驱动芯片输入的数据线控制信号Data from IC通过第一MOS管T1输入至数据线，并对数据线进行复位。
进一步参见图2，像素电路包括R、G、B三个子像素电路，以一像素单元中的R子像素电路为例，每个子像素电路10还包括第二MOS管T2、第三MOS管T3以及第一MOS管单元101，第二MOS管的栅极接第一扫描信号Scan(n)，漏极与第三MOS管T3的漏极连接，第三MOS管T3的栅极和源极与第一MOS管单元101连接，第一MOS管单元101还接第一扫描信号Scan(n)，其中第三MOS管T3的栅极的电位为子像素的电位。
在步骤S11中，依次针对R、G、B子像素，第一扫描信号Scan(n)控制第二MOS管T2和第一MOS管单元101导通，数据线选择信号控制第一MOS管T1导通；驱动芯片输入的数据线控制信号Data from IC通过第一MOS管T1和第二MOS管T2对子像素进行充电至目标电位。具体地，在第一扫描信号Scan(n)控制R、G、B子像素中的第二MOS管T2导通时，首先数据线选择信号Mux R控制R子像素对应的第一MOS管T1导通，驱动芯片输入的数据线控制信号Data from IC通过R子像素中的第一MOS管T1和第二MOS管T2对R子像素进行充电至目标电位。然后数据线选择信号Mux G控制G子像素对应的第一MOS管T1导通，驱动芯片输入的数据线控制信号Data from IC通过G子像素中的第一MOS管T1和第二MOS管T2对G子像素进行充电至目标电位。最后数据线选择信号Mux B控制B子像素对应的第一MOS管T1导通，驱动芯片输入的数据线控制信号Data from IC通过B子像素中的第一MOS管T1和第二MOS管T2对B子像素进行充电至目标电位。其中，目标电位为数据线控制信号Data from IC的电位与与第三MOS管的阈值电压Vth之和。
在本发明实施例中，第一MOS管单元101包括第四MOS管T4和第五MOS管T5，第四MOS管T4和第五MOS管T5的栅极接第一扫描信号Scan(n)，第四MOS管T4的漏极与第三MOS管T3的栅极连接，源极与第五MOS管T5的漏极连接，第五MOS管T5的源极与第三MOS管T3的源极连接。第一扫描信号Scan(n)控制第一MOS管单元101导通时，第一扫描信号Scan(n)需要控制第四MOS管T4和第五MOS管T5同时导通。当然在本发明的其他实施例中，第一MOS管单元101也可以只包括一个MOS管即可。
另外，在本发明实施例中，第一MOS管T1、第二MOS管T2、第三MOS管T3、第四MOS管T4以及第五MOS管T5可以为PMOS管。第一MOS管T1、第二MOS管T2、第三MOS管T3、第四MOS管T4以及第五MOS管T5也可以为NMOS管。
步骤S12：接收控制信号控制像素单元根据目标电位显示对应的灰阶。
在本发明实施例中，每个子像素电路还包括第六MOS管T6以及第七MOS管T7，第六MOS管T6和第七MOS管T7的栅极接控制信号EM，第六MOS管T6的漏极接第一参考电压VDD，源极与第三MOS管T3的漏极连接，第七MOS管T7的漏极与第三MOS管T3的源极连接，源极与发光二极管OLED的正极连接，发光二极管OLED的负极接第二参考电压。
在步骤S12中，控制信号EM控制第六MOS管T6和第七MOS管T7导通，发光二极管OLED根据目标电位形成的电流发光，显示对应的灰阶。
在本发明实施例中，每个子像素电路10还包括第八MOS管T8以及第九MOS管T9，第八MOS管T8和第九MOS管T9的栅极接第二扫描信号Scan(n+1)，第八MOS管T8的漏极与第三MOS管T3的栅极连接，第八MOS管T8的源极与第九MOS管T9的漏极连接，第九MOS管T9的源极接复位信号VI。对应地，在步骤S10之前，第二扫描信号Scan(n+1)控制第八MOS管T8和第九MOS管T9导通，复位信号VI传输至第三MOS管T3的栅极并进行复位。
图4是本发明实施例的像素电路的时序图。对应的像素电路参见图2-3，其中，第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管、第六MOS管T8、第七MOS管T9、第八MOS管T10以及第九MOS管T11可以为PMOS管。
如图4所示，该时序的工作过程如下：
先将数据线选择信号Mux R、Mux G、Mux B同时打开时，数据线控制信号data from IC将R、G、B三个子像素对应的数据线Data-R、Data-G、Data-B复位为复位信号VI。然后第一扫描信号scan(n)信号变为低电平，数据线选择信号Mux R为低电平时，数据线控制信号Data from IC给第n行的R子像素对应的数据线Data-R进行充电，R子像素中第三MOS管T3的栅极Red(n)G的电位变为VData-R+Vth；然后，数据线选择信号Mux G变为低电平，数据线控制信号Data from IC给第n行的G子像素对应的数据线Data-G进行充电，G子像素中第三MOS管T3的栅极Green(n)G的电位变为VData-G+Vth；然后，数据线选择信号Mux B变为低电平，数据线控制信号Data from IC给第n行的B子像素对应的数据线Data-B进行充电，B子像素中第三MOS管T3的栅极Blue(n)G的电位变为VData-B+Vth，如此完成了第n行R、G、B子像素的充电，将R、G、B子像素都充电到了目标电位。在接下来给n+1行充电前，又将数据线选择信号Mux R、Mux G、Mux B同时打开，数据线控制信号data from IC将R、G、B三个子像素对应的数据线Data-R、Data-G、Data-B复位为复位信号VI。之后，控制信号EM控制第六MOS管T6和第七MOS管T7导通，发光二极管OLED根据目标电位形成的电流发光，显示对应的灰阶。
此时，R、G、B三个子像素对应的数据线Data-R、Data-G、Data-B存在浮点电位Vfloating较高，如果下一周期直接对进行R、G、B三个子像素对应的数据 线Data-R、Data-G、Data-B进行充电，若数据线Data-G需要充电的电位VData-G小于Vfloating，则会导致无法充电，数据线Data-G仍维持在浮点电位Vfloating，进而使得该周期G子像素达不到目标电位VData-G+Vth，而维持在充电电位Vfloating+Vth。VData-G越小，灰阶越高，该现象越明显。
因此，在本发明实施例中，当scan(n+1)信号变为低电平的同时，数据线选择信号Mux R也变为低电平，数据线控制信号Data from IC给第n+1行的R子像素对应的数据线Data-R进行充电，第n+1行的R子像素中第三MOS管T3的栅极Red(n)G的电位变为VData-R+Vth。此时G子像素对应的数据线Data-G、B子像素对应的数据线Data-B都为复位信号VI，是很低的电平，将不会有G子像素中第三MOS管T3的栅极Green(n+1)G或者B子像素中第三MOS管T3的栅极Blue(n+1)G错充为电位Vfloating+Vth的情况。如此，在本时序中，每个子像素都能正常地充电到目标电位，能够有效的防止电位错充而产生画面显示异常，画面显示质量大幅提高。
其中，图4中虚线部分为浮点电位Vfloating，其具体值不确定，与前一周期对应子像素显示的灰阶相关。
综上所述，本发明通过接收驱动芯片输入的数据线控制信号，并根据数据线控制信号对像素单元的数据线进行复位；根据数据线控制信号向像素单元充电至目标电位；接收控制信号控制像素单元根据目标电位显示对应的灰阶，能够有效的防止电位错充而产生画面显示异常。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种像素电路的驱动方法，其中，所述驱动方法包括：
    接收驱动芯片输入的数据线控制信号，并根据所述数据线控制信号对像素单元的数据线进行复位，其中，所述像素单元包括R、G、B三个子像素，根据接收的所述数据线控制信号同时对所述R、G、B三个子像素进行复位；
    根据所述数据线控制信号向所述像素单元充电至目标电位；
    接收控制信号控制所述像素单元根据所述目标电位显示对应的灰阶；
    其中，所述像素电路包括第一MOS管，所述第一MOS管的栅极接数据线选择信号，漏极接收所述驱动芯片输入的数据线控制信号，源极接所述数据线；所述接收驱动芯片输入的数据线控制信号，并根据所述数据线控制信号对像素单元的数据线进行复位的步骤包括：所述数据线选择信号控制所述第一MOS管导通，所述驱动芯片输入的数据线控制信号通过所述第一MOS管输入至所述数据线，并对所述数据线进行复位。
  2. 根据权利要求1所述的驱动方法，其中，所述向所述像素单元充电至目标电位的步骤包括：依次分别向所述R、G、B三个子像素充电至对应的目标电位。
  3. 根据权利要求1所述的驱动方法，其中，所述像素电路包括R、G、B三个子像素电路，每个所述子像素电路还包括第二MOS管、第三MOS管以及第一MOS管单元，所述第二MOS管的栅极接第一扫描信号，漏极与所述第三MOS管的漏极连接，所述第三MOS管的栅极和源极与所述第一MOS管单元连接，所述第一MOS管单元还接所述第一扫描信号，其中所述第三MOS管的栅极的电位为所述子像素的电位；
    所述根据所述数据线控制信号向所述像素单元充电至目标电位的步骤包括：依次针对所述R、G、B子像素，
    所述第一扫描信号控制所述第二MOS管和所述第一MOS管单元导通，所述数据线选择信号控制所述第一MOS管导通；
    所述驱动芯片输入的数据线控制信号通过所述第一MOS管和所述第二MOS管对所述子像素进行充电至目标电位。
  4. 根据权利要求3所述的驱动方法，其中，所述第一MOS管单元包括第四 MOS管和第五MOS管，所述第四MOS管和所述第五MOS管的栅极接所述第一扫描信号，所述第四MOS管的漏极与所述第三MOS管的栅极连接，源极与所述第五MOS管的漏极连接，所述第五MOS管的源极与所述第三MOS管的源极连接；
    所述第一扫描信号控制所述第一MOS管单元导通的步骤包括：所述第一扫描信号控制所述第四MOS管和所述第五MOS管同时导通。
  5. 根据权利要求4所述的驱动方法，其中，所述第一MOS管、所述第二MOS管、所述第三MOS管、第四MOS管以及第五MOS管为PMOS管。
  6. 根据权利要求4所述的驱动方法，其中，所述第一MOS管、所述第二MOS管、所述第三MOS管、第四MOS管以及第五MOS管为NMOS管。
  7. 根据权利要求4所述的驱动方法，其中，每个子像素电路还包括第六MOS管以及第七MOS管，所述第六MOS管和所述第七MOS管的栅极接所述控制信号，所述第六MOS管的漏极接第一参考电压，源极与所述第三MOS管的漏极连接，所述第七MOS管的漏极与所述第三MOS管的源极连接，源极与发光二极管的正极连接，所述发光二极管的负极接第二参考电压；
    所述接收控制信号控制所述像素单元根据所述目标电位显示对应的灰阶的步骤包括：所述控制信号控制所述第六MOS管和第七MOS管导通，所述发光二极管根据所述目标电位形成的电流发光，显示对应的灰阶。
  8. 根据权利要求4所述的驱动方法，其中，每个子像素电路还包括第八MOS管以及第九MOS管，所述第八MOS管和所述第九MOS管的栅极接第二扫描信号，所述第八MOS管的漏极与所述第三MOS管的栅极连接，所述第八MOS管的源极与所述第九MOS管的漏极连接，所述第九MOS管的源极接复位信号；
    所述接收驱动芯片输入的数据线控制信号的步骤之前，所述第二扫描信号控制所述第八MOS管和所述第九MOS管导通，所述复位信号传输至所述第三MOS管的栅极并进行复位。
  9. 一种像素电路的驱动方法，其中，所述驱动方法包括：
    接收驱动芯片输入的数据线控制信号，并根据所述数据线控制信号对像素单元的数据线进行复位；
    根据所述数据线控制信号向所述像素单元充电至目标电位；
    接收控制信号控制所述像素单元根据所述目标电位显示对应的灰阶。
  10. 根据权利要求9所述的驱动方法，其中，所述像素单元包括R、G、B 三个子像素，所述对像素单元的数据线进行复位的步骤包括：根据接收的所述数据线控制信号同时对所述R、G、B三个子像素进行复位。
  11. 根据权利要求10所述的驱动方法，其中，所述向所述像素单元充电至目标电位的步骤包括：依次分别向所述R、G、B三个子像素充电至对应的目标电位。
  12. 根据权利要求9所述的驱动方法，其中，所述像素电路包括第一MOS管，所述第一MOS管的栅极接数据线选择信号，漏极接收所述驱动芯片输入的数据线控制信号，源极接所述数据线；
    所述接收驱动芯片输入的数据线控制信号，并根据所述数据线控制信号对像素单元的数据线进行复位的步骤包括：所述数据线选择信号控制所述第一MOS管导通，所述驱动芯片输入的数据线控制信号通过所述第一MOS管输入至所述数据线，并对所述数据线进行复位。
  13. 根据权利要求12所述的驱动方法，其中，所述像素电路包括R、G、B三个子像素电路，每个所述子像素电路还包括第二MOS管、第三MOS管以及第一MOS管单元，所述第二MOS管的栅极接第一扫描信号，漏极与所述第三MOS管的漏极连接，所述第三MOS管的栅极和源极与所述第一MOS管单元连接，所述第一MOS管单元还接所述第一扫描信号，其中所述第三MOS管的栅极的电位为所述子像素的电位；
    所述根据所述数据线控制信号向所述像素单元充电至目标电位的步骤包括：依次针对所述R、G、B子像素，
    所述第一扫描信号控制所述第二MOS管和所述第一MOS管单元导通，所述数据线选择信号控制所述第一MOS管导通；
    所述驱动芯片输入的数据线控制信号通过所述第一MOS管和所述第二MOS管对所述子像素进行充电至目标电位。
  14. 根据权利要求13所述的驱动方法，其中，所述第一MOS管单元包括第四MOS管和第五MOS管，所述第四MOS管和所述第五MOS管的栅极接所述第一扫描信号，所述第四MOS管的漏极与所述第三MOS管的栅极连接，源极与所述第五MOS管的漏极连接，所述第五MOS管的源极与所述第三MOS管的源极连接；
    所述第一扫描信号控制所述第一MOS管单元导通的步骤包括：所述第一扫描信号控制所述第四MOS管和所述第五MOS管同时导通。
  15. 根据权利要求14所述的驱动方法，其中，所述第一MOS管、所述第二MOS管、所述第三MOS管、第四MOS管以及第五MOS管为PMOS管。
  16. 根据权利要求14所述的驱动方法，其中，所述第一MOS管、所述第二MOS管、所述第三MOS管、第四MOS管以及第五MOS管为NMOS管。
  17. 根据权利要求14所述的驱动方法，其中，每个子像素电路还包括第六MOS管以及第七MOS管，所述第六MOS管和所述第七MOS管的栅极接所述控制信号，所述第六MOS管的漏极接第一参考电压，源极与所述第三MOS管的漏极连接，所述第七MOS管的漏极与所述第三MOS管的源极连接，源极与发光二极管的正极连接，所述发光二极管的负极接第二参考电压；
    所述接收控制信号控制所述像素单元根据所述目标电位显示对应的灰阶的步骤包括：所述控制信号控制所述第六MOS管和第七MOS管导通，所述发光二极管根据所述目标电位形成的电流发光，显示对应的灰阶。
  18. 根据权利要求14所述的驱动方法，其中，每个子像素电路还包括第八MOS管以及第九MOS管，所述第八MOS管和所述第九MOS管的栅极接第二扫描信号，所述第八MOS管的漏极与所述第三MOS管的栅极连接，所述第八MOS管的源极与所述第九MOS管的漏极连接，所述第九MOS管的源极接复位信号；
    所述接收驱动芯片输入的数据线控制信号的步骤之前，所述第二扫描信号控制所述第八MOS管和所述第九MOS管导通，所述复位信号传输至所述第三MOS管的栅极并进行复位。
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