WO2018034065A1 - Light-emitting element and manufacturing method for light-emitting element - Google Patents

Light-emitting element and manufacturing method for light-emitting element Download PDF

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Publication number
WO2018034065A1
WO2018034065A1 PCT/JP2017/023656 JP2017023656W WO2018034065A1 WO 2018034065 A1 WO2018034065 A1 WO 2018034065A1 JP 2017023656 W JP2017023656 W JP 2017023656W WO 2018034065 A1 WO2018034065 A1 WO 2018034065A1
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Prior art keywords
layer
emitting element
light emitting
light
substrate
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PCT/JP2017/023656
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French (fr)
Japanese (ja)
Inventor
石崎　順也
翔吾 古屋
鈴木　金吾
池田　淳
鈴木　謙一
山田　雅人
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信越半導体株式会社
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Priority to CN201780045605.4A priority Critical patent/CN109643744B/en
Publication of WO2018034065A1 publication Critical patent/WO2018034065A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the present invention relates to a light emitting device made of a compound semiconductor and a method for manufacturing the same.
  • a light emitting element (LED) made of a compound semiconductor such as AlGaInP is formed with a SiO 2 protective film in order to prevent deterioration or leakage due to humidity or non-adherence of foreign matters during the process (see, for example, Patent Document 1).
  • the SiO 2 film used for protecting the side surface of the light emitting layer is preferably formed of a material and a reaction system having high shape following characteristics, and is formed by plasma CVD using TEOS and oxygen.
  • the side surface of the light emitting layer can be satisfactorily covered and the function as a protective film can be sufficiently achieved.
  • the roughened surface is uniformly covered as the light extraction surface, and therefore, there is an effect that the unevenness (R z ) is reduced.
  • the unevenness of the SiO 2 film surface By reducing the unevenness of the SiO 2 film surface, the anchor effect when the resin is coated is reduced, the resin adhesion is reduced, and the resin is peeled off in a high-humidity environment when resin sealing is performed. There was a problem that occurred.
  • the present invention has been made in view of the above-mentioned problems, and is capable of suppressing the occurrence of resin peeling in a high-humidity environment when resin sealing is performed without reducing resin adhesion. And it aims at providing the manufacturing method of a light emitting element.
  • the present invention is a light emitting device having a light emitting portion made of a compound semiconductor, an electrode, and a protective film, and on the surface of the protective film covering at least a part of the light emitting device, Provided is a light-emitting element in which irregularities having Rz exceeding 5 nm are formed.
  • the protective film is preferably SiO 2 .
  • SiO 2 can be suitably used as the protective film.
  • the light emission efficiency of the light emitting element can be improved.
  • the present invention is a method for manufacturing a light emitting element having a light emitting portion made of a compound semiconductor, an electrode, and a protective film, and the SiO 2 film as the protective film covering at least a part of the light emitting element,
  • a method for manufacturing a light-emitting element wherein irregularities are formed on the surface of the SiO 2 film by performing a frost treatment with a mixture of hydrofluoric acid and a monovalent to tetravalent inorganic acid or organic acid.
  • the light emitting device of the present invention can increase the resin adhesion and suppress the occurrence of resin peeling when resin sealing is performed. Moreover, if the manufacturing method of the light emitting element of this invention is used, the light emitting element which increases resin adhesiveness and can suppress that resin peeling will generate
  • FIG. 18 is a schematic cross-sectional view showing a light emitting element of Comparative Example 1.
  • FIG. 6 is a schematic cross-sectional view showing a light emitting element of Comparative Example 2.
  • FIG. 12 is a schematic cross-sectional view showing a light emitting element of Comparative Example 3.
  • FIG. 10 is a schematic cross-sectional view showing a light emitting element of Comparative Example 4.
  • the SiO 2 film used for protecting the side surface of the light emitting layer is a material having high shape followability, and is preferably formed by plasma CVD using a reaction between TEOS and oxygen.
  • the above-mentioned SiO 2 film has high shape followability, the surface roughened as the light extraction surface is uniformly covered, and thus the unevenness of the SiO 2 film surface is reduced. For this reason, when the resin is coated, the anchor effect is reduced, the resin adhesion is reduced, and the resin is peeled off by the existing technology when the resin is sealed.
  • the present inventors have intensively studied a light-emitting element that can suppress the occurrence of resin peeling when resin sealing is performed without reducing resin adhesion.
  • a light-emitting element that can suppress the occurrence of resin peeling when resin sealing is performed without reducing resin adhesion.
  • Rz represents the surface ten-point average roughness (JIS B0601-1994).
  • FIG. 1 shows a light emitting device 10 according to a first embodiment of the present invention.
  • the light emitting element 10 includes a support substrate 130 having a second electrode 162 and a second bonding metal layer 131, and an interface SiO 2 portion 120 having a conductive portion 121 in a part of the surface on the first bonding metal layer 122.
  • the second conductivity type current propagation layer 107 (thickness 0.5 to 5.0 ⁇ m), the second conductivity type buffer layer 106 for relaxing the lattice irregularity with the current propagation layer 107, the second conductivity type second Semiconductor layer 105 (thickness 0.5 to 1.0 ⁇ m), active layer 104 (thickness layer 0.1 to 1.0 ⁇ m), first conductivity type first semiconductor layer 103 (thickness 0.5 to 1.0 ⁇ m) ),
  • a first electrode 161 is formed thereon, and a substrate on which the SiO 2 film 170 is formed on the surface of the semiconductor layer is bonded, and the R z is 5 nm on the surface of the SiO 2 film 170. Concavities and convexities that exceed are formed.
  • Rz of the unevenness formed is preferably 50 nm or more, and more preferably 100 nm or more. Further, the upper limit of the Rz of the unevenness is preferably 780 nm which is not more than the visible light emission wavelength. As described above, the surface roughness of the SiO 2 film 170 having Rz exceeding 5 nm increases the anchor effect when the resin is coated, increases the resin adhesion, and performs resin sealing. It can suppress that resin peeling generate
  • the materials of the first conductive type first semiconductor layer 103, the active layer 104, the second conductive type second semiconductor layer 105, and the second conductive type buffer layer 106 are (Al x Ga 1-x ) y In 1-y P (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1) or Al z Ga 1-z As (0 ⁇ z ⁇ 1).
  • the current propagation layer 107 can be made of Al z Ga 1-z As (0 ⁇ z ⁇ 1) or GaAs w P 1-w (0 ⁇ w ⁇ 1).
  • the first semiconductor layer 103 is composed of a layer having two or more types of Al composition, and the layer (second layer) 103B is closer to the active layer 104 and the Al composition is closer to the first electrode 161.
  • a structure having a lower layer (first layer) 103A can be employed (see FIG. 1).
  • the second layer 103B is a functional layer having a function of a clad layer, and does not mean a single composition or a single condition
  • the surface of the light emitting unit 108 (that is, a part of the surface of the first semiconductor layer 103) is roughened. With such a configuration, the light emission efficiency of the light emitting element can be improved.
  • a substrate (starting substrate) 101 whose crystal axis is inclined in the [110] direction from the [001] direction is prepared (GaAs or Ge can be suitably used as the substrate 101). If the substrate 101 is selected from the above materials, the material of the active layer 104 can be epitaxially grown in a lattice-matched system, so that the quality of the active layer can be easily improved, and luminance can be increased and lifetime characteristics can be improved.
  • a first conductive type first semiconductor layer 103, an active layer 104, a second conductive type second semiconductor layer 105, and a current propagation layer 107 having substantially the same lattice constant as the substrate are epitaxially grown on the starting substrate 101.
  • a selective etching layer 102 for removing the substrate is inserted between the starting substrate 101 and the first semiconductor layer 103.
  • the selective etching layer 102 has a layer structure of two or more layers, and has at least a layer 102A in contact with the starting substrate 101 and a layer 102B in contact with the first semiconductor layer 103.
  • the layers 102A and 102B may be composed of different materials or compositions.
  • the first conductive type first semiconductor layer 103 is formed on the starting substrate 101 by, for example, MOVPE (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), or CBE (chemical beam epitaxy). Then, an epitaxial substrate 109 is produced by epitaxially growing a buffer layer 106 and a current propagation layer 107 in this order on the light emitting portion 108 composed of the active layer 104 and the second conductive type second semiconductor layer 105.
  • MOVPE metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • CBE chemical beam epitaxy
  • the active layer 104 has (Al x Ga 1-x ) y In 1-y P (0 ⁇ x ⁇ 1, 0.4 ⁇ y ⁇ 0.6) or Al z Ga 1-z As (0 ⁇ z ⁇ 0.45).
  • AlGaInP When it is applied to visible light illumination, it is preferable to select AlGaInP, and when it is applied to infrared illumination, it is preferable to select AlGaAs or InGaAs.
  • the design of the active layer is not limited to the above materials because the wavelength can be adjusted by using a superlattice or the like other than the wavelength resulting from the material composition.
  • AlGaInP or AlGaAs is selected for the first semiconductor layer 103 and the second semiconductor layer 105, and the selection is not necessarily the same material system as that of the active layer 104.
  • the first semiconductor layer 103, the active layer 104, or the second semiconductor layer 105 generally includes a plurality of layers in order to improve characteristics, and the first semiconductor layer 103, the active layer 104, or the second semiconductor layer 105 is generally included in each layer.
  • the two semiconductor layers 105 are not limited to being a single layer.
  • AlGaAs, GaAsP, or GaP can be suitably used as the current propagation layer 107.
  • the buffer layer 106 is most preferably formed of InGaP or AlInP. Since there is a lattice mismatch between GaAs x P 1-x (x ⁇ 1) and the AlGaInP-based material or AlGaAs-based material, GaAs x P 1-x (x ⁇ 1) has high-density strain and Threading dislocation enters. The threading dislocation density can be adjusted by the composition x.
  • the interface SiO 2 part 120 is deposited on at least a part of the current propagation layer 107 in the epitaxial substrate 109, and the interface metal part (conductive layer) is formed on at least a part of the region having no interface SiO 2 part.
  • Part) 121 and a first bonding metal layer 122 that covers at least a part of the interface SiO 2 part 120 and the interface metal part 121 are provided to form the first laminated body 123.
  • the second bonding metal layer 131 is provided on the permanent substrate (support substrate) 130 to form the second laminated body 132.
  • a bonded substrate obtained by contacting at least a part of the first bonding metal layer 122 and the second bonding metal layer 131 and bonding the first laminate 123 and the second laminate 132 by applying a pressure of 1000 N and heat of 150 ° C. or more. 140 is formed.
  • the starting substrate 101 is removed from the bonding substrate 140 by a wet etching method to expose the first semiconductor layer 103.
  • etching is performed with a mixed solution of ammonia water and hydrogen peroxide water.
  • etching stop layer 102A By using a material different from that of the starting substrate 101 for the etching stop layer 102A, etching using a mixed solution of ammonia water and hydrogen peroxide water can be selectively stopped.
  • AlInP can be used as the etching stop layer 102A.
  • the etching stop layer 102A is removed.
  • AlInP is used as the etching stop layer 102A
  • hydrochloric acid can be used for removal.
  • the etching stop layer 102B can be made of GaAs in order to stop etching with hydrochloric acid.
  • a first electrode 161 in contact with the first semiconductor layer 103 is formed, a second electrode 162 in contact with the permanent substrate 130 is formed, and an insulating layer 170 covering at least a part of the first semiconductor layer 103 is formed.
  • a light-emitting element substrate 171 is manufactured.
  • the first electrode 161 When the first conductivity type is n-type, the first electrode 161 includes at least one material selected from Au, Ag, Al, Ni, Pd, Ge, Si, and Sn, and has a film thickness of 100 nm or more. It can be. When the first conductivity type is p-type, it may include at least one material of Au, Be, Mg, and Zn and have a thickness of 100 nm or more. When the second conductivity type is n-type, the second electrode 162 includes at least one material of Au, Ag, Al, Ni, Pd, Ge, Si, and Sn and has a thickness of 100 nm or more. It can be. When the second conductivity type is p-type, it can include at least one material of Au, Be, Mg, and Zn and have a film thickness of 100 nm or more.
  • the insulating layer 170 of the light-emitting element substrate 171 is subjected to a frost treatment using a liquid in which hydrofluoric acid and a monovalent to tetravalent inorganic acid or organic acid are mixed.
  • the inorganic acid is at least one of sulfuric acid, hydrochloric acid, and phosphoric acid
  • the organic acid can be at least one of malonic acid, acetic acid, citric acid, tartaric acid, and malic acid.
  • the frosted substrate 180 having unevenness on the surface of the insulating layer 170 is manufactured.
  • the frosted substrate 180 is separated into individual dice, a wire is provided on the first electrode 161, the second electrode 162 is fixed to the stem with a conductive resin, and then sealed with an epoxy resin to produce a light emitting diode.
  • FIG. 2 shows a light emitting device 20 according to the second embodiment of the present invention.
  • the light emitting element 20 includes a support substrate 230 having a second electrode 262 and a second bonding metal layer 231, an interfacial transparent conductive film layer 220 having a contact portion 208 on the first bonding metal layer 222, and a second conductive film on the support conductive film 230.
  • Type current propagation layer 207 (thickness 0.5 to 5.0 ⁇ m)
  • second conductivity type buffer layer 206 that relaxes lattice irregularities with current propagation layer 207
  • second conductivity type second semiconductor layer 205 thickness 0.
  • Rz of the unevenness formed is preferably 50 nm or more, and more preferably 100 nm or more.
  • the anchor effect when the resin is coated is increased as in the first embodiment, It is possible to increase resin adhesion and suppress the occurrence of resin peeling when resin sealing is performed.
  • the materials of the first conductivity type first semiconductor layer 203, the active layer 204, the second conductivity type second semiconductor layer 205, and the second conductivity type buffer layer 206 are (Al x Ga 1-x ) y In 1-y P (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1) or Al z Ga 1-z As (0 ⁇ z ⁇ 1).
  • the current propagation layer 207 can be made of Al z Ga 1-z As (0 ⁇ z ⁇ 1) or GaAs w P 1-w (0 ⁇ w ⁇ 1).
  • the first semiconductor layer 203 is composed of a layer having two or more types of Al composition
  • the layer (second layer) 203B is closer to the active layer 204 and the Al composition is closer to the first electrode 261.
  • a structure having a lower layer (first layer) 203A can be employed (see FIG. 2).
  • the second layer 203B is a functional layer having the function of a cladding layer, and does not mean a single composition or a single condition layer.
  • the interfacial transparent conductive film layer 220 is composed of an oxide containing at least one of Mg, Ni, Cu, Ga, In, and Sn.
  • a substrate (starting substrate) 201 whose crystal axis is inclined in the [110] direction from the [001] direction is prepared (GaAs or Ge can be suitably used as the substrate 201).
  • a first conductivity type first semiconductor layer 203, an active layer 204, a second conductivity type second semiconductor layer 205, a current propagation layer 207, and a contact layer having substantially the same lattice constant as the substrate. 208 are sequentially formed by epitaxial growth to form an epitaxial substrate 210.
  • the first semiconductor layer 203, the active layer 204, and the second semiconductor layer 205 constitute a light emitting unit 209.
  • a selective etching layer 202 for removing the substrate is inserted between the starting substrate 201 and the first semiconductor layer 203.
  • the selective etching layer has a layer structure of two or more layers, and has at least a layer 202A in contact with the starting substrate and a layer 202B in contact with the first semiconductor layer.
  • the layers 202A and 202B may be composed of different materials or compositions.
  • the first semiconductor layer 203, the active layer 204, the second semiconductor layer 205, and the current propagation layer 207 are the same as the first semiconductor layer 103, the active layer 104, the second semiconductor layer 105, and the current propagation layer 107 of the first embodiment.
  • the same material can be used.
  • the contact layer 208 may be made of the same material as the current propagation layer 207 or may be made of a different material.
  • a part of the contact layer 208 is removed, and a first transparent conductive film 220 is deposited so as to be in contact with at least a part of both the contact part 208 and the current propagation layer 207. Then, a first bonding metal layer 222 that covers at least a part of the first transparent conductive film 220 is provided to form the first laminate 223.
  • the second bonding metal layer 231 is provided on the permanent substrate (supporting substrate) 230 to form the second stacked body 232.
  • a bonded substrate obtained by contacting at least a part of the first bonding metal layer 222 and the second bonding metal layer 231 and bonding the first laminate 223 and the second laminate 232 by applying a pressure of 1000 N and heat of 150 ° C. or more. 240 is formed.
  • the starting substrate 201 is removed from the bonding substrate 240 by a wet etching method to expose the first semiconductor layer 203. Etching can be performed in the same manner as in the first embodiment.
  • the etching stop layer 202A is removed.
  • the same material as the etching stop layers 102A and 102B of the first embodiment can be used.
  • a first electrode 261 in contact with the first semiconductor layer 203 is formed, a second electrode 262 in contact with the permanent substrate 230 is formed, and an insulating layer 270 that covers at least a part of the first semiconductor layer 203 is formed.
  • a light-emitting element substrate 271 is manufactured.
  • the first electrode 261 and the second electrode 262 can be made of the same material as the first electrode 161 and the second electrode 162 of the first embodiment, and can have the same film thickness.
  • the insulating layer 270 of the light emitting element substrate 271 is subjected to a frost treatment in the same manner as in the first embodiment.
  • the frosted substrate 280 having unevenness on the surface of the insulating layer 270 is manufactured.
  • the frosted substrate 280 is separated into individual dies, a wire is provided on the first electrode 261, the second electrode 262 is fixed to the stem with a conductive resin, and then a light emitting diode sealed with an epoxy resin is manufactured.
  • FIG. 3 shows a light emitting device 30 according to the third embodiment of the present invention.
  • the light emitting element 30 includes a support substrate 330 having a second dielectric film 321 and a second adhesive layer 325, a first dielectric film 320 on the first adhesive layer 324, and a second conductivity type current propagation layer 307 thereon.
  • Second conductivity type buffer layer 306 that relaxes lattice irregularity with current propagation layer 307
  • second conductivity type second semiconductor layer 305 (thickness 0.5 to 1.0 ⁇ m)
  • An active layer 304 (thickness layer 0.1 to 1.0 ⁇ m) and a first conductive type first semiconductor layer 303 (thickness 0.5 to 1.0 ⁇ m) are stacked, and a first electrode 350 is formed thereon.
  • a part of the semiconductor layer is notched to the second conductivity type current propagation layer 307, and the second electrode 351 is formed on the notched second conductivity type current propagation layer 307, and further the surface of the semiconductor layer Is a light-emitting element in which a substrate on which a SiO 2 film 370 is formed is bonded, and SiO 2 Irregularities with Rz exceeding 5 nm are formed on the surface of the film 370.
  • Rz of the unevenness formed is preferably 50 nm or more, and more preferably 100 nm or more.
  • the anchor effect when the resin is coated is increased as in the first embodiment, It is possible to increase resin adhesion and suppress the occurrence of resin peeling when resin sealing is performed.
  • the materials of the first conductivity type first semiconductor layer 303, the active layer 304, the second conductivity type second semiconductor layer 305, and the second conductivity type buffer layer 306 are (Al x Ga 1-x ) y In 1-y P (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1) or Al z Ga 1-z As (0 ⁇ z ⁇ 1).
  • the current propagation layer 307 can be Al z Ga 1-z As (0 ⁇ z ⁇ 1) or GaAs w P 1-w (0 ⁇ w ⁇ 1).
  • the first semiconductor layer 303 is composed of a layer having two or more types of Al composition, and the layer (second layer) 303B is closer to the active layer 304 and the Al composition is closer to the first electrode 350.
  • a structure having a lower layer (first layer) 303A can be employed (see FIG. 3).
  • the second layer 303B is a functional layer having a function of a clad layer, and does not mean a single composition or a single condition layer.
  • a substrate (starting substrate) 301 having a crystal axis tilted in the [110] direction from the [001] direction is prepared (GaAs or Ge can be suitably used as the substrate 301).
  • a first conductive type first semiconductor layer 303, an active layer 304, a second conductive type second semiconductor layer 305, and a current propagation layer 307 having substantially the same lattice constant as the substrate are epitaxially grown on the starting substrate 301.
  • the epitaxial substrate 309 is formed sequentially.
  • the first semiconductor layer 303, the active layer 304, and the second semiconductor layer 305 constitute a light emitting unit 308.
  • a selective etching layer 302 for removing the substrate is inserted between the starting substrate 301 and the first semiconductor layer 303.
  • the selective etching layer 302 has a layer structure of two or more layers, and has at least a layer 302A in contact with the starting substrate and a layer 302B in contact with the first semiconductor layer.
  • the layers 302A and 302B may be made of different materials or compositions.
  • the first semiconductor layer 303, the active layer 304, the second semiconductor layer 305, and the current propagation layer 307 are the same as the first semiconductor layer 103, the active layer 104, the second semiconductor layer 105, and the current propagation layer 107 of the first embodiment.
  • the same material can be used.
  • a first SiO 2 film 320 is deposited on the current propagation layer 307 in the epitaxial substrate 309.
  • the first SiO 2 film 320 can be formed by optical CVD, sputtering, or PECVD.
  • a transparent adhesive layer 325 is formed on the first SiO 2 film 320, and a first bonding substrate 326 is formed.
  • the transparent adhesive layer 325 can be selected from BCB (benzocyclobutene) or epoxy. It is preferable to select a material that can be formed by a dipping method or a spin coating method. For example, in the case of cycloten, which is a BCB material that can be deposited by spin coating, cycloten is dropped on the first SiO 2 film 320 and spin coating is performed at a rotational speed of 1,000 to 5,000 rpm.
  • any adhesive can be applied as long as the adhesive can be applied uniformly, any of the aforementioned rotational speeds can be selected, but a rotational speed of 3,000 rpm or more is suitable.
  • the solvent is volatilized by holding on a hot plate at 80 to 110 ° C. for 30 seconds or more. Since the solvent only needs to be volatilized, any of the above-mentioned conditions can be selected. However, it is preferable to select a holding time of 90 ° C. or more and 60 seconds or more.
  • a second SiO 2 film 321 is deposited on the transparent substrate (support substrate) 330 to form a second bonding substrate 331.
  • the second SiO 2 film 321 can be formed by optical CVD, sputtering, or PECVD.
  • the transparent adhesive layer 325 is provided only on the first bonding substrate 326
  • the same effect can be obtained even if the transparent bonding layer is provided on the second bonding substrate 331.
  • a transparent adhesive layer can be provided on both the first bonding substrate 326 and the second bonding substrate 331.
  • the first bonding substrate 326 and the second bonding substrate 331 are placed so that the transparent adhesive layer 325 and the second SiO 2 film 321 face each other and do not come into contact with each other, and a vacuum atmosphere of 30 Pa or less.
  • the transparent adhesive layer 325 and the second SiO 2 film 321 are brought into contact with each other and controlled so as to reach a pressure of 5000 N and a temperature between 100 to 200 ° C. for 5 minutes or more, and then 300 ° C. or more.
  • the first bonding substrate 326 and the second bonding substrate 331 are pressure-bonded to form the bonding substrate 340.
  • the starting substrate 301 is removed from the bonding substrate 340 by etching. Etching can be performed in the same manner as in the first embodiment.
  • the etching stop layer 302A is removed.
  • the etching stop layers 302A and 302B can use the same material as the etching stop layers 102A and 102B of the first embodiment.
  • a first electrode 350 in contact with the first semiconductor layer 303 is formed.
  • the first electrode 350 can be made of the same material as the first electrode 161 of the first embodiment, and can have a thickness of 300 nm or more.
  • a pattern in which the first semiconductor layer 303 and the active layer 304 in the region 360 other than the area where the first electrode 350 is present is formed by etching using a dry method or a wet method.
  • FIG. 15 shows an example in which the current propagation layer 307 is cut out, the same function is obtained even if the etching is stopped with the second semiconductor layer 305 or the buffer layer 306 exposed.
  • a region other than the region 360 is represented as a flat surface. However, the region is not limited to a flat surface, and a region other than the region 360 may be a rough surface or an uneven surface.
  • Insulating layer 370 that covers at least part of the first semiconductor layer 303 is formed.
  • Insulating layer 370 is SiO 2.
  • FIG. 16 illustrates an example in which a part of the active layer 304, the second semiconductor layer 305, the buffer layer 306, and the current propagation layer 307 is covered, the present invention is not limited to this mode.
  • the second electrode 351 can use the same material as the second electrode 162 of the first embodiment, and can have a film thickness of 300 nm or more.
  • the insulating layer 370 of the light emitting element substrate 371 is subjected to frost treatment on the surface in the same manner as in the first embodiment, and a frosted substrate 380 having irregularities on the surface of the insulating layer 370 is formed. Make it.
  • the dies are fixed to the stem, wires are provided on the first electrode 350 and the second electrode 351, and sealed with an epoxy resin. A stopped light emitting diode is produced.
  • FIG. 4 shows a light emitting device 40 according to the fourth embodiment of the present invention.
  • the light emitting element 40 includes a second conductivity type current propagation layer 407 (thickness 30 to 150 ⁇ m), a second conductivity type buffer layer 406 that relaxes lattice irregularities with the current propagation layer 407, and a second conductivity type second semiconductor layer 405.
  • the first electrode 450 is formed thereon, and a part of the semiconductor layer is notched up to the second conductivity type current propagation layer 407, and the first electrode 450 is formed on the notched second conductivity type current propagation layer 407.
  • Rz of the unevenness formed is preferably 50 nm or more, and more preferably 100 nm or more. Also in the fourth embodiment, by forming irregularities with R z exceeding 5 nm on the surface of the SiO 2 film 470, the anchor effect when coating the resin as in the first embodiment is increased, It is possible to increase resin adhesion and suppress the occurrence of resin peeling when resin sealing is performed.
  • the materials of the first conductive type first semiconductor layer 403, the active layer 404, the second conductive type second semiconductor layer 405, and the second conductive type buffer layer 406 are (Al x Ga 1-x ) y In 1-y P (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1) or Al z Ga 1-z As (0 ⁇ z ⁇ 1).
  • the current propagation layer 407 can be Al z Ga 1-z As (0 ⁇ z ⁇ 1) or GaAs w P 1-w (0 ⁇ w ⁇ 1).
  • the first semiconductor layer 403 is composed of a layer having two or more types of Al composition
  • the layer (second layer) 403B is closer to the active layer 404
  • the Al composition is closer to the first electrode 450.
  • a structure having a lower layer (first layer) 403A can be employed (see FIG. 4).
  • the second layer 403B is a functional layer having the function of a cladding layer, and does not mean a single composition or a single condition layer.
  • a substrate (starting substrate) 401 whose crystal axis is inclined in the [110] direction from the [001] direction is prepared (GaAs or Ge can be suitably used as the substrate 401).
  • a first conductivity type first semiconductor layer 403, an active layer 404, a second conductivity type second semiconductor layer 405, and a current propagation layer 407 having substantially the same lattice constant as the substrate are epitaxially grown on the starting substrate 401.
  • the epitaxial substrate 409 is formed sequentially.
  • the first semiconductor layer 403, the active layer 404, and the second semiconductor layer 405 constitute a light emitting unit 408.
  • a selective etching layer 402 for removing the substrate is inserted between the starting substrate 401 and the first semiconductor layer 403.
  • the selective etching layer has a layer structure of two or more layers, and has at least a layer 402A in contact with the starting substrate and a layer 402B in contact with the first semiconductor layer.
  • the layers 402A and 402B may be made of different materials or compositions.
  • the first semiconductor layer 403, the active layer 404, the second semiconductor layer 405, and the current propagation layer 407 are the same as the first semiconductor layer 103, the active layer 104, the second semiconductor layer 105, and the current propagation layer 107 of the first embodiment.
  • the same material can be used.
  • the first semiconductor layer 403 is made of a layer having two or more types of Al composition.
  • the layer (second layer) 403B is closer to the active layer 404 and the layer with lower Al composition is closer to the starting substrate 401 ( The first layer) 403A can be employed.
  • the layer 403B is a functional layer having a function of a clad layer, and does not mean a single composition or a single condition layer.
  • the starting substrate 401 is removed by etching. Etching can be performed in the same manner as in the first embodiment.
  • the etching stop layer 402A is removed.
  • the etching stop layers 402A and 402B can use the same material as the etching stop layers 102A and 102B of the first embodiment.
  • FIG. 19 shows an example in which the current propagation layer 407 is cut out, the same function is obtained even if etching is stopped with the second semiconductor layer 405 or the buffer layer 406 exposed.
  • a region other than the region 460 is represented as a flat surface.
  • the region is not limited to a flat surface, and a region other than the region 460 may be a rough surface or an uneven surface.
  • the first electrode 450 in contact with at least part of the first semiconductor layer 403, at least part of the region 460, and at least part of the region other than the region 460 are insulated.
  • Layer 470 is formed. Insulating layer 470 is SiO 2. Then, a light emitting element substrate 471 in which the second electrode 451 is formed in part of the region 460 is formed.
  • the first electrode 450 can be made of the same material as the first electrode 161 of the first embodiment, and can have a thickness of 300 nm or more.
  • the second electrode 451 can use the same material as the second electrode 162 of the first embodiment, and can have a film thickness of 300 nm or more.
  • the surface of the insulating layer 470 of the light-emitting element substrate 471 is subjected to a frost treatment in the same manner as in the first embodiment, and the surface of the insulating layer 470 has a frost treatment substrate 480. Is made.
  • the dice are fixed to the stem, wires are provided on the first electrode 450 and the second electrode 451, and light emission is sealed with an epoxy resin A diode is fabricated.
  • Example 1 A light emitting device 10 as shown in FIG. 1 was manufactured.
  • the first semiconductor layer 103, the active layer 104, and the second semiconductor layer 105 of the light emitting element 10 are made of the same material, AlInGaP.
  • the first semiconductor layer 103 is made of a layer having two or more types of Al composition.
  • the layer (second layer) 103B is closer to the active layer 104, and the lower Al composition is closer to the first electrode 161.
  • (First layer) 103A is included.
  • the second layer 103B is a functional layer having the function of a cladding layer.
  • the first conductivity type is n-type
  • the electrode material of the first electrode 161 is an AuGeNi alloy
  • the film thickness is 500 nm.
  • the second conductivity type is p-type, and the electrode material of the second electrode 162 is AuBe alloy, and the film thickness is 500 nm.
  • the insulating layer 170 a SiO 2 film was formed by P-CVD using TEOS and O 2 as raw materials. The film thickness was 300 nm.
  • This light emitting device is manufactured from eight wafers in which irregularities are formed on the surface of the SiO 2 film 170 by frost processing of conditions 1 to 8 shown in Table 1 on the epitaxial substrate during the manufacturing process.
  • Table 1 shows the frost treatment conditions (acetic acid, which is a monovalent organic acid, malic acid, which is a trivalent organic acid, tartaric acid, which is a tetravalent organic acid, and citric acid, which is a tetravalent organic acid).
  • R z surface roughness in a frost treatment with a mixture of either hydrofluoric acid or buffered hydrofluoric acid.
  • Example 2 A light emitting device 20 as shown in FIG. 2 was produced.
  • the first semiconductor layer 203, the active layer 204, and the second semiconductor layer 205 of this light emitting element were made of AlInGaP which is the same material.
  • the first semiconductor layer 203 is made of a layer having two or more types of Al composition, and the layer (second layer) 203B is closer to the active layer 204 and the layer having a lower Al composition is closer to the first electrode 261.
  • the layer 203B is a functional layer having a function of a cladding layer.
  • the first conductivity type is n-type
  • the electrode material of the first electrode 261 is an alloy of AuGeNi
  • the film thickness is 500 nm.
  • the second conductivity type is p-type, and the electrode material of the second electrode 262 is an AuBe alloy, and the film thickness is 500 nm.
  • the insulating layer 270 a SiO 2 film was formed by P-CVD using TEOS and O 2 as raw materials. The film thickness was 300 nm. This light emitting device is manufactured from eight wafers in which irregularities are formed on the surface of the SiO 2 film 270 by frost processing of conditions 1 to 8 shown in Table 1 on the epitaxial substrate during the manufacturing process.
  • Example 3 A light emitting device 30 as shown in FIG. 3 was produced.
  • the first semiconductor layer 303, the active layer 304, and the second semiconductor layer 305 of this light emitting element were made of the same material, AlInGaP.
  • the first semiconductor layer 303 is composed of two or more types of Al compositions, and the layer (second layer) 303B is closer to the active layer 304, and the lower Al composition is closer to the first electrode 350.
  • (First layer) 303A was included.
  • the layer 303B is a functional layer having a function of a clad layer.
  • the transparent adhesive layer 325 was cycloten, which is a BCB material that can be deposited by spin coating.
  • Cycloten was dropped on the first SiO 2 film 320 and spin coating was performed at a rotational speed of 3,000 rpm. After spin coating, the solvent was volatilized by maintaining at 90 ° C. for 60 seconds or longer on a hot plate.
  • the first conductivity type is n-type
  • the electrode material of the first electrode 350 is an AuGeNi alloy, and the film thickness is 500 nm.
  • the second conductivity type is p-type, and the electrode material of the second electrode 351 is AuBe alloy, and the film thickness is 500 nm.
  • As the insulating layer 370 a SiO 2 film was formed by P-CVD using TEOS and O 2 as raw materials. The film thickness was 300 nm. This light emitting device is manufactured from eight wafers in which irregularities are formed on the surface of the SiO 2 film 370 by frost processing of conditions 1 to 8 shown in Table 1 on the epitaxial substrate in the manufacturing process.
  • Example 4 A light emitting device 40 as shown in FIG. 4 was produced.
  • the first semiconductor layer 403, the active layer 404, and the second semiconductor layer 405 of this light emitting element are made of the same material, AlInGaP.
  • the first semiconductor layer 403 is made of a layer having two or more types of Al composition.
  • the layer (second layer) 403B is closer to the active layer 404, and the lower Al composition is closer to the first electrode 450.
  • (First layer) 403A was provided.
  • the layer 403B is a functional layer having a function of a cladding layer.
  • the first conductivity type was n-type, and an alloy of AuGeNi was selected as the electrode material of the first electrode 450, and the film thickness was 500 nm.
  • the second conductivity type is p-type, and the electrode material of the second electrode 451 is selected from AuBe alloy, and the film thickness is set to 500 nm.
  • the insulating layer 470 a SiO 2 film was formed by P-CVD using TEOS and O 2 as raw materials. The film thickness was 300 nm. This light-emitting element is manufactured from eight wafers in which irregularities are formed on the surface of the SiO 2 film 470 by frost processing of conditions 1 to 8 shown in Table 1 on the epitaxial substrate during the manufacturing process.
  • Example 1 A light emitting device 50 as shown in FIG. 23 was manufactured.
  • This light-emitting element has the same structure as that of Example 1 except that the surface of the SiO 2 protective film 170 is not frosted.
  • the light emitting device is manufactured from one epitaxial wafer which has not been frosted.
  • Example 2 A light emitting device 60 as shown in FIG. 24 was manufactured. This light emitting element has the same structure as that of Example 2 except that the surface of the SiO 2 protective film 270 is not frosted. The light emitting device is manufactured from one epitaxial wafer which has not been frosted.
  • Example 3 A light emitting device 70 as shown in FIG. 25 was produced.
  • This light emitting element has the same structure as that of Example 3 except that the surface of the SiO 2 protective film 370 is not frosted.
  • the light emitting device is manufactured from one epitaxial wafer which has not been frosted.
  • Example 4 A light emitting device 80 as shown in FIG. 26 was manufactured. This light-emitting element has the same structure as that of Example 4 except that the SiO 2 protective film 470 is not subjected to frost processing. The light emitting device is manufactured from one epitaxial wafer which has not been frosted.
  • Example 1 in which the frost treatment was performed has a significantly improved peeling rate compared to Comparative Example 1 in which the frost treatment is not carried out.
  • Example 2 in which the frost treatment was performed had a significantly higher peeling rate than Comparative Example 2 in which the frost treatment was not performed. You can see that it has improved.
  • Example 3 in which the frost treatment was performed had a significantly higher peeling rate than Comparative Example 3 in which the frost treatment was not performed. You can see that it has improved.
  • Example 4 in which the frost treatment is performed has a significantly higher peeling rate than Comparative Example 4 in which the frost treatment is not performed. You can see that it has improved.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

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Abstract

The present invention is a light-emitting element comprising: a light-emitting unit formed of a compound semiconductor; electrodes; and a protective membrane. The light-emitting element is characterized in that the protective membrane covering at least a part of the light-emitting element has recesses and projections formed on the surface thereof, and the Rz of the recesses and projections exceeds 5 nm. Due to this configuration, occurrence of resin stripping can be suppressed without reducing resin adhesion when resin sealing is conducted.

Description

発光素子及び発光素子の製造方法Light emitting device and method for manufacturing light emitting device
　本発明は、化合物半導体からなる発光素子及びその製造方法に関する。 The present invention relates to a light emitting device made of a compound semiconductor and a method for manufacturing the same.
　化合物半導体、例えばＡｌＧａＩｎＰからなる発光素子（ＬＥＤ）は湿度やプロセス中の異物不着による劣化もしくはリークを防止するため、ＳｉＯ２保護膜を形成している（例えば、特許文献１を参照）。 A light emitting element (LED) made of a compound semiconductor such as AlGaInP is formed with a SiO 2 protective film in order to prevent deterioration or leakage due to humidity or non-adherence of foreign matters during the process (see, for example, Patent Document 1).
　特に発光層側面を保護するために使用するＳｉＯ２膜は形状追随性が高い材料及び反応系で形成するのが好適で、ＴＥＯＳと酸素を用いたプラズマＣＶＤで形成する。このことにより、発光層側面を良好に被覆し、保護膜としての機能を十分に果たすことができる。 In particular, the SiO 2 film used for protecting the side surface of the light emitting layer is preferably formed of a material and a reaction system having high shape following characteristics, and is formed by plasma CVD using TEOS and oxygen. Thus, the side surface of the light emitting layer can be satisfactorily covered and the function as a protective film can be sufficiently achieved.
特開２００７－２６６６４６号公報JP 2007-266646 A
　その一方、上記のＳｉＯ２膜は形状追随性が高いため、光取り出し面として粗面化した表面をも一様に被覆するため、凹凸（Ｒｚ）が小さくなる効果も有する。ＳｉＯ２膜表面の凹凸が小さくなることで、樹脂を被覆した際のアンカー効果が小さくなり、樹脂密着性を低下させ、樹脂封止を行った際に、既存技術では高湿環境下において樹脂剥離が発生するといった問題があった。 On the other hand, since the above-mentioned SiO 2 film has high shape followability, the roughened surface is uniformly covered as the light extraction surface, and therefore, there is an effect that the unevenness (R z ) is reduced. By reducing the unevenness of the SiO 2 film surface, the anchor effect when the resin is coated is reduced, the resin adhesion is reduced, and the resin is peeled off in a high-humidity environment when resin sealing is performed. There was a problem that occurred.
　本発明は、上記問題点に鑑みてなされたもので、樹脂密着性を低下させることなく、樹脂封止を行った際に、高湿環境下において樹脂剥離の発生を抑制することができる発光素子及び発光素子の製造方法を提供することを目的とする。 The present invention has been made in view of the above-mentioned problems, and is capable of suppressing the occurrence of resin peeling in a high-humidity environment when resin sealing is performed without reducing resin adhesion. And it aims at providing the manufacturing method of a light emitting element.
　上記目的を達成するために、本発明は、化合物半導体からなる発光部と、電極と、保護膜とを有する発光素子であって、前記発光素子の少なくとも一部を覆う前記保護膜の表面に、Ｒｚが５ｎｍを超える凹凸が形成されているものであることを特徴とする発光素子を提供する。 In order to achieve the above object, the present invention is a light emitting device having a light emitting portion made of a compound semiconductor, an electrode, and a protective film, and on the surface of the protective film covering at least a part of the light emitting device, Provided is a light-emitting element in which irregularities having Rz exceeding 5 nm are formed.
　このように、保護膜の表面にＲｚが５ｎｍを超える凹凸が形成されていることで樹脂を被覆した際のアンカー効果が大きくなり、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できる。 Thus, when the surface of the protective film has irregularities with Rz exceeding 5 nm, the anchor effect when the resin is coated is increased, the resin adhesion is increased, and the resin is sealed. Generation | occurrence | production of resin peeling can be suppressed.
　このとき、前記保護膜がＳｉＯ２であることが好ましい。 At this time, the protective film is preferably SiO 2 .
　保護膜として、ＳｉＯ２を好適に用いることができる。 SiO 2 can be suitably used as the protective film.
　このとき、前記発光部の表面の少なくとも一部が粗面化されているものであることが好ましい。 At this time, it is preferable that at least a part of the surface of the light emitting part is roughened.
　このような構成により、発光素子の発光効率を向上させることができる。 With such a configuration, the light emission efficiency of the light emitting element can be improved.
　また、本発明は、化合物半導体からなる発光部と、電極と、保護膜とを有する発光素子の製造方法であって、前記発光素子の少なくとも一部を覆う前記保護膜であるＳｉＯ２膜に、弗酸と１価～４価の無機酸あるいは有機酸とを混合した液によりフロスト処理することで、前記ＳｉＯ２膜の表面に凹凸を形成することを特徴とする発光素子の製造方法を提供する。 Further, the present invention is a method for manufacturing a light emitting element having a light emitting portion made of a compound semiconductor, an electrode, and a protective film, and the SiO 2 film as the protective film covering at least a part of the light emitting element, Provided is a method for manufacturing a light-emitting element, wherein irregularities are formed on the surface of the SiO 2 film by performing a frost treatment with a mixture of hydrofluoric acid and a monovalent to tetravalent inorganic acid or organic acid. .
　このような方法であれば、比較的簡便にＳｉＯ２膜表面に凹凸を形成することができ、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できる発光素子を製造することができる。 With such a method, it is possible to relatively easily form irregularities on the surface of the SiO 2 film, increase the resin adhesion, and suppress the occurrence of resin peeling when resin sealing is performed. An element can be manufactured.
　このとき、前記無機酸として、硫酸、塩酸、燐酸のうちの少なくともいずれか１種を用い、前記有機酸として、マロン酸、酢酸、クエン酸、酒石酸、リンゴ酸のうちの少なくともいずれか１種を用いることが好ましい。 At this time, at least one of sulfuric acid, hydrochloric acid, and phosphoric acid is used as the inorganic acid, and at least one of malonic acid, acetic acid, citric acid, tartaric acid, and malic acid is used as the organic acid. It is preferable to use it.
　無機酸あるいは有機酸として、上記のようなものを用いれば、より確実にＳｉＯ２膜表面に凹凸を形成することができる。 If an inorganic acid or an organic acid as described above is used, irregularities can be more reliably formed on the surface of the SiO 2 film.
　以上のように、本発明の発光素子であれば、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できる。また、本発明の発光素子の製造方法を用いれば、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できる発光素子を比較的簡便に製造することができる。 As described above, the light emitting device of the present invention can increase the resin adhesion and suppress the occurrence of resin peeling when resin sealing is performed. Moreover, if the manufacturing method of the light emitting element of this invention is used, the light emitting element which increases resin adhesiveness and can suppress that resin peeling will generate | occur | produce when resin sealing is performed can be manufactured comparatively simply. .
本発明の発光素子の第一の実施形態を示す概略断面図である。It is a schematic sectional drawing which shows 1st embodiment of the light emitting element of this invention. 本発明の発光素子の第二の実施形態を示す概略断面図である。It is a schematic sectional drawing which shows 2nd embodiment of the light emitting element of this invention. 本発明の発光素子の第三の実施形態を示す概略断面図である。It is a schematic sectional drawing which shows 3rd embodiment of the light emitting element of this invention. 本発明の発光素子の第四の実施形態を示す概略断面図である。It is a schematic sectional drawing which shows 4th embodiment of the light emitting element of this invention. 本発明の発光素子の製造方法の第一の実施形態を示す工程断面図である。It is process sectional drawing which shows 1st embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第一の実施形態を示す工程断面図（図５の続き）である。It is process sectional drawing (continuation of FIG. 5) which shows 1st embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第一の実施形態を示す工程断面図（図６の続き）である。It is process sectional drawing (continuation of FIG. 6) which shows 1st embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第一の実施形態を示す工程断面図（図７の続き）である。It is process sectional drawing (continuation of FIG. 7) which shows 1st embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第二の実施形態を示す工程断面図である。It is process sectional drawing which shows 2nd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第二の実施形態を示す工程断面図（図９の続き）である。It is process sectional drawing (continuation of FIG. 9) which shows 2nd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第二の実施形態を示す工程断面図（図１０の続き）である。It is process sectional drawing (continuation of FIG. 10) which shows 2nd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第二の実施形態を示す工程断面図（図１１の続き）である。It is process sectional drawing (continuation of FIG. 11) which shows 2nd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第三の実施形態を示す工程断面図である。It is process sectional drawing which shows 3rd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第三の実施形態を示す工程断面図（図１３の続き）である。It is process sectional drawing (continuation of FIG. 13) which shows 3rd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第三の実施形態を示す工程断面図（図１４の続き）である。It is process sectional drawing (continuation of FIG. 14) which shows 3rd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第三の実施形態を示す工程断面図（図１５の続き）である。It is process sectional drawing (continuation of FIG. 15) which shows 3rd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第三の実施形態を示す工程断面図（図１６の続き）である。It is process sectional drawing (continuation of FIG. 16) which shows 3rd embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第四の実施形態を示す工程断面図である。It is process sectional drawing which shows 4th embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第四の実施形態を示す工程断面図（図１８の続き）である。It is process sectional drawing (continuation of FIG. 18) which shows 4th embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第四の実施形態を示す工程断面図（図１９の続き）である。It is process sectional drawing (continuation of FIG. 19) which shows 4th embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第四の実施形態を示す工程断面図（図２０の続き）である。It is process sectional drawing (continuation of FIG. 20) which shows 4th embodiment of the manufacturing method of the light emitting element of this invention. フロスト処理条件と、樹脂剥離率の関係を示す図である。It is a figure which shows the relationship between frost process conditions and the resin peeling rate. 比較例１の発光素子を示す概略断面図である。6 is a schematic cross-sectional view showing a light emitting element of Comparative Example 1. FIG. 比較例２の発光素子を示す概略断面図である。6 is a schematic cross-sectional view showing a light emitting element of Comparative Example 2. FIG. 比較例３の発光素子を示す概略断面図である。12 is a schematic cross-sectional view showing a light emitting element of Comparative Example 3. FIG. 比較例４の発光素子を示す概略断面図である。10 is a schematic cross-sectional view showing a light emitting element of Comparative Example 4. FIG.
　前述したように、発光層側面を保護するために使用するＳｉＯ２膜は形状追随性が高い材料であり、ＴＥＯＳと酸素の反応を用いたプラズマＣＶＤで形成するのが好適である。一方で、上記のＳｉＯ２膜は形状追随性が高いため、光取り出し面として粗面化した表面をも一様に被覆するため、ＳｉＯ２膜表面の凹凸が小さくなる。このため、樹脂を被覆した際のアンカー効果が小さくなり、樹脂密着性を低下させ、樹脂封止を行った際に、既存技術では樹脂剥離が発生するといった問題があった。 As described above, the SiO 2 film used for protecting the side surface of the light emitting layer is a material having high shape followability, and is preferably formed by plasma CVD using a reaction between TEOS and oxygen. On the other hand, since the above-mentioned SiO 2 film has high shape followability, the surface roughened as the light extraction surface is uniformly covered, and thus the unevenness of the SiO 2 film surface is reduced. For this reason, when the resin is coated, the anchor effect is reduced, the resin adhesion is reduced, and the resin is peeled off by the existing technology when the resin is sealed.
　本発明者らは、樹脂密着性を低下させることなく、樹脂封止を行った際に、樹脂剥離の発生を抑制することができる発光素子について鋭意検討した。その結果、ＳｉＯ２膜の表面にＲｚが５ｎｍを超える凹凸が形成されていることで、樹脂を被覆した際のアンカー効果が大きくなり、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できることを見出し、本発明を完成させた。なお、本願におけるＲｚは表面の十点平均粗さ（ＪＩＳ　Ｂ０６０１－１９９４）を示すものとする。 The present inventors have intensively studied a light-emitting element that can suppress the occurrence of resin peeling when resin sealing is performed without reducing resin adhesion. As a result, when the surface roughness of the SiO 2 film has irregularities with Rz exceeding 5 nm, the anchor effect when the resin is coated is increased, the resin adhesion is increased, and the resin is sealed. The inventors have found that it is possible to suppress the occurrence of resin peeling, and have completed the present invention. In the present application, R z represents the surface ten-point average roughness (JIS B0601-1994).
　以下、本発明について、実施態様の一例として、図を参照しながら詳細に説明するが、本発明はこれに限定されるものではない。 Hereinafter, the present invention will be described in detail as an example of an embodiment with reference to the drawings, but the present invention is not limited thereto.
（第一の実施形態）
　まず、図１を参照しながら、本発明の第一の実施形態となる発光素子について説明する。
　図１に本発明の第一の実施形態となる発光素子１０を示す。
　この発光素子１０は、第二電極１６２と第二接合金属層１３１を有する支持基板１３０と、第一接合金属層１２２上に面内の一部に導電部１２１を有する界面ＳｉＯ２部１２０が設けられ、その上に第二導電型電流伝播層１０７（厚さ０．５～５．０μｍ）、電流伝播層１０７との格子不整を緩和する第二導電型緩衝層１０６、第二導電型第二半導体層１０５（厚さ０．５～１．０μｍ）、活性層１０４（厚さ層０．１～１．０μｍ）、第一導電型第一半導体層１０３（厚さ０．５～１．０μｍ）が積層され、その上に第一電極１６１が形成され、半導体層表面にＳｉＯ２膜１７０が形成された基板とが接合された発光素子であり、ＳｉＯ２膜１７０の表面にＲｚが５ｎｍを超える凹凸が形成されている。ここで、形成される凹凸のＲｚは、５０ｎｍ以上であることが好ましく、１００ｎｍ以上であることがより好ましい。また、凹凸のＲｚの上限は、可視発光波長以下の７８０ｎｍが好ましい。
　このようにＳｉＯ２膜１７０の表面にＲｚが５ｎｍを超える凹凸が形成されていることで、樹脂を被覆した際のアンカー効果が大きくなり、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できる。 (First embodiment)
First, a light-emitting element according to a first embodiment of the present invention will be described with reference to FIG.
FIG. 1 shows a light emitting device 10 according to a first embodiment of the present invention.
The light emitting element 10 includes a support substrate 130 having a second electrode 162 and a second bonding metal layer 131, and an interface SiO 2 portion 120 having a conductive portion 121 in a part of the surface on the first bonding metal layer 122. The second conductivity type current propagation layer 107 (thickness 0.5 to 5.0 μm), the second conductivity type buffer layer 106 for relaxing the lattice irregularity with the current propagation layer 107, the second conductivity type second Semiconductor layer 105 (thickness 0.5 to 1.0 μm), active layer 104 (thickness layer 0.1 to 1.0 μm), first conductivity type first semiconductor layer 103 (thickness 0.5 to 1.0 μm) ), A first electrode 161 is formed thereon, and a substrate on which the SiO 2 film 170 is formed on the surface of the semiconductor layer is bonded, and the R z is 5 nm on the surface of the SiO 2 film 170. Concavities and convexities that exceed are formed. Here, Rz of the unevenness formed is preferably 50 nm or more, and more preferably 100 nm or more. Further, the upper limit of the Rz of the unevenness is preferably 780 nm which is not more than the visible light emission wavelength.
As described above, the surface roughness of the SiO 2 film 170 having Rz exceeding 5 nm increases the anchor effect when the resin is coated, increases the resin adhesion, and performs resin sealing. It can suppress that resin peeling generate | occur | produces in the case.
　なお、第一導電型第一半導体層１０３、活性層１０４、第二導電型第二半導体層１０５、第二導電型緩衝層１０６の材料は（ＡｌｘＧａ１－ｘ）ｙＩｎ１－ｙＰ（０≦ｘ≦１、０≦ｙ≦１）あるいはＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦１）とすることができる。また、電流伝播層１０７はＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦１）またはＧａＡｓｗＰ１－ｗ（０≦ｗ≦１）とすることができる。また、例えば、第一半導体層１０３は二種類以上のＡｌ組成からなる層からなり、活性層１０４に近い側に層（第二の層）１０３Ｂを、第一電極１６１に近い側にＡｌ組成の低い層（第一の層）１０３Ａを有する構成とすることができる（図１参照）。第二の層１０３Ｂはクラッド層の機能を有する機能層であり、単一組成あるいは単一条件層を意味しない。 The materials of the first conductive type first semiconductor layer 103, the active layer 104, the second conductive type second semiconductor layer 105, and the second conductive type buffer layer 106 are (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) or Al z Ga 1-z As (0 ≦ z ≦ 1). The current propagation layer 107 can be made of Al z Ga 1-z As (0 ≦ z ≦ 1) or GaAs w P 1-w (0 ≦ w ≦ 1). Further, for example, the first semiconductor layer 103 is composed of a layer having two or more types of Al composition, and the layer (second layer) 103B is closer to the active layer 104 and the Al composition is closer to the first electrode 161. A structure having a lower layer (first layer) 103A can be employed (see FIG. 1). The second layer 103B is a functional layer having a function of a clad layer, and does not mean a single composition or a single condition layer.
　ここで、発光部１０８の表面の少なくとも一部（すなわち、第一半導体層１０３の表面の一部）が粗面化されているものであることが好ましい。このような構成により、発光素子の発光効率を向上させることができる。 Here, it is preferable that at least a part of the surface of the light emitting unit 108 (that is, a part of the surface of the first semiconductor layer 103) is roughened. With such a configuration, the light emission efficiency of the light emitting element can be improved.
　次に、このような第一の実施形態となる発光素子の製造方法を図５～８により説明する。 Next, a method for manufacturing the light emitting device according to the first embodiment will be described with reference to FIGS.
　図５に示すように結晶軸が［００１］方向より［１１０］方向に傾斜した基板（出発基板）１０１を準備する（基板１０１としては、ＧａＡｓまたはＧｅを好適に用いることができる）。基板１０１を上記材料から選択すれば、活性層１０４の材料を格子整合系でエピタキシャル成長を行うことができるため、活性層の品質を向上させやすく、輝度上昇や寿命特性の向上が得られる。 As shown in FIG. 5, a substrate (starting substrate) 101 whose crystal axis is inclined in the [110] direction from the [001] direction is prepared (GaAs or Ge can be suitably used as the substrate 101). If the substrate 101 is selected from the above materials, the material of the active layer 104 can be epitaxially grown in a lattice-matched system, so that the quality of the active layer can be easily improved, and luminance can be increased and lifetime characteristics can be improved.
　次に、出発基板１０１上に、基板と格子定数が略同一の第一導電型の第一半導体層１０３、活性層１０４、第二導電型の第二半導体層１０５、電流伝播層１０７をエピタキシャル成長により順次形成する。また、出発基板１０１と第一半導体層１０３の間には、基板除去用の選択エッチング層１０２が挿入される。選択エッチング層１０２は二層以上の層構造からなり、出発基板１０１に接する層１０２Ａ、第一半導体層１０３に接する層１０２Ｂを少なくとも有する。層１０２Ａと層１０２Ｂは異なる材料あるいは組成から構成しても良い。 Next, a first conductive type first semiconductor layer 103, an active layer 104, a second conductive type second semiconductor layer 105, and a current propagation layer 107 having substantially the same lattice constant as the substrate are epitaxially grown on the starting substrate 101. Sequentially formed. A selective etching layer 102 for removing the substrate is inserted between the starting substrate 101 and the first semiconductor layer 103. The selective etching layer 102 has a layer structure of two or more layers, and has at least a layer 102A in contact with the starting substrate 101 and a layer 102B in contact with the first semiconductor layer 103. The layers 102A and 102B may be composed of different materials or compositions.
　更に具体的に説明すると、出発基板１０１上に例えばＭＯＶＰＥ法（有機金属気相成長法）やＭＢＥ（分子線エピタキシー法）、ＣＢＥ（化学線エピタキシー法）により第一導電型の第一半導体層１０３、活性層１０４、第二導電型の第二半導体層１０５から成る発光部１０８上に、緩衝層１０６、電流伝播層１０７をこの順にエピタキシャル成長したエピタキシャル基板１０９を作製する。 More specifically, the first conductive type first semiconductor layer 103 is formed on the starting substrate 101 by, for example, MOVPE (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), or CBE (chemical beam epitaxy). Then, an epitaxial substrate 109 is produced by epitaxially growing a buffer layer 106 and a current propagation layer 107 in this order on the light emitting portion 108 composed of the active layer 104 and the second conductive type second semiconductor layer 105.
　活性層１０４は発光波長に応じて（ＡｌｘＧａ１－ｘ）ｙＩｎ１－ｙＰ（０≦ｘ≦１、０．４≦ｙ≦０．６）またはＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦０．４５）で形成される。可視光照明に適用する場合、ＡｌＧａＩｎＰを選択するのが好適であり、赤外照明に適用する場合、ＡｌＧａＡｓあるいはＩｎＧａＡｓを選択するのが好適である。ただし、活性層の設計に関しては、超格子等の利用により波長は材料組成に起因する波長以外に調整可能であるため、上記の材料に限られない。 The active layer 104 has (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0.4 ≦ y ≦ 0.6) or Al z Ga 1-z As (0 ≦ z ≦ 0.45). When it is applied to visible light illumination, it is preferable to select AlGaInP, and when it is applied to infrared illumination, it is preferable to select AlGaAs or InGaAs. However, the design of the active layer is not limited to the above materials because the wavelength can be adjusted by using a superlattice or the like other than the wavelength resulting from the material composition.
　第一半導体層１０３、第二半導体層１０５はＡｌＧａＩｎＰもしくはＡｌＧａＡｓが選択され、その選択は活性層１０４と必ずしも同一の材料系でなくともよい。 AlGaInP or AlGaAs is selected for the first semiconductor layer 103 and the second semiconductor layer 105, and the selection is not necessarily the same material system as that of the active layer 104.
　なお、第一半導体層１０３、活性層１０４あるいは第二半導体層１０５は特性向上のため、各層内には複数層が含まれるのが一般的であり、第一半導体層１０３、活性層１０４あるいは第二半導体層１０５が単一層であることに限定されない。 The first semiconductor layer 103, the active layer 104, or the second semiconductor layer 105 generally includes a plurality of layers in order to improve characteristics, and the first semiconductor layer 103, the active layer 104, or the second semiconductor layer 105 is generally included in each layer. The two semiconductor layers 105 are not limited to being a single layer.
　電流伝播層１０７としては、ＡｌＧａＡｓまたはＧａＡｓＰまたはＧａＰを好適に用いる事ができる。 As the current propagation layer 107, AlGaAs, GaAsP, or GaP can be suitably used.
　電流伝播層１０７をＧａＡｓｘＰ１－ｘ（０≦ｘ＜１）で形成した場合、緩衝層１０６はＩｎＧａＰあるいはＡｌＩｎＰで形成するのが最も好適である。ＧａＡｓｘＰ１－ｘ（ｘ≠１）と、ＡｌＧａＩｎＰ系材料またはＡｌＧａＡｓ系材料との間には格子不整が存在するため、ＧａＡｓｘＰ１－ｘ（ｘ≠１）には高密度のひずみや貫通転位が入る。貫通転位密度は組成ｘにより調整可能である。 When the current propagation layer 107 is formed of GaAs x P 1-x (0 ≦ x <1), the buffer layer 106 is most preferably formed of InGaP or AlInP. Since there is a lattice mismatch between GaAs x P 1-x (x ≠ 1) and the AlGaInP-based material or AlGaAs-based material, GaAs x P 1-x (x ≠ 1) has high-density strain and Threading dislocation enters. The threading dislocation density can be adjusted by the composition x.
　次に図６に示すように、エピタキシャル基板１０９における電流伝播層１０７上の少なくとも一部に界面ＳｉＯ２部１２０を堆積し、界面ＳｉＯ２部を有しない領域の少なくとも一部に界面金属部（導電部）１２１を設け、界面ＳｉＯ２部１２０と界面金属部１２１の少なくとも一部を被覆する第一接合金属層１２２を設けて、第一積層体１２３を形成する。 Next, as shown in FIG. 6, the interface SiO 2 part 120 is deposited on at least a part of the current propagation layer 107 in the epitaxial substrate 109, and the interface metal part (conductive layer) is formed on at least a part of the region having no interface SiO 2 part. Part) 121 and a first bonding metal layer 122 that covers at least a part of the interface SiO 2 part 120 and the interface metal part 121 are provided to form the first laminated body 123.
　次に、永久基板（支持基板）１３０上に第二接合金属層１３１を設けて、第二積層体１３２を形成する。第一接合金属層１２２と第二接合金属層１３１の少なくとも一部を接して、第一積層体１２３と第二積層体１３２とを１０００Ｎの圧力と１５０℃以上の熱を加えて接合した接合基板１４０を形成する。 Next, the second bonding metal layer 131 is provided on the permanent substrate (support substrate) 130 to form the second laminated body 132. A bonded substrate obtained by contacting at least a part of the first bonding metal layer 122 and the second bonding metal layer 131 and bonding the first laminate 123 and the second laminate 132 by applying a pressure of 1000 N and heat of 150 ° C. or more. 140 is formed.
　次に図７に示すように接合基板１４０より出発基板１０１をウェットエッチング法により除去して、第一半導体層１０３を露出させる。エッチングに際しては、アンモニア水と過酸化水素水の混合液にてエッチングを行う。エッチングストップ層１０２Ａを出発基板１０１と異なる材料にしておくことで、アンモニア水と過酸化水素水の混合液によるエッチングを選択的に停止させることができる。エッチングストップ層１０２ＡとしてＡｌＩｎＰを用いることができる。 Next, as shown in FIG. 7, the starting substrate 101 is removed from the bonding substrate 140 by a wet etching method to expose the first semiconductor layer 103. In the etching, etching is performed with a mixed solution of ammonia water and hydrogen peroxide water. By using a material different from that of the starting substrate 101 for the etching stop layer 102A, etching using a mixed solution of ammonia water and hydrogen peroxide water can be selectively stopped. AlInP can be used as the etching stop layer 102A.
　出発基板１０１除去後、エッチングストップ層１０２Ａを除去する。エッチングストップ層１０２ＡとしてＡｌＩｎＰを用いた場合、除去には塩酸を用いることができる。エッチングストップ層１０２Ｂは塩酸によるエッチングを停止させるため、ＧａＡｓを用いることができる。 After the starting substrate 101 is removed, the etching stop layer 102A is removed. When AlInP is used as the etching stop layer 102A, hydrochloric acid can be used for removal. The etching stop layer 102B can be made of GaAs in order to stop etching with hydrochloric acid.
　次に、第一半導体層１０３に接する第一電極１６１を形成し、永久基板１３０に接する第二電極１６２を形成し、第一半導体層１０３の少なくとも一部を被覆する絶縁層１７０を形成して発光素子基板１７１を作製する。 Next, a first electrode 161 in contact with the first semiconductor layer 103 is formed, a second electrode 162 in contact with the permanent substrate 130 is formed, and an insulating layer 170 covering at least a part of the first semiconductor layer 103 is formed. A light-emitting element substrate 171 is manufactured.
　第一導電型がｎ型の場合、第一電極１６１はＡｕ、Ａｇ、Ａｌ、Ｎｉ、Ｐｄ、Ｇｅ、Ｓｉ、Ｓｎのうちの少なくとも一種類以上の材料を含み、１００ｎｍ以上の膜厚を有するものとすることができる。第一導電型がｐ型の場合、Ａｕ、Ｂｅ、Ｍｇ、Ｚｎのうちの少なくとも一種類以上の材料を含み、１００ｎｍ以上の膜厚を有するものとすることができる。第二導電型がｎ型の場合、第二電極１６２はＡｕ、Ａｇ、Ａｌ、Ｎｉ、Ｐｄ、Ｇｅ、Ｓｉ、Ｓｎのうちの少なくとも一種類以上の材料を含み、１００ｎｍ以上の膜厚を有するものとすることができる。第二導電型がｐ型の場合、Ａｕ、Ｂｅ、Ｍｇ、Ｚｎのうちの少なくとも一種類以上の材料を含み、１００ｎｍ以上の膜厚を有するものとすることができる。 When the first conductivity type is n-type, the first electrode 161 includes at least one material selected from Au, Ag, Al, Ni, Pd, Ge, Si, and Sn, and has a film thickness of 100 nm or more. It can be. When the first conductivity type is p-type, it may include at least one material of Au, Be, Mg, and Zn and have a thickness of 100 nm or more. When the second conductivity type is n-type, the second electrode 162 includes at least one material of Au, Ag, Al, Ni, Pd, Ge, Si, and Sn and has a thickness of 100 nm or more. It can be. When the second conductivity type is p-type, it can include at least one material of Au, Be, Mg, and Zn and have a film thickness of 100 nm or more.
　次に図８に示すように発光素子基板１７１の絶縁層１７０に対して弗酸と１価～４価の無機酸あるいは有機酸を混合した液を用いてフロスト処理する。ここで無機酸は硫酸・塩酸・燐酸のうちの少なくともいずれか１種であり、有機酸はマロン酸、酢酸、クエン酸、酒石酸、リンゴ酸のうちの少なくともいずれか１種とすることができる。こうして、絶縁層１７０の表面に凹凸を有するフロスト処理基板１８０を作製する。次にフロスト処理基板１８０を個別ダイスに分離し、第一電極１６１にワイヤーを設け、第二電極１６２を導電性樹脂でステムに固定したのち、エポキシ樹脂で封止して発光ダイオードを作製する。 Next, as shown in FIG. 8, the insulating layer 170 of the light-emitting element substrate 171 is subjected to a frost treatment using a liquid in which hydrofluoric acid and a monovalent to tetravalent inorganic acid or organic acid are mixed. Here, the inorganic acid is at least one of sulfuric acid, hydrochloric acid, and phosphoric acid, and the organic acid can be at least one of malonic acid, acetic acid, citric acid, tartaric acid, and malic acid. In this way, the frosted substrate 180 having unevenness on the surface of the insulating layer 170 is manufactured. Next, the frosted substrate 180 is separated into individual dice, a wire is provided on the first electrode 161, the second electrode 162 is fixed to the stem with a conductive resin, and then sealed with an epoxy resin to produce a light emitting diode.
（第二の実施形態）
　次に、図２を参照しながら、本発明の第二の実施形態となる発光素子について説明する。
　図２に本発明の第二の実施形態となる発光素子２０を示す。
　この発光素子２０は、第二電極２６２と第二接合金属層２３１を有する支持基板２３０と、第一接合金属層２２２上にコンタクト部２０８を有する界面透明導電膜層２２０、その上に第二導電型電流伝播層２０７（厚さ０．５～５．０μｍ）、電流伝播層２０７との格子不整を緩和する第二導電型緩衝層２０６、第二導電型第二半導体層２０５（厚さ０．５～１．０μｍ）、活性層２０４（厚さ層０．１～１．０μｍ）、第一導電型第一半導体層２０３（厚さ０．５～１．０μｍ）が積層され、その上に第一電極２６１が形成され、半導体層表面にＳｉＯ２膜２７０が形成された基板とが接合された発光素子であり、ＳｉＯ２膜２７０の表面にＲｚが５ｎｍを超える凹凸が形成されている。ここで、形成される凹凸のＲｚは、５０ｎｍ以上であることが好ましく、１００ｎｍ以上であることがより好ましい。第二の実施形態においても、ＳｉＯ２膜２７０の表面にＲｚが５ｎｍを超える凹凸が形成されていることで、第一の実施形態と同様に樹脂を被覆した際のアンカー効果が大きくなり、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できる。 (Second embodiment)
Next, a light-emitting element according to a second embodiment of the present invention will be described with reference to FIG.
FIG. 2 shows a light emitting device 20 according to the second embodiment of the present invention.
The light emitting element 20 includes a support substrate 230 having a second electrode 262 and a second bonding metal layer 231, an interfacial transparent conductive film layer 220 having a contact portion 208 on the first bonding metal layer 222, and a second conductive film on the support conductive film 230. Type current propagation layer 207 (thickness 0.5 to 5.0 μm), second conductivity type buffer layer 206 that relaxes lattice irregularities with current propagation layer 207, and second conductivity type second semiconductor layer 205 (thickness 0. 5 μm). 5 to 1.0 μm), an active layer 204 (thickness layer 0.1 to 1.0 μm), and a first conductivity type first semiconductor layer 203 (thickness 0.5 to 1.0 μm) are stacked on top of each other. A light-emitting element in which a first electrode 261 is formed and a substrate on which a SiO 2 film 270 is formed on a surface of a semiconductor layer is bonded, and unevenness having an R z exceeding 5 nm is formed on the surface of the SiO 2 film 270. . Here, Rz of the unevenness formed is preferably 50 nm or more, and more preferably 100 nm or more. Also in the second embodiment, by forming irregularities with R z exceeding 5 nm on the surface of the SiO 2 film 270, the anchor effect when the resin is coated is increased as in the first embodiment, It is possible to increase resin adhesion and suppress the occurrence of resin peeling when resin sealing is performed.
　なお、第一導電型第一半導体層２０３、活性層２０４、第二導電型第二半導体層２０５、第二導電型緩衝層２０６の材料は（ＡｌｘＧａ１－ｘ）ｙＩｎ１－ｙＰ（０≦ｘ≦１、０≦ｙ≦１）あるいはＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦１）とすることができる。また、電流伝播層２０７はＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦１）またはＧａＡｓｗＰ１－ｗ（０≦ｗ≦１）とすることができる。また、例えば、第一半導体層２０３は二種類以上のＡｌ組成からなる層からなり、活性層２０４に近い側に層（第二の層）２０３Ｂを、第一電極２６１に近い側にＡｌ組成の低い層（第一の層）２０３Ａを有する構成とすることができる（図２参照）。第二の層２０３Ｂはクラッド層の機能を有する機能層であり、単一組成あるいは単一条件層を意味しない。
　また、界面透明導電膜層２２０は、Ｍｇ、Ｎｉ、Ｃｕ、Ｇａ、Ｉｎ、Ｓｎのうちいずれか一種類以上を含む酸化物から構成される。 The materials of the first conductivity type first semiconductor layer 203, the active layer 204, the second conductivity type second semiconductor layer 205, and the second conductivity type buffer layer 206 are (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) or Al z Ga 1-z As (0 ≦ z ≦ 1). In addition, the current propagation layer 207 can be made of Al z Ga 1-z As (0 ≦ z ≦ 1) or GaAs w P 1-w (0 ≦ w ≦ 1). Further, for example, the first semiconductor layer 203 is composed of a layer having two or more types of Al composition, and the layer (second layer) 203B is closer to the active layer 204 and the Al composition is closer to the first electrode 261. A structure having a lower layer (first layer) 203A can be employed (see FIG. 2). The second layer 203B is a functional layer having the function of a cladding layer, and does not mean a single composition or a single condition layer.
The interfacial transparent conductive film layer 220 is composed of an oxide containing at least one of Mg, Ni, Cu, Ga, In, and Sn.
　次に、このような第二の実施形態となる発光素子２０の製造方法を図９～１２により説明する。 Next, a method for manufacturing the light emitting element 20 according to the second embodiment will be described with reference to FIGS.
　図９に示すように結晶軸が［００１］方向より［１１０］方向に傾斜した基板（出発基板）２０１を準備する（基板２０１としては、ＧａＡｓまたはＧｅを好適に用いることができる）。 As shown in FIG. 9, a substrate (starting substrate) 201 whose crystal axis is inclined in the [110] direction from the [001] direction is prepared (GaAs or Ge can be suitably used as the substrate 201).
　次に、出発基板２０１上に、基板と格子定数が略同一の第一導電型の第一半導体層２０３、活性層２０４、第二導電型の第二半導体層２０５、電流伝播層２０７、コンタクト層２０８をエピタキシャル成長により順次形成し、エピタキシャル基板２１０を形成する。なお、第一半導体層２０３、活性層２０４、第二半導体層２０５は、発光部２０９を構成する。また、出発基板２０１と第一半導体層２０３の間には、基板除去用の選択エッチング層２０２が挿入される。選択エッチング層は二層以上の層構造からなり、出発基板に接する層２０２Ａ、第一半導体層に接する層２０２Ｂを少なくとも有する。層２０２Ａと層２０２Ｂは異なる材料あるいは組成から構成しても良い。 Next, on the starting substrate 201, a first conductivity type first semiconductor layer 203, an active layer 204, a second conductivity type second semiconductor layer 205, a current propagation layer 207, and a contact layer having substantially the same lattice constant as the substrate. 208 are sequentially formed by epitaxial growth to form an epitaxial substrate 210. Note that the first semiconductor layer 203, the active layer 204, and the second semiconductor layer 205 constitute a light emitting unit 209. A selective etching layer 202 for removing the substrate is inserted between the starting substrate 201 and the first semiconductor layer 203. The selective etching layer has a layer structure of two or more layers, and has at least a layer 202A in contact with the starting substrate and a layer 202B in contact with the first semiconductor layer. The layers 202A and 202B may be composed of different materials or compositions.
　第一半導体層２０３、活性層２０４、第二半導体層２０５、電流伝播層２０７は、第一の実施形態の第一半導体層１０３、活性層１０４、第二半導体層１０５、電流伝播層１０７と同様の材料を用いることができ、同様の構成とすることができる。コンタクト層２０８は電流伝播層２０７と同一の材料で構成しても良いし、異なる材料で構成してもかまわない。 The first semiconductor layer 203, the active layer 204, the second semiconductor layer 205, and the current propagation layer 207 are the same as the first semiconductor layer 103, the active layer 104, the second semiconductor layer 105, and the current propagation layer 107 of the first embodiment. The same material can be used. The contact layer 208 may be made of the same material as the current propagation layer 207 or may be made of a different material.
　次に図１０に示すようにエピタキシャル基板２１０において、コンタクト層２０８の一部を除去し、コンタクト部２０８と電流伝播層２０７の両者の少なくとも一部に接するように第一透明導電膜２２０を堆積し、第一透明導電膜２２０の少なくとも一部を被覆する第一接合金属層２２２を設けて、第一積層体２２３を形成する。 Next, as shown in FIG. 10, in the epitaxial substrate 210, a part of the contact layer 208 is removed, and a first transparent conductive film 220 is deposited so as to be in contact with at least a part of both the contact part 208 and the current propagation layer 207. Then, a first bonding metal layer 222 that covers at least a part of the first transparent conductive film 220 is provided to form the first laminate 223.
　次に、永久基板（支持基板）２３０上に第二接合金属層２３１を設けて、第２積層体２３２を形成する。第一接合金属層２２２と第二接合金属層２３１の少なくとも一部を接して、第一積層体２２３と第２積層体２３２とを１０００Ｎの圧力と１５０℃以上の熱を加えて接合した接合基板２４０を形成する。 Next, the second bonding metal layer 231 is provided on the permanent substrate (supporting substrate) 230 to form the second stacked body 232. A bonded substrate obtained by contacting at least a part of the first bonding metal layer 222 and the second bonding metal layer 231 and bonding the first laminate 223 and the second laminate 232 by applying a pressure of 1000 N and heat of 150 ° C. or more. 240 is formed.
　次に図１１に示すように接合基板２４０より出発基板２０１をウェットエッチング法により除去して、第一半導体層２０３を露出させる。エッチングに際しては、第一の実施形態と同様にして行うことができる。 Next, as shown in FIG. 11, the starting substrate 201 is removed from the bonding substrate 240 by a wet etching method to expose the first semiconductor layer 203. Etching can be performed in the same manner as in the first embodiment.
　出発基板２０１除去後、エッチングストップ層２０２Ａを除去する。エッチングストップ層２０２Ａ、２０２Ｂは、第一の実施形態のエッチングストップ層１０２Ａ、１０２Ｂと同様の材料を用いることができる。 After removing the starting substrate 201, the etching stop layer 202A is removed. For the etching stop layers 202A and 202B, the same material as the etching stop layers 102A and 102B of the first embodiment can be used.
　次に、第一半導体層２０３に接する第一電極２６１を形成し、永久基板２３０に接する第二電極２６２を形成し、第一半導体層２０３の少なくとも一部を被覆する絶縁層２７０を形成して発光素子基板２７１を作製する。第一電極２６１、第二電極２６２は、第一の実施形態の第一電極１６１、第二電極１６２と同様な材料を用いることができ、同様の膜厚とすることができる。 Next, a first electrode 261 in contact with the first semiconductor layer 203 is formed, a second electrode 262 in contact with the permanent substrate 230 is formed, and an insulating layer 270 that covers at least a part of the first semiconductor layer 203 is formed. A light-emitting element substrate 271 is manufactured. The first electrode 261 and the second electrode 262 can be made of the same material as the first electrode 161 and the second electrode 162 of the first embodiment, and can have the same film thickness.
　次に図１２に示すように、発光素子基板２７１の絶縁層２７０に対して、第一の実施形態と同様にしてフロスト処理する。こうして、絶縁層２７０の表面に凹凸を有するフロスト処理基板２８０を作製する。次にフロスト処理基板２８０を個別ダイスに分離し、第一電極２６１にワイヤーを設け、第二電極２６２を導電性樹脂でステムに固定したのち、エポキシ樹脂で封止した発光ダイオードを作製する。 Next, as shown in FIG. 12, the insulating layer 270 of the light emitting element substrate 271 is subjected to a frost treatment in the same manner as in the first embodiment. Thus, the frosted substrate 280 having unevenness on the surface of the insulating layer 270 is manufactured. Next, the frosted substrate 280 is separated into individual dies, a wire is provided on the first electrode 261, the second electrode 262 is fixed to the stem with a conductive resin, and then a light emitting diode sealed with an epoxy resin is manufactured.
（第三の実施形態）
　次に、図３を参照しながら、本発明の第三の実施形態となる発光素子について説明する。
　図３に本発明の第三の実施形態となる発光素子３０を示す。
　この発光素子３０は、第二誘電体膜３２１と第二接着層３２５を有する支持基板３３０と、第一接着層３２４上に第一誘電体膜３２０、その上に第二導電型電流伝播層３０７（厚さ０．５～５．０μｍ）、電流伝播層３０７との格子不整を緩和する第二導電型緩衝層３０６、第二導電型第二半導体層３０５（厚さ０．５～１．０μｍ）、活性層３０４（厚さ層０．１～１．０μｍ）、第一導電型第一半導体層３０３（厚さ０．５～１．０μｍ）が積層されその上に第一電極３５０が形成され、また、一部半導体層が第二導電型電流伝播層３０７まで切り欠かれており、切り欠かれた第二導電型電流伝播層３０７上に第二電極３５１が形成され、さらに半導体層表面にＳｉＯ２膜３７０が形成された基板とが接合された発光素子であり、ＳｉＯ２膜３７０の表面にＲｚが５ｎｍを超える凹凸が形成されている。ここで、形成される凹凸のＲｚは、５０ｎｍ以上であることが好ましく、１００ｎｍ以上であることがより好ましい。第三の実施形態においても、ＳｉＯ２膜３７０の表面にＲｚが５ｎｍを超える凹凸が形成されていることで、第一の実施形態と同様に樹脂を被覆した際のアンカー効果が大きくなり、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できる。 (Third embodiment)
Next, a light-emitting element according to a third embodiment of the present invention will be described with reference to FIG.
FIG. 3 shows a light emitting device 30 according to the third embodiment of the present invention.
The light emitting element 30 includes a support substrate 330 having a second dielectric film 321 and a second adhesive layer 325, a first dielectric film 320 on the first adhesive layer 324, and a second conductivity type current propagation layer 307 thereon. (Thickness 0.5 to 5.0 μm), second conductivity type buffer layer 306 that relaxes lattice irregularity with current propagation layer 307, second conductivity type second semiconductor layer 305 (thickness 0.5 to 1.0 μm) ), An active layer 304 (thickness layer 0.1 to 1.0 μm) and a first conductive type first semiconductor layer 303 (thickness 0.5 to 1.0 μm) are stacked, and a first electrode 350 is formed thereon. In addition, a part of the semiconductor layer is notched to the second conductivity type current propagation layer 307, and the second electrode 351 is formed on the notched second conductivity type current propagation layer 307, and further the surface of the semiconductor layer Is a light-emitting element in which a substrate on which a SiO 2 film 370 is formed is bonded, and SiO 2 Irregularities with Rz exceeding 5 nm are formed on the surface of the film 370. Here, Rz of the unevenness formed is preferably 50 nm or more, and more preferably 100 nm or more. Also in the third embodiment, by forming irregularities with R z exceeding 5 nm on the surface of the SiO 2 film 370, the anchor effect when the resin is coated is increased as in the first embodiment, It is possible to increase resin adhesion and suppress the occurrence of resin peeling when resin sealing is performed.
　なお、第一導電型第一半導体層３０３、活性層３０４、第二導電型第二半導体層３０５、第二導電型緩衝層３０６の材料は（ＡｌｘＧａ１－ｘ）ｙＩｎ１－ｙＰ（０≦ｘ≦１、０≦ｙ≦１）あるいはＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦１）とすることができる。また、電流伝播層３０７はＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦１）またはＧａＡｓｗＰ１－ｗ（０≦ｗ≦１）とすることができる。また、例えば、第一半導体層３０３は二種類以上のＡｌ組成からなる層からなり、活性層３０４に近い側に層（第二の層）３０３Ｂを、第一電極３５０に近い側にＡｌ組成の低い層（第一の層）３０３Ａを有する構成とすることができる（図３参照）。第二の層３０３Ｂはクラッド層の機能を有する機能層であり、単一組成あるいは単一条件層を意味しない。 The materials of the first conductivity type first semiconductor layer 303, the active layer 304, the second conductivity type second semiconductor layer 305, and the second conductivity type buffer layer 306 are (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) or Al z Ga 1-z As (0 ≦ z ≦ 1). The current propagation layer 307 can be Al z Ga 1-z As (0 ≦ z ≦ 1) or GaAs w P 1-w (0 ≦ w ≦ 1). Further, for example, the first semiconductor layer 303 is composed of a layer having two or more types of Al composition, and the layer (second layer) 303B is closer to the active layer 304 and the Al composition is closer to the first electrode 350. A structure having a lower layer (first layer) 303A can be employed (see FIG. 3). The second layer 303B is a functional layer having a function of a clad layer, and does not mean a single composition or a single condition layer.
　次に、このような第三の実施形態となる発光素子３０の製造方法を図１３～１７により説明する。 Next, a method for manufacturing the light emitting element 30 according to the third embodiment will be described with reference to FIGS.
　図１３に示すように結晶軸が［００１］方向より［１１０］方向に傾斜した基板（出発基板）３０１を準備する（基板３０１としては、ＧａＡｓまたはＧｅを好適に用いることができる）。 As shown in FIG. 13, a substrate (starting substrate) 301 having a crystal axis tilted in the [110] direction from the [001] direction is prepared (GaAs or Ge can be suitably used as the substrate 301).
　次に、出発基板３０１上に、基板と格子定数が略同一の第一導電型の第一半導体層３０３、活性層３０４、第二導電型の第二半導体層３０５、電流伝播層３０７をエピタキシャル成長により順次形成し、エピタキシャル基板３０９を形成する。なお、第一半導体層３０３、活性層３０４、第二半導体層３０５は、発光部３０８を構成する。また、出発基板３０１と第一半導体層３０３の間には、基板除去用の選択エッチング層３０２が挿入される。選択エッチング層３０２は二層以上の層構造からなり、出発基板に接する層３０２Ａ、第一半導体層に接する層３０２Ｂを少なくとも有する。層３０２Ａと層３０２Ｂは異なる材料あるいは組成から構成しても良い。 Next, a first conductive type first semiconductor layer 303, an active layer 304, a second conductive type second semiconductor layer 305, and a current propagation layer 307 having substantially the same lattice constant as the substrate are epitaxially grown on the starting substrate 301. The epitaxial substrate 309 is formed sequentially. Note that the first semiconductor layer 303, the active layer 304, and the second semiconductor layer 305 constitute a light emitting unit 308. A selective etching layer 302 for removing the substrate is inserted between the starting substrate 301 and the first semiconductor layer 303. The selective etching layer 302 has a layer structure of two or more layers, and has at least a layer 302A in contact with the starting substrate and a layer 302B in contact with the first semiconductor layer. The layers 302A and 302B may be made of different materials or compositions.
　第一半導体層３０３、活性層３０４、第二半導体層３０５、電流伝播層３０７は、第一の実施形態の第一半導体層１０３、活性層１０４、第二半導体層１０５、電流伝播層１０７と同様の材料を用いることができ、同様の構成とすることができる。 The first semiconductor layer 303, the active layer 304, the second semiconductor layer 305, and the current propagation layer 307 are the same as the first semiconductor layer 103, the active layer 104, the second semiconductor layer 105, and the current propagation layer 107 of the first embodiment. The same material can be used.
　次に図１４に示すようにエピタキシャル基板３０９における電流伝播層３０７上に第一ＳｉＯ２膜３２０を堆積する。第一ＳｉＯ２膜３２０は、光ＣＶＤ、スパッタ法、ＰＥＣＶＤ法にて形成することができる。 Next, as shown in FIG. 14, a first SiO 2 film 320 is deposited on the current propagation layer 307 in the epitaxial substrate 309. The first SiO 2 film 320 can be formed by optical CVD, sputtering, or PECVD.
　次に第一ＳｉＯ２膜３２０上に透明接着層３２５を形成し、第一接合基板３２６を形成する。透明接着層３２５はＢＣＢ（ベンゾシクロブテン）あるいはエポキシ等が選択可能である。形成方法はディップ法あるいはスピンコート法により形成可能な材料を選択することが好適である。例えばスピンコート法により堆積が可能なＢＣＢ材であるシクロテンの場合、第一ＳｉＯ２膜３２０上にシクロテンを滴下し、１，０００～５，０００ｒｐｍの回転数によりスピンコートを実施する。接着剤が均一に塗布できればよいため、前述のどの回転数でも選択可能だが、３，０００ｒｐｍ以上の回転数が好適である。スピンコート後、ホットプレート上に８０～１１０℃の範囲で３０秒以上保持して溶剤を揮発させる。溶剤が揮発すればよいため、前述のどの条件でも選択可能だが、温度９０℃以上、６０秒以上の保持時間を選択することが好適である。 Next, a transparent adhesive layer 325 is formed on the first SiO 2 film 320, and a first bonding substrate 326 is formed. The transparent adhesive layer 325 can be selected from BCB (benzocyclobutene) or epoxy. It is preferable to select a material that can be formed by a dipping method or a spin coating method. For example, in the case of cycloten, which is a BCB material that can be deposited by spin coating, cycloten is dropped on the first SiO 2 film 320 and spin coating is performed at a rotational speed of 1,000 to 5,000 rpm. Since any adhesive can be applied as long as the adhesive can be applied uniformly, any of the aforementioned rotational speeds can be selected, but a rotational speed of 3,000 rpm or more is suitable. After spin coating, the solvent is volatilized by holding on a hot plate at 80 to 110 ° C. for 30 seconds or more. Since the solvent only needs to be volatilized, any of the above-mentioned conditions can be selected. However, it is preferable to select a holding time of 90 ° C. or more and 60 seconds or more.
　次に透明基板（支持基板）３３０上に第二ＳｉＯ２膜３２１を堆積し、第二接合基板３３１を形成する。第二ＳｉＯ２膜３２１は、光ＣＶＤ、スパッタ法、ＰＥＣＶＤ法にて形成することができる。 Next, a second SiO 2 film 321 is deposited on the transparent substrate (support substrate) 330 to form a second bonding substrate 331. The second SiO 2 film 321 can be formed by optical CVD, sputtering, or PECVD.
　第一接合基板３２６のみに透明接着層３２５を設けた例を開示したが、第二接合基板３３１に透明接着層を設けても同様の効果が得られる。また、第一接合基板３２６及び第二接合基板３３１の両方に透明接着層を設けることもできる。 Although the example in which the transparent adhesive layer 325 is provided only on the first bonding substrate 326 has been disclosed, the same effect can be obtained even if the transparent bonding layer is provided on the second bonding substrate 331. In addition, a transparent adhesive layer can be provided on both the first bonding substrate 326 and the second bonding substrate 331.
　次に、図１４に示すように、第一接合基板３２６と第二接合基板３３１を透明接着層３２５と第二ＳｉＯ２膜３２１を対向させ、かつ接触しないように設置し、３０Ｐａ以下の真空雰囲気にする。真空雰囲気後、透明接着層３２５と第二ＳｉＯ２膜３２１を接触させ、かつ、５０００Ｎの圧力と１００～２００℃の間の温度になる様に制御して５分以上保持した後、３００℃以上の熱を加えて第一接合基板３２６と第二接合基板３３１を圧着して接合基板３４０を形成する。 Next, as shown in FIG. 14, the first bonding substrate 326 and the second bonding substrate 331 are placed so that the transparent adhesive layer 325 and the second SiO 2 film 321 face each other and do not come into contact with each other, and a vacuum atmosphere of 30 Pa or less. To. After the vacuum atmosphere, the transparent adhesive layer 325 and the second SiO 2 film 321 are brought into contact with each other and controlled so as to reach a pressure of 5000 N and a temperature between 100 to 200 ° C. for 5 minutes or more, and then 300 ° C. or more. Then, the first bonding substrate 326 and the second bonding substrate 331 are pressure-bonded to form the bonding substrate 340.
　接合基板３４０より出発基板３０１をエッチングにより除去する。エッチングに際しては、第一の実施形態と同様にして行うことができる。 The starting substrate 301 is removed from the bonding substrate 340 by etching. Etching can be performed in the same manner as in the first embodiment.
　出発基板３０１除去後、エッチングストップ層３０２Ａを除去する。エッチングストップ層３０２Ａ、３０２Ｂは、第一の実施形態のエッチングストップ層１０２Ａ、１０２Ｂと同様の材料を用いることができる。 After removing the starting substrate 301, the etching stop layer 302A is removed. The etching stop layers 302A and 302B can use the same material as the etching stop layers 102A and 102B of the first embodiment.
　次に図１５に示すように、第一半導体層３０３に接する第一電極３５０を形成する。第一電極３５０は、第一の実施形態の第一電極１６１と同様な材料を用いることができ、３００ｎｍ以上の膜厚を有するものとすることができる。次にドライ法あるいはウェット法によるエッチングによって、第一電極３５０が存在する以外の領域３６０の第一半導体層３０３、活性層３０４を切り欠いたパターンを形成する。図１５では電流伝播層３０７まで切り欠いた例を示しているが、第二半導体層３０５あるいは緩衝層３０６が露出した状態でエッチングを止めても同様の機能を有する。図１５において、領域３６０以外の領域を平坦面として表しているが、平坦面に限定されるものではなく、領域３６０以外の領域を粗面あるいは凹凸面としても良い。 Next, as shown in FIG. 15, a first electrode 350 in contact with the first semiconductor layer 303 is formed. The first electrode 350 can be made of the same material as the first electrode 161 of the first embodiment, and can have a thickness of 300 nm or more. Next, a pattern in which the first semiconductor layer 303 and the active layer 304 in the region 360 other than the area where the first electrode 350 is present is formed by etching using a dry method or a wet method. Although FIG. 15 shows an example in which the current propagation layer 307 is cut out, the same function is obtained even if the etching is stopped with the second semiconductor layer 305 or the buffer layer 306 exposed. In FIG. 15, a region other than the region 360 is represented as a flat surface. However, the region is not limited to a flat surface, and a region other than the region 360 may be a rough surface or an uneven surface.
　次に図１６に示すように、第一半導体層３０３の少なくとも一部を被覆する絶縁層３７０を形成する。絶縁層３７０は、ＳｉＯ２である。図１６では、活性層３０４、第二半導体層３０５、緩衝層３０６、電流伝播層３０７の一部を被覆する例を図示しているが、この形態に限定されない。 Next, as shown in FIG. 16, an insulating layer 370 that covers at least part of the first semiconductor layer 303 is formed. Insulating layer 370 is SiO 2. Although FIG. 16 illustrates an example in which a part of the active layer 304, the second semiconductor layer 305, the buffer layer 306, and the current propagation layer 307 is covered, the present invention is not limited to this mode.
　次に領域３６０の一部に第二電極３５１を形成した発光素子基板３７１を形成する。第二電極３５１は、第一の実施形態の第二電極１６２と同様な材料を用いることができ、３００ｎｍ以上の膜厚を有するものとすることができる。 Next, a light emitting element substrate 371 having the second electrode 351 formed on a part of the region 360 is formed. The second electrode 351 can use the same material as the second electrode 162 of the first embodiment, and can have a film thickness of 300 nm or more.
　次に図１７に示すように、発光素子基板３７１の絶縁層３７０に対して第一の実施形態と同様にして表面にフロスト処理を施し、絶縁層３７０の表面に凹凸を有するフロスト処理基板３８０を作製する。 Next, as shown in FIG. 17, the insulating layer 370 of the light emitting element substrate 371 is subjected to frost treatment on the surface in the same manner as in the first embodiment, and a frosted substrate 380 having irregularities on the surface of the insulating layer 370 is formed. Make it.
　次に、フロスト処理基板３８０をステルスダイシング法、あるいはブレードダイシング法等によって個別ダイスに分割したのち、ダイスをステムに固定し、第一電極３５０、第二電極３５１にワイヤーを設け、エポキシ樹脂で封止した発光ダイオードを作製する。 Next, after the frosted substrate 380 is divided into individual dies by a stealth dicing method or a blade dicing method, the dies are fixed to the stem, wires are provided on the first electrode 350 and the second electrode 351, and sealed with an epoxy resin. A stopped light emitting diode is produced.
（第四の実施形態）
　次に、図４を参照しながら、本発明の第四の実施形態となる発光素子について説明する。
　図４に本発明の第四の実施形態となる発光素子４０を示す。
　この発光素子４０は、第二導電型電流伝播層４０７（厚さ３０～１５０μｍ）、電流伝播層４０７との格子不整を緩和する第二導電型緩衝層４０６、第二導電型第二半導体層４０５（厚さ０．５～１．０μｍ）、活性層４０４（厚さ層０．１～１．０μｍ）、第一導電型第一半導体層４０３（厚さ０．５～１．０μｍ）が積層され、その上に第一電極４５０が形成され、また、一部半導体層が第二導電型電流伝播層４０７まで切り欠かれており、切り欠かれた第二導電型電流伝播層４０７上に第二電極４５１が形成され、さらに半導体層表面にＳｉＯ２膜４７０が形成された発光素子であり、ＳｉＯ２膜４７０の表面にＲｚが５ｎｍを超える凹凸が形成されている。ここで、形成される凹凸のＲｚは、５０ｎｍ以上であることが好ましく、１００ｎｍ以上であることがより好ましい。第四の実施形態においても、ＳｉＯ２膜４７０の表面にＲｚが５ｎｍを超える凹凸が形成されていることで、第一の実施形態と同様に樹脂を被覆した際のアンカー効果が大きくなり、樹脂密着性を増大させ、樹脂封止を行った際に樹脂剥離が発生することを抑制できる。 (Fourth embodiment)
Next, a light-emitting element according to a fourth embodiment of the present invention will be described with reference to FIG.
FIG. 4 shows a light emitting device 40 according to the fourth embodiment of the present invention.
The light emitting element 40 includes a second conductivity type current propagation layer 407 (thickness 30 to 150 μm), a second conductivity type buffer layer 406 that relaxes lattice irregularities with the current propagation layer 407, and a second conductivity type second semiconductor layer 405. (Thickness 0.5 to 1.0 μm), active layer 404 (thickness layer 0.1 to 1.0 μm), first conductivity type first semiconductor layer 403 (thickness 0.5 to 1.0 μm) are laminated The first electrode 450 is formed thereon, and a part of the semiconductor layer is notched up to the second conductivity type current propagation layer 407, and the first electrode 450 is formed on the notched second conductivity type current propagation layer 407. A light emitting element in which two electrodes 451 are formed and an SiO 2 film 470 is further formed on the surface of the semiconductor layer, and irregularities having an R z exceeding 5 nm are formed on the surface of the SiO 2 film 470. Here, Rz of the unevenness formed is preferably 50 nm or more, and more preferably 100 nm or more. Also in the fourth embodiment, by forming irregularities with R z exceeding 5 nm on the surface of the SiO 2 film 470, the anchor effect when coating the resin as in the first embodiment is increased, It is possible to increase resin adhesion and suppress the occurrence of resin peeling when resin sealing is performed.
　なお、第一導電型第一半導体層４０３、活性層４０４、第二導電型第二半導体層４０５、第二導電型緩衝層４０６の材料は（ＡｌｘＧａ１－ｘ）ｙＩｎ１－ｙＰ（０≦ｘ≦１、０≦ｙ≦１）あるいはＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦１）とすることができる。また、電流伝播層４０７はＡｌｚＧａ１－ｚＡｓ（０≦ｚ≦１）またはＧａＡｓｗＰ１－ｗ（０≦ｗ≦１）とすることができる。また、例えば、第一半導体層４０３は二種類以上のＡｌ組成からなる層からなり、活性層４０４に近い側に層（第二の層）４０３Ｂを、第一電極４５０に近い側にＡｌ組成の低い層（第一の層）４０３Ａを有する構成とすることができる（図４参照）。第二の層４０３Ｂはクラッド層の機能を有する機能層であり、単一組成あるいは単一条件層を意味しない。 The materials of the first conductive type first semiconductor layer 403, the active layer 404, the second conductive type second semiconductor layer 405, and the second conductive type buffer layer 406 are (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) or Al z Ga 1-z As (0 ≦ z ≦ 1). The current propagation layer 407 can be Al z Ga 1-z As (0 ≦ z ≦ 1) or GaAs w P 1-w (0 ≦ w ≦ 1). Further, for example, the first semiconductor layer 403 is composed of a layer having two or more types of Al composition, the layer (second layer) 403B is closer to the active layer 404, and the Al composition is closer to the first electrode 450. A structure having a lower layer (first layer) 403A can be employed (see FIG. 4). The second layer 403B is a functional layer having the function of a cladding layer, and does not mean a single composition or a single condition layer.
　次に、このような第四の実施形態となる発光素子４０の製造方法を図１８～２１により説明する。 Next, a method for manufacturing the light emitting element 40 according to the fourth embodiment will be described with reference to FIGS.
　図１８に示すように結晶軸が［００１］方向より［１１０］方向に傾斜した基板（出発基板）４０１を準備する（基板４０１としては、ＧａＡｓまたはＧｅを好適に用いることができる。 As shown in FIG. 18, a substrate (starting substrate) 401 whose crystal axis is inclined in the [110] direction from the [001] direction is prepared (GaAs or Ge can be suitably used as the substrate 401).
　次に、出発基板４０１上に、基板と格子定数が略同一の第一導電型の第一半導体層４０３、活性層４０４、第二導電型の第二半導体層４０５、電流伝播層４０７をエピタキシャル成長により順次形成し、エピタキシャル基板４０９を形成する。なお、第一半導体層４０３、活性層４０４、第二半導体層４０５は、発光部４０８を構成する。また、出発基板４０１と第一半導体層４０３の間には、基板除去用の選択エッチング層４０２が挿入される。選択エッチング層は二層以上の層構造からなり、出発基板に接する層４０２Ａ、第一半導体層に接する層４０２Ｂを少なくとも有する。層４０２Ａと層４０２Ｂは異なる材料あるいは組成から構成しても良い。 Next, a first conductivity type first semiconductor layer 403, an active layer 404, a second conductivity type second semiconductor layer 405, and a current propagation layer 407 having substantially the same lattice constant as the substrate are epitaxially grown on the starting substrate 401. The epitaxial substrate 409 is formed sequentially. Note that the first semiconductor layer 403, the active layer 404, and the second semiconductor layer 405 constitute a light emitting unit 408. Further, a selective etching layer 402 for removing the substrate is inserted between the starting substrate 401 and the first semiconductor layer 403. The selective etching layer has a layer structure of two or more layers, and has at least a layer 402A in contact with the starting substrate and a layer 402B in contact with the first semiconductor layer. The layers 402A and 402B may be made of different materials or compositions.
　第一半導体層４０３、活性層４０４、第二半導体層４０５、電流伝播層４０７は、第一の実施形態の第一半導体層１０３、活性層１０４、第二半導体層１０５、電流伝播層１０７と同様の材料を用いることができ、同様の構成とすることができる。
　また、第一半導体層４０３は二種類以上のＡｌ組成からなる層からなり、活性層４０４に近い側に層（第二の層）４０３Ｂを、出発基板４０１に近い側にＡｌ組成の低い層（第一の層）４０３Ａを有する構成とすることができる。層４０３Ｂはクラッド層の機能を有する機能層であり、単一組成あるいは単一条件層を意味しない。 The first semiconductor layer 403, the active layer 404, the second semiconductor layer 405, and the current propagation layer 407 are the same as the first semiconductor layer 103, the active layer 104, the second semiconductor layer 105, and the current propagation layer 107 of the first embodiment. The same material can be used.
The first semiconductor layer 403 is made of a layer having two or more types of Al composition. The layer (second layer) 403B is closer to the active layer 404 and the layer with lower Al composition is closer to the starting substrate 401 ( The first layer) 403A can be employed. The layer 403B is a functional layer having a function of a clad layer, and does not mean a single composition or a single condition layer.
　次に図１９に示すように、出発基板４０１をエッチングにより除去する。エッチングに際しては、第一の実施形態と同様にして行うことができる。 Next, as shown in FIG. 19, the starting substrate 401 is removed by etching. Etching can be performed in the same manner as in the first embodiment.
　出発基板４０１除去後、エッチングストップ層４０２Ａを除去する。エッチングストップ層４０２Ａ、４０２Ｂは、第一の実施形態のエッチングストップ層１０２Ａ、１０２Ｂと同様の材料を用いることができる。 After removing the starting substrate 401, the etching stop layer 402A is removed. The etching stop layers 402A and 402B can use the same material as the etching stop layers 102A and 102B of the first embodiment.
　次に、ドライ法あるいはウェット法によるエッチングによって第一半導体層４０３、活性層４０４の領域４６０を切り欠いたパターンを形成する。図１９では電流伝播層４０７まで切り欠いた例を図示しているが、第二半導体層４０５あるいは緩衝層４０６が露出した状態でエッチングを止めても同様の機能を有する。図１９の例において、領域４６０以外の領域を平坦面として表しているが、平坦面に限定されるものではなく、領域４６０以外の領域を粗面あるいは凹凸面としても良い。 Next, a pattern in which the region 460 of the first semiconductor layer 403 and the active layer 404 is notched is formed by etching by a dry method or a wet method. Although FIG. 19 shows an example in which the current propagation layer 407 is cut out, the same function is obtained even if etching is stopped with the second semiconductor layer 405 or the buffer layer 406 exposed. In the example of FIG. 19, a region other than the region 460 is represented as a flat surface. However, the region is not limited to a flat surface, and a region other than the region 460 may be a rough surface or an uneven surface.
　次に、図２０に示すように、第一半導体層４０３の少なくとも一部に接する第一電極４５０と、領域４６０の少なくとも一部と、領域４６０以外の領域の少なくとも一部を被覆する様に絶縁層４７０を形成する。絶縁層４７０は、ＳｉＯ２である。そして領域４６０の一部に第二電極４５１を形成した発光素子基板４７１を形成する。 Next, as shown in FIG. 20, the first electrode 450 in contact with at least part of the first semiconductor layer 403, at least part of the region 460, and at least part of the region other than the region 460 are insulated. Layer 470 is formed. Insulating layer 470 is SiO 2. Then, a light emitting element substrate 471 in which the second electrode 451 is formed in part of the region 460 is formed.
　第一電極４５０は、第一の実施形態の第一電極１６１と同様な材料を用いることができ、３００ｎｍ以上の膜厚を有するものとすることができる。第二電極４５１は、第一の実施形態の第二電極１６２と同様な材料を用いることができ、３００ｎｍ以上の膜厚を有するものとすることができる。 The first electrode 450 can be made of the same material as the first electrode 161 of the first embodiment, and can have a thickness of 300 nm or more. The second electrode 451 can use the same material as the second electrode 162 of the first embodiment, and can have a film thickness of 300 nm or more.
　次に、図２１に示すように、発光素子基板４７１の絶縁層４７０に対して第一の実施形態と同様にして表面にフロスト処理を施し、絶縁層４７０の表面に凹凸を有するフロスト処理基板４８０を作製する。 Next, as shown in FIG. 21, the surface of the insulating layer 470 of the light-emitting element substrate 471 is subjected to a frost treatment in the same manner as in the first embodiment, and the surface of the insulating layer 470 has a frost treatment substrate 480. Is made.
　次に、ステルスダイシング法、スクライブ法、あるいはブレードダイシング法等によって個別ダイスに分割したのちダイスをステムに固定し、第一電極４５０、第二電極４５１にワイヤーを設け、エポキシ樹脂で封止した発光ダイオードを作製する。 Next, after dividing into individual dies by a stealth dicing method, a scribe method, a blade dicing method, etc., the dice are fixed to the stem, wires are provided on the first electrode 450 and the second electrode 451, and light emission is sealed with an epoxy resin A diode is fabricated.
　以下、実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれらに限定されるものではない。 Hereinafter, the present invention will be described more specifically with reference to Examples and Comparative Examples, but the present invention is not limited to these.
（実施例１）
　図１に示すような発光素子１０を作製した。この発光素子１０の第一半導体層１０３、活性層１０４、第二半導体層１０５は同一材料であるＡｌＩｎＧａＰとした。また、第一半導体層１０３は二種類以上のＡｌ組成からなる層からなり、活性層１０４に近い側に層（第二の層）１０３Ｂを、第一電極１６１に近い側にＡｌ組成の低い層（第１の層）１０３Ａを有する。第二の層１０３Ｂはクラッド層の機能を有する機能層である。また、第一導電型はｎ型で第一電極１６１の電極材料はＡｕＧｅＮｉの合金を選択し、その膜厚を５００ｎｍとした。第二導電型はｐ型で第二電極１６２の電極材料はＡｕＢｅの合金を選択し、その膜厚を５００ｎｍとした。絶縁層１７０はＴＥＯＳとＯ２を原料とするＰ－ＣＶＤ法によりＳｉＯ２膜を形成した。また、膜厚は３００ｎｍとした。 (Example 1)
A light emitting device 10 as shown in FIG. 1 was manufactured. The first semiconductor layer 103, the active layer 104, and the second semiconductor layer 105 of the light emitting element 10 are made of the same material, AlInGaP. The first semiconductor layer 103 is made of a layer having two or more types of Al composition. The layer (second layer) 103B is closer to the active layer 104, and the lower Al composition is closer to the first electrode 161. (First layer) 103A is included. The second layer 103B is a functional layer having the function of a cladding layer. The first conductivity type is n-type, and the electrode material of the first electrode 161 is an AuGeNi alloy, and the film thickness is 500 nm. The second conductivity type is p-type, and the electrode material of the second electrode 162 is AuBe alloy, and the film thickness is 500 nm. As the insulating layer 170, a SiO 2 film was formed by P-CVD using TEOS and O 2 as raw materials. The film thickness was 300 nm.
　この発光素子は製造過程でエピタキシャル基板に表１に示す条件１～８のフロスト加工によりＳｉＯ２膜１７０の表面に凹凸を形成した８枚のウェーハから製造したものである。なお、表１には、各フロスト処理条件（１価の有機酸である酢酸、３価の有機酸であるリンゴ酸、４価の有機酸である酒石酸、４価の有機酸であるクエン酸のいずれかと、弗酸又はバッファード弗酸とを混合した液によるフロスト処理）における表面ラフネス（Ｒｚ）も示されている。 This light emitting device is manufactured from eight wafers in which irregularities are formed on the surface of the SiO 2 film 170 by frost processing of conditions 1 to 8 shown in Table 1 on the epitaxial substrate during the manufacturing process. Table 1 shows the frost treatment conditions (acetic acid, which is a monovalent organic acid, malic acid, which is a trivalent organic acid, tartaric acid, which is a tetravalent organic acid, and citric acid, which is a tetravalent organic acid). Also shown is the surface roughness (R z ) in a frost treatment with a mixture of either hydrofluoric acid or buffered hydrofluoric acid.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　上記のようにして製造した発光素子について、各フロスト処理条件における樹脂剥離率を調べた。その結果を図２２に示す。 The resin peeling rate under each frost treatment condition was examined for the light emitting device manufactured as described above. The result is shown in FIG.
（実施例２）
　図２に示すような発光素子２０を作製した。この発光素子の第一半導体層２０３、活性層２０４、第二半導体層２０５は同一材料であるＡｌＩｎＧａＰとした。また、第一半導体層２０３は二種類以上のＡｌ組成からなる層からなり、活性層２０４に近い側に層（第二の層）２０３Ｂを、第一電極２６１に近い側にＡｌ組成の低い層（第一の層）２０３Ａを有する構成とした。層２０３Ｂはクラッド層の機能を有する機能層である。第一導電型はｎ型で第一電極２６１の電極材料はＡｕＧｅＮｉの合金を選択し、その膜厚を５００ｎｍとした。第二導電型はｐ型で第二電極２６２の電極材料はＡｕＢｅの合金を選択し、その膜厚を５００ｎｍとした。絶縁層２７０はＴＥＯＳとＯ２を原料とするＰ－ＣＶＤ法によりＳｉＯ２膜を形成した。また、膜厚は３００ｎｍとした。
　この発光素子は製造過程でエピタキシャル基板に表１に示す条件１～８のフロスト加工によりＳｉＯ２膜２７０の表面に凹凸を形成した８枚のウェーハから製造したものである。 (Example 2)
A light emitting device 20 as shown in FIG. 2 was produced. The first semiconductor layer 203, the active layer 204, and the second semiconductor layer 205 of this light emitting element were made of AlInGaP which is the same material. The first semiconductor layer 203 is made of a layer having two or more types of Al composition, and the layer (second layer) 203B is closer to the active layer 204 and the layer having a lower Al composition is closer to the first electrode 261. (First layer) 203A. The layer 203B is a functional layer having a function of a cladding layer. The first conductivity type is n-type, and the electrode material of the first electrode 261 is an alloy of AuGeNi, and the film thickness is 500 nm. The second conductivity type is p-type, and the electrode material of the second electrode 262 is an AuBe alloy, and the film thickness is 500 nm. As the insulating layer 270, a SiO 2 film was formed by P-CVD using TEOS and O 2 as raw materials. The film thickness was 300 nm.
This light emitting device is manufactured from eight wafers in which irregularities are formed on the surface of the SiO 2 film 270 by frost processing of conditions 1 to 8 shown in Table 1 on the epitaxial substrate during the manufacturing process.
　上記のようにして製造した発光素子について、各フロスト処理条件における樹脂剥離率を調べた。その結果を図２２に示す。 The resin peeling rate under each frost treatment condition was examined for the light emitting device manufactured as described above. The result is shown in FIG.
（実施例３）
　図３に示すような発光素子３０を作製した。この発光素子の第一半導体層３０３、活性層３０４、第二半導体層３０５は同一材料であるＡｌＩｎＧａＰとした。また、第一半導体層３０３は二種類以上のＡｌ組成からなる層からなり、活性層３０４に近い側に層（第二の層）３０３Ｂを、第一電極３５０に近い側にＡｌ組成の低い層（第一の層）３０３Ａを有する構成とした。層３０３Ｂはクラッド層の機能を有する機能層である。透明接着層３２５はスピンコート法により堆積が可能なＢＣＢ材であるシクロテンとした。第一ＳｉＯ２膜３２０上にシクロテンを滴下し、３，０００ｒｐｍの回転数によりスピンコートを実施した。スピンコート後、ホットプレート上に９０℃で６０秒以上保持して溶剤を揮発させた。第一導電型はｎ型で第一電極３５０の電極材料はＡｕＧｅＮｉの合金を選択し、その膜厚を５００ｎｍとした。第二導電型はｐ型で第二電極３５１の電極材料はＡｕＢｅの合金を選択し、その膜厚を５００ｎｍとした。絶縁層３７０はＴＥＯＳとＯ２を原料とするＰ－ＣＶＤ法によりＳｉＯ２膜を形成した。また、膜厚は３００ｎｍとした。
　この発光素子は製造過程でエピタキシャル基板に表１に示す条件１～８のフロスト加工によりＳｉＯ２膜３７０の表面に凹凸を形成した８枚のウェーハから製造したものである。 (Example 3)
A light emitting device 30 as shown in FIG. 3 was produced. The first semiconductor layer 303, the active layer 304, and the second semiconductor layer 305 of this light emitting element were made of the same material, AlInGaP. The first semiconductor layer 303 is composed of two or more types of Al compositions, and the layer (second layer) 303B is closer to the active layer 304, and the lower Al composition is closer to the first electrode 350. (First layer) 303A was included. The layer 303B is a functional layer having a function of a clad layer. The transparent adhesive layer 325 was cycloten, which is a BCB material that can be deposited by spin coating. Cycloten was dropped on the first SiO 2 film 320 and spin coating was performed at a rotational speed of 3,000 rpm. After spin coating, the solvent was volatilized by maintaining at 90 ° C. for 60 seconds or longer on a hot plate. The first conductivity type is n-type, and the electrode material of the first electrode 350 is an AuGeNi alloy, and the film thickness is 500 nm. The second conductivity type is p-type, and the electrode material of the second electrode 351 is AuBe alloy, and the film thickness is 500 nm. As the insulating layer 370, a SiO 2 film was formed by P-CVD using TEOS and O 2 as raw materials. The film thickness was 300 nm.
This light emitting device is manufactured from eight wafers in which irregularities are formed on the surface of the SiO 2 film 370 by frost processing of conditions 1 to 8 shown in Table 1 on the epitaxial substrate in the manufacturing process.
　上記のようにして製造した発光素子について、各フロスト処理条件における樹脂剥離率を調べた。その結果を図２２に示す。 The resin peeling rate under each frost treatment condition was examined for the light emitting device manufactured as described above. The result is shown in FIG.
（実施例４）
　図４に示すような発光素子４０を作製した。この発光素子の第一半導体層４０３、活性層４０４、第二半導体層４０５は同一材料であるＡｌＩｎＧａＰとした。また、第一半導体層４０３は二種類以上のＡｌ組成からなる層からなり、活性層４０４に近い側に層（第二の層）４０３Ｂを、第一電極４５０に近い側にＡｌ組成の低い層（第一の層）４０３Ａを有する構成とした。層４０３Ｂはクラッド層の機能を有する機能層である。第一導電型はｎ型で第一電極４５０の電極材料はＡｕＧｅＮｉの合金を選択し、その膜厚を５００ｎｍとした。第二導電型はｐ型で第二電極４５１の電極材料はＡｕＢｅの合金を選択し、その膜厚を５００ｎｍとした。絶縁層４７０はＴＥＯＳとＯ２を原料とするＰ－ＣＶＤ法によりＳｉＯ２膜を形成した。また、膜厚は３００ｎｍとした。
　この発光素子は製造過程でエピタキシャル基板に表１に示す条件１～８のフロスト加工によりＳｉＯ２膜４７０の表面に凹凸を形成した８枚のウェーハから製造したものである。 Example 4
A light emitting device 40 as shown in FIG. 4 was produced. The first semiconductor layer 403, the active layer 404, and the second semiconductor layer 405 of this light emitting element are made of the same material, AlInGaP. The first semiconductor layer 403 is made of a layer having two or more types of Al composition. The layer (second layer) 403B is closer to the active layer 404, and the lower Al composition is closer to the first electrode 450. (First layer) 403A was provided. The layer 403B is a functional layer having a function of a cladding layer. The first conductivity type was n-type, and an alloy of AuGeNi was selected as the electrode material of the first electrode 450, and the film thickness was 500 nm. The second conductivity type is p-type, and the electrode material of the second electrode 451 is selected from AuBe alloy, and the film thickness is set to 500 nm. As the insulating layer 470, a SiO 2 film was formed by P-CVD using TEOS and O 2 as raw materials. The film thickness was 300 nm.
This light-emitting element is manufactured from eight wafers in which irregularities are formed on the surface of the SiO 2 film 470 by frost processing of conditions 1 to 8 shown in Table 1 on the epitaxial substrate during the manufacturing process.
　上記のようにして製造した発光素子について、各フロスト加工条件における樹脂剥離率を調べた。その結果を図２２に示す。 The resin peeling rate under each frost processing condition was examined for the light emitting device manufactured as described above. The result is shown in FIG.
（比較例１）
　図２３に示すような発光素子５０を作製した。この発光素子はＳｉＯ２保護膜１７０の表面にフロスト加工を行わない点を除き実施例１と同じ構造である。またこの発光素子はフロスト加工を行わなかった１枚のエピタキシャルウェーハから製造したものである。 (Comparative Example 1)
A light emitting device 50 as shown in FIG. 23 was manufactured. This light-emitting element has the same structure as that of Example 1 except that the surface of the SiO 2 protective film 170 is not frosted. The light emitting device is manufactured from one epitaxial wafer which has not been frosted.
　上記のようにして製造した発光素子について、樹脂剥離率を調べた。その結果を図２２に示す。 The resin peeling rate was examined for the light emitting device manufactured as described above. The result is shown in FIG.
（比較例２）
　図２４に示すような発光素子６０を作製した。この発光素子はＳｉＯ２保護膜２７０の表面にフロスト加工を行わない点を除き実施例２と同じ構造である。またこの発光素子はフロスト加工を行わなかった１枚のエピタキシャルウェーハから製造したものである。 (Comparative Example 2)
A light emitting device 60 as shown in FIG. 24 was manufactured. This light emitting element has the same structure as that of Example 2 except that the surface of the SiO 2 protective film 270 is not frosted. The light emitting device is manufactured from one epitaxial wafer which has not been frosted.
　上記のようにして製造した発光素子について、樹脂剥離率を調べた。その結果を図２２に示す。 The resin peeling rate was examined for the light emitting device manufactured as described above. The result is shown in FIG.
（比較例３）
　図２５に示すような発光素子７０を作製した。この発光素子はＳｉＯ２保護膜３７０の表面にフロスト加工を行わない点を除き実施例３と同じ構造である。またこの発光素子はフロスト加工を行わなかった１枚のエピタキシャルウェーハから製造したものである。 (Comparative Example 3)
A light emitting device 70 as shown in FIG. 25 was produced. This light emitting element has the same structure as that of Example 3 except that the surface of the SiO 2 protective film 370 is not frosted. The light emitting device is manufactured from one epitaxial wafer which has not been frosted.
　上記のようにして製造した発光素子について、樹脂剥離率を調べた。その結果を図２２に示す。 The resin peeling rate was examined for the light emitting device manufactured as described above. The result is shown in FIG.
（比較例４）
　図２６に示すような発光素子８０を作製した。この発光素子はＳｉＯ２保護膜４７０にフロスト加工を行わない点を除き実施例４と同じ構造である。またこの発光素子はフロスト加工を行わなかった１枚のエピタキシャルウェーハから製造したものである。 (Comparative Example 4)
A light emitting device 80 as shown in FIG. 26 was manufactured. This light-emitting element has the same structure as that of Example 4 except that the SiO 2 protective film 470 is not subjected to frost processing. The light emitting device is manufactured from one epitaxial wafer which has not been frosted.
　上記のようにして製造した発光素子について、樹脂剥離率を調べた。その結果を図２２に示す。 The resin peeling rate was examined for the light emitting device manufactured as described above. The result is shown in FIG.
　図２２に示すように、フロスト処理条件が条件１～条件８のいずれの条件においても、フロスト処理を行った実施例１はフロスト処理を行なわない比較例１に比べて剥離率が大幅に改善されたのが分かる。
　また、図２２に示すように、フロスト処理条件が条件１～条件８のいずれの条件においても、フロスト処理を行った実施例２はフロスト処理を行なわない比較例２に比べて剥離率が大幅に改善されたのが分かる。
　また、図２２に示すように、フロスト処理条件が条件１～条件８のいずれの条件においても、フロスト処理を行った実施例３はフロスト処理を行なわない比較例３に比べて剥離率が大幅に改善されたのが分かる。
　また、図２２に示すように、フロスト処理条件が条件１～条件８のいずれの条件においても、フロスト処理を行った実施例４はフロスト処理を行なわない比較例４に比べて剥離率が大幅に改善されたのが分かる。 As shown in FIG. 22, in any of the conditions 1 to 8 for the frost treatment conditions, Example 1 in which the frost treatment was performed has a significantly improved peeling rate compared to Comparative Example 1 in which the frost treatment is not carried out. I understand that.
Further, as shown in FIG. 22, in any of the conditions 1 to 8 for the frost treatment conditions, Example 2 in which the frost treatment was performed had a significantly higher peeling rate than Comparative Example 2 in which the frost treatment was not performed. You can see that it has improved.
Further, as shown in FIG. 22, in any of the conditions 1 to 8 for the frost treatment conditions, Example 3 in which the frost treatment was performed had a significantly higher peeling rate than Comparative Example 3 in which the frost treatment was not performed. You can see that it has improved.
Further, as shown in FIG. 22, in any of the conditions 1 to 8 for the frost treatment conditions, Example 4 in which the frost treatment is performed has a significantly higher peeling rate than Comparative Example 4 in which the frost treatment is not performed. You can see that it has improved.
　なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。 Note that the present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

Claims (5)

  1. 　化合物半導体からなる発光部と、電極と、保護膜とを有する発光素子であって、
    　前記発光素子の少なくとも一部を覆う前記保護膜の表面に、Ｒｚが５ｎｍを超える凹凸が形成されているものであることを特徴とする発光素子。     A light-emitting element having a light-emitting portion made of a compound semiconductor, an electrode, and a protective film,
    The light emitting device is characterized in that the surface of the protective film covering at least a part of the light emitting device has irregularities with Rz exceeding 5 nm.
  2. 　前記保護膜がＳｉＯ２であることを特徴とする請求項１に記載の発光素子。 The light emitting device according to claim 1, wherein the protective film is made of SiO 2 .
  3. 　前記発光部の表面の少なくとも一部が粗面化されているものであることを特徴とする請求項１又は請求項２に記載の発光素子。 3. The light-emitting element according to claim 1, wherein at least a part of the surface of the light-emitting portion is roughened.
  4. 　化合物半導体からなる発光部と、電極と、保護膜とを有する発光素子の製造方法であって、
    　前記発光素子の少なくとも一部を覆う前記保護膜であるＳｉＯ２膜に、弗酸と１価～４価の無機酸あるいは有機酸とを混合した液によりフロスト処理することで、前記ＳｉＯ２膜の表面に凹凸を形成することを特徴とする発光素子の製造方法。     A method for manufacturing a light-emitting element having a light-emitting portion made of a compound semiconductor, an electrode, and a protective film,
    The SiO 2 film, which is the protective film covering at least a part of the light-emitting element, is subjected to a frost treatment with a mixture of hydrofluoric acid and a monovalent to tetravalent inorganic acid or organic acid, whereby the SiO 2 film A method for manufacturing a light-emitting element, comprising forming irregularities on a surface.
  5. 　前記無機酸として、硫酸、塩酸、燐酸のうちの少なくともいずれか１種を用い、前記有機酸として、マロン酸、酢酸、クエン酸、酒石酸、リンゴ酸のうちの少なくともいずれか１種を用いることを特徴とする請求項４に記載の発光素子の製造方法。 Using at least one of sulfuric acid, hydrochloric acid, and phosphoric acid as the inorganic acid, and using at least one of malonic acid, acetic acid, citric acid, tartaric acid, and malic acid as the organic acid. The manufacturing method of the light emitting element of Claim 4 characterized by the above-mentioned.
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