WO2018032684A1 - Mandrin, chambre de réaction et appareil de traitement de semi-conducteurs - Google Patents

Mandrin, chambre de réaction et appareil de traitement de semi-conducteurs Download PDF

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Publication number
WO2018032684A1
WO2018032684A1 PCT/CN2016/112387 CN2016112387W WO2018032684A1 WO 2018032684 A1 WO2018032684 A1 WO 2018032684A1 CN 2016112387 W CN2016112387 W CN 2016112387W WO 2018032684 A1 WO2018032684 A1 WO 2018032684A1
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WO
WIPO (PCT)
Prior art keywords
wafer
bearing surface
chuck
gas
roughness
Prior art date
Application number
PCT/CN2016/112387
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English (en)
Chinese (zh)
Inventor
张虎威
Original Assignee
北京北方微电子基地设备工艺研究中心有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of WO2018032684A1 publication Critical patent/WO2018032684A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/02—Details
    • H01J37/20—Means for supporting or positioning the objects or the material; Means for adjusting diaphragms or lenses associated with the support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67213—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping

Definitions

  • the present invention relates to the field of semiconductor manufacturing, and in particular to a chuck, a reaction chamber, and a semiconductor processing apparatus.
  • Electrostatic Chuck is widely used in the manufacturing process of integrated circuits, especially plasma etching, physical vapor deposition (PVD), chemical vapor deposition (Chemical Vapor Deposition).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • CVD requires ESC to fix the wafer in the reaction chamber, provide DC bias to the wafer, and rapidly cool the surface of the wafer so that the high temperature generated by the wafer surface during the process can be effectively controlled.
  • an electrostatic chuck includes an insulating layer 1 and an aluminum base 4 for supporting the insulating layer 1.
  • the upper surface of the insulating layer 1 is made of a ceramic material for carrying and insulating the wafer 2.
  • a DC electrode (not shown) is embedded in the insulating layer 1 to electrically electrostatically attract the insulating layer 1 and the wafer 2.
  • a cooling passage 3 is provided in the insulating layer 1 for conveying a cooling gas between the insulating layer 1 and the wafer 2 to cool the wafer 2.
  • a cooling water passage 41 is provided inside the aluminum base 4, and the insulating layer 1 is cooled by passing cooling water into the cooling water passage 41.
  • FIG. 2 is a plan view of the conventional electrostatic chuck shown in FIG. 1.
  • an annular boss 10 and a plurality of bumps 11 are disposed on the upper surface of the insulating layer 1.
  • the annular boss 10 is circumferentially disposed at the edge of the insulating layer 1 for sealing the edge of the wafer 2.
  • a plurality of bumps 11 are located inside the annular boss 10 and are evenly distributed, and the upper surface of the bump 11 and the upper surface of the annular boss 10 are in contact with the wafer 2 for supporting the wafer 2 in common.
  • the heat transfer between the insulating layer 1 and the wafer 2 mainly depends on the plurality of bumps 11 contacting the lower surface of the wafer 2, and the cooling gas between the insulating layer 1 and the wafer 2, but due to the bumps 11 and the wafer 2
  • the lower surface is a point contact, and the contact area is limited, which cannot meet the requirement of rapid cooling of the wafer 2.
  • the surface temperature of the wafer 2 rises rapidly, so that the wafer 2 is damaged due to high temperature.
  • the present invention is directed to at least one of the technical problems existing in the prior art, and proposes a chuck, a reaction chamber, and a semiconductor processing apparatus.
  • the chuck, the reaction chamber and the semiconductor processing apparatus provided by the invention can improve the efficiency of heat conduction of the wafer to the chuck, thereby avoiding wafer damage caused by excessive temperature rise of the wafer surface.
  • a chuck comprising an insulating layer and a base body, the insulating layer comprising a first bearing surface and a second bearing surface surrounding the outer circumference of the first bearing surface, the first bearing surface a central region for carrying a wafer, the second bearing surface for carrying an edge region of the wafer, wherein the first bearing surface has a first roughness, and the first roughness can be guaranteed to be located at the first Under the premise that the gas between the bearing surface and the wafer is evenly distributed, the contact area between the wafer and the first bearing surface is increased.
  • the first roughness is 0.6-0.8 um.
  • the second bearing surface has a second roughness, and the second roughness enables the second bearing surface to be in close contact with the wafer to seal the gas between the first bearing surface and the wafer.
  • the second roughness is less than or equal to 0.4 um.
  • the first roughness is greater than the second roughness.
  • At least two gas passages are disposed under the insulating layer for introducing gas between the first bearing surface and the wafer.
  • each of the gas passages is an annular passage, and at least two of the annular passages are concentric rings.
  • the annular channel comprises: a circular annular channel, an elliptical annular channel and/or an irregular annular channel.
  • the annular passage of the outermost ring is located at an edge of the first bearing surface.
  • the annular passage is centered on a center of the first bearing surface.
  • the present invention also provides a reaction chamber comprising the above-described chuck provided by the present invention.
  • the present invention also provides an inverse semiconductor processing apparatus including the above-described reaction chamber provided by the present invention.
  • the chuck provided by the present invention has an insulating layer including a first bearing surface and a second bearing surface surrounding the outer circumference of the first bearing surface, the first bearing surface and the second bearing surface for respectively carrying the central area and the edge area of the wafer .
  • the first bearing surface has a first roughness, which can increase the contact area between the wafer and the bearing surface under the premise of ensuring uniform distribution of the gas between the first bearing surface and the wafer, thereby Improve the efficiency of heat transfer from the wafer to the insulating layer of the chuck, improve the cooling effect on the wafer, thereby not only improving the temperature-controlled cooling process of the conventional wafer, but also solving the new wafer (such as system integrated wafer SOG) in the high temperature process.
  • the problem of rapid rise in wafer temperature prevents high temperature damage of the wafer.
  • the reaction chamber provided by the invention can not only improve the process effect of temperature control and cooling of the conventional wafer by using the above-mentioned chuck provided by the invention, but also solve the problem that the wafer temperature rises rapidly when the new wafer is subjected to a high temperature process. To avoid high temperature damage to the wafer.
  • the semiconductor processing apparatus provided by the invention can not only improve the process effect of the temperature control cooling of the conventional wafer by using the reaction chamber provided by the invention, but also can avoid the temperature rise of the wafer surface too fast when the new wafer is subjected to a high temperature process. Causes high temperature damage to the wafer.
  • Figure 1 is a partial cross-sectional view of a conventional electrostatic chuck
  • Figure 2 is a plan view of the conventional electrostatic chuck shown in Figure 1;
  • FIG. 3 is a cross-sectional view of a chuck according to an embodiment of the present invention.
  • Figure 4 is an enlarged view of the area I in Figure 3;
  • Fig. 5 is a schematic view showing the structure and positional relationship of a gas passage in an embodiment of the present invention.
  • the reference numerals are: insulating layer 1, wafer 2, cooling channel 3, aluminum base 4, cooling water channel 41, annular boss 10, bump 11, insulating layer 5, substrate 7, gas passage 8, gas distribution plate 9.
  • FIG. 3 is a cross-sectional view of a chuck according to an embodiment of the present invention.
  • Figure 4 is an enlarged view of the area I in Figure 3.
  • the chuck includes an insulating layer 5 and a base body 7, wherein the insulating layer 5 includes a first bearing surface 51 and a second bearing surface 52 surrounding the outer circumference of the first bearing surface 51, A carrier surface 51 is used to carry the central area of the wafer 6, and a second carrier surface 52 is used to carry the edge regions of the wafer 6.
  • the first bearing surface 51 has a first roughness, which can increase the wafer 6 and the first bearing surface 51 under the premise that the gas between the first bearing surface 51 and the wafer 6 is evenly distributed. The area of contact between.
  • the gas is delivered between the first bearing surface 51 and the wafer 6 to increase heat transfer therebetween.
  • the gas may be an inert gas such as helium.
  • the first roughness can save the first bearing surface 51 and the wafer 6.
  • the gap enables the gas to form a convection in the gap, thereby achieving uniform distribution of the gas, thereby improving the heat dissipation efficiency of the wafer 6 to the gas.
  • the first bearing surface 51 and the lower surface of the wafer 6 still belong to the surface contact, which ensures the contact area between the two, thereby improving the efficiency of heat conduction of the wafer 6 to the chuck and improving the cooling effect on the wafer 6.
  • the new wafer (such as the system integrated wafer SOG) can be prevented from being damaged by the high temperature of the wafer 6 due to the excessive temperature rise of the surface of the wafer 6 during the high temperature process. .
  • the first roughness ranges from 0.6 to 0.8 um. Within this range of values, the contact area between the first carrying surface 51 and the wafer 6 is maximized, so that the efficiency of heat transfer of the wafer 6 to the first carrying surface 51 can be improved.
  • the roughness is the roughness of the corresponding surface, the rougher the surface, the greater the roughness; the smoother the surface, the greater the roughness.
  • the second bearing surface 52 has a second roughness, which enables the second bearing surface 52 to be in close contact with the wafer 6, thereby sealing the gas between the first bearing surface 51 and the wafer 6, thereby avoiding Gas leaks.
  • the second roughness is less than or equal to 0.4 um. Within this range of values, the sealing effect on the gas is better.
  • the first roughness is greater than the second roughness.
  • the first bearing surface is more favorable for heat conduction of the wafer to the first bearing surface, and the second bearing surface can be in closer contact with the wafer during electrostatic adsorption, sealing the first The gas between the bearing surface and the wafer.
  • a gas passage may be disposed under the insulating layer.
  • the chuck provided in this embodiment is provided with a gas passage 8 , specifically a first gas passage 81 and a second gas passage 82 , between the first bearing surface 51 and the wafer 6 below the insulating layer 5 .
  • Pass the above gas the first gas passage 81 and the second gas passage 82 are both annular passages and are concentric rings.
  • the annular passage of the outermost ring that is, the second gas passage 82 is located at a position on the first bearing surface 51 adjacent to the second bearing surface 52, that is, the second gas passage 82 is located at the edge of the first bearing surface 51. Therefore, it is possible to improve the heat dissipation efficiency of the edge region of the wafer 6 to the gas.
  • the region inside the second gas passage 82 is the region where the first bearing surface 51 is located, and the region can be further divided by the first gas passage 81. It is an intermediate area 511 and a central area 512.
  • the first roughness of the intermediate region 511 and the central region 512 can be designed to be the same or different in order to accommodate different heat dissipation requirements and adsorption requirements.
  • the annular passage is a circular passage and is centered on the center of the first bearing surface 51. This makes it possible to distribute the gas more evenly between the first bearing surface 51 and the wafer 6, so that the heat dissipation efficiency of the wafer 6 to the gas can be further improved.
  • the present invention is not limited thereto, and in practical applications, the number of gas passages may be three or more.
  • the shape of the gas passage is not limited to the circular passage adopted in the embodiment, and it may also employ, for example, an elliptical annular passage and/or an irregular annular passage.
  • the irregular annular passage may include a passage formed by a closed curve of any shape, and may also include a passage formed by any non-closed curve of a serpentine passage, a spiral passage, or the like.
  • the above chuck is an electrostatic chuck.
  • a gas distribution plate 9 is disposed between the insulating layer 5 and the base 7, wherein the insulating layer 5 is made of an insulating material, such as ceramic, the first bearing surface 51 and the first The second bearing surface 52 is the surface of the insulating layer 5.
  • a DC electrode (not shown) is provided in the insulating layer 5, and a direct current is applied to the DC electrode to cause electrostatic attraction between the DC electrode and the wafer 6, thereby fixing the wafer 6.
  • the gas passage 8 is disposed in the gas distribution
  • the plate 9 is in the shape of a groove; and a plurality of intake holes are provided in the insulating layer 5 to introduce a gas above the insulating layer 5.
  • the gas passage 82 is disposed in the gas distribution plate 9 in which a gas passage inlet 822 is provided to introduce gas from an external gas source to the gas passage 82 via the base 7.
  • a plurality of intake holes 821 communicating with the gas passages 82 are uniformly distributed in the insulating layer 5 to uniformly introduce the gas in the gas passages 82 above the insulating layer 5 to cool the wafer 6.
  • the gas passage is disposed in the gas distribution plate in the embodiment, the gas passage may be disposed in the base body in a practical application, and uniformly connected to the gas passage in the gas distribution plate and the insulation layer.
  • the chuck may not include a gas distribution plate, so that the gas passage may be disposed in the base body, and a plurality of air inlet holes communicating with the gas passage are uniformly disposed in the insulation layer; or The thickness of the insulating layer is increased, and a gas passage is disposed therein, and a plurality of intake holes communicating with the gas passage are uniformly disposed on the upper surface of the insulating layer. That is to say, in practical applications, it is only necessary to arrange the gas passage under the insulating layer and to uniformly introduce the gas above the insulating layer, without particularly limiting in which layer the gas passage is specifically disposed.
  • the base 7 is made of a metal material such as aluminum for supporting and cooling the insulating layer 5. Specifically, a cooling water passage 71 is provided in the base body 7, and the insulating layer 5 is cooled by passing cooling water into the cooling water passage 71, thereby indirectly carrying away heat generated by the wafer 6.
  • an embodiment of the present invention further provides a reaction chamber in which a chuck is disposed for carrying a wafer, and the chuck can adopt the chuck provided by the above embodiment of the present invention.
  • the reaction chamber provided by the embodiment of the present invention can not only improve the process effect of temperature control and cooling of the conventional wafer by using the chuck provided by the above embodiment of the present invention, but also can avoid New wafers (such as system-integrated wafer SOG) cause high temperature damage to the wafer due to excessive temperature rise on the wafer surface during high temperature processing.
  • New wafers such as system-integrated wafer SOG
  • an embodiment of the present invention further provides a semiconductor processing apparatus including a reaction chamber using the reaction chamber provided by the above embodiment of the present invention.
  • the semiconductor processing apparatus provided by the embodiments of the present invention can not only improve the process effect of the temperature control cooling of the conventional wafer by using the reaction chamber provided by the above embodiments of the present invention, but also avoid the novel wafer (such as the system integrated wafer SOG).
  • the novel wafer such as the system integrated wafer SOG.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

L'invention porte sur un mandrin, une chambre de réaction et sur un appareil de traitement de semi-conducteurs. Le mandrin comprend une couche isolante (5) et un substrat (7). La couche isolante (5) comprend une première surface d'appui (51) pour supporter une zone centrale d'une tranche (6) et une seconde surface d'appui (52) entourant la périphérie externe de la première surface d'appui (51) pour supporter une zone de bord de la tranche (6), la première surface d'appui (51) ayant une première rugosité qui peut augmenter la zone de contact entre la tranche (6) et la première surface d'appui (51) dans une condition telle que le gaz entre la première surface d'appui (51) et la tranche (6) soit distribué de manière uniforme. La chambre de réaction comprend le mandrin. L'équipement de traitement de semi-conducteurs comprend la chambre de réaction. Le mandrin, la chambre de réaction et l'équipement de traitement de semi-conducteurs peuvent améliorer l'efficacité de conduction de chaleur de la tranche au mandrin, ce qui permet d'éviter des dommages provoqués par un chauffage trop rapide de la surface de tranche.
PCT/CN2016/112387 2016-08-16 2016-12-27 Mandrin, chambre de réaction et appareil de traitement de semi-conducteurs WO2018032684A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610675069.3 2016-08-16
CN201610675069.3A CN107768300B (zh) 2016-08-16 2016-08-16 卡盘、反应腔室及半导体加工设备

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Publication Number Publication Date
WO2018032684A1 true WO2018032684A1 (fr) 2018-02-22

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PCT/CN2016/112387 WO2018032684A1 (fr) 2016-08-16 2016-12-27 Mandrin, chambre de réaction et appareil de traitement de semi-conducteurs

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CN (1) CN107768300B (fr)
TW (1) TWI642139B (fr)
WO (1) WO2018032684A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021520639A (ja) * 2018-04-09 2021-08-19 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ パターニング用途のためのカーボンハードマスク及び関連方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6692012B1 (ja) * 2018-06-26 2020-05-13 株式会社キルトプランニングオフィス 照明装置
JP6839314B2 (ja) * 2019-03-19 2021-03-03 日本碍子株式会社 ウエハ載置装置及びその製法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211810A (zh) * 2006-12-30 2008-07-02 北京北方微电子基地设备工艺研究中心有限责任公司 静电卡盘装置
US20080190367A1 (en) * 2007-02-12 2008-08-14 Samsung Electronics Co., Ltd. Chuck assembly and high density plasma equipment having the same
CN104124127A (zh) * 2013-04-27 2014-10-29 北京北方微电子基地设备工艺研究中心有限责任公司 托盘及等离子体加工设备
CN105074902A (zh) * 2013-03-29 2015-11-18 住友大阪水泥股份有限公司 静电卡盘装置
CN105390368A (zh) * 2014-09-09 2016-03-09 北京北方微电子基地设备工艺研究中心有限责任公司 晶片预清洗腔室及半导体加工设备

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3859937B2 (ja) * 2000-06-02 2006-12-20 住友大阪セメント株式会社 静電チャック
JP4439135B2 (ja) * 2001-04-27 2010-03-24 京セラ株式会社 静電チャック
US6552892B2 (en) * 2001-05-09 2003-04-22 Axcelis Technologies, Inc. Method and apparatus for the grounding of process wafers by the use of conductive regions created by ion implantation into the surface of an electrostatic clamp
JP2003224180A (ja) * 2002-01-28 2003-08-08 Kyocera Corp ウエハ支持部材
US20040055709A1 (en) * 2002-09-19 2004-03-25 Applied Materials, Inc. Electrostatic chuck having a low level of particle generation and method of fabricating same
CN100468619C (zh) * 2006-08-23 2009-03-11 北京北方微电子基地设备工艺研究中心有限责任公司 刻蚀设备的控温装置及其控制晶片温度的方法
KR101680787B1 (ko) * 2009-05-15 2016-11-29 엔테그리스, 아이엔씨. 중합체 돌기들을 가지는 정전 척
KR100997374B1 (ko) * 2009-08-21 2010-11-30 주식회사 코미코 정전척 및 이의 제조 방법
TWI558841B (zh) * 2009-12-22 2016-11-21 應用材料股份有限公司 狹縫閥通道支撐件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211810A (zh) * 2006-12-30 2008-07-02 北京北方微电子基地设备工艺研究中心有限责任公司 静电卡盘装置
US20080190367A1 (en) * 2007-02-12 2008-08-14 Samsung Electronics Co., Ltd. Chuck assembly and high density plasma equipment having the same
CN105074902A (zh) * 2013-03-29 2015-11-18 住友大阪水泥股份有限公司 静电卡盘装置
CN104124127A (zh) * 2013-04-27 2014-10-29 北京北方微电子基地设备工艺研究中心有限责任公司 托盘及等离子体加工设备
CN105390368A (zh) * 2014-09-09 2016-03-09 北京北方微电子基地设备工艺研究中心有限责任公司 晶片预清洗腔室及半导体加工设备

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021520639A (ja) * 2018-04-09 2021-08-19 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ パターニング用途のためのカーボンハードマスク及び関連方法
US11784042B2 (en) 2018-04-09 2023-10-10 Applied Materials, Inc. Carbon hard masks for patterning applications and methods related thereto
JP7407121B2 (ja) 2018-04-09 2023-12-28 アプライド マテリアルズ インコーポレイテッド パターニング用途のためのカーボンハードマスク及び関連方法

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TW201807774A (zh) 2018-03-01
TWI642139B (zh) 2018-11-21
CN107768300A (zh) 2018-03-06
CN107768300B (zh) 2021-09-17

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