WO2018029921A1 - Semiconductor package and wiring board - Google Patents

Semiconductor package and wiring board Download PDF

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Publication number
WO2018029921A1
WO2018029921A1 PCT/JP2017/017343 JP2017017343W WO2018029921A1 WO 2018029921 A1 WO2018029921 A1 WO 2018029921A1 JP 2017017343 W JP2017017343 W JP 2017017343W WO 2018029921 A1 WO2018029921 A1 WO 2018029921A1
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Prior art keywords
external electrode
capacitor
integrated circuit
electrode
semiconductor integrated
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Application number
PCT/JP2017/017343
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French (fr)
Japanese (ja)
Inventor
秀一 鍋倉
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株式会社村田製作所
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Publication of WO2018029921A1 publication Critical patent/WO2018029921A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a semiconductor package and a wiring board on which the semiconductor package is mounted.
  • a semiconductor package including a semiconductor integrated circuit is incorporated in various electronic devices such as a smartphone and a personal computer.
  • Some semiconductor packages include a bypass capacitor (decoupling capacitor) mounted between the power supply and the ground of the semiconductor integrated circuit in order to suppress voltage fluctuation during operation of the semiconductor integrated circuit, to eliminate noise, and the like.
  • the power source impedance is desirably as low as possible from the viewpoint of suppressing voltage fluctuation.
  • Patent Document 1 discloses a semiconductor integrated circuit including a semiconductor integrated circuit chip body, an input / output terminal formed on an external surface of the semiconductor integrated circuit chip body, and a decoupling capacitor electrically connected to the input / output terminal.
  • a circuit chip and a semiconductor integrated circuit chip package in which the semiconductor integrated circuit chip is mounted on a package substrate are disclosed. With this configuration, since the inductance between the decoupling capacitor and the semiconductor integrated circuit chip main body is minimized, the power source impedance is reduced.
  • Patent Document 1 can reduce the power supply impedance, but does not consider heat dissipation.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor package and a wiring board capable of improving heat dissipation while reducing power source impedance.
  • a semiconductor package includes a semiconductor integrated circuit, a relay member on which the semiconductor integrated circuit is mounted, a shield member that covers the semiconductor integrated circuit and is electrically connected to a ground provided on the relay member, and a semiconductor integrated circuit
  • a capacitor electrically connected between a power source and a ground of the circuit, and a first power source terminal, a second power source terminal, and a ground terminal are provided on the upper surface of the semiconductor integrated circuit, and the capacitor includes a dielectric layer.
  • the capacitor has a first external electrode electrically connected to the first power supply terminal of the semiconductor integrated circuit, a second external electrode electrically connected to the second power supply terminal of the semiconductor integrated circuit, and a third The external electrode is electrically connected to the ground terminal of the semiconductor integrated circuit, and the fourth external electrode is electrically connected to the shield member, so that the external electrode is mounted between the semiconductor integrated circuit and the shield member.
  • a capacitor (bypass capacitor) is mounted between the semiconductor integrated circuit and the shield member, and the third and fourth external electrodes connected to the second internal electrode of the capacitor are the semiconductor integrated circuit. Connected to ground terminal and shield member.
  • heat generated in the semiconductor integrated circuit is conducted from the ground terminal through the third external electrode, the second internal electrode, and the fourth external electrode of the capacitor to the shield member, and is radiated from the shield member.
  • the metal electrode has high thermal conductivity, it can conduct heat efficiently.
  • the capacitor is directly disposed on the upper surface of the semiconductor integrated circuit, the heat generated in the semiconductor integrated circuit can be efficiently radiated through the capacitor.
  • the heat dissipation can be improved by providing the heat path using the capacitor between the semiconductor integrated circuit and the shield member.
  • the ground terminal of the semiconductor integrated circuit and the shield member are connected to the ground of the capacitor. Therefore, the path between the power source and the ground of the capacitor is increased, and the inductance of the semiconductor package is reduced. Can do.
  • the capacitor since the capacitor is configured as a three-terminal capacitor, the inductance can be reduced.
  • the capacitor since the capacitor is directly disposed on the semiconductor integrated circuit, the inductance of the wiring between the capacitor and the semiconductor integrated circuit can be reduced.
  • condenser can be suppressed with a capacitor
  • the first internal electrode and the second internal electrode of the capacitor are preferably disposed substantially perpendicular to the upper surface of the semiconductor integrated circuit.
  • a semiconductor package includes a semiconductor integrated circuit, a relay member on which the semiconductor integrated circuit is mounted, a shield member that covers the semiconductor integrated circuit and is electrically connected to a ground provided on the relay member, and a semiconductor integrated circuit
  • a capacitor electrically connected between the power source and the ground of the circuit, and a first power source terminal, a second power source terminal and a ground terminal are provided on the upper surface of the relay member, and the capacitor sandwiches the dielectric layer
  • the first internal electrode and the second internal electrode are stacked, the first external electrode connected to the first internal electrode is provided on the lower surface of the multilayer body, and the lower surface of the multilayer body is provided.
  • the fourth external electrode is electrically connected to the shield member, and is mounted between the relay member and the shield member.
  • a capacitor (bypass capacitor) is mounted between the relay member and the shield member, and the third and fourth external electrodes connected to the second internal electrode of the capacitor are the ground terminals of the relay member. And connected to the shield member.
  • the semiconductor package according to the present invention since there are the ground terminal of the relay member and the shield member as the connection point of the capacitor to the ground, the path between the power source and the ground of the capacitor is increased, and the inductance of the semiconductor package can be reduced. it can.
  • the capacitor since the capacitor is configured as a three-terminal capacitor, the inductance can be reduced.
  • condenser can be suppressed with a capacitor
  • the semiconductor package according to the present invention even when static electricity enters from the outside of the shield member, the fourth external electrode and the second internal electrode of the capacitor from the shield member and the path for directly discharging the static electricity from the shield member to the ground of the relay member Since there is a path to escape to the ground of the relay member through the third external electrode, it is excellent in ESD (Electro Static Discharge) resistance.
  • ESD Electro Static Discharge
  • the first internal electrode and the second internal electrode of the capacitor are arranged substantially perpendicular to the upper surface of the relay member.
  • the ground terminal is disposed between the first power terminal and the second power terminal, the first external electrode is disposed on one end side of the lower surface of the stacked body, and the second external electrode is The third external electrode is preferably disposed between the first external electrode and the second external electrode on the bottom surface of the multilayer body.
  • the power supply terminals first external electrode and second external electrode
  • the ground terminal third external electrode
  • the first external electrode is provided on a part of one side surface of the multilayer body from one end side of the lower surface of the multilayer body, and the second external electrode is laminated from the other end side of the lower surface of the multilayer body. It is preferable to be provided on a part of the other side facing the one side of the body.
  • ESL Equivalent Series Inductance
  • the fourth external electrode is preferably provided over the entire top surface of the stack.
  • the distance between the power supply terminals (first external electrode and second external electrode) on the lower surface of the capacitor and the ground terminal (fourth external electrode) on the upper surface of the capacitor is reduced, and the inductance (ESL) of the capacitor is reduced. ) Can be reduced.
  • the ground contact area to the shield member is increased by increasing the area of the fourth external electrode, the heat dissipation can be further improved.
  • the fourth external electrode is provided on a part of one side surface of the multilayer body and a part of the other side surface facing the one side surface from the top surface of the multilayer body.
  • the relay member is preferably an interposer. With this configuration, the terminal interval and the like can be converted while the semiconductor integrated circuit is supported by the interposer.
  • a wiring board according to the present invention includes a mother board and a semiconductor package mounted on the mother board.
  • the semiconductor package is each of the semiconductor packages described above, and the relay member of the semiconductor package includes the mother board and the semiconductor package. It is characterized by relaying to a semiconductor integrated circuit.
  • the semiconductor package having the above-described effects is mounted on the mother board, it is possible to improve heat dissipation and reduce power supply impedance.
  • FIG. 2 is a perspective view of the capacitor shown in FIG. 1, (a) is a perspective view seen from the upper surface side, and (b) is a perspective view seen from the lower surface side.
  • FIG. 3 is a side sectional view of the capacitor shown in FIG. 2, (a) is a side sectional view of a portion where a first internal electrode is disposed, and (b) is a side sectional view of a portion where a second external electrode is disposed. is there.
  • FIG. 3 is an exploded perspective view showing a laminated state of the multilayer body of the capacitor shown in FIG. 2.
  • FIG. 6 is a side sectional view of the capacitor shown in FIG. 5, (a) is a side sectional view of a place where the first internal electrode is arranged, and (b) is a side sectional view of a place where the second external electrode is arranged. is there. It is a disassembled perspective view which shows the lamination
  • FIG. 1 is a side sectional view showing a configuration of a wiring board 2 on which an IC package 1 according to the first embodiment is mounted.
  • the IC package 1 is mounted on the mother board 3 of the wiring board 2.
  • a printed wiring 3b made of, for example, copper foil or the like is formed on the upper surface 3a of the mother substrate 3, and the IC package 1 is electrically connected to the printed wiring 3b.
  • a portion where the IC package 1 and the mother substrate 3 are connected is sealed with, for example, an underfill 4.
  • a power supply circuit and the like are mounted on the mother board 3 in addition to the IC package 1.
  • the IC package 1 includes a silicon die 10 (corresponding to the semiconductor integrated circuit recited in the claims), an interposer 20 (corresponding to the relay member recited in the claims), and a shield case 30 (shielding according to the claims). And a capacitor 40.
  • the IC package 1 is formed into, for example, a BGA (Ball Grid Array) package.
  • the silicon die 10 is a chip on which a semiconductor integrated circuit is formed.
  • the silicon die 10 is mounted on the interposer 20.
  • the lower surface of the silicon die 10 is provided with substantially hemispherical solder balls (bumps) arranged in a lattice pattern.
  • the silicon die 10 is electrically connected to the mother substrate 3 through the interposer 20 by mounting the IC package 1 on the mother substrate 3.
  • the silicon die 10 is supplied with power from, for example, a power supply circuit mounted on the mother substrate 3.
  • a capacitor 40 is mounted on the upper surface (top surface) 10 a of the silicon die 10.
  • two power terminals (power pads) 11 and 12 and one ground terminal (ground pad) 13 are provided on the upper surface 10 a of the silicon die 10 for each mounted capacitor 40. It has been.
  • the power terminals 11 and 12 are connected to a power line in the silicon die 10.
  • the ground terminal 13 is connected to a ground line in the silicon die 10.
  • the power supply terminals 11 and 12 have a size that can be joined to first and second external electrodes of a capacitor 40 to be described later, and are, for example, rectangular.
  • the power supply terminals 11 and 12 are made of, for example, copper.
  • the power supply terminal 11 and the power supply terminal 12 are arranged at a predetermined interval corresponding to the arrangement of the first external electrode and the second external electrode of the capacitor 40.
  • a first external electrode of the capacitor 40 is electrically connected to the power supply terminal 11.
  • a second external electrode of the capacitor 40 is electrically connected to the power supply terminal 12.
  • the ground terminal 13 has a size that can be joined to a third external electrode of the capacitor 40 described later, and is, for example, rectangular.
  • the ground terminal 13 is made of copper, for example.
  • the ground terminal 13 is disposed between the power supply terminal 11 and the power supply terminal 12.
  • a third external electrode of the capacitor 40 is electrically connected to the ground terminal 13.
  • the interposer 20 is a substrate that supports the silicon die 10 and relays between the silicon die 10 and the mother substrate 3.
  • the interposer 20 converts a terminal interval between the silicon die 10 and the mother substrate 3 and electrically connects the silicon die 10 and the mother substrate 3 by mounting the IC package 1 on the mother substrate 3.
  • the silicon die 10 is mounted on the upper surface (top surface) 20 a of the interposer 20.
  • a printed wiring made of copper foil or the like is formed on the upper surface 20a of the interposer 20, and the silicon die 10 is electrically connected to the printed wiring.
  • a shield case 30 is joined to the upper surface 20a of the interposer 20.
  • a ground 21 is provided on the upper surface 20 a of the interposer 20, and a shield case 30 is electrically connected to the ground 21.
  • the ground 21 is disposed at a location where the shield case 30 is joined.
  • the ground 21 may be provided at the entire location where the shield case 30 is joined (rectangular annular ground), or may be provided at a portion of the location where the shield case 30 is joined.
  • the interposer 20 On the lower surface (bottom surface) 20b of the interposer 20, substantially hemispherical solder balls 22 arranged in a grid are provided.
  • the interposer 20 is a BGA type substrate.
  • the solder balls 22 of the interposer 20 are electrically connected to the printed wiring 3b of the mother board 3.
  • the shield case 30 is a case that covers the silicon die 10 to be shielded.
  • the shield case 30 is bonded to the upper surface 20a of the interposer 20 on which the silicon die 10 is mounted, and covers the silicon die 10 while being bonded to the interposer 20.
  • the shield case 30 is formed of a metal material (conductive material), and is formed, for example, by bending a metal plate into a box shape.
  • the shield case 30 may be, for example, a metal material applied to the entire inner surface of a resin plate molded in a box shape.
  • the shield case 30 is electrically connected to a ground 21 provided on the upper surface 20a of the interposer 20.
  • a fourth external electrode of a capacitor 40 described later is electrically connected to the inner surface 30a of the shield case 30.
  • the capacitor 40 is a bypass capacitor provided between the power source of the silicon die 10 and the ground.
  • the capacitor 40 has a function of suppressing voltage fluctuation of the DC power supply, a function of removing noise (for example, noise entering between the power supply and the ground, noise generated by the operation of the silicon die 10), and the like.
  • the capacitor 40 is mounted between the upper surface 10a of the silicon die 10 and the inner surface 30a of the shield case 30.
  • the capacitor 40 is a chip-type multilayer capacitor and has a substantially rectangular parallelepiped shape.
  • the capacitor 40 is a three-terminal capacitor. Although two capacitors 40 are shown in FIG. 1, a predetermined number of capacitors necessary as bypass capacitors for the silicon die 10 are actually mounted. A part of the predetermined number of bypass capacitors may be mounted on the upper surface 20 a of the interposer 20.
  • FIGS. 2A and 2B are perspective views of the capacitor 40, where FIG. 2A is a perspective view seen from the upper surface side, and FIG. 2B is a perspective view seen from the lower surface side.
  • 3A and 3B are side sectional views of the capacitor 40, where FIG. 3A is a side sectional view of a portion where the first internal electrode is disposed, and FIG. 3B is a side sectional view of a portion where the second external electrode is disposed. It is.
  • FIG. 4 is an exploded perspective view showing a laminated state of the laminated body of the capacitors 40.
  • the capacitor 40 includes a multilayer body 41, a first external electrode 42, a second external electrode 43, a third external electrode 44, and a fourth external electrode 45.
  • the capacitor 40 is a three-terminal capacitor including a first external electrode 42 and a second external electrode 43 serving as power supply terminals, and a third external electrode 44 and a fourth external electrode 45 serving as ground terminals.
  • the first to third external electrodes 42, 43, 44 are provided on the lower surface (bottom surface) 41 b of the multilayer body 41.
  • the fourth external electrode 45 is provided on the upper surface (top surface) 41 a of the multilayer body 41.
  • the laminated body 41 has a plurality of dielectric layers 46 and a plurality of first internal electrodes 47 and second internal electrodes 48.
  • the laminated body 41 has a rectangular parallelepiped shape.
  • the stacked body 41 is a vertically stacked structure in which the first internal electrodes 47 and the second internal electrodes 48 are alternately stacked with the dielectric layer 46 sandwiched along the horizontal direction (horizontal direction). Therefore, the stacking direction D of the stacked body 41 is substantially parallel to the upper surface 10a of the silicon die 10 on which the capacitor 40 is mounted. Therefore, the dielectric layer 46, the first internal electrode 47, and the second internal electrode 48 stacked by the stacked body 41 are substantially perpendicular to the upper surface 10 a of the silicon die 10.
  • the dielectric layer 46 is formed in a rectangular film shape.
  • the dielectric layer 46 is made of, for example, a dielectric ceramic mainly composed of BaTiO 3 , CaTiO 3 , SrTiO 3 , CaZrO 3 or the like. Note that subcomponents such as a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound may be added to these main components.
  • the first and second internal electrodes 47 and 48 are formed in a thin film shape.
  • the first and second internal electrodes 47 and 48 are made of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like.
  • the first internal electrodes 47 and the second internal electrodes 48 are alternately stacked so as to face each other with the dielectric layer 46 interposed therebetween.
  • the first internal electrode 47 includes a main body portion 47a, a lead portion 47b, and a lead portion 47c.
  • the main body 47 a is disposed inside the peripheral edge of the dielectric layer 46 and has a rectangular shape smaller than the dielectric layer 46.
  • the lead portion 47b is provided at one end portion of the lower end portion of the main body portion 47a, and is led out to the lower end portion of the dielectric layer 46 (the lower surface 41b of the multilayer body 41).
  • the lead portion 47 c is provided at the other end portion of the lower end portion of the main body portion 47 a and is led out to the lower end portion of the dielectric layer 46.
  • the second internal electrode 48 includes a main body portion 48a, a lead portion 48b, and a lead portion 48c.
  • the main body 48a faces the main body 47a of the first internal electrode 47 through the dielectric layer 46, and has the same rectangular shape as the main body 47a.
  • the lead portion 48b is provided at an intermediate portion (with a predetermined gap between the lead portion 47b and the lead portion 47c of the first internal electrode 47) at the lower end portion of the main body portion 48a, and the lower end portion of the dielectric layer 46 ( The bottom surface 41b) of the laminate 41 is drawn out.
  • the lead portion 48c is provided at an intermediate portion at the upper end portion of the main body portion 48a, and is led out to the upper end portion of the dielectric layer 46 (the upper surface 41a of the multilayer body 41).
  • the lead portion 48b and the lead portion 48c face each other with the main body portion 48a interposed therebetween.
  • the first to fourth external electrodes 42 to 45 include, for example, a Cu electrode and a plating layer (for example, a nickel plating layer and a tin plating layer covering the nickel plating layer) formed so as to cover the Cu electrode. ing.
  • a plating layer for example, a nickel plating layer and a tin plating layer covering the nickel plating layer
  • the first external electrode 42 is provided on one side in the longitudinal direction on the lower surface 41 b of the multilayer body 41.
  • the first external electrode 42 is electrically connected to the lead portions 47 b of the plurality of first internal electrodes 47.
  • the second external electrode 43 is provided on the other side in the longitudinal direction on the lower surface 41 b of the multilayer body 41.
  • the second external electrode 43 is electrically connected to the lead portions 47 c of the plurality of first internal electrodes 47.
  • the third external electrode 44 is provided at an intermediate portion in the longitudinal direction on the lower surface 41b of the multilayer body 41.
  • the third external electrode 44 is disposed with a predetermined gap between the first external electrode 42 and the second external electrode 43.
  • the third external electrode 44 is electrically connected to the lead portions 48 b of the plurality of second internal electrodes 48.
  • the fourth external electrode 45 is provided at an intermediate portion in the longitudinal direction on the upper surface 41 a of the multilayer body 41.
  • the fourth external electrode 45 and the third external electrode 44 face each other with the stacked body 41 interposed therebetween.
  • the fourth external electrode 45 is electrically connected to the lead portions 48 c of the plurality of second internal electrodes 48.
  • the first external electrode 42 is electrically connected to the power supply terminal 11 on the upper surface 10 a of the silicon die 10
  • the second external electrode 43 is electrically connected to the power supply terminal 12 on the upper surface 10 a of the silicon die 10.
  • the third external electrode 44 is electrically connected to the ground terminal 13 on the upper surface 10a of the silicon die 10
  • the fourth external electrode 45 is electrically connected to the inner surface 30a of the shield case 30. It is mounted between the upper surface 10 a and the inner surface 30 a of the shield case 30.
  • FIGS. 5A and 5B are perspective views of the capacitor 50, where FIG. 5A is a perspective view seen from the upper surface side, and FIG. 5B is a perspective view seen from the lower surface side.
  • 6A and 6B are side sectional views of the capacitor 50, where FIG. 6A is a side sectional view of a location where the first internal electrode is disposed, and FIG. 6B is a side sectional view of a location where the second external electrode is disposed. It is.
  • FIG. 7 is an exploded perspective view showing a laminated state of the laminated body of the capacitors 50.
  • the capacitor 50 includes a multilayer body 51, a first external electrode 52, a second external electrode 53, a third external electrode 54, and a fourth external electrode 55.
  • the capacitor 50 is a three-terminal capacitor including a first external electrode 52 and a second external electrode 53 that are power supply terminals, and a third external electrode 54 and a fourth external electrode 55 that are ground terminals.
  • the first to third external electrodes 52, 53, 54 are provided on the lower surface (bottom surface) 51 b of the multilayer body 51.
  • the first external electrode 52 is provided not only on the lower surface 51 b of the multilayer body 51 but also on a part of the side surface 51 c of the multilayer body 51.
  • the second external electrode 53 is provided not only on the lower surface 51 b of the multilayer body 51 but also on a part of the side surface 51 d facing the side surface 51 c of the multilayer body 51.
  • the fourth external electrode 55 is provided on the entire upper surface (top surface) 51 a of the multilayer body 51.
  • the fourth external electrode 55 is provided not only on the upper surface 51 a of the multilayer body 51 but also on part of the side surfaces 51 c and 51 d facing the multilayer body 51.
  • the multilayer body 51 includes a plurality of dielectric layers 56, a plurality of first internal electrodes 57, and second internal electrodes 58, with the dielectric layer 56 interposed therebetween.
  • the first internal electrodes 57 and the second internal electrodes 58 are alternately stacked.
  • the laminated body 51 is different from the laminated body 41 in the shapes of the first internal electrode 57 and the second internal electrode 58.
  • the first internal electrode 57 includes a main body portion 57a, a lead portion 57b, and a lead portion 57c.
  • the main body portion 57a has the same shape as the main body portion 47a of the first internal electrode 47 of the capacitor 40 described above.
  • the lead portion 57b is provided at one end portion of the lower end portion of the main body portion 57a.
  • the lower end portion of the dielectric layer 56 (the lower surface 51b of the stacked body 51) and one side end portion (laminated body) connected to the lower end portion. 51 to the side 51c).
  • the lead portion 57c is provided at the other end portion of the lower end portion of the main body portion 57a, and is led out to the lower end portion of the dielectric layer 56 and the other side end portion (side surface 51d of the stacked body 51) connected to the lower end portion. ing.
  • the second internal electrode 58 includes a main body portion 58a, a lead portion 58b, and a lead portion 58c.
  • the main body portion 58a has the same shape as the main body portion 48a of the second internal electrode 48 of the capacitor 40 described above.
  • the lead portion 58b is provided at an intermediate portion (with a predetermined interval between the lead portion 57b and the lead portion 57c of the first internal electrode 57) at the lower end portion of the main body portion 58a, and the lower end portion of the dielectric layer 56 ( The bottom surface 51b) of the laminate 51 is drawn out.
  • the lead portion 58c is provided over the entire upper end portion of the main body portion 58a, and the entire upper end portion of the dielectric layer 56 (the upper surface 51a of the stacked body 51) and the side end portions on both sides connected to the upper end portion (the side surfaces 51c of the stacked body 51) , 51d).
  • the drawer portion 58b and the drawer portion 58c face each other with the main body portion 58a interposed therebetween.
  • the first to fourth external electrodes 52 to 55 have shapes of the first external electrode 52, the second external electrode 53, and the fourth external electrode 55 as compared with the first to fourth external electrodes 42 to 45 of the capacitor 40 described above. Is different.
  • the first external electrode 52 is provided on one side in the longitudinal direction of the lower surface 51b of the multilayer body 51 and a part of one side surface 51c of the multilayer body 51 connected to the end portion on the one side. Therefore, the first external electrode 52 extends from one end side of the lower surface 51b of the multilayer body 51 to a part of the side surface 51c, and has a substantially L-shaped cross section. The first external electrode 52 is electrically connected to the lead portions 57 b of the plurality of first internal electrodes 57.
  • the second external electrode 53 is provided on the other side in the longitudinal direction of the lower surface 51b of the multilayer body 51 and a part of the other side surface 51d of the multilayer body 51 connected to the end of the other side. Therefore, the second external electrode 53 extends from the other end side of the lower surface 51b of the multilayer body 51 to a part of the side surface 51d, and has a substantially L-shaped cross section.
  • the second external electrode 53 is electrically connected to the lead portions 57 c of the plurality of first internal electrodes 57.
  • the fourth external electrode 55 is provided on the entire upper surface 51a of the multilayer body 51 and part of the side surfaces 51c and 51d on both sides of the multilayer body 51 connected to the end of the upper surface 51a. Therefore, the fourth external electrode 55 extends from the entire top surface 51a of the multilayer body 51 to a part of the side surfaces 51c and 51d on both sides, and has a substantially U-shaped cross section.
  • the fourth external electrode 55 is electrically connected to the lead portions 58 c of the plurality of second internal electrodes 58.
  • the fourth external electrode 55 and the first external electrode 52 are disposed on the side surface 51c of the multilayer body 51 with a predetermined interval. Further, the fourth external electrode 55 and the second external electrode 53 are arranged on the side surface 51d of the multilayer body 51 with a predetermined interval.
  • the first external electrode 52 is electrically connected to the power supply terminal 11 on the upper surface 10 a of the silicon die 10
  • the second external electrode 53 is electrically connected to the power supply terminal 12 on the upper surface 10 a of the silicon die 10.
  • the third external electrode 54 is electrically connected to the ground terminal 13 on the upper surface 10a of the silicon die 10
  • the fourth external electrode 55 is electrically connected to the inner surface 30a of the shield case 30. It is mounted between the upper surface 10 a and the inner surface 30 a of the shield case 30.
  • a three-terminal capacitor 40 (bypass capacitor) is mounted between the upper surface 10 a of the silicon die 10 and the inner surface 30 a of the shield case 30, and is connected to the second internal electrode 48 of the capacitor 40.
  • Four external electrodes 44 and 45 are connected to the ground terminal 13 on the upper surface 10 a and the inner surface 30 a of the shield case 30. Since the stacking direction D of the capacitor 40 is substantially parallel to the upper surface 10a of the silicon die 10, the second internal electrode 48 is disposed along the vertical direction between the upper surface 10a and the inner surface 30a. A path is formed between the upper surface 10a and the inner surface 30a by the second internal electrode 48 extending in the vertical direction and the third and fourth external electrodes 44 and 45 connected above and below the second internal electrode 48. .
  • the heat is conducted from the ground terminal 13 on the upper surface 10a through the third external electrode 44, the second internal electrode 48, and the fourth external electrode 45 of the capacitor 40 to the shield case 30, It is discharged to the outside of the shield case 30. Since the metal electrodes 44, 45, and 48 have higher thermal conductivity than resin (for example, grease provided between a silicon die and a shield case in a conventional IC package), heat is efficiently conducted. be able to. In particular, in the IC package 1, the capacitor 40 is directly disposed on the upper surface 10 a of the silicon die 10.
  • the second internal electrode 48 of the capacitor 40 is disposed substantially perpendicular to the upper surface 10 a of the silicon die 10, so that the capacitor 40 formed between the silicon die 10 and the shield case 30.
  • the length of the heat path using is short. Therefore, in the IC package 1, the heat generated in the silicon die 10 can be efficiently radiated through the capacitor 40.
  • the inductance of the IC package 1 can be reduced. Further, in the IC package 1, since the capacitor 40 is configured as a three-terminal capacitor, the inductance of the capacitor 40 can be reduced. Further, in the IC package 1, since the capacitor 40 is directly arranged on the silicon die 10, the inductance of the wiring between the capacitor 40 and the silicon die 10 can be reduced.
  • the capacitor 40 is mounted between the upper surface 10a of the silicon die 10 and the inner surface 30a of the shield case 30 as described above.
  • a heat path using the capacitor 40 is formed between the inner surface 30a and the inner surface 30a, and heat dissipation can be improved.
  • the IC package 1 and the wiring board 2 according to the first embodiment since the inductance is reduced as described above, the anti-resonance between the capacitance of the silicon die 10 and the inductance of the capacitor 40 is suppressed by the capacitor 40. The power supply impedance can be reduced.
  • the fourth external electrode 55 is provided from the upper surface 51 a of the multilayer body 51 to a part of the side surfaces 51 c and 51 d, and the first and second external electrodes 52 and 53 are the lower surface 51 b of the multilayer body 51.
  • the physical distance between the fourth external electrode 55 serving as the ground terminal and the first and second external electrodes 52 and 53 serving as the power supply terminal is reduced.
  • Inductance (ESL) can be further reduced.
  • ESL Inductance
  • FIG. 8 is a side sectional view showing a configuration of the wiring board 6 on which the IC package 5 according to the second embodiment is mounted.
  • the IC package 5 differs from the IC package 1 according to the first embodiment in that a capacitor is mounted between the interposer and the shield case.
  • the wiring board 6 is different from the wiring board 2 according to the first embodiment in that an IC package 5 is mounted instead of the IC package 1 according to the first embodiment. Therefore, in the following description, only the IC package 5 will be described.
  • the IC package 5 includes a silicon die 70 (corresponding to the semiconductor integrated circuit recited in the claims), an interposer 80 (corresponding to the relay member recited in the claims), and a shield case 90 (shielding according to the claims). And a capacitor 100.
  • the silicon die 70 is different from the silicon die 10 of the IC package 1 according to the first embodiment in that a bypass capacitor is not mounted on the upper surface 70a. Therefore, the electrode terminal and the ground terminal are not provided on the upper surface 70 a of the silicon die 70. In order to improve heat dissipation, grease or the like may be provided between the upper surface 70a of the silicon die 70 and the inner surface 90a of the shield case 90.
  • the interposer 80 is different from the interposer 20 of the IC package 1 according to the first embodiment in that the capacitor 100 is mounted on the upper surface (top surface) 80a.
  • two power terminals (power pads) 82 and 83 and one ground terminal (ground pad) 84 are provided on the upper surface 80 a of the interposer 80 for each mounted capacitor 100.
  • the arrangement and shape of the power terminals 82 and 83 and the ground terminal 84 are the same as those of the power terminals 11 and 12 and the ground terminal 13 provided on the silicon die 10 of the IC package 1 according to the first embodiment.
  • the power terminals 82 and 83 are connected to a power line in the interposer 80.
  • the ground terminal 84 is connected to a ground line in the interposer 80.
  • a first external electrode of the capacitor 100 is electrically connected to the power supply terminal 82.
  • a second external electrode of the capacitor 100 is electrically connected to the power supply terminal 83.
  • a third external electrode of the capacitor 100 is electrically connected to the ground terminal 84.
  • the shield case 90 is a shield case similar to the shield case 30 of the IC package 1 according to the first embodiment.
  • the shield case 90 is electrically connected to a ground 81 provided on the upper surface 80a of the interposer 80.
  • the fourth external electrode of the capacitor 100 mounted between the inner surface 90a of the shield case 90 and the upper surface 80a of the interposer 80 is electrically connected.
  • the capacitor 100 is a bypass capacitor provided between the power source of the silicon die 70 and the ground.
  • the capacitor 100 differs from the capacitor 40 according to the first embodiment in that it is mounted between the upper surface 80a of the interposer 80 and the inner surface 90a of the shield case 90.
  • the capacitor 100 for example, a capacitor having the same structure as the capacitor 40 and the capacitor 50 described in the first embodiment is applied. However, since the capacitor 100 is mounted between the upper surface 80a of the interposer 80 and the inner surface 90a of the shield case 90, the size is different from that of the capacitors 40 and 50 according to the first embodiment (at least in the vertical direction). Increase in size).
  • the capacitor 100 is disposed around the silicon die 70.
  • the capacitor 100 is preferably disposed near the silicon die 70 in order to reduce the inductance of the wiring between the silicon die 70 and the capacitor 100.
  • the first external electrode 42 is electrically connected to the power supply terminal 82 on the upper surface 80 a of the interposer 80
  • the second external electrode 43 is connected to the power supply terminal 83 on the upper surface 80 a of the interposer 80.
  • the third external electrode 44 is electrically connected to the ground terminal 84 on the upper surface 80a of the interposer 80
  • the fourth external electrode 45 is electrically connected to the inner surface 90a of the shield case 90
  • Capacitor 100 is mounted between upper surface 80 a of interposer 80 and inner surface 90 a of shield case 90.
  • a three-terminal capacitor 100 (bypass capacitor) is mounted between the upper surface 80 a of the interposer 80 and the inner surface 90 a of the shield case 90, and is connected to the second internal electrode 48 of the capacitor 100.
  • the external electrodes 44 and 45 are connected to the ground terminal 84 on the upper surface 80 a and the inner surface 90 a of the shield case 90. Since the stacking direction D of the capacitor 100 is substantially parallel to the upper surface 80a of the interposer 80, the second internal electrode 48 is disposed along the vertical direction between the upper surface 80a and the inner surface 90a. A path is formed between the upper surface 80a and the inner surface 90a by the second internal electrode 48 extending in the vertical direction and the third and fourth external electrodes 44, 45 connected above and below the second internal electrode 48. .
  • the heat generated in the silicon die 70 is conducted to the lower interposer 80, the third external electrode 44, the second internal electrode 48, and the fourth external electrode 45 of the capacitor 100 from the ground terminal 84 on the upper surface 80 a of the interposer 80. It is conducted to the shield case 90 through the path and discharged to the outside of the shield case 90.
  • the second internal electrode 48 is disposed substantially perpendicular to the upper surface 80 a of the interposer 80, so that heat generated by using the capacitor 100 formed between the interposer 80 and the shield case 90 can be obtained.
  • the path length is short. Therefore, in the IC package 5, the heat generated in the silicon die 70 can be efficiently radiated through the capacitor 100.
  • the inductance of the IC package 5 can be reduced. Further, in the IC package 5, since the capacitor 100 is configured as a three-terminal capacitor, the inductance (ESL) of the capacitor 100 can be reduced.
  • the capacitor 100 is mounted between the upper surface 80a of the interposer 80 and the inner surface 90a of the shield case 90 as described above.
  • a heat path using the capacitor 100 can be formed between the inner surface 90a and the heat dissipation can be improved.
  • the capacitor 100 since the inductance is reduced as described above, the anti-resonance between the capacitance of the silicon die 70 and the inductance of the capacitor 100 is suppressed by the capacitor 100.
  • the power supply impedance can be reduced.
  • the ESD resistance is excellent, and the influence of static electricity on the silicon die 70 can be suppressed.
  • the present invention is not limited to the above-described embodiments, and various modifications can be made.
  • the above embodiment has been described in the state of the wiring boards 2 and 6 in which the IC packages 1 and 5 are mounted on the mother board 3, the present invention may be applied to the IC packages 1 and 5 alone.
  • the grounds 21 and 81 are provided on the upper surfaces 20a and 80a of the interposers 20 and 80, and the shield cases 30 and 90 are joined to the upper surfaces 20a and 80a of the interposers 20 and 80 and electrically connected to the grounds 21 and 81.
  • the shield case may be joined to the side surface of the interposer and electrically connected to the ground provided in the interposer.
  • the first internal electrode 47 and the second internal electrode 48 are arranged substantially perpendicular to the upper surface 10a of the silicon die 10 by being stacked in a stacking direction that is substantially parallel to the upper surface 10a of the silicon die 10.
  • the capacitor 40 and the like are illustrated, the first internal electrode and the second internal electrode are disposed substantially perpendicular to the upper surface of the silicon die by being stacked in a stacking direction that is substantially perpendicular to the upper surface of the silicon die. It is also possible to produce a capacitor.
  • the interposer 20 is applied as the relay member, but a rewiring layer or the like may be applied as the relay member.

Abstract

An IC package (1) is provided with a silicon die (10), an interposer (20), a shield case (30) that is connected to a ground (21), and a capacitor (40), and on an upper surface (10a) of the silicon die (10), first and second power supply terminals (11, 12) and a ground terminal (13) are provided. The capacitor (40) has: a laminated body wherein a first internal electrode and a second internal electrode are laminated by having a dielectric layer therebetween; a first external electrode and a second external electrode, which are provided on a lower surface of the laminated body, and are connected to the first internal electrode; a third external electrode, which is provided on the lower surface of the laminated body, and is connected to the second internal electrode; and a fourth external electrode, which is provided on an upper surface of the laminated body, and is connected to the second internal electrode. The first external electrode is connected to the first power supply terminal (11), the second external electrode is connected to the second power supply terminal (12), the third external electrode is connected to the ground terminal (13), and the fourth external electrode is connected to the shield case (30).

Description

半導体パッケージ、及び、配線基板Semiconductor package and wiring board
　本発明は、半導体パッケージ、及び、この半導体パッケージが実装された配線基板に関する。 The present invention relates to a semiconductor package and a wiring board on which the semiconductor package is mounted.
　半導体集積回路を備える半導体パッケージは、例えば、スマートフォン、パーソナルコンピュータ等の各種電子機器に組み込まれている。半導体パッケージには、半導体集積回路の動作中の電圧変動の抑制やノイズの除去等のために、半導体集積回路の電源－グランド間に実装されるバイパスコンデンサ（デカップリングコンデンサ）を備えるものがある。バイパスコンデンサが実装された場合、電圧変動を抑制する観点から、電源インピーダンスは可能な限り低いことが望ましい。 A semiconductor package including a semiconductor integrated circuit is incorporated in various electronic devices such as a smartphone and a personal computer. Some semiconductor packages include a bypass capacitor (decoupling capacitor) mounted between the power supply and the ground of the semiconductor integrated circuit in order to suppress voltage fluctuation during operation of the semiconductor integrated circuit, to eliminate noise, and the like. When a bypass capacitor is mounted, the power source impedance is desirably as low as possible from the viewpoint of suppressing voltage fluctuation.
　例えば、特許文献１には、半導体集積回路チップ本体と、半導体集積回路チップ本体の外部面に形成された入出力端子と、入出力端子に電気的に連結されたデカップリングキャパシタとを含む半導体集積回路チップ、及び、この半導体集積回路チップがパッケージ基板に実装された半導体集積回路チップパッケージが開示されている。この構成により、デカップリングキャパシタと半導体集積回路チップ本体との間のインダクタンスが最小化されるので、電源インピーダンスが低減される。 For example, Patent Document 1 discloses a semiconductor integrated circuit including a semiconductor integrated circuit chip body, an input / output terminal formed on an external surface of the semiconductor integrated circuit chip body, and a decoupling capacitor electrically connected to the input / output terminal. A circuit chip and a semiconductor integrated circuit chip package in which the semiconductor integrated circuit chip is mounted on a package substrate are disclosed. With this configuration, since the inductance between the decoupling capacitor and the semiconductor integrated circuit chip main body is minimized, the power source impedance is reduced.
特開２０１０－１１８６３９号公報JP 2010-118639 A
　ところで、近年、スマートフォン等の電子機器では、高性能化や多機能化に伴い、半導体集積回路の高集積化や低電圧・大電流による高速駆動化が進んでいる。これに伴って、半導体集積回路の発熱量が増大している。そのため、半導体集積回路で発生した熱を半導体パッケージから効率良く放熱させることが望まれている。しかしながら、特許文献１に開示された技術は、電源インピーダンスを低減することはできるが、放熱については考慮されていない。 By the way, in recent years, electronic devices such as smartphones have become increasingly integrated with semiconductor integrated circuits and driven at a high speed due to a low voltage and a large current in accordance with higher performance and more functions. As a result, the amount of heat generated in the semiconductor integrated circuit is increasing. Therefore, it is desired to efficiently dissipate heat generated in the semiconductor integrated circuit from the semiconductor package. However, the technique disclosed in Patent Document 1 can reduce the power supply impedance, but does not consider heat dissipation.
　本発明は、上記問題点を解消する為になされたものであり、電源インピーダンスを低減しつつ放熱性を向上させることが可能な半導体パッケージ及び配線基板を提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor package and a wiring board capable of improving heat dissipation while reducing power source impedance.
　本発明に係る半導体パッケージは、半導体集積回路と、半導体集積回路が実装される中継部材と、半導体集積回路を覆うと共に中継部材に設けられたグランドに電気的に接続されるシールド部材と、半導体集積回路の電源－グランド間に電気的に接続されるコンデンサと、を備え、半導体集積回路の上面には、第１電源端子、第２電源端子及びグランド端子が設けられ、コンデンサは、誘電体層を挟んで第１内部電極と第２内部電極とが積層された積層体と、積層体の下面に設けられ、第１内部電極に接続された第１外部電極と、積層体の下面に設けられ、第１内部電極に接続された第２外部電極と、積層体の下面に設けられ、第２内部電極に接続された第３外部電極と、積層体の上面に設けられ、第２内部電極に接続された第４外部電極と、を有し、コンデンサは、第１外部電極が半導体集積回路の第１電源端子に電気的に接続され、第２外部電極が半導体集積回路の第２電源端子に電気的に接続され、第３外部電極が半導体集積回路のグランド端子に電気的に接続され、第４外部電極がシールド部材に電気的に接続されることで、半導体集積回路とシールド部材との間に実装されることを特徴とする。 A semiconductor package according to the present invention includes a semiconductor integrated circuit, a relay member on which the semiconductor integrated circuit is mounted, a shield member that covers the semiconductor integrated circuit and is electrically connected to a ground provided on the relay member, and a semiconductor integrated circuit A capacitor electrically connected between a power source and a ground of the circuit, and a first power source terminal, a second power source terminal, and a ground terminal are provided on the upper surface of the semiconductor integrated circuit, and the capacitor includes a dielectric layer. A laminated body in which the first internal electrode and the second internal electrode are laminated, and a first external electrode connected to the first internal electrode, provided on a lower surface of the laminated body, and provided on a lower surface of the laminated body; A second external electrode connected to the first internal electrode, a third external electrode provided on the lower surface of the multilayer body and connected to the second internal electrode, and provided on an upper surface of the multilayer body and connected to the second internal electrode Fourth external electrode The capacitor has a first external electrode electrically connected to the first power supply terminal of the semiconductor integrated circuit, a second external electrode electrically connected to the second power supply terminal of the semiconductor integrated circuit, and a third The external electrode is electrically connected to the ground terminal of the semiconductor integrated circuit, and the fourth external electrode is electrically connected to the shield member, so that the external electrode is mounted between the semiconductor integrated circuit and the shield member. To do.
　本発明に係る半導体パッケージでは、コンデンサ（バイパスコンデンサ）が半導体集積回路とシールド部材との間に実装され、このコンデンサの第２内部電極に接続された第３、第４外部電極が半導体集積回路のグランド端子とシールド部材に接続されている。この構成により、半導体集積回路で発生する熱が、グランド端子からコンデンサの第３外部電極、第２内部電極、第４外部電極のパスを通ってシールド部材に伝導され、シールド部材から放熱される。金属製の電極は、熱伝導率が高いので、熱を効率良く伝導することができる。特に、コンデンサが半導体集積回路の上面に直接配置されているので、半導体集積回路で発生した熱をコンデンサを介して効率良く放熱することができる。このように、本発明に係る半導体パッケージによれば、半導体集積回路とシールド部材との間にコンデンサを利用した熱のパスを設けることにより、放熱性を向上させることができる。 In the semiconductor package according to the present invention, a capacitor (bypass capacitor) is mounted between the semiconductor integrated circuit and the shield member, and the third and fourth external electrodes connected to the second internal electrode of the capacitor are the semiconductor integrated circuit. Connected to ground terminal and shield member. With this configuration, heat generated in the semiconductor integrated circuit is conducted from the ground terminal through the third external electrode, the second internal electrode, and the fourth external electrode of the capacitor to the shield member, and is radiated from the shield member. Since the metal electrode has high thermal conductivity, it can conduct heat efficiently. In particular, since the capacitor is directly disposed on the upper surface of the semiconductor integrated circuit, the heat generated in the semiconductor integrated circuit can be efficiently radiated through the capacitor. As described above, according to the semiconductor package of the present invention, the heat dissipation can be improved by providing the heat path using the capacitor between the semiconductor integrated circuit and the shield member.
　また、本発明に係る半導体パッケージでは、コンデンサのグランドへの接続箇所として半導体集積回路のグランド端子とシールド部材があるので、コンデンサの電源―グランド間のパスが増え、半導体パッケージのインダクタンスを低減することができる。また、本発明に係る半導体パッケージでは、コンデンサが３端子コンデンサとして構成されているので、インダクタンスを低減することができる。また、本発明に係る半導体パッケージでは、コンデンサが半導体集積回路に直接配置されているので、コンデンサと半導体集積回路との間の配線のインダクタンスを低減することができる。これにより、本発明に係る半導体パッケージによれば、半導体集積回路の容量とコンデンサのインダクタンスとの間の反共振をコンデンサによって抑制することができ、電源インピーダンスを低減することができる。したがって、本発明に係る半導体パッケージによれば、電源インピーダンスを低減しつつ放熱性を向上させることが可能となる。 Further, in the semiconductor package according to the present invention, the ground terminal of the semiconductor integrated circuit and the shield member are connected to the ground of the capacitor. Therefore, the path between the power source and the ground of the capacitor is increased, and the inductance of the semiconductor package is reduced. Can do. In the semiconductor package according to the present invention, since the capacitor is configured as a three-terminal capacitor, the inductance can be reduced. In the semiconductor package according to the present invention, since the capacitor is directly disposed on the semiconductor integrated circuit, the inductance of the wiring between the capacitor and the semiconductor integrated circuit can be reduced. Thereby, according to the semiconductor package which concerns on this invention, the antiresonance between the capacity | capacitance of a semiconductor integrated circuit and the inductance of a capacitor | condenser can be suppressed with a capacitor | condenser, and power supply impedance can be reduced. Therefore, according to the semiconductor package of the present invention, it is possible to improve heat dissipation while reducing the power source impedance.
　本発明に係る半導体パッケージでは、コンデンサの第１内部電極及び第２内部電極は、半導体集積回路の上面に対して略垂直に配置されることが好ましい。このように構成することで、半導体集積回路とシールド部材との間に形成されるコンデンサを利用した熱のパスの長さが短くなるので、コンデンサを介して効率良く放熱することができる。 In the semiconductor package according to the present invention, the first internal electrode and the second internal electrode of the capacitor are preferably disposed substantially perpendicular to the upper surface of the semiconductor integrated circuit. With this configuration, the length of the heat path using the capacitor formed between the semiconductor integrated circuit and the shield member is shortened, so that heat can be efficiently radiated through the capacitor.
　本発明に係る半導体パッケージは、半導体集積回路と、半導体集積回路が実装される中継部材と、半導体集積回路を覆うと共に中継部材に設けられたグランドに電気的に接続されるシールド部材と、半導体集積回路の電源－グランド間に電気的に接続されるコンデンサと、を備え、中継部材の上面には、第１電源端子、第２電源端子及びグランド端子が設けられ、コンデンサは、誘電体層を挟んで第１内部電極と第２内部電極とが積層された積層体と、積層体の下面に設けられ、第１内部電極に接続された第１外部電極と、積層体の下面に設けられ、第１内部電極に接続された第２外部電極と、積層体の下面に設けられ、第２内部電極に接続された第３外部電極と、積層体の上面に設けられ、第２内部電極に接続された第４外部電極と、を有し、コンデンサは、第１外部電極が中継部材の第１電源端子に電気的に接続され、第２外部電極が中継部材の第２電源端子に電気的に接続され、第３外部電極が中継部材のグランド端子に電気的に接続され、第４外部電極がシールド部材に電気的に接続されることで、中継部材とシールド部材との間に実装されることを特徴とする。 A semiconductor package according to the present invention includes a semiconductor integrated circuit, a relay member on which the semiconductor integrated circuit is mounted, a shield member that covers the semiconductor integrated circuit and is electrically connected to a ground provided on the relay member, and a semiconductor integrated circuit A capacitor electrically connected between the power source and the ground of the circuit, and a first power source terminal, a second power source terminal and a ground terminal are provided on the upper surface of the relay member, and the capacitor sandwiches the dielectric layer The first internal electrode and the second internal electrode are stacked, the first external electrode connected to the first internal electrode is provided on the lower surface of the multilayer body, and the lower surface of the multilayer body is provided. A second external electrode connected to one internal electrode; a third external electrode connected to the second internal electrode; and a third external electrode connected to the second internal electrode; connected to the second internal electrode. A fourth external electrode; In the capacitor, the first external electrode is electrically connected to the first power supply terminal of the relay member, the second external electrode is electrically connected to the second power supply terminal of the relay member, and the third external electrode is connected to the relay member. The fourth external electrode is electrically connected to the shield member, and is mounted between the relay member and the shield member.
　本発明に係る半導体パッケージでは、コンデンサ（バイパスコンデンサ）が中継部材とシールド部材との間に実装され、このコンデンサの第２内部電極に接続された第３、第４外部電極が中継部材のグランド端子とシールド部材に接続されている。この構成により、半導体集積回路で発生する熱が、中継部材に伝導すると、中継部材のグランド端子からコンデンサの第３外部電極、第２内部電極、第４外部電極のパスを通ってシールド部材に伝導され、シールド部材から放熱される。金属製の電極は、熱伝導率が高いので、熱を効率良く伝導することができる。このように、本発明に係る半導体パッケージによれば、中継部材とシールド部材との間にコンデンサを利用した熱のパスを設けることにより、放熱性を向上させることができる。 In the semiconductor package according to the present invention, a capacitor (bypass capacitor) is mounted between the relay member and the shield member, and the third and fourth external electrodes connected to the second internal electrode of the capacitor are the ground terminals of the relay member. And connected to the shield member. With this configuration, when heat generated in the semiconductor integrated circuit is conducted to the relay member, the heat is conducted from the ground terminal of the relay member to the shield member through the path of the third external electrode, the second internal electrode, and the fourth external electrode of the capacitor. Then, heat is radiated from the shield member. Since the metal electrode has high thermal conductivity, it can conduct heat efficiently. As described above, according to the semiconductor package of the present invention, the heat dissipation can be improved by providing the heat path using the capacitor between the relay member and the shield member.
　また、本発明に係る半導体パッケージでは、コンデンサのグランドへの接続箇所として中継部材のグランド端子とシールド部材があるので、コンデンサの電源―グランド間のパスが増え、半導体パッケージのインダクタンスを低減することができる。また、本発明に係る半導体パッケージでは、コンデンサが３端子コンデンサとして構成されているので、インダクタンスを低減することができる。これにより、本発明に係る半導体パッケージによれば、半導体集積回路の容量とコンデンサのインダクタンスとの間の反共振をコンデンサによって抑制することができ、電源インピーダンスを低減することができる。したがって、本発明に係る半導体パッケージによれば、電源インピーダンスを低減しつつ放熱性を向上させることが可能となる。 Further, in the semiconductor package according to the present invention, since there are the ground terminal of the relay member and the shield member as the connection point of the capacitor to the ground, the path between the power source and the ground of the capacitor is increased, and the inductance of the semiconductor package can be reduced. it can. In the semiconductor package according to the present invention, since the capacitor is configured as a three-terminal capacitor, the inductance can be reduced. Thereby, according to the semiconductor package which concerns on this invention, the antiresonance between the capacity | capacitance of a semiconductor integrated circuit and the inductance of a capacitor | condenser can be suppressed with a capacitor | condenser, and power supply impedance can be reduced. Therefore, according to the semiconductor package of the present invention, it is possible to improve heat dissipation while reducing the power source impedance.
　特に、本発明に係る半導体パッケージでは、シールド部材の外部から静電気が入った場合でも、静電気をシールド部材から中継部材のグランドに直接逃すパスやシールド部材からコンデンサの第４外部電極、第２内部電極、第３外部電極を通って中継部材のグランドに逃すパスがあるので、ＥＳＤ（Ｅｌｅｃｔｒｏ　Ｓｔａｔｉｃ　Ｄｉｓｃｈａｒｇｅ）耐性に優れている。 In particular, in the semiconductor package according to the present invention, even when static electricity enters from the outside of the shield member, the fourth external electrode and the second internal electrode of the capacitor from the shield member and the path for directly discharging the static electricity from the shield member to the ground of the relay member Since there is a path to escape to the ground of the relay member through the third external electrode, it is excellent in ESD (Electro Static Discharge) resistance.
　本発明に係る半導体パッケージでは、コンデンサの第１内部電極及び第２内部電極は、中継部材の上面に対して略垂直に配置されることが好ましい。このように構成することで、中継部材とシールド部材との間に形成されるコンデンサを利用した熱のパスの長さが短くなるので、コンデンサを介して効率良く放熱することができる。 In the semiconductor package according to the present invention, it is preferable that the first internal electrode and the second internal electrode of the capacitor are arranged substantially perpendicular to the upper surface of the relay member. With this configuration, the length of the heat path using the capacitor formed between the relay member and the shield member is shortened, so that heat can be efficiently radiated through the capacitor.
　本発明に係る半導体パッケージでは、グランド端子は、第１電源端子と第２電源端子との間に配置され、第１外部電極は、積層体の下面の一端側に配置され、第２外部電極は、積層体の下面の他端側に配置され、第３外部電極は、積層体の下面の第１外部電極と第２外部電極との間に配置されることが好ましい。このように構成することで、コンデンサの下面（底面）には両端部に電源用端子（第１外部電極、第２外部電極）が配置されると共にその間にグランド用端子（第３外部電極）が配置され、上面（頂面）にはグランド用端子（第４外部電極）が配置される３端子コンデンサを構成することができる。 In the semiconductor package according to the present invention, the ground terminal is disposed between the first power terminal and the second power terminal, the first external electrode is disposed on one end side of the lower surface of the stacked body, and the second external electrode is The third external electrode is preferably disposed between the first external electrode and the second external electrode on the bottom surface of the multilayer body. With this configuration, the power supply terminals (first external electrode and second external electrode) are arranged at both ends of the lower surface (bottom surface) of the capacitor, and the ground terminal (third external electrode) is interposed therebetween. It is possible to configure a three-terminal capacitor that is disposed and has a ground terminal (fourth external electrode) disposed on the top surface (top surface).
　本発明に係る半導体パッケージでは、第１外部電極は、積層体の下面の一端側から積層体の一側面の一部に設けられ、第２外部電極は、積層体の下面の他端側から積層体の一側面に対向する他側面の一部に設けられることが好ましい。このように構成することで、コンデンサの下面の電源用端子（第１外部電極、第２外部電極）とコンデンサの上面のグランド用端子（第４外部電極）との距離が近くなり、コンデンサのインダクタンス（ＥＳＬ（Ｅｑｕｉｖａｌｅｎｔ　Ｓｅｒｉｅｓ　Ｉｎｄｕｃｔａｎｃｅ：等価直列インダクタンス））を低減することができる。 In the semiconductor package according to the present invention, the first external electrode is provided on a part of one side surface of the multilayer body from one end side of the lower surface of the multilayer body, and the second external electrode is laminated from the other end side of the lower surface of the multilayer body. It is preferable to be provided on a part of the other side facing the one side of the body. With this configuration, the distance between the power supply terminals (first external electrode and second external electrode) on the lower surface of the capacitor and the ground terminal (fourth external electrode) on the upper surface of the capacitor is reduced, and the inductance of the capacitor is reduced. (ESL (Equivalent Series Inductance)) can be reduced.
　本発明に係る半導体パッケージでは、第４外部電極は、積層体の上面全体に設けられることが好ましい。このように構成することで、コンデンサの下面の電源端子（第１外部電極、第２外部電極）とコンデンサの上面のグランド端子（第４外部電極）との距離が近くなり、コンデンサのインダクタンス（ＥＳＬ）を低減することができる。また、第４外部電極の面積を大きくすることで、シールド部材への接地面積が大きくなるので、放熱性を更に向上させることができる。 In the semiconductor package according to the present invention, the fourth external electrode is preferably provided over the entire top surface of the stack. With this configuration, the distance between the power supply terminals (first external electrode and second external electrode) on the lower surface of the capacitor and the ground terminal (fourth external electrode) on the upper surface of the capacitor is reduced, and the inductance (ESL) of the capacitor is reduced. ) Can be reduced. Moreover, since the ground contact area to the shield member is increased by increasing the area of the fourth external electrode, the heat dissipation can be further improved.
　本発明に係る半導体パッケージでは、第４外部電極は、積層体の上面から積層体の一側面の一部及び当該一側面に対向する他側面の一部に設けられることが好ましい。このように構成することで、コンデンサの下面の電源端子（第１外部電極、第２外部電極）とコンデンサの上面のグランド端子（第４外部電極）との距離が更に近くなり、コンデンサのインダクタンス（ＥＳＬ）を低減することができる。 In the semiconductor package according to the present invention, it is preferable that the fourth external electrode is provided on a part of one side surface of the multilayer body and a part of the other side surface facing the one side surface from the top surface of the multilayer body. With this configuration, the distance between the power supply terminals (first external electrode and second external electrode) on the lower surface of the capacitor and the ground terminal (fourth external electrode) on the upper surface of the capacitor is further reduced, and the inductance ( ESL) can be reduced.
　本発明に係る半導体パッケージでは、中継部材は、インターポーザであることが好ましい。このように構成することで、インターポーザにより半導体集積回路を支持しつつ端子間隔等を変換することができる。 In the semiconductor package according to the present invention, the relay member is preferably an interposer. With this configuration, the terminal interval and the like can be converted while the semiconductor integrated circuit is supported by the interposer.
　本発明に係る配線基板は、マザー基板と、マザー基板に実装される半導体パッケージと、を備え、半導体パッケージは、上述した各半導体パッケージであり、半導体パッケージの中継部材は、マザー基板と半導体パッケージの半導体集積回路とを中継することを特徴とする。 A wiring board according to the present invention includes a mother board and a semiconductor package mounted on the mother board. The semiconductor package is each of the semiconductor packages described above, and the relay member of the semiconductor package includes the mother board and the semiconductor package. It is characterized by relaying to a semiconductor integrated circuit.
　本発明に係る配線基板によれば、マザー基板に上述した効果を奏する半導体パッケージが実装されているので、放熱性を向上させることができると共に、電源インピーダンスを低減することができる。 According to the wiring board according to the present invention, since the semiconductor package having the above-described effects is mounted on the mother board, it is possible to improve heat dissipation and reduce power supply impedance.
　本発明によれば、電源インピーダンスを低減しつつ放熱性を向上させることが可能となる。 According to the present invention, it is possible to improve heat dissipation while reducing power source impedance.
第１実施形態に係る半導体パッケージが実装された配線基板の構成を示す側断面図である。It is a sectional side view which shows the structure of the wiring board with which the semiconductor package which concerns on 1st Embodiment was mounted. 図１に示すコンデンサの斜視図であり、（ａ）が上面側から見た斜視図であり、（ｂ）が下面側から見た斜視図である。FIG. 2 is a perspective view of the capacitor shown in FIG. 1, (a) is a perspective view seen from the upper surface side, and (b) is a perspective view seen from the lower surface side. 図２に示すコンデンサの側断面図であり、（ａ）が第１内部電極が配置される箇所の側断面図であり、（ｂ）が第２外部電極が配置される箇所の側断面図である。FIG. 3 is a side sectional view of the capacitor shown in FIG. 2, (a) is a side sectional view of a portion where a first internal electrode is disposed, and (b) is a side sectional view of a portion where a second external electrode is disposed. is there. 図２に示すコンデンサの積層体の積層状態を示す分解斜視図である。FIG. 3 is an exploded perspective view showing a laminated state of the multilayer body of the capacitor shown in FIG. 2. 他の構造のコンデンサの斜視図であり、（ａ）が上面側から見た斜視図であり、（ｂ）が下面側から見た斜視図である。It is the perspective view of the capacitor | condenser of another structure, (a) is the perspective view seen from the upper surface side, (b) is the perspective view seen from the lower surface side. 図５に示すコンデンサの側断面図であり、（ａ）が第１内部電極が配置される箇所の側断面図であり、（ｂ）が第２外部電極が配置される箇所の側断面図である。FIG. 6 is a side sectional view of the capacitor shown in FIG. 5, (a) is a side sectional view of a place where the first internal electrode is arranged, and (b) is a side sectional view of a place where the second external electrode is arranged. is there. 図５に示すコンデンサの積層体の積層状態を示す分解斜視図である。It is a disassembled perspective view which shows the lamination | stacking state of the laminated body of the capacitor | condenser shown in FIG. 第２実施形態に係る半導体パッケージが実装された配線基板の構成を示す側断面図である。It is a sectional side view which shows the structure of the wiring board with which the semiconductor package concerning 2nd Embodiment was mounted.
　以下、図面を参照して本発明の好適な実施形態について詳細に説明する。なお、図中、同一又は相当部分には同一符号を用いることとする。また、各図において、同一要素には同一符号を付して重複する説明を省略する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals are used for the same or corresponding parts. Moreover, in each figure, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.
　図１を参照して、第１実施形態に係るＩＣパッケージ１（請求の範囲に記載の半導体パッケージに相当）及びＩＣパッケージ１が実装された配線基板２について説明する。図１は、第１実施形態に係るＩＣパッケージ１が実装された配線基板２の構成を示す側断面図である。 With reference to FIG. 1, an IC package 1 (corresponding to the semiconductor package described in the claims) according to the first embodiment and a wiring board 2 on which the IC package 1 is mounted will be described. FIG. 1 is a side sectional view showing a configuration of a wiring board 2 on which an IC package 1 according to the first embodiment is mounted.
　ＩＣパッケージ１は、配線基板２のマザー基板３に実装されている。マザー基板３の上面３ａには、例えば、銅箔等からなるプリント配線３ｂが形成され、このプリント配線３ｂにＩＣパッケージ１が電気的に接続される。このＩＣパッケージ１とマザー基板３とが接続される箇所は、例えば、アンダーフィル４により封止されている。なお、図１で図示を省略しているが、例えば、マザー基板３にはＩＣパッケージ１以外にも電源回路等が実装されている。 The IC package 1 is mounted on the mother board 3 of the wiring board 2. A printed wiring 3b made of, for example, copper foil or the like is formed on the upper surface 3a of the mother substrate 3, and the IC package 1 is electrically connected to the printed wiring 3b. A portion where the IC package 1 and the mother substrate 3 are connected is sealed with, for example, an underfill 4. Although not shown in FIG. 1, for example, a power supply circuit and the like are mounted on the mother board 3 in addition to the IC package 1.
　ＩＣパッケージ１は、シリコンダイ１０（請求の範囲に記載の半導体集積回路に相当）と、インターポーザ２０（請求の範囲に記載の中継部材に相当）と、シールドケース３０（請求の範囲に記載のシールド部材に相当）と、コンデンサ４０と、を備えている。ＩＣパッケージ１は、例えば、ＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）パッケージ化されている。 The IC package 1 includes a silicon die 10 (corresponding to the semiconductor integrated circuit recited in the claims), an interposer 20 (corresponding to the relay member recited in the claims), and a shield case 30 (shielding according to the claims). And a capacitor 40. The IC package 1 is formed into, for example, a BGA (Ball Grid Array) package.
　シリコンダイ１０は、半導体集積回路が形成されたチップである。シリコンダイ１０は、インターポーザ２０に実装される。インターポーザ２０に実装するために、例えば、シリコンダイ１０の下面には格子状に並べられた略半球形のはんだボール（バンプ）が設けられている。シリコンダイ１０は、ＩＣパッケージ１がマザー基板３に実装されることで、インターポーザ２０を介してマザー基板３に電気的に接続される。シリコンダイ１０は、例えば、マザー基板３に実装された電源回路から給電される。 The silicon die 10 is a chip on which a semiconductor integrated circuit is formed. The silicon die 10 is mounted on the interposer 20. In order to be mounted on the interposer 20, for example, the lower surface of the silicon die 10 is provided with substantially hemispherical solder balls (bumps) arranged in a lattice pattern. The silicon die 10 is electrically connected to the mother substrate 3 through the interposer 20 by mounting the IC package 1 on the mother substrate 3. The silicon die 10 is supplied with power from, for example, a power supply circuit mounted on the mother substrate 3.
　シリコンダイ１０の上面（頂面）１０ａには、コンデンサ４０が実装される。コンデンサ４０を実装するために、シリコンダイ１０の上面１０ａには、実装されるコンデンサ４０毎に、２個の電源端子（電源パッド）１１，１２と１個のグランド端子（グランドパッド）１３が設けられている。電源端子１１，１２は、シリコンダイ１０内の電源ラインに接続されている。グランド端子１３は、シリコンダイ１０内のグランドラインに接続されている。 A capacitor 40 is mounted on the upper surface (top surface) 10 a of the silicon die 10. In order to mount the capacitor 40, two power terminals (power pads) 11 and 12 and one ground terminal (ground pad) 13 are provided on the upper surface 10 a of the silicon die 10 for each mounted capacitor 40. It has been. The power terminals 11 and 12 are connected to a power line in the silicon die 10. The ground terminal 13 is connected to a ground line in the silicon die 10.
　電源端子１１，１２は、後述するコンデンサ４０の第１、第２外部電極と接合可能な大きさを有しており、例えば、矩形状である。電源端子１１，１２は、例えば、銅で形成される。電源端子１１と電源端子１２とは、コンデンサ４０の第１外部電極と第２外部電極との配置に対応して所定の間隔をあけて配置されている。電源端子１１には、コンデンサ４０の第１外部電極が電気的に接続される。電源端子１２には、コンデンサ４０の第２外部電極が電気的に接続される。 The power supply terminals 11 and 12 have a size that can be joined to first and second external electrodes of a capacitor 40 to be described later, and are, for example, rectangular. The power supply terminals 11 and 12 are made of, for example, copper. The power supply terminal 11 and the power supply terminal 12 are arranged at a predetermined interval corresponding to the arrangement of the first external electrode and the second external electrode of the capacitor 40. A first external electrode of the capacitor 40 is electrically connected to the power supply terminal 11. A second external electrode of the capacitor 40 is electrically connected to the power supply terminal 12.
　グランド端子１３は、後述するコンデンサ４０の第３外部電極と接合可能な大きさを有しており、例えば、矩形状である。グランド端子１３は、例えば、銅で形成される。グランド端子１３は、電源端子１１と電源端子１２との間に配置されている。グランド端子１３には、コンデンサ４０の第３外部電極が電気的に接続される。 The ground terminal 13 has a size that can be joined to a third external electrode of the capacitor 40 described later, and is, for example, rectangular. The ground terminal 13 is made of copper, for example. The ground terminal 13 is disposed between the power supply terminal 11 and the power supply terminal 12. A third external electrode of the capacitor 40 is electrically connected to the ground terminal 13.
　インターポーザ２０は、シリコンダイ１０を支持しつつ、シリコンダイ１０とマザー基板３との間を中継する基板である。インターポーザ２０は、シリコンダイ１０とマザー基板３との間の端子間隔等を変換し、ＩＣパッケージ１がマザー基板３に実装されることでシリコンダイ１０とマザー基板３とを電気的に接続する。 The interposer 20 is a substrate that supports the silicon die 10 and relays between the silicon die 10 and the mother substrate 3. The interposer 20 converts a terminal interval between the silicon die 10 and the mother substrate 3 and electrically connects the silicon die 10 and the mother substrate 3 by mounting the IC package 1 on the mother substrate 3.
　インターポーザ２０の上面（頂面）２０ａには、シリコンダイ１０が実装される。シリコンダイ１０を実装するために、例えば、インターポーザ２０の上面２０ａには銅箔等からなるプリント配線が形成されており、このプリント配線にシリコンダイ１０が電気的に接続される。 The silicon die 10 is mounted on the upper surface (top surface) 20 a of the interposer 20. In order to mount the silicon die 10, for example, a printed wiring made of copper foil or the like is formed on the upper surface 20a of the interposer 20, and the silicon die 10 is electrically connected to the printed wiring.
　また、インターポーザ２０の上面２０ａには、シールドケース３０が接合される。インターポーザ２０の上面２０ａには、グランド２１が設けられており、このグランド２１にシールドケース３０が電気的に接続される。グランド２１は、シールドケース３０が接合される箇所に配置される。グランド２１は、シールドケース３０が接合される箇所全体に設けられるもの（矩形の環状のグランド）でもよいし、あるいは、シールドケース３０が接合される箇所の一部分に設けられるものでもよい。 Also, a shield case 30 is joined to the upper surface 20a of the interposer 20. A ground 21 is provided on the upper surface 20 a of the interposer 20, and a shield case 30 is electrically connected to the ground 21. The ground 21 is disposed at a location where the shield case 30 is joined. The ground 21 may be provided at the entire location where the shield case 30 is joined (rectangular annular ground), or may be provided at a portion of the location where the shield case 30 is joined.
　インターポーザ２０の下面（底面）２０ｂには、格子状に並べられた略半球形のはんだボール２２が設けられている。このように、インターポーザ２０は、ＢＧＡタイプの基板である。このインターポーザ２０のはんだボール２２は、マザー基板３のプリント配線３ｂに電気的に接続される。 On the lower surface (bottom surface) 20b of the interposer 20, substantially hemispherical solder balls 22 arranged in a grid are provided. Thus, the interposer 20 is a BGA type substrate. The solder balls 22 of the interposer 20 are electrically connected to the printed wiring 3b of the mother board 3.
　シールドケース３０は、シールド対象のシリコンダイ１０を覆うケースである。シールドケース３０は、シリコンダイ１０が実装されるインターポーザ２０の上面２０ａに接合され、インターポーザ２０に接合された状態でシリコンダイ１０を覆う。シールドケース３０は、金属材料（導電材料）で形成され、例えば、金属板が箱状に折り曲げ加工等されて形成される。なお、シールドケース３０は、例えば、箱状に成型された樹脂板の内面全体に金属材料が塗布されたものでもよい。 The shield case 30 is a case that covers the silicon die 10 to be shielded. The shield case 30 is bonded to the upper surface 20a of the interposer 20 on which the silicon die 10 is mounted, and covers the silicon die 10 while being bonded to the interposer 20. The shield case 30 is formed of a metal material (conductive material), and is formed, for example, by bending a metal plate into a box shape. The shield case 30 may be, for example, a metal material applied to the entire inner surface of a resin plate molded in a box shape.
　シールドケース３０は、インターポーザ２０の上面２０ａに設けられたグランド２１に電気的に接続される。シールドケース３０の内面３０ａには、後述するコンデンサ４０の第４外部電極が電気的に接続される。 The shield case 30 is electrically connected to a ground 21 provided on the upper surface 20a of the interposer 20. A fourth external electrode of a capacitor 40 described later is electrically connected to the inner surface 30a of the shield case 30.
　コンデンサ４０は、シリコンダイ１０の電源－グランド間に設けられるバイパスコンデンサである。コンデンサ４０は、直流電源の電圧変動を抑制する機能やノイズ（例えば、電源－グランド間に入るノイズ、シリコンダイ１０の動作により発生するノイズ）を除去する機能等を有している。 The capacitor 40 is a bypass capacitor provided between the power source of the silicon die 10 and the ground. The capacitor 40 has a function of suppressing voltage fluctuation of the DC power supply, a function of removing noise (for example, noise entering between the power supply and the ground, noise generated by the operation of the silicon die 10), and the like.
　コンデンサ４０は、シリコンダイ１０の上面１０ａとシールドケース３０の内面３０ａとの間に実装される。コンデンサ４０は、チップ型の積層コンデンサであり、略直方体形である。また、コンデンサ４０は、３端子コンデンサである。なお、図１ではコンデンサ４０を２個示しているが、実際にはシリコンダイ１０のバイパスコンデンサとして必要な所定個のコンデンサが実装される。この所定個のバイパスコンデンサの一部は、インターポーザ２０の上面２０ａに実装されてもよい。 The capacitor 40 is mounted between the upper surface 10a of the silicon die 10 and the inner surface 30a of the shield case 30. The capacitor 40 is a chip-type multilayer capacitor and has a substantially rectangular parallelepiped shape. The capacitor 40 is a three-terminal capacitor. Although two capacitors 40 are shown in FIG. 1, a predetermined number of capacitors necessary as bypass capacitors for the silicon die 10 are actually mounted. A part of the predetermined number of bypass capacitors may be mounted on the upper surface 20 a of the interposer 20.
　このコンデンサ４０の構造を、図２～図４を参照して説明する。図２は、コンデンサ４０の斜視図であり、（ａ）が上面側から見た斜視図であり、（ｂ）が下面側から見た斜視図である。図３は、コンデンサ４０の側断面図であり、（ａ）が第１内部電極が配置される箇所の側断面図であり、（ｂ）が第２外部電極が配置される箇所の側断面図である。図４は、コンデンサ４０の積層体の積層状態を示す分解斜視図である。 The structure of the capacitor 40 will be described with reference to FIGS. 2A and 2B are perspective views of the capacitor 40, where FIG. 2A is a perspective view seen from the upper surface side, and FIG. 2B is a perspective view seen from the lower surface side. 3A and 3B are side sectional views of the capacitor 40, where FIG. 3A is a side sectional view of a portion where the first internal electrode is disposed, and FIG. 3B is a side sectional view of a portion where the second external electrode is disposed. It is. FIG. 4 is an exploded perspective view showing a laminated state of the laminated body of the capacitors 40.
　コンデンサ４０は、積層体４１と、第１外部電極４２と、第２外部電極４３と、第３外部電極４４と、第４外部電極４５と、を備えている。コンデンサ４０は、電源用端子となる第１外部電極４２及び第２外部電極４３と、グランド用端子となる第３外部電極４４及び第４外部電極４５とからなる３端子コンデンサである。第１～第３外部電極４２，４３，４４は、積層体４１の下面（底面）４１ｂに設けられている。第４外部電極４５は、積層体４１の上面（頂面）４１ａに設けられている。 The capacitor 40 includes a multilayer body 41, a first external electrode 42, a second external electrode 43, a third external electrode 44, and a fourth external electrode 45. The capacitor 40 is a three-terminal capacitor including a first external electrode 42 and a second external electrode 43 serving as power supply terminals, and a third external electrode 44 and a fourth external electrode 45 serving as ground terminals. The first to third external electrodes 42, 43, 44 are provided on the lower surface (bottom surface) 41 b of the multilayer body 41. The fourth external electrode 45 is provided on the upper surface (top surface) 41 a of the multilayer body 41.
　積層体４１は、複数の誘電体層４６と複数の第１内部電極４７及び第２内部電極４８とを有している。積層体４１は、直方体形状である。積層体４１は、横方向（水平方向）に沿って誘電体層４６を挟んで第１内部電極４７と第２内部電極４８とが交互に積層されており、縦積層である。したがって、積層体４１の積層方向Ｄは、コンデンサ４０が実装されるシリコンダイ１０の上面１０ａに対して略平行となる。したがって、積層体４１で積層されている誘電体層４６、第１内部電極４７、第２内部電極４８は、シリコンダイ１０の上面１０ａに対して略垂直となる。 The laminated body 41 has a plurality of dielectric layers 46 and a plurality of first internal electrodes 47 and second internal electrodes 48. The laminated body 41 has a rectangular parallelepiped shape. The stacked body 41 is a vertically stacked structure in which the first internal electrodes 47 and the second internal electrodes 48 are alternately stacked with the dielectric layer 46 sandwiched along the horizontal direction (horizontal direction). Therefore, the stacking direction D of the stacked body 41 is substantially parallel to the upper surface 10a of the silicon die 10 on which the capacitor 40 is mounted. Therefore, the dielectric layer 46, the first internal electrode 47, and the second internal electrode 48 stacked by the stacked body 41 are substantially perpendicular to the upper surface 10 a of the silicon die 10.
　誘電体層４６は、長方形状の膜状に形成されている。誘電体層４６は、例えば、ＢａＴｉＯ３、ＣａＴｉＯ３、ＳｒＴｉＯ３、ＣａＺｒＯ３等を主成分とする誘電体セラミックからなる。なお、これらの主成分には、Ｍｎ化合物、Ｆｅ化合物、Ｃｒ化合物、Ｃｏ化合物、Ｎｉ化合物等の副成分が添加されていてもよい。 The dielectric layer 46 is formed in a rectangular film shape. The dielectric layer 46 is made of, for example, a dielectric ceramic mainly composed of BaTiO 3 , CaTiO 3 , SrTiO 3 , CaZrO 3 or the like. Note that subcomponents such as a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound may be added to these main components.
　第１、第２内部電極４７，４８は、薄膜状に形成されている。第１、第２内部電極４７，４８は、例えば、Ｎｉ、Ｃｕ、Ａｇ、Ｐｄ、Ａｇ－Ｐｄ合金、Ａｕ等からなる。第１内部電極４７と第２内部電極４８とは、誘電体層４６を介して互いに対向するように、交互に積層されている。 The first and second internal electrodes 47 and 48 are formed in a thin film shape. The first and second internal electrodes 47 and 48 are made of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like. The first internal electrodes 47 and the second internal electrodes 48 are alternately stacked so as to face each other with the dielectric layer 46 interposed therebetween.
　第１内部電極４７は、図３（ａ）に示すように、本体部４７ａと、引き出し部４７ｂと、引き出し部４７ｃとからなる。本体部４７ａは、誘電体層４６の周縁部よりも内側に配置され、誘電体層４６よりも小さい長方形状である。引き出し部４７ｂは、本体部４７ａの下端部における一方側の端部に設けられ、誘電体層４６の下端部（積層体４１の下面４１ｂ）まで引き出されている。引き出し部４７ｃは、本体部４７ａの下端部における他方側の端部に設けられ、誘電体層４６の下端部まで引き出されている。 As shown in FIG. 3A, the first internal electrode 47 includes a main body portion 47a, a lead portion 47b, and a lead portion 47c. The main body 47 a is disposed inside the peripheral edge of the dielectric layer 46 and has a rectangular shape smaller than the dielectric layer 46. The lead portion 47b is provided at one end portion of the lower end portion of the main body portion 47a, and is led out to the lower end portion of the dielectric layer 46 (the lower surface 41b of the multilayer body 41). The lead portion 47 c is provided at the other end portion of the lower end portion of the main body portion 47 a and is led out to the lower end portion of the dielectric layer 46.
　第２内部電極４８は、図３（ｂ）に示すように、本体部４８ａと、引き出し部４８ｂと、引き出し部４８ｃとからなる。本体部４８ａは、誘電体層４６を介して第１内部電極４７の本体部４７ａと対向し、本体部４７ａと同様の長方形状である。引き出し部４８ｂは、本体部４８ａの下端部における中間部（第１内部電極４７の引き出し部４７ｂと引き出し部４７ｃとの間に所定の間隔をあけて）設けられ、誘電体層４６の下端部（積層体４１の下面４１ｂ）まで引き出されている。引き出し部４８ｃは、本体部４８ａの上端部における中間部に設けられ、誘電体層４６の上端部（積層体４１の上面４１ａ）まで引き出されている。引き出し部４８ｂと引き出し部４８ｃとは、本体部４８ａを挟んで対向する。 As shown in FIG. 3B, the second internal electrode 48 includes a main body portion 48a, a lead portion 48b, and a lead portion 48c. The main body 48a faces the main body 47a of the first internal electrode 47 through the dielectric layer 46, and has the same rectangular shape as the main body 47a. The lead portion 48b is provided at an intermediate portion (with a predetermined gap between the lead portion 47b and the lead portion 47c of the first internal electrode 47) at the lower end portion of the main body portion 48a, and the lower end portion of the dielectric layer 46 ( The bottom surface 41b) of the laminate 41 is drawn out. The lead portion 48c is provided at an intermediate portion at the upper end portion of the main body portion 48a, and is led out to the upper end portion of the dielectric layer 46 (the upper surface 41a of the multilayer body 41). The lead portion 48b and the lead portion 48c face each other with the main body portion 48a interposed therebetween.
　第１～第４外部電極４２～４５は、例えば、Ｃｕ電極と、Ｃｕ電極を覆うように形成されたメッキ層（例えば、ニッケルメッキ層とこのニッケルメッキ層を覆うスズメッキ層）と、を有している。 The first to fourth external electrodes 42 to 45 include, for example, a Cu electrode and a plating layer (for example, a nickel plating layer and a tin plating layer covering the nickel plating layer) formed so as to cover the Cu electrode. ing.
　第１外部電極４２は、積層体４１の下面４１ｂにおける長手方向の一方側に設けられている。第１外部電極４２は、複数の第１内部電極４７の引き出し部４７ｂに電気的に接続される。 The first external electrode 42 is provided on one side in the longitudinal direction on the lower surface 41 b of the multilayer body 41. The first external electrode 42 is electrically connected to the lead portions 47 b of the plurality of first internal electrodes 47.
　第２外部電極４３は、積層体４１の下面４１ｂにおける長手方向の他方側に設けられている。第２外部電極４３は、複数の第１内部電極４７の引き出し部４７ｃに電気的に接続される。 The second external electrode 43 is provided on the other side in the longitudinal direction on the lower surface 41 b of the multilayer body 41. The second external electrode 43 is electrically connected to the lead portions 47 c of the plurality of first internal electrodes 47.
　第３外部電極４４は、積層体４１の下面４１ｂにおける長手方向の中間部に設けられている。第３外部電極４４は、第１外部電極４２と第２外部電極４３との間に所定の間隔をあけて配置される。第３外部電極４４は、複数の第２内部電極４８の引き出し部４８ｂに電気的に接続される。 The third external electrode 44 is provided at an intermediate portion in the longitudinal direction on the lower surface 41b of the multilayer body 41. The third external electrode 44 is disposed with a predetermined gap between the first external electrode 42 and the second external electrode 43. The third external electrode 44 is electrically connected to the lead portions 48 b of the plurality of second internal electrodes 48.
　第４外部電極４５は、積層体４１の上面４１ａにおける長手方向の中間部に設けられている。第４外部電極４５と第３外部電極４４とは、積層体４１を挟んで対向する。第４外部電極４５は、複数の第２内部電極４８の引き出し部４８ｃに電気的に接続される。 The fourth external electrode 45 is provided at an intermediate portion in the longitudinal direction on the upper surface 41 a of the multilayer body 41. The fourth external electrode 45 and the third external electrode 44 face each other with the stacked body 41 interposed therebetween. The fourth external electrode 45 is electrically connected to the lead portions 48 c of the plurality of second internal electrodes 48.
　このコンデンサ４０は、第１外部電極４２がシリコンダイ１０の上面１０ａの電源端子１１に電気的に接続され、第２外部電極４３がシリコンダイ１０の上面１０ａの電源端子１２に電気的に接続され、第３外部電極４４がシリコンダイ１０の上面１０ａのグランド端子１３に電気的に接続され、第４外部電極４５がシールドケース３０の内面３０ａに電気的に接続されることで、シリコンダイ１０の上面１０ａとシールドケース３０の内面３０ａとの間に実装される。 In this capacitor 40, the first external electrode 42 is electrically connected to the power supply terminal 11 on the upper surface 10 a of the silicon die 10, and the second external electrode 43 is electrically connected to the power supply terminal 12 on the upper surface 10 a of the silicon die 10. The third external electrode 44 is electrically connected to the ground terminal 13 on the upper surface 10a of the silicon die 10, and the fourth external electrode 45 is electrically connected to the inner surface 30a of the shield case 30. It is mounted between the upper surface 10 a and the inner surface 30 a of the shield case 30.
　シリコンダイ１０の上面１０ａとシールドケース３０の内面３０ａとの間に実装するコンデンサとしては、コンデンサ４０に代えて、例えば、他の構造のコンデンサ５０を適用してもよい。このコンデンサ５０について図５～図７を参照して説明する。図５は、コンデンサ５０の斜視図であり、（ａ）が上面側から見た斜視図であり、（ｂ）が下面側から見た斜視図である。図６は、コンデンサ５０の側断面図であり、（ａ）が第１内部電極が配置される箇所の側断面図であり、（ｂ）が第２外部電極が配置される箇所の側断面図である。図７は、コンデンサ５０の積層体の積層状態を示す分解斜視図である。 As a capacitor mounted between the upper surface 10a of the silicon die 10 and the inner surface 30a of the shield case 30, for example, a capacitor 50 having another structure may be applied instead of the capacitor 40. The capacitor 50 will be described with reference to FIGS. 5A and 5B are perspective views of the capacitor 50, where FIG. 5A is a perspective view seen from the upper surface side, and FIG. 5B is a perspective view seen from the lower surface side. 6A and 6B are side sectional views of the capacitor 50, where FIG. 6A is a side sectional view of a location where the first internal electrode is disposed, and FIG. 6B is a side sectional view of a location where the second external electrode is disposed. It is. FIG. 7 is an exploded perspective view showing a laminated state of the laminated body of the capacitors 50.
　コンデンサ５０は、積層体５１と、第１外部電極５２と、第２外部電極５３と、第３外部電極５４と、第４外部電極５５と、を備えている。コンデンサ５０は、電源用端子となる第１外部電極５２及び第２外部電極５３と、グランド用端子となる第３外部電極５４及び第４外部電極５５とからなる３端子コンデンサである。第１～第３外部電極５２，５３，５４は、積層体５１の下面（底面）５１ｂに設けられている。特に、第１外部電極５２は、積層体５１の下面５１ｂだけでなく、積層体５１の側面５１ｃの一部まで設けられている。第２外部電極５３は、積層体５１の下面５１ｂだけでなく、積層体５１の側面５１ｃに対向する側面５１ｄの一部まで設けられている。第４外部電極５５は、積層体５１の上面（頂面）５１ａ全体に設けられている。特に、第４外部電極５５は、積層体５１の上面５１ａだけでなく、積層体５１の対向する側面５１ｃ，５１ｄの一部まで設けられている。 The capacitor 50 includes a multilayer body 51, a first external electrode 52, a second external electrode 53, a third external electrode 54, and a fourth external electrode 55. The capacitor 50 is a three-terminal capacitor including a first external electrode 52 and a second external electrode 53 that are power supply terminals, and a third external electrode 54 and a fourth external electrode 55 that are ground terminals. The first to third external electrodes 52, 53, 54 are provided on the lower surface (bottom surface) 51 b of the multilayer body 51. In particular, the first external electrode 52 is provided not only on the lower surface 51 b of the multilayer body 51 but also on a part of the side surface 51 c of the multilayer body 51. The second external electrode 53 is provided not only on the lower surface 51 b of the multilayer body 51 but also on a part of the side surface 51 d facing the side surface 51 c of the multilayer body 51. The fourth external electrode 55 is provided on the entire upper surface (top surface) 51 a of the multilayer body 51. In particular, the fourth external electrode 55 is provided not only on the upper surface 51 a of the multilayer body 51 but also on part of the side surfaces 51 c and 51 d facing the multilayer body 51.
　積層体５１は、上述したコンデンサ４０の積層体４１と同様に、複数の誘電体層５６と複数の第１内部電極５７及び第２内部電極５８とを有しており、誘電体層５６を挟んで第１内部電極５７と第２内部電極５８とが交互に積層されている。積層体５１は、積層体４１と比較すると、第１内部電極５７と第２内部電極５８の形状が異なる。 Like the multilayer body 41 of the capacitor 40 described above, the multilayer body 51 includes a plurality of dielectric layers 56, a plurality of first internal electrodes 57, and second internal electrodes 58, with the dielectric layer 56 interposed therebetween. Thus, the first internal electrodes 57 and the second internal electrodes 58 are alternately stacked. The laminated body 51 is different from the laminated body 41 in the shapes of the first internal electrode 57 and the second internal electrode 58.
　第１内部電極５７は、図６（ａ）に示すように、本体部５７ａと、引き出し部５７ｂと、引き出し部５７ｃとからなる。本体部５７ａは、上述したコンデンサ４０の第１内部電極４７の本体部４７ａと同様の形状である。引き出し部５７ｂは、本体部５７ａの下端部における一方側の端部に設けられ、誘電体層５６の下端部（積層体５１の下面５１ｂ）及びこの下端部に繋がる一方の側端部（積層体５１の側面５１ｃ）まで引き出されている。引き出し部５７ｃは、本体部５７ａの下端部における他方側の端部に設けられ、誘電体層５６の下端部及びこの下端部に繋がる他方の側端部（積層体５１の側面５１ｄ）まで引き出されている。 As shown in FIG. 6A, the first internal electrode 57 includes a main body portion 57a, a lead portion 57b, and a lead portion 57c. The main body portion 57a has the same shape as the main body portion 47a of the first internal electrode 47 of the capacitor 40 described above. The lead portion 57b is provided at one end portion of the lower end portion of the main body portion 57a. The lower end portion of the dielectric layer 56 (the lower surface 51b of the stacked body 51) and one side end portion (laminated body) connected to the lower end portion. 51 to the side 51c). The lead portion 57c is provided at the other end portion of the lower end portion of the main body portion 57a, and is led out to the lower end portion of the dielectric layer 56 and the other side end portion (side surface 51d of the stacked body 51) connected to the lower end portion. ing.
　第２内部電極５８は、図６（ｂ）に示すように、本体部５８ａと、引き出し部５８ｂと、引き出し部５８ｃとからなる。本体部５８ａは、上述したコンデンサ４０の第２内部電極４８の本体部４８ａと同様の形状である。引き出し部５８ｂは、本体部５８ａの下端部における中間部（第１内部電極５７の引き出し部５７ｂと引き出し部５７ｃとの間に所定の間隔をあけて）設けられ、誘電体層５６の下端部（積層体５１の下面５１ｂ）まで引き出されている。引き出し部５８ｃは、本体部５８ａの上端部全体に設けられ、誘電体層５６の上端部（積層体５１の上面５１ａ）全体及びこの上端部に繋がる両側の側端部（積層体５１の側面５１ｃ，５１ｄ）まで引き出されている。引き出し部５８ｂと引き出し部５８ｃとは、本体部５８ａを挟んで対向する。 As shown in FIG. 6B, the second internal electrode 58 includes a main body portion 58a, a lead portion 58b, and a lead portion 58c. The main body portion 58a has the same shape as the main body portion 48a of the second internal electrode 48 of the capacitor 40 described above. The lead portion 58b is provided at an intermediate portion (with a predetermined interval between the lead portion 57b and the lead portion 57c of the first internal electrode 57) at the lower end portion of the main body portion 58a, and the lower end portion of the dielectric layer 56 ( The bottom surface 51b) of the laminate 51 is drawn out. The lead portion 58c is provided over the entire upper end portion of the main body portion 58a, and the entire upper end portion of the dielectric layer 56 (the upper surface 51a of the stacked body 51) and the side end portions on both sides connected to the upper end portion (the side surfaces 51c of the stacked body 51) , 51d). The drawer portion 58b and the drawer portion 58c face each other with the main body portion 58a interposed therebetween.
　第１～第４外部電極５２～５５は、上述したコンデンサ４０の第１～第４外部電極４２～４５と比較すると、第１外部電極５２、第２外部電極５３及び第４外部電極５５の形状が異なる。 The first to fourth external electrodes 52 to 55 have shapes of the first external electrode 52, the second external electrode 53, and the fourth external electrode 55 as compared with the first to fourth external electrodes 42 to 45 of the capacitor 40 described above. Is different.
　第１外部電極５２は、積層体５１の下面５１ｂにおける長手方向の一方側及びこの一方側の端部に繋がる積層体５１の一方の側面５１ｃの一部に設けられている。したがって、第１外部電極５２は、積層体５１の下面５１ｂの一端側から側面５１ｃの一部まで延在し、断面が略Ｌ字形状である。第１外部電極５２は、複数の第１内部電極５７の引き出し部５７ｂに電気的に接続される。 The first external electrode 52 is provided on one side in the longitudinal direction of the lower surface 51b of the multilayer body 51 and a part of one side surface 51c of the multilayer body 51 connected to the end portion on the one side. Therefore, the first external electrode 52 extends from one end side of the lower surface 51b of the multilayer body 51 to a part of the side surface 51c, and has a substantially L-shaped cross section. The first external electrode 52 is electrically connected to the lead portions 57 b of the plurality of first internal electrodes 57.
　第２外部電極５３は、積層体５１の下面５１ｂにおける長手方向の他方側及びこの他方側の端部に繋がる積層体５１の他方の側面５１ｄの一部に設けられている。したがって、第２外部電極５３は、積層体５１の下面５１ｂの他端側から側面５１ｄの一部まで延在し、断面が略Ｌ字形状である。第２外部電極５３は、複数の第１内部電極５７の引き出し部５７ｃに電気的に接続される。 The second external electrode 53 is provided on the other side in the longitudinal direction of the lower surface 51b of the multilayer body 51 and a part of the other side surface 51d of the multilayer body 51 connected to the end of the other side. Therefore, the second external electrode 53 extends from the other end side of the lower surface 51b of the multilayer body 51 to a part of the side surface 51d, and has a substantially L-shaped cross section. The second external electrode 53 is electrically connected to the lead portions 57 c of the plurality of first internal electrodes 57.
　第４外部電極５５は、積層体５１の上面５１ａの全体及びこの上面５１ａの端部に繋がる積層体５１の両側の側面５１ｃ，５１ｄの一部に設けられている。したがって、第４外部電極５５は、積層体５１の上面５１ａ全体から両側の側面５１ｃ，５１ｄの一部まで延在し、断面が略コ字形状である。第４外部電極５５は、複数の第２内部電極５８の引き出し部５８ｃに電気的に接続される。なお、積層体５１の側面５１ｃには、所定の間隔をあけて第４外部電極５５と第１外部電極５２とが配置されている。また、積層体５１の側面５１ｄには、所定の間隔をあけて第４外部電極５５と第２外部電極５３とが配置されている。 The fourth external electrode 55 is provided on the entire upper surface 51a of the multilayer body 51 and part of the side surfaces 51c and 51d on both sides of the multilayer body 51 connected to the end of the upper surface 51a. Therefore, the fourth external electrode 55 extends from the entire top surface 51a of the multilayer body 51 to a part of the side surfaces 51c and 51d on both sides, and has a substantially U-shaped cross section. The fourth external electrode 55 is electrically connected to the lead portions 58 c of the plurality of second internal electrodes 58. The fourth external electrode 55 and the first external electrode 52 are disposed on the side surface 51c of the multilayer body 51 with a predetermined interval. Further, the fourth external electrode 55 and the second external electrode 53 are arranged on the side surface 51d of the multilayer body 51 with a predetermined interval.
　このコンデンサ５０は、第１外部電極５２がシリコンダイ１０の上面１０ａの電源端子１１に電気的に接続され、第２外部電極５３がシリコンダイ１０の上面１０ａの電源端子１２に電気的に接続され、第３外部電極５４がシリコンダイ１０の上面１０ａのグランド端子１３に電気的に接続され、第４外部電極５５がシールドケース３０の内面３０ａに電気的に接続されることで、シリコンダイ１０の上面１０ａとシールドケース３０の内面３０ａとの間に実装される。 In the capacitor 50, the first external electrode 52 is electrically connected to the power supply terminal 11 on the upper surface 10 a of the silicon die 10, and the second external electrode 53 is electrically connected to the power supply terminal 12 on the upper surface 10 a of the silicon die 10. The third external electrode 54 is electrically connected to the ground terminal 13 on the upper surface 10a of the silicon die 10, and the fourth external electrode 55 is electrically connected to the inner surface 30a of the shield case 30. It is mounted between the upper surface 10 a and the inner surface 30 a of the shield case 30.
　ＩＣパッケージ１（配線基板２）の作用について説明する。ＩＣパッケージ１では、３端子のコンデンサ４０（バイパスコンデンサ）がシリコンダイ１０の上面１０ａとシールドケース３０の内面３０ａ間に実装され、このコンデンサ４０の第２内部電極４８に接続された第３、第４外部電極４４，４５が上面１０ａのグランド端子１３とシールドケース３０の内面３０ａに接続されている。このコンデンサ４０は、積層方向Ｄがシリコンダイ１０の上面１０ａと略平行であるので、上面１０ａと内面３０ａとの間に第２内部電極４８が上下方向に沿って配置されている。この上下方向に延在する第２内部電極４８と第２内部電極４８の上下に接続された第３、第４外部電極４４，４５により、上面１０ａと内面３０ａとの間にパスが形成される。 The operation of the IC package 1 (wiring board 2) will be described. In the IC package 1, a three-terminal capacitor 40 (bypass capacitor) is mounted between the upper surface 10 a of the silicon die 10 and the inner surface 30 a of the shield case 30, and is connected to the second internal electrode 48 of the capacitor 40. Four external electrodes 44 and 45 are connected to the ground terminal 13 on the upper surface 10 a and the inner surface 30 a of the shield case 30. Since the stacking direction D of the capacitor 40 is substantially parallel to the upper surface 10a of the silicon die 10, the second internal electrode 48 is disposed along the vertical direction between the upper surface 10a and the inner surface 30a. A path is formed between the upper surface 10a and the inner surface 30a by the second internal electrode 48 extending in the vertical direction and the third and fourth external electrodes 44 and 45 connected above and below the second internal electrode 48. .
　シリコンダイ１０で発熱すると、その熱が、上面１０ａのグランド端子１３からコンデンサ４０の第３外部電極４４、第２内部電極４８、第４外部電極４５のパスを通ってシールドケース３０に伝導され、シールドケース３０の外部に放出される。金属製の電極４４，４５，４８は、樹脂（例えば、従来のＩＣパッケージにおいてシリコンダイとシールドケースとの間に設けられるグリス）などに比べて熱伝導率が高いので、熱を効率良く伝導することができる。特に、ＩＣパッケージ１では、シリコンダイ１０の上面１０ａにコンデンサ４０が直接配置されている。また、ＩＣパッケージ１では、コンデンサ４０の第２内部電極４８がシリコンダイ１０の上面１０ａに対して略垂直に配置されているので、シリコンダイ１０とシールドケース３０との間に形成されるコンデンサ４０を利用した熱のパスの長さが短い。したがって、ＩＣパッケージ１では、シリコンダイ１０で発生した熱をコンデンサ４０を介して効率良く放熱することができる。 When the silicon die 10 generates heat, the heat is conducted from the ground terminal 13 on the upper surface 10a through the third external electrode 44, the second internal electrode 48, and the fourth external electrode 45 of the capacitor 40 to the shield case 30, It is discharged to the outside of the shield case 30. Since the metal electrodes 44, 45, and 48 have higher thermal conductivity than resin (for example, grease provided between a silicon die and a shield case in a conventional IC package), heat is efficiently conducted. be able to. In particular, in the IC package 1, the capacitor 40 is directly disposed on the upper surface 10 a of the silicon die 10. In the IC package 1, the second internal electrode 48 of the capacitor 40 is disposed substantially perpendicular to the upper surface 10 a of the silicon die 10, so that the capacitor 40 formed between the silicon die 10 and the shield case 30. The length of the heat path using is short. Therefore, in the IC package 1, the heat generated in the silicon die 10 can be efficiently radiated through the capacitor 40.
　また、ＩＣパッケージ１では、コンデンサ４０のグランドへの接続箇所としてシリコンダイ１０のグランド端子１３とグランド２１に接続されるシールドケース３０があるので、コンデンサ４０（バイパスコンデンサ）の電源―グランド間のパスが増え、ＩＣパッケージ１のインダクタンスを低減することができる。また、ＩＣパッケージ１では、コンデンサ４０が３端子コンデンサとして構成されているので、コンデンサ４０のインダクタンスを低減することができる。また、ＩＣパッケージ１では、コンデンサ４０がシリコンダイ１０に直接配置されているので、コンデンサ４０とシリコンダイ１０との間の配線のインダクタンスを低減することができる。 Further, in the IC package 1, since there is a shield case 30 connected to the ground terminal 13 of the silicon die 10 and the ground 21 as a connection point of the capacitor 40 to the ground, a path between the power source of the capacitor 40 (bypass capacitor) and the ground. And the inductance of the IC package 1 can be reduced. Further, in the IC package 1, since the capacitor 40 is configured as a three-terminal capacitor, the inductance of the capacitor 40 can be reduced. Further, in the IC package 1, since the capacitor 40 is directly arranged on the silicon die 10, the inductance of the wiring between the capacitor 40 and the silicon die 10 can be reduced.
　第１実施形態に係るＩＣパッケージ１及び配線基板２によれば、上述したようにコンデンサ４０がシリコンダイ１０の上面１０ａとシールドケース３０の内面３０ａとの間に実装されているので、この上面１０ａと内面３０ａとの間にコンデンサ４０を利用した熱のパスができ、放熱性を向上させることができる。また、第１実施形態に係るＩＣパッケージ１及び配線基板２によれば、上述したようにインダクタンスが低減するので、シリコンダイ１０の容量とコンデンサ４０のインダクタンスとの間の反共振をコンデンサ４０によって抑制することができ、電源インピーダンスを低減することができる。 According to the IC package 1 and the wiring board 2 according to the first embodiment, the capacitor 40 is mounted between the upper surface 10a of the silicon die 10 and the inner surface 30a of the shield case 30 as described above. A heat path using the capacitor 40 is formed between the inner surface 30a and the inner surface 30a, and heat dissipation can be improved. Further, according to the IC package 1 and the wiring board 2 according to the first embodiment, since the inductance is reduced as described above, the anti-resonance between the capacitance of the silicon die 10 and the inductance of the capacitor 40 is suppressed by the capacitor 40. The power supply impedance can be reduced.
　コンデンサ４０の構造の場合、コンデンサ５０の構造と比べて、外部電極（第４外部電極４４など）を塗工し易いので、製造し易く、生産性を向上させることができる。また、コンデンサ５０の構造の場合、第４外部電極５５が積層体５１の上面５１ａから側面５１ｃ，５１ｄの一部まで設けられ、第１、第２外部電極５２，５３が積層体５１の下面５１ｂから側面５１ｃ，５１ｄの一部まで設けられているので、グランド用端子となる第４外部電極５５と電源用端子となる第１、第２外部電極５２，５３との物理的距離が近くなるので、インダクタンス（ＥＳＬ）を更に低減することができる。また、第４外部電極５５の面積を大きくすることで、シールドケース３０への接地面積が大きくなるので、放熱性を更に向上させることができる。 In the case of the structure of the capacitor 40, compared to the structure of the capacitor 50, it is easy to apply the external electrode (the fourth external electrode 44, etc.), so that it is easy to manufacture and the productivity can be improved. In the structure of the capacitor 50, the fourth external electrode 55 is provided from the upper surface 51 a of the multilayer body 51 to a part of the side surfaces 51 c and 51 d, and the first and second external electrodes 52 and 53 are the lower surface 51 b of the multilayer body 51. To part of the side surfaces 51c and 51d, the physical distance between the fourth external electrode 55 serving as the ground terminal and the first and second external electrodes 52 and 53 serving as the power supply terminal is reduced. Inductance (ESL) can be further reduced. Further, by increasing the area of the fourth external electrode 55, the ground contact area to the shield case 30 is increased, so that the heat dissipation can be further improved.
　次に、図８を参照して、第２実施形態に係るＩＣパッケージ５（請求の範囲に記載の半導体パッケージに相当）及びＩＣパッケージ５が実装された配線基板６について説明する。図８は、第２実施形態に係るＩＣパッケージ５が実装された配線基板６の構成を示す側断面図である。 Next, the IC package 5 (corresponding to the semiconductor package described in claims) and the wiring board 6 on which the IC package 5 is mounted will be described with reference to FIG. FIG. 8 is a side sectional view showing a configuration of the wiring board 6 on which the IC package 5 according to the second embodiment is mounted.
　ＩＣパッケージ５は、第１実施形態に係るＩＣパッケージ１と比較すると、コンデンサをインターポーザとシールドケース間に実装する点が異なる。配線基板６は、第１実施形態に係る配線基板２と比較すると、第１実施形態に係るＩＣパッケージ１に代えてＩＣパッケージ５が実装される点が異なる。そこで、以下の説明では、ＩＣパッケージ５についてのみ説明する。 The IC package 5 differs from the IC package 1 according to the first embodiment in that a capacitor is mounted between the interposer and the shield case. The wiring board 6 is different from the wiring board 2 according to the first embodiment in that an IC package 5 is mounted instead of the IC package 1 according to the first embodiment. Therefore, in the following description, only the IC package 5 will be described.
　ＩＣパッケージ５は、シリコンダイ７０（請求の範囲に記載の半導体集積回路に相当）と、インターポーザ８０（請求の範囲に記載の中継部材に相当）と、シールドケース９０（請求の範囲に記載のシールド部材に相当）と、コンデンサ１００と、を備えている。 The IC package 5 includes a silicon die 70 (corresponding to the semiconductor integrated circuit recited in the claims), an interposer 80 (corresponding to the relay member recited in the claims), and a shield case 90 (shielding according to the claims). And a capacitor 100.
　シリコンダイ７０は、第１実施形態に係るＩＣパッケージ１のシリコンダイ１０と比較すると、上面７０ａにバイパスコンデンサが実装されない点が異なる。したがって、シリコンダイ７０の上面７０ａには、電極端子及びグランド端子が設けられていない。なお、放熱性を向上させるために、シリコンダイ７０の上面７０ａとシールドケース９０の内面９０ａとの間にグリスなどを設けてもよい。 The silicon die 70 is different from the silicon die 10 of the IC package 1 according to the first embodiment in that a bypass capacitor is not mounted on the upper surface 70a. Therefore, the electrode terminal and the ground terminal are not provided on the upper surface 70 a of the silicon die 70. In order to improve heat dissipation, grease or the like may be provided between the upper surface 70a of the silicon die 70 and the inner surface 90a of the shield case 90.
　インターポーザ８０は、第１実施形態に係るＩＣパッケージ１のインターポーザ２０と比較すると、上面（頂面）８０ａにコンデンサ１００が実装される点が異なる。コンデンサ１００を実装するために、インターポーザ８０の上面８０ａには、実装されるコンデンサ１００毎に、２個の電源端子（電源パッド）８２，８３と１個のグランド端子（グランドパッド）８４が設けられている。電源端子８２，８３、グランド端子８４の配置や形状は、第１実施形態に係るＩＣパッケージ１のシリコンダイ１０に設けられる電源端子１１，１２、グランド端子１３と同様である。電源端子８２，８３は、インターポーザ８０内の電源ラインに接続されている。グランド端子８４は、インターポーザ８０内のグランドラインに接続されている。電源端子８２には、コンデンサ１００の第１外部電極が電気的に接続される。電源端子８３には、コンデンサ１００の第２外部電極が電気的に接続される。グランド端子８４には、コンデンサ１００の第３外部電極が電気的に接続される。 The interposer 80 is different from the interposer 20 of the IC package 1 according to the first embodiment in that the capacitor 100 is mounted on the upper surface (top surface) 80a. In order to mount the capacitor 100, two power terminals (power pads) 82 and 83 and one ground terminal (ground pad) 84 are provided on the upper surface 80 a of the interposer 80 for each mounted capacitor 100. ing. The arrangement and shape of the power terminals 82 and 83 and the ground terminal 84 are the same as those of the power terminals 11 and 12 and the ground terminal 13 provided on the silicon die 10 of the IC package 1 according to the first embodiment. The power terminals 82 and 83 are connected to a power line in the interposer 80. The ground terminal 84 is connected to a ground line in the interposer 80. A first external electrode of the capacitor 100 is electrically connected to the power supply terminal 82. A second external electrode of the capacitor 100 is electrically connected to the power supply terminal 83. A third external electrode of the capacitor 100 is electrically connected to the ground terminal 84.
　シールドケース９０は、第１実施形態に係るＩＣパッケージ１のシールドケース３０と同様のシールドケースである。シールドケース９０は、インターポーザ８０の上面８０ａに設けられたグランド８１に電気的に接続されている。特に、シールドケース９０の内面９０ａには、インターポーザ８０の上面８０ａとの間に実装されるコンデンサ１００の第４外部電極が電気的に接続される。 The shield case 90 is a shield case similar to the shield case 30 of the IC package 1 according to the first embodiment. The shield case 90 is electrically connected to a ground 81 provided on the upper surface 80a of the interposer 80. In particular, the fourth external electrode of the capacitor 100 mounted between the inner surface 90a of the shield case 90 and the upper surface 80a of the interposer 80 is electrically connected.
　コンデンサ１００は、シリコンダイ７０の電源－グランド間に設けられるバイパスコンデンサである。特に、コンデンサ１００は、第１実施形態に係るコンデンサ４０と比較すると、インターポーザ８０の上面８０ａとシールドケース９０の内面９０ａとの間に実装される点が異なる。 The capacitor 100 is a bypass capacitor provided between the power source of the silicon die 70 and the ground. In particular, the capacitor 100 differs from the capacitor 40 according to the first embodiment in that it is mounted between the upper surface 80a of the interposer 80 and the inner surface 90a of the shield case 90.
　コンデンサ１００としては、例えば、第１実施形態で説明したコンデンサ４０やコンデンサ５０と同様の構造のものが適用される。但し、コンデンサ１００は、インターポーザ８０の上面８０ａとシールドケース９０の内面９０ａとの間に実装されるので、第１実施形態に係るコンデンサ４０，５０と比較して、サイズが異なる（少なくとも上下方向のサイズが大きくなる）。 As the capacitor 100, for example, a capacitor having the same structure as the capacitor 40 and the capacitor 50 described in the first embodiment is applied. However, since the capacitor 100 is mounted between the upper surface 80a of the interposer 80 and the inner surface 90a of the shield case 90, the size is different from that of the capacitors 40 and 50 according to the first embodiment (at least in the vertical direction). Increase in size).
　コンデンサ１００は、シリコンダイ７０の周りに配置される。特に、コンデンサ１００は、シリコンダイ７０との間の配線のインダクタンスを低減するために、シリコンダイ７０の近くに配置されることが望ましい。 The capacitor 100 is disposed around the silicon die 70. In particular, the capacitor 100 is preferably disposed near the silicon die 70 in order to reduce the inductance of the wiring between the silicon die 70 and the capacitor 100.
　例えば、コンデンサ１００がコンデンサ４０の構造の場合、第１外部電極４２がインターポーザ８０の上面８０ａの電源端子８２に電気的に接続され、第２外部電極４３がインターポーザ８０の上面８０ａの電源端子８３に電気的に接続され、第３外部電極４４がインターポーザ８０の上面８０ａのグランド端子８４に電気的に接続され、第４外部電極４５がシールドケース９０の内面９０ａに電気的に接続されることで、コンデンサ１００がインターポーザ８０の上面８０ａとシールドケース９０の内面９０ａとの間に実装される。 For example, when the capacitor 100 has the structure of the capacitor 40, the first external electrode 42 is electrically connected to the power supply terminal 82 on the upper surface 80 a of the interposer 80, and the second external electrode 43 is connected to the power supply terminal 83 on the upper surface 80 a of the interposer 80. By being electrically connected, the third external electrode 44 is electrically connected to the ground terminal 84 on the upper surface 80a of the interposer 80, and the fourth external electrode 45 is electrically connected to the inner surface 90a of the shield case 90, Capacitor 100 is mounted between upper surface 80 a of interposer 80 and inner surface 90 a of shield case 90.
　ＩＣパッケージ５（配線基板６）の作用について説明する。以下の説明では、コンデンサ１００としてコンデンサ４０の構造のものが用いられている場合で説明する。 The operation of the IC package 5 (wiring board 6) will be described. In the following description, the case where the capacitor 100 having the structure of the capacitor 40 is used will be described.
　ＩＣパッケージ５では、３端子のコンデンサ１００（バイパスコンデンサ）がインターポーザ８０の上面８０ａとシールドケース９０の内面９０ａ間に実装され、このコンデンサ１００の第２内部電極４８に接続された第３、第４外部電極４４，４５が上面８０ａのグランド端子８４とシールドケース９０の内面９０ａに接続されている。このコンデンサ１００は、積層方向Ｄがインターポーザ８０の上面８０ａと略平行であるので、上面８０ａと内面９０ａとの間に第２内部電極４８が上下方向に沿って配置されている。この上下方向に延在する第２内部電極４８と第２内部電極４８の上下に接続された第３、第４外部電極４４，４５により、上面８０ａと内面９０ａとの間にパスが形成される。 In the IC package 5, a three-terminal capacitor 100 (bypass capacitor) is mounted between the upper surface 80 a of the interposer 80 and the inner surface 90 a of the shield case 90, and is connected to the second internal electrode 48 of the capacitor 100. The external electrodes 44 and 45 are connected to the ground terminal 84 on the upper surface 80 a and the inner surface 90 a of the shield case 90. Since the stacking direction D of the capacitor 100 is substantially parallel to the upper surface 80a of the interposer 80, the second internal electrode 48 is disposed along the vertical direction between the upper surface 80a and the inner surface 90a. A path is formed between the upper surface 80a and the inner surface 90a by the second internal electrode 48 extending in the vertical direction and the third and fourth external electrodes 44, 45 connected above and below the second internal electrode 48. .
　シリコンダイ７０で発生した熱が、下方のインターポーザ８０に伝導されると、インターポーザ８０の上面８０ａのグランド端子８４からコンデンサ１００の第３外部電極４４、第２内部電極４８、第４外部電極４５のパスを通ってシールドケース９０に伝導され、シールドケース９０の外部に放出される。特に、ＩＣパッケージ５では、第２内部電極４８がインターポーザ８０の上面８０ａに対して略垂直に配置されているので、インターポーザ８０とシールドケース９０との間に形成されるコンデンサ１００を利用した熱のパスの長さが短い。したがって、ＩＣパッケージ５では、シリコンダイ７０で発生した熱をコンデンサ１００を介して効率良く放熱することができる。 When the heat generated in the silicon die 70 is conducted to the lower interposer 80, the third external electrode 44, the second internal electrode 48, and the fourth external electrode 45 of the capacitor 100 from the ground terminal 84 on the upper surface 80 a of the interposer 80. It is conducted to the shield case 90 through the path and discharged to the outside of the shield case 90. In particular, in the IC package 5, the second internal electrode 48 is disposed substantially perpendicular to the upper surface 80 a of the interposer 80, so that heat generated by using the capacitor 100 formed between the interposer 80 and the shield case 90 can be obtained. The path length is short. Therefore, in the IC package 5, the heat generated in the silicon die 70 can be efficiently radiated through the capacitor 100.
　また、ＩＣパッケージ５では、第１実施形態に係るＩＣパッケージ１と同様に、コンデンサ１００の電源―グランド間のパスが増えるので、ＩＣパッケージ５のインダクタンスを低減することができる。また、ＩＣパッケージ５では、コンデンサ１００が３端子コンデンサとして構成されているので、コンデンサ１００のインダクタンス（ＥＳＬ）を低減することができる。 Further, in the IC package 5, since the path between the power source and the ground of the capacitor 100 increases as in the IC package 1 according to the first embodiment, the inductance of the IC package 5 can be reduced. Further, in the IC package 5, since the capacitor 100 is configured as a three-terminal capacitor, the inductance (ESL) of the capacitor 100 can be reduced.
　特に、ＩＣパッケージ５では、シールドケース９０の外部から静電気が入った場合でも、静電気をシールドケース９０からインターポーザ８０のグランド８１に直接逃すパスやシールドケース９０からコンデンサ１００の第４外部電極４５、第２内部電極４８、第３外部電極４４を通ってインターポーザ８０のグランド端子８４に逃すパスがあるので、静電気を効率良くグランドに逃すことができる。 In particular, in the IC package 5, even when static electricity enters from the outside of the shield case 90, a path for directly discharging the static electricity from the shield case 90 to the ground 81 of the interposer 80, the fourth external electrode 45 of the capacitor 100 from the shield case 90, 2 Since there is a path for passing through the internal electrode 48 and the third external electrode 44 to the ground terminal 84 of the interposer 80, static electricity can be efficiently released to the ground.
　第２実施形態に係るＩＣパッケージ５及び配線基板６によれば、上述したようにコンデンサ１００がインターポーザ８０の上面８０ａとシールドケース９０の内面９０ａとの間に実装されているので、この上面８０ａと内面９０ａとの間にコンデンサ１００を利用した熱のパスができ、放熱性を向上させることができる。また、第２実施形態に係るＩＣパッケージ５及び配線基板６によれば、上述したようにインダクタンスが低減するので、シリコンダイ７０の容量とコンデンサ１００のインダクタンスとの間の反共振をコンデンサ１００によって抑制することができ、電源インピーダンスを低減することができる。また、第２実施形態に係るＩＣパッケージ５及び配線基板６によれば、ＥＳＤ耐性に優れ、シリコンダイ７０に対する静電気の影響を抑制することができる。 According to the IC package 5 and the wiring board 6 according to the second embodiment, the capacitor 100 is mounted between the upper surface 80a of the interposer 80 and the inner surface 90a of the shield case 90 as described above. A heat path using the capacitor 100 can be formed between the inner surface 90a and the heat dissipation can be improved. Further, according to the IC package 5 and the wiring board 6 according to the second embodiment, since the inductance is reduced as described above, the anti-resonance between the capacitance of the silicon die 70 and the inductance of the capacitor 100 is suppressed by the capacitor 100. The power supply impedance can be reduced. Further, according to the IC package 5 and the wiring substrate 6 according to the second embodiment, the ESD resistance is excellent, and the influence of static electricity on the silicon die 70 can be suppressed.
　以上、本発明の実施の形態について説明したが、本発明は、上記実施形態に限定されるものではなく種々の変形が可能である。例えば、上記実施形態ではマザー基板３にＩＣパッケージ１，５が実装された配線基板２，６の状態で説明したが、ＩＣパッケージ１，５単体に適用してもよい。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, although the above embodiment has been described in the state of the wiring boards 2 and 6 in which the IC packages 1 and 5 are mounted on the mother board 3, the present invention may be applied to the IC packages 1 and 5 alone.
　上記実施形態ではインターポーザ２０，８０の上面２０ａ，８０ａにグランド２１，８１が設けられ、シールドケース３０，９０がインターポーザ２０，８０の上面２０ａ，８０ａに接合されると共にグランド２１，８１に電気的に接続される構成としたが、シールドケースがインターポーザの側面に接合されると共にインターポーザに設けられたグランドに電気的に接続される構成としてもよい。 In the above embodiment, the grounds 21 and 81 are provided on the upper surfaces 20a and 80a of the interposers 20 and 80, and the shield cases 30 and 90 are joined to the upper surfaces 20a and 80a of the interposers 20 and 80 and electrically connected to the grounds 21 and 81. However, the shield case may be joined to the side surface of the interposer and electrically connected to the ground provided in the interposer.
　上記実施形態ではシリコンダイ１０の上面１０ａと略平行となる積層方向で積層されることで、第１内部電極４７及び第２内部電極４８がシリコンダイ１０の上面１０ａに対して略垂直に配置されるコンデンサ４０等を例示したが、シリコンダイの上面と略垂直となる積層方向で積層されることで、第１内部電極及び第２内部電極がシリコンダイの上面に対して略垂直に配置されるコンデンサを作製することも可能である。 In the above embodiment, the first internal electrode 47 and the second internal electrode 48 are arranged substantially perpendicular to the upper surface 10a of the silicon die 10 by being stacked in a stacking direction that is substantially parallel to the upper surface 10a of the silicon die 10. Although the capacitor 40 and the like are illustrated, the first internal electrode and the second internal electrode are disposed substantially perpendicular to the upper surface of the silicon die by being stacked in a stacking direction that is substantially perpendicular to the upper surface of the silicon die. It is also possible to produce a capacitor.
　上記第１実施形態では中継部材としてインターポーザ２０を適用したが、中継部材として再配線層等を適用してもよい。 In the first embodiment, the interposer 20 is applied as the relay member, but a rewiring layer or the like may be applied as the relay member.
　１，５　ＩＣパッケージ（半導体パッケージ）
　２，６　配線基板
　３　マザー基板
　１０，７０　シリコンダイ（半導体集積回路）
　１１，１２　電源端子
　１３　グランド端子
　２０，８０　インターポーザ（中継部材）
　２１，８１　グランド
　８２，８３　電源端子
　８４　グランド端子
　３０，９０　シールドケース（シールド部材）
　４０，５０，１００　コンデンサ
　４１，５１　積層体
　４２，５２　第１外部電極
　４３，５３　第２外部電極
　４４，５４　第３外部電極
　４５，５５　第４外部電極
　４６，５６　誘電体層
　４７，５７　第１内部電極
　４８，５８　第２内部電極 1,5 IC package (semiconductor package)
2,6 Wiring board 3 Mother board 10,70 Silicon die (semiconductor integrated circuit)
11, 12 Power terminal 13 Ground terminal 20, 80 Interposer (relay member)
21, 81 Ground 82, 83 Power supply terminal 84 Ground terminal 30, 90 Shield case (shield member)
40, 50, 100 Capacitor 41, 51 Laminate 42, 52 First external electrode 43, 53 Second external electrode 44, 54 Third external electrode 45, 55 Fourth external electrode 46, 56 Dielectric layer 47, 57 First Internal electrode 48, 58 Second internal electrode

Claims (10)

  1. 　半導体集積回路と、
    　前記半導体集積回路が実装される中継部材と、
    　前記半導体集積回路を覆うと共に前記中継部材に設けられたグランドに電気的に接続されるシールド部材と、
    　前記半導体集積回路の電源－グランド間に電気的に接続されるコンデンサと、
    　を備え、
    　前記半導体集積回路の上面には、第１電源端子、第２電源端子及びグランド端子が設けられ、
    　前記コンデンサは、誘電体層を挟んで第１内部電極と第２内部電極とが積層された積層体と、前記積層体の下面に設けられ、前記第１内部電極に接続された第１外部電極と、前記積層体の下面に設けられ、前記第１内部電極に接続された第２外部電極と、前記積層体の下面に設けられ、前記第２内部電極に接続された第３外部電極と、前記積層体の上面に設けられ、前記第２内部電極に接続された第４外部電極と、を有し、
    　前記コンデンサは、前記第１外部電極が前記半導体集積回路の前記第１電源端子に電気的に接続され、前記第２外部電極が前記半導体集積回路の前記第２電源端子に電気的に接続され、前記第３外部電極が前記半導体集積回路の前記グランド端子に電気的に接続され、前記第４外部電極が前記シールド部材に電気的に接続されることで、前記半導体集積回路と前記シールド部材との間に実装されることを特徴とする半導体パッケージ。     A semiconductor integrated circuit;
    A relay member on which the semiconductor integrated circuit is mounted;
    A shield member that covers the semiconductor integrated circuit and is electrically connected to a ground provided in the relay member;
    A capacitor electrically connected between the power supply and ground of the semiconductor integrated circuit;
    With
    A first power supply terminal, a second power supply terminal, and a ground terminal are provided on the upper surface of the semiconductor integrated circuit,
    The capacitor includes a laminated body in which a first internal electrode and a second internal electrode are laminated with a dielectric layer interposed therebetween, and a first external electrode provided on a lower surface of the laminated body and connected to the first internal electrode A second external electrode provided on the lower surface of the multilayer body and connected to the first internal electrode; a third external electrode provided on the lower surface of the multilayer body and connected to the second internal electrode; A fourth external electrode provided on the top surface of the laminate and connected to the second internal electrode;
    In the capacitor, the first external electrode is electrically connected to the first power supply terminal of the semiconductor integrated circuit, the second external electrode is electrically connected to the second power supply terminal of the semiconductor integrated circuit, The third external electrode is electrically connected to the ground terminal of the semiconductor integrated circuit, and the fourth external electrode is electrically connected to the shield member, whereby the semiconductor integrated circuit and the shield member A semiconductor package characterized by being mounted between.
  2. 　前記コンデンサの前記第１内部電極及び前記第２内部電極は、前記半導体集積回路の上面に対して略垂直に配置されることを特徴とする請求項１に記載の半導体パッケージ。 2. The semiconductor package according to claim 1, wherein the first internal electrode and the second internal electrode of the capacitor are disposed substantially perpendicular to the upper surface of the semiconductor integrated circuit.
  3. 　半導体集積回路と、
    　前記半導体集積回路が実装される中継部材と、
    　前記半導体集積回路を覆うと共に前記中継部材に設けられたグランドに電気的に接続されるシールド部材と、
    　前記半導体集積回路の電源－グランド間に電気的に接続されるコンデンサと、
    　を備え、
    　前記中継部材の上面には、第１電源端子、第２電源端子及びグランド端子が設けられ、
    　前記コンデンサは、誘電体層を挟んで第１内部電極と第２内部電極とが積層された積層体と、前記積層体の下面に設けられ、前記第１内部電極に接続された第１外部電極と、前記積層体の下面に設けられ、前記第１内部電極に接続された第２外部電極と、前記積層体の下面に設けられ、前記第２内部電極に接続された第３外部電極と、前記積層体の上面に設けられ、前記第２内部電極に接続された第４外部電極と、を有し、
    　前記コンデンサは、前記第１外部電極が前記中継部材の前記第１電源端子に電気的に接続され、前記第２外部電極が前記中継部材の前記第２電源端子に電気的に接続され、前記第３外部電極が前記中継部材の前記グランド端子に電気的に接続され、前記第４外部電極が前記シールド部材に電気的に接続されることで、前記中継部材と前記シールド部材との間に実装されることを特徴とする半導体パッケージ。     A semiconductor integrated circuit;
    A relay member on which the semiconductor integrated circuit is mounted;
    A shield member that covers the semiconductor integrated circuit and is electrically connected to a ground provided in the relay member;
    A capacitor electrically connected between the power supply and ground of the semiconductor integrated circuit;
    With
    A first power supply terminal, a second power supply terminal, and a ground terminal are provided on the upper surface of the relay member,
    The capacitor includes a laminated body in which a first internal electrode and a second internal electrode are laminated with a dielectric layer interposed therebetween, and a first external electrode provided on a lower surface of the laminated body and connected to the first internal electrode A second external electrode provided on the lower surface of the multilayer body and connected to the first internal electrode; a third external electrode provided on the lower surface of the multilayer body and connected to the second internal electrode; A fourth external electrode provided on the top surface of the laminate and connected to the second internal electrode;
    The capacitor has the first external electrode electrically connected to the first power supply terminal of the relay member, the second external electrode electrically connected to the second power supply terminal of the relay member, 3 external electrodes are electrically connected to the ground terminal of the relay member, and the fourth external electrode is electrically connected to the shield member, so that it is mounted between the relay member and the shield member. A semiconductor package characterized by that.
  4. 　前記コンデンサの前記第１内部電極及び前記第２内部電極は、前記中継部材の上面に対して略垂直に配置されることを特徴とする請求項３に記載の半導体パッケージ。 4. The semiconductor package according to claim 3, wherein the first internal electrode and the second internal electrode of the capacitor are disposed substantially perpendicular to the upper surface of the relay member.
  5. 　前記グランド端子は、前記第１電源端子と前記第２電源端子との間に配置され、
    　前記第１外部電極は、前記積層体の下面の一端側に配置され、
    　前記第２外部電極は、前記積層体の下面の他端側に配置され、
    　前記第３外部電極は、前記積層体の下面の前記第１外部電極と前記第２外部電極との間に配置されることを特徴とする請求項１～請求項４の何れか一項に記載の半導体パッケージ。     The ground terminal is disposed between the first power supply terminal and the second power supply terminal,
    The first external electrode is disposed on one end side of the lower surface of the laminate,
    The second external electrode is disposed on the other end side of the lower surface of the laminate,
    5. The third external electrode according to claim 1, wherein the third external electrode is disposed between the first external electrode and the second external electrode on a lower surface of the multilayer body. Semiconductor package.
  6. 　前記第１外部電極は、前記積層体の下面の一端側から前記積層体の一側面の一部に設けられ、
    　前記第２外部電極は、前記積層体の下面の他端側から前記積層体の前記一側面に対向する他側面の一部に設けられることを特徴とする請求項５に記載の半導体パッケージ。     The first external electrode is provided on a part of one side surface of the multilayer body from one end side of the lower surface of the multilayer body,
    The semiconductor package according to claim 5, wherein the second external electrode is provided on a part of the other side surface facing the one side surface of the multilayer body from the other end side of the lower surface of the multilayer body.
  7. 　前記第４外部電極は、前記積層体の上面全体に設けられることを特徴とする請求項１～請求項６の何れか一項に記載の半導体パッケージ。 The semiconductor package according to any one of claims 1 to 6, wherein the fourth external electrode is provided on the entire top surface of the multilayer body.
  8. 　前記第４外部電極は、前記積層体の上面から前記積層体の一側面の一部及び当該一側面に対向する他側面の一部に設けられることを特徴とする請求項７に記載の半導体パッケージ。 The semiconductor package according to claim 7, wherein the fourth external electrode is provided on a part of one side surface of the multilayer body and a part of the other side surface facing the one side surface from the upper surface of the multilayer body. .
  9. 　前記中継部材は、インターポーザであることを特徴とする請求項１～請求項８の何れか一項に記載の半導体パッケージ The semiconductor package according to any one of claims 1 to 8, wherein the relay member is an interposer.
  10. 　マザー基板と、
    　前記マザー基板に実装される半導体パッケージと、
    　を備え、
    　前記半導体パッケージは、請求項１～請求項９の何れか一項の半導体パッケージであり、
    　前記半導体パッケージの前記中継部材は、前記マザー基板と前記半導体パッケージの前記半導体集積回路とを中継することを特徴とする配線基板。     A mother board,
    A semiconductor package mounted on the mother board;
    With
    The semiconductor package is the semiconductor package according to any one of claims 1 to 9,
    The wiring board, wherein the relay member of the semiconductor package relays the mother board and the semiconductor integrated circuit of the semiconductor package.
PCT/JP2017/017343 2016-08-09 2017-05-08 Semiconductor package and wiring board WO2018029921A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09266394A (en) * 1996-03-28 1997-10-07 Toshiba Corp High frequency semiconductor device
JP2006086359A (en) * 2004-09-16 2006-03-30 Taiyo Yuden Co Ltd Multilayer ceramic capacitor
JP2012084635A (en) * 2010-10-08 2012-04-26 Nec Casio Mobile Communications Ltd Electronic component mounting structure and electronic device
JP2012151353A (en) * 2011-01-20 2012-08-09 Sharp Corp Semiconductor module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09266394A (en) * 1996-03-28 1997-10-07 Toshiba Corp High frequency semiconductor device
JP2006086359A (en) * 2004-09-16 2006-03-30 Taiyo Yuden Co Ltd Multilayer ceramic capacitor
JP2012084635A (en) * 2010-10-08 2012-04-26 Nec Casio Mobile Communications Ltd Electronic component mounting structure and electronic device
JP2012151353A (en) * 2011-01-20 2012-08-09 Sharp Corp Semiconductor module

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