WO2018008147A1

WO2018008147A1 - Image processing device and display unit

Info

Publication number: WO2018008147A1
Application number: PCT/JP2016/070286
Authority: WO
Inventors: 坂井　満
Original assignee: 三菱電機株式会社
Priority date: 2016-07-08
Filing date: 2016-07-08
Publication date: 2018-01-11
Also published as: JPWO2018008147A1; JP6744052B2

Abstract

The present invention comprises: a phase adjustment unit (101) for determining a first delay amount for the output timing for outputting a first drive signal to a first display device (5) and a second delay amount for the output timing for outputting a second drive signal to a second display device (6) on the basis of the phase of a first synchronous signal input from a first video output device (1) and the phase of a second synchronous signal input from a second video output device (2); and a delay unit for controlling the output timing for the first drive signal on the basis of the determined first delay amount and controlling the output timing for the second drive signal on the basis of the determined second delay amount.

Description

Image processing apparatus and display unit

The present invention relates to a technique for displaying video information.

Conventionally, when video information is displayed on a plurality of display devices, the drive timing of the plurality of display devices is shifted by shifting the timing of starting a frame of video data output from the video output device, thereby driving the plurality of display devices. A technique for reducing the peak value of electric power has been proposed.
For example, in the image processing device disclosed in Patent Document 1, the video data output from one video output device is divided into a plurality of regions in the horizontal direction, the plurality of divided synchronization signals and the plurality of video data are delayed, The timing of the synchronization signal and the video data is shifted at the stage of input to each display device.

Japanese Patent Laying-Open No. 2015-203851

In recent years, for example, a plurality of display devices are mounted in a passenger compartment of a vehicle, and each display device is not limited to a case where video data is output from one video output device, but a plurality of video data from a plurality of video output devices. Is often output. The technique described in Patent Document 1 described above is applicable when video data is output from a single video output device to a plurality of display devices. However, video data output from a plurality of video output devices is It could not be adapted to output to multiple display devices. This is because even if a plurality of video data output from a plurality of video output devices are synchronization signals of the same timing, the synchronization signal when input to the display device is over time due to an error of the original oscillation. This is because they are displaced. Thus, in the technique described in Patent Document 1 described above, when a plurality of video data output from a plurality of video output devices are displayed on a plurality of display devices, the peak value of the driving power of the display device is set. There was a problem that it was difficult to reduce.

The present invention has been made in order to solve the above-described problems. When a plurality of video data output from a plurality of video output devices are displayed on a plurality of display units, the driving power of the plurality of display units is provided. It aims at reducing the peak value of.

The image processing device according to the present invention is based on the phase of the first synchronization signal input from the first video output device and the phase of the second synchronization signal input from the second video output device. A phase adjustment unit for determining a first delay amount for the output timing of the first drive signal for one display unit and a second delay amount for the output timing of the second drive signal for the second display unit; The output timing of the first drive signal is controlled based on the first delay amount determined by the phase adjustment unit, and the output timing of the second drive signal is controlled based on the second delay amount determined by the phase adjustment unit. And a delay unit.

According to the present invention, even when a plurality of video data output from a plurality of video output devices are displayed on a plurality of display units, it is possible to avoid overlapping of the drive timings of the respective display units. Thereby, the peak value of the drive electric power of a some display part can be reduced.

1 is a block diagram illustrating a configuration of a display system including an image processing device according to Embodiment 1. FIG. 1 is a block diagram illustrating a configuration of an image processing device according to Embodiment 1. FIG. 3A and 3B are diagrams illustrating a hardware configuration of the image processing apparatus according to the first embodiment. 3 is a flowchart illustrating an operation of the image processing apparatus according to the first embodiment. 4 is a timing chart showing drive timing and drive power of the display device when the delay processing of the image processing device according to the first embodiment is not applied. 6 is a timing chart showing drive timing and drive power of the display device when the delay processing of the image processing device according to the first embodiment is applied. 6 is a block diagram illustrating a configuration of an image processing apparatus according to Embodiment 2. FIG. 6 is a flowchart illustrating an operation of the image processing apparatus according to the second embodiment. 10 is a timing chart showing drive timing and drive power of a display device when delay processing of an image processing device according to Embodiment 2 is applied. 6 is a diagram illustrating another configuration example of the image processing apparatus according to Embodiment 1. FIG.

Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram illustrating a configuration of a display system including an image processing apparatus according to the first embodiment. Here, a display system mounted on a vehicle is shown as an example.
The display system includes a first video output device 1, a second video output device 2, an image processing device 3, a control device 4, and a first display device (corresponding to the “first display unit” of the present invention) 5. , A second display device (corresponding to the “second display portion” of the present invention) 6 and a power supply circuit 7.
The first video output device 1 is composed of, for example, an instrument cluster unit (ICU), and includes a speedometer indicating the vehicle speed, first video data for displaying various information indicating the vehicle state, and a first Output sync signal. The second video output device 2 is composed of, for example, a head unit (HU), and outputs second video data and a second synchronization signal for displaying information of a navigation device and an audio device mounted on the vehicle. .

The image processing apparatus 3 includes the first and second synchronization signals output from the first and second video output apparatuses 1 and 2 and the first and second synchronization signals synchronized with the first and second synchronization signals, respectively. Is a timing controller that receives input of video data and generates display data and drive signals to be displayed on the first and

second display devices

5 and 6. The control device 4 controls the first video output device 1, the second video output device 2, and the image processing device 3 that are connected to each other via an in-vehicle network such as CAN (Controller Area Network). The first display device 5 is an instrument cluster for displaying various information on a speedometer and a vehicle, for example. The second display device 6 is a CID (Center Information Display) that displays information such as a navigation device and an audio device. The power supply circuit 7 supplies a drive current to the first and

second display devices

5 and 6.

1, the image processing device 3, the control device 4, the first display device 5, the second display device 6 and the power supply circuit 7 constitute a display unit 8. The power supply circuit 7 may be provided outside the display unit 8.

The resolution, synchronization frequency, timing, etc. of the first video data output from the first video output device 1 shown in FIG. 1 and the second video data output from the second video output device 2 are shown. The format is assumed to be the same, for example. On the other hand, since the first and second video output apparatuses 1 and 2 have different reference clock source crystal resonators in each of the first and second video output apparatuses 1 and 2, an error occurs in the original oscillation. There may be deviation. Therefore, the image processing device 3 generates display data and drive signals to be output to the first and

second display devices

5 and 6 in consideration of the phase difference shift of the synchronization signal.

Although FIG. 1 shows a display system including two video output devices and two display devices, the number of video output devices and display devices is not limited to this. Good. This is the same in all examples shown below.

Next, details of the image processing apparatus 3 will be described.
FIG. 2 is a block diagram illustrating a configuration of the image processing apparatus 3 according to the first embodiment.
The image processing apparatus 3 includes a phase adjustment unit 101, a first video delay unit 102, a first synchronization delay unit 103, a second video delay unit 104, a second synchronization delay unit 105, and a first video processing unit 106. , A first drive signal generation unit 107, a second video processing unit 108, and a second drive signal generation unit 109.
As shown in FIG. 1, the image processing device 3 is connected to the first and second video output devices 1 and 2 and the first and

second display devices

5 and 6 described above. Further, the first and second video output devices 1 and 2 send the first and second synchronization signals to the image processing device 3, and the first and second synchronization signals synchronized with the first and second synchronization signals, respectively. Video data is input. In FIG. 2, the description of the control device 4 is omitted.

The phase adjustment unit 101 uses the first synchronization signal input from the first video output device 1 and the second synchronization signal output from the second video output device 2 to generate a first delay amount. And a second delay amount is calculated.
When the first video data is input from the first video output device 1, the first video delay unit 102 delays the timing by the first delay amount input from the phase adjustment unit 101, The image is output to the video processing unit 106. When the first synchronization signal is input from the first video output device 1, the first synchronization delay unit 103 delays the timing by the first delay amount input from the phase adjustment unit 101, This is output to the drive signal generation unit 107.
In the first embodiment, the output timing of the first video data is adjusted so that the synchronization relationship between the first video data and the first synchronization signal is not lost.

When the second video data is input from the second video output device 2, the second video delay unit 104 delays the timing by the second delay amount input from the phase adjustment unit 101, Output to the video processing unit 108. When the second synchronization signal is input from the second video output device 2, the second synchronization delay unit 105 delays the timing by the second delay amount input from the phase adjustment unit 101, This is output to the drive signal generator 109.
In the first embodiment, the output timing of the second video data is adjusted so that the synchronization relationship between the second video data and the second synchronization signal is not lost.

The first video processing unit 106 performs first display from the first video data input from the first video delay unit 102 and the first synchronization signal input from the first synchronization delay unit 103. First display data to be displayed on the device 5 is generated. The first drive signal generation unit 107 generates a first drive signal for driving the first display device 5 based on the first synchronization signal input from the first synchronization delay unit 103. The first display device 5 connected to the image processing device 3 is driven according to the first drive signal input from the first drive signal generation unit 107 and is input from the first video processing unit 106. Display the display data.

The second video processing unit 108 generates a second display from the second video data input from the second video delay unit 104 and the second synchronization signal input from the second synchronization delay unit 105. Second display data to be displayed on the device 6 is generated. The second drive signal generation unit 109 generates a second drive signal for driving the second display device 6 based on the second synchronization signal input from the second synchronization delay unit 105. The second display device 6 connected to the image processing device 3 is driven according to the second drive signal input from the second drive signal generation unit 109 and is input from the second video processing unit 108. Display the display data.

Note that the first video delay unit 102, the first synchronization delay unit 103, the second video delay unit 104, and the second synchronization delay unit 105 shown in FIG. 2 constitute a delay unit. Further, the first video processing unit 106, the first drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109 constitute a signal processing unit.

Next, a hardware configuration example of the image processing apparatus 3 will be described.
3A and 3B are diagrams illustrating a hardware configuration example of the image processing apparatus 3 according to the first embodiment.
In the image processing device 3, the phase adjustment unit 101, the first video delay unit 102, the first synchronization delay unit 103, the second video delay unit 104, the second synchronization delay unit 105, and the first video processing unit 106. The first drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109 may be a processing circuit 100a that is dedicated hardware as shown in FIG. 3A. As shown in FIG. 3B, a processor 100b that executes a program stored in the memory 100c may be used.

As shown in FIG. 3A, the phase adjustment unit 101, the first video delay unit 102, the first synchronization delay unit 103, the second video delay unit 104, the second synchronization delay unit 105, and the first video processing unit. 106, when the first drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109 are dedicated hardware, the processing circuit 100a includes, for example, a single circuit, a composite circuit, A programmed processor, a processor programmed in parallel, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-programmable Gate Array), or a combination thereof is applicable. Phase adjustment unit 101, first video delay unit 102, first synchronization delay unit 103, second video delay unit 104, second synchronization delay unit 105, first video processing unit 106, first drive signal The functions of the respective units of the generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109 may be realized by a processing circuit, or the functions of the respective units may be realized by a single processing circuit. Also good.

As shown in FIG. 3B, the phase adjustment unit 101, the first video delay unit 102, the first synchronization delay unit 103, the second video delay unit 104, the second synchronization delay unit 105, and the first video processing unit. 106, when the first drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109 are the processor 100b, the function of each unit is software, firmware, or a combination of software and firmware. It is realized by. Software or firmware is described as a program and stored in the memory 100c. The processor 100b reads and executes the program stored in the memory 100c, thereby executing the phase adjustment unit 101, the first video delay unit 102, the first synchronization delay unit 103, the second video delay unit 104, and the second video delay unit 104. The synchronization delay unit 105, the first video processing unit 106, the first drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109 are realized. That is, the phase adjustment unit 101, the first video delay unit 102, the first synchronization delay unit 103, the second video delay unit 104, the second synchronization delay unit 105, the first video processing unit 106, the first video processing unit 106, When the drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109 are executed by the processor 100b, each step shown in FIG. 4 to be described later is executed as a result. A memory 100c for storing the program. In addition, these programs include a phase adjustment unit 101, a first video delay unit 102, a first synchronization delay unit 103, a second video delay unit 104, a second synchronization delay unit 105, and a first video processing unit. 106, it can be said that the computer executes the procedure or method of the first drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109.

Here, the processor 100b is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a processor, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor).
The memory 100c may be a nonvolatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable ROM), or an EEPROM (Electrically EPROM). Further, it may be a magnetic disk such as a hard disk or a flexible disk, or an optical disk such as a mini disk, CD (Compact Disc), or DVD (Digital Versatile Disc).

The phase adjustment unit 101, the first video delay unit 102, the first synchronization delay unit 103, the second video delay unit 104, the second synchronization delay unit 105, the first video processing unit 106, the first A part of each function of the drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109 is realized by dedicated hardware, and a part thereof is realized by software or firmware. Also good. As described above, the processing circuit 100a in the image processing apparatus 3 can realize the above-described functions by hardware, software, firmware, or a combination thereof.

Next, the operation of the image processing apparatus 3 will be described.
FIG. 4 is a flowchart showing the operation of the image processing apparatus 3 according to the first embodiment.
In FIG. 4, the case where two video data and two synchronization signals are input to the image processing device 3 from the first video output device 1 and the second video output device 2 will be described as an example. Note that the flowchart of FIG. 4 can be applied with appropriate modifications according to the number of video output devices connected to the image processing device 3.

When the first synchronization signal is input from the first video output device 1 (step ST1), the phase adjustment unit 101 of the image processing device 3 receives the first synchronization signal from the second video output device 2. The immediately preceding second synchronization signal or the second synchronization signal input simultaneously with the first synchronization signal is acquired (step ST2). The phase adjustment unit 101 detects the phase difference between the first synchronization signal input in step ST1 and the second synchronization signal acquired in step ST2 (step ST3). The phase adjustment unit 101 determines the initial value of the first delay amount and the second value based on the phase difference detected in step ST3 and the delay times set in the first display device 5 and the second display device 6, respectively. An initial value of the delay amount is calculated (step ST4).
Here, the delay time is from when a drive signal is input to the first display device 5 and the second display device 6 until the first display device 5 and the second display device 6 are driven by the drive signal. It is the time required for each display device, and is a predetermined time for each display device. Note that the timing at which the drive signal is output to the first display device 5 and the second display device 6 can be accurately controlled if the delay time is taken into account. The initial value of the delay amount may be calculated based only on the phase difference.

The phase adjustment unit 101 drives the first drive signal when the initial value of the first delay amount calculated at step ST4 is applied, and the second when the initial value of the second delay amount is applied. It is determined whether or not the drive timing of the drive signal is longer than a preset time (step ST5). When the distance is longer than the preset time (step ST5; YES), the phase adjustment unit 101 sets the initial value of the first delay amount calculated in step ST4 to the first video delay unit 102 and the first synchronization delay unit 103. The initial value of the second delay amount is output to the second video delay unit 104 and the second synchronization delay unit 105 (step ST6).

On the other hand, when the time is not longer than the preset time (step ST5; NO), the phase adjustment unit 101 causes the drive timing of the first drive signal and the drive timing of the second drive signal to be more than the preset time. In addition, at least one of the initial value of the first delay amount and the initial value of the second delay amount calculated in step ST4 is adjusted (step ST7). The phase adjustment unit 101 outputs the first delay amount adjusted in step ST7 to the first video delay unit 102 and the first synchronization delay unit 103, and the adjusted second delay amount is output to the second video delay unit. 104 and the second synchronization delay section 105 (step ST8).

The first video delay unit 102 outputs the output timing of the first video data input from the first video output device 1 to the first video processing unit 106 in the first step ST6 or ST8. Is delayed using the delay amount (step ST9). Similarly, in step ST9, the second video delay unit 104 determines the output timing of the second video data input from the second video output device 2 to the second video processing unit 108, in step ST6 or step ST9. Delay is performed using the second delay amount input in ST8.

The first synchronization delay unit 103 outputs the output timing of the first synchronization signal input in step ST1 to the first drive signal generation unit 107, and the first delay amount input in step ST6 or step ST8. To delay (step ST10). Similarly, in step ST10, the second synchronization delay unit 105 receives the output timing of the second synchronization signal input in step ST1 to the second drive signal generation unit 109 in step ST6 or step ST8. Delay using the second delay amount

The first video processing unit 106 displays the video data on the first display device 5 using the first video data input in step ST9 and the first synchronization signal input in step ST10. First display data is generated and output to the first display device 5 (step ST11). Similarly, as step ST11, the second video processing unit 108 uses the second video data input at step ST9 and the second synchronization signal input at step ST10 to use the second display device. Second display data for displaying video data on 6 is generated and output to the second display device 6.

The first drive signal generation unit 107 generates a first drive signal for displaying video data on the first display device 5 using the first synchronization signal input in step ST10. Are output to the display device 5 (step ST12). Similarly, in step ST12, the second drive signal generation unit 109 uses the second synchronization signal input in step ST10 to perform second drive for displaying video data on the second display device 6. A signal is generated and output to the second display device 6. Thus, the process ends.

Next, how the peak value of the driving power of the plurality of display devices is suppressed by the delay processing by the image processing device 3 will be described with reference to a timing chart.
First, FIG. 5 shows a timing chart showing drive timing and drive power of the first display device 5 and the second display device 6 when the delay processing by the image processing device 3 is not applied.
In FIG. 5, in order from the top, the first horizontal synchronization signal, the first video data, the second horizontal synchronization signal, the second video data, the first drive signal, the first display data, and the second drive. A timing chart of signals, second display data, and driving power of the first and

second display devices

5 and 6 is shown.

In FIG. 5, the timing Pa of the first horizontal synchronization signal and the timing Pb of the second horizontal synchronization signal are the same. In the example of FIG. 5, since the delay processing by the image processing device 3 is not performed, the drive position Qa of the first drive signal and the drive position Qb of the second drive signal are the same. Thereby, the drive timings of the first display device 5 and the second display device 6 are also the same, and the first display data and the second display data are displayed at the same timing. As a result, the driving power peaks of the first and

second display devices

5 and 6 overlap at the position R.

Next, FIG. 6 shows a timing chart showing the drive timing and drive power of the first display device 5 and the second display device 6 when the delay processing by the image processing device 3 is performed.
In FIG. 6, in order from the top, the first horizontal synchronization signal, the first video data, the second horizontal synchronization signal, the second video data, the delayed first horizontal synchronization signal, and the delayed first Video data, delayed second horizontal synchronization signal, delayed second video data, first drive signal, first display data, second drive signal, second display data, and first and first 2 is a timing chart of drive power of the

display devices

5 and 6 of FIG.

The timing Pa of the first horizontal synchronization signal and the timing Pb of the second horizontal synchronization signal are the same, and the display timings of the first video data and the second video data are also the same. Based on the detected phase difference between the first horizontal synchronization signal and the second horizontal synchronization signal, and the delay times of the first display device 5 and the second display device 6, the phase adjustment unit 101 The timing at which the drive signal and the second drive signal are output is estimated. In the example of FIG. 6, the phase adjustment unit 101 does not leave the timings of the first drive signal and the second drive signal more than a predetermined time based on the estimated timings of the first drive signal and the second drive signal. Judge. The phase adjustment unit 101 adjusts the first delay amount and the second delay amount so that the first drive signal and the second drive signal are separated by a predetermined time or more.

The flat sync signal and video data delayed by using the adjusted first delay amount and the adjusted second delay amount are the same as the delayed first horizontal sync signal and delayed first shown in FIG. The video data, the delayed second horizontal synchronization signal, and the delayed second video data. In the example of FIG. 6, the output timing of the second horizontal synchronization signal and the second video data is delayed by a second delay amount. The output timing of the delayed second horizontal synchronization signal is delayed from timing Pb to timing Pc. As a result, the drive position Qa of the first drive signal and the drive position Qc of the second drive signal are separated from each other, the peak of the drive power of the first display device 5 becomes the position Ra, and the drive of the second display device 6 is performed. The power peak is at position Rb. Thus, the peak positions of the driving power of the first and

second display devices

5 and 6 are separated, and the peak value of the driving power is suppressed.

When the phase adjustment unit 101 determines whether or not the phase differences of the plurality of horizontal synchronization signals are apart from each other by a preset time, the preset time is, for example, the number of video data input to the image processing device 3 To be determined. As shown in FIG. 2, when two pieces of video data of the first video data and the second video data are input to the image processing device 3, 1/2 of the horizontal period of the horizontal synchronization signal of one video data. It is desirable that the first horizontal synchronizing signal and the second horizontal synchronizing signal are alternately output at the intervals. Specifically, as shown in the timing chart of FIG. 6, the timing Pc of the second horizontal synchronization signal is output at a position of about ½ period of the horizontal period T of the timing Pa of the first horizontal synchronization signal. The timing is desirable. Therefore, the time set in advance in the phase adjustment unit 101 is set based on this timing.

In addition, when three video data are input to the image processing device 3, three horizontal sync signals are sequentially output at intervals of about 1/3 of the horizontal cycle of the horizontal sync signal of any one video data. It is desirable to be done. The time set in advance in the phase adjustment unit 101 is set based on this timing.
Since the peak of the driving power may vary depending on the configuration of the display device, it is desirable that the preset time is set with a predetermined allowable range based on the horizontal period. Further, the predetermined allowable range is set according to the degree to which the overlapping of the driving power peaks of the first and

second display devices

5 and 6 as the display unit 8 is allowed.

Next, the case where the first display device 5 and the second display device 6 are liquid crystal displays will be described.
When displaying video data on a liquid crystal display, the control reference signal includes a horizontal synchronization signal for synchronizing the liquid crystal panel of the liquid crystal display in the horizontal direction and a reference for synchronizing the liquid crystal panel in the vertical direction. A vertical synchronization signal used as a signal, a data enable signal indicating a period during which video data input is valid, and the like are included.
Further, in the display control of the liquid crystal display, a vertical blanking period which is a gap time for shifting to the next rewriting cycle in the vertical synchronization signal is provided. In the image processing apparatus 3, the phase adjustment unit 101 performs a delay process for video data and a delay process for a synchronization signal during the vertical blanking period.

In addition, when displaying video data on a liquid crystal display, a positive voltage with respect to the reference potential (hereinafter referred to as a positive voltage) and a negative voltage with respect to the reference potential (hereinafter referred to as a negative voltage) for the purpose of preventing burn-in of the liquid crystal display. AC is applied alternately. In the AC application cycle of this voltage, when a cycle in which a positive voltage is applied is one AC application cycle, and an AC application cycle in which a negative voltage is applied is also one AC application cycle, every even number of AC application cycles During the vertical blanking period, video data delay processing and synchronization signal delay processing are performed.

As described above, according to the first embodiment, the phase of the first synchronization signal input from the first video output device 1 and the second synchronization signal input from the second video output device 2 are changed. Based on the phase, the first delay amount for the output timing of the first drive signal to the first display device 5 and the second delay for the output timing of the second drive signal to the second display device 6 A phase adjustment unit 101 that determines the amount, a first synchronization delay unit 103 that controls the output timing of the first drive signal based on the determined first delay amount, and a determined second delay amount. Since the second synchronization delay unit 105 that controls the output timing of the second drive signal is provided, when a plurality of video data output from a plurality of video output devices are displayed on a plurality of display devices. Even each display device It is possible to avoid the drive timing from overlapping in. Thereby, the peak value of the drive electric power of a some display apparatus can be reduced.

Thereby, the image processing apparatus can perform the delay process with a configuration using only the line memory that temporarily holds the video data output from the video output apparatus. That is, the image processing apparatus does not need to include a frame memory, and can suppress an increase in the circuit scale of the image processing apparatus and an increase in product cost.

Furthermore, by reducing the peak value of the drive power of the display device, the circuit configuration of the power circuit of the display unit is simplified, the EMC (Electro-Magnetic Compatibility) level of the display unit is reduced, and the wiring pattern of the display unit is simplified. Thus, it is possible to reduce the substrate area and weight.

Further, according to the first embodiment, the phase adjustment unit 101 detects the phase difference between the first synchronization signal and the second synchronization signal, and the first delay amount based on the detected phase difference. In addition, since the second delay amount is determined, it is possible to avoid the overlapping of the drive timings of the display devices and to reduce the peak value of the drive power of the plurality of display devices.

Further, according to the first embodiment, the phase adjustment unit 101 sets the threshold based on the period of one of the first synchronization signal and the second synchronization signal, and the phase difference is set. Since the first delay amount and the second delay amount are determined based on whether or not the threshold value is greater than or equal to the threshold value, the drive timing of each display device can be separated by a predetermined amount, and the drive of each display device can be separated. It is possible to avoid overlapping timing.

In addition, according to the first embodiment, when the first and

second display devices

5 and 6 are liquid crystal displays, the phase adjustment unit 101 has an alternating current application period of positive voltage applied to the liquid crystal display. In the case of alternately applying a positive voltage and a negative voltage with an alternating current application period of a negative voltage as one alternating current application period, the output timing of the first drive signal and the second time are output every even number of alternating current application periods. Since the first delay amount and the second delay amount that control the output timing of the drive signal are determined, the burn-in of the liquid crystal display is prevented and the drive timings of the display devices are prevented from overlapping. be able to.

Embodiment 2. FIG.
In the second embodiment, a configuration in which a delay process is performed on a drive signal is shown.
FIG. 7 is a block diagram showing a configuration of the image processing apparatus 3a according to the second embodiment.
The image processing device 3a according to the second embodiment includes a first video delay unit 102, a first synchronization delay unit 103, and a second video delay unit 104 of the image processing device 3 according to the first embodiment shown in FIG. In place of the second synchronization delay unit 105, the first video processing unit 106, the first drive signal generation unit 107, the second video processing unit 108, and the second drive signal generation unit 109, the first video A processing unit 106a, a first drive signal generation unit 107a, a second video processing unit 108a, a second drive signal generation unit 109a, a first drive delay unit 110, and a second drive delay unit 111 are provided. ing.
In the following, the same or corresponding parts as the components of the image processing apparatus 3 according to the first embodiment are denoted by the same reference numerals as those used in the first embodiment, and description thereof is omitted or simplified.

The first video processing unit 106 a uses the first video data and the first synchronization signal input from the first video output device 1 to display the first display data to be displayed on the first display device 5. Is generated. The first drive signal generation unit 107 a generates a first drive signal for driving the first display device 5 from the first synchronization signal input from the first video output device 1. The second video processing unit 108 a uses the first video data and the second synchronization signal output from the second video output device 2 to display the second display data to be displayed on the second display device 6. Is generated. The second drive signal generation unit 109 a generates a second drive signal for driving the second display device 6 from the second synchronization signal output from the second video output device 2.

The phase adjustment unit 101 performs the same processing as in the first embodiment, and calculates the first delay amount and the second delay amount. When the first drive signal generated by the first drive signal generation unit 107a is input, the first drive delay unit 110 delays the timing by the first delay amount input from the phase adjustment unit 101. 1 to the display device 5. When the second drive signal generated by the second drive signal generation unit 109a is input, the second drive delay unit 111 delays the timing by the second delay amount input from the phase adjustment unit 101. 2 to the display device 6.

The first display device 5 connected to the image processing device 3 is driven according to the delayed first drive signal input from the first drive delay unit 110 and input from the first video processing unit 106a. The first display data is displayed. The second display device 6 connected to the image processing device 3 is driven according to the delayed second drive signal input from the second drive delay unit 111 and input from the second video processing unit 108a. The second display data is displayed.

The first video processing unit 106a, the first drive signal generation unit 107a, the second video processing unit 108a, and the second drive signal generation unit 107a shown in FIG. 7 constitute a signal processing unit. Further, the first drive delay unit 110 and the second drive delay unit 111 constitute a delay unit.

Next, a hardware configuration example of the image processing apparatus 3a will be described. The hardware configuration example of the image processing apparatus 3a according to the second embodiment is the same as that illustrated in FIGS. 3A and 3B according to the first embodiment, and thus the illustration thereof is omitted.
In the image processing apparatus 3a, the phase adjustment unit 101, the first video processing unit 106a, the first drive signal generation unit 107a, the second video processing unit 108a, the second drive signal generation unit 109a, and the first drive delay. The unit 110 and the second drive delay unit 111 may be a processing circuit 100a which is dedicated hardware as shown in FIG. 3A, or execute a program stored in the memory 100c as shown in FIG. 3B. It may be the processor 100b.

As shown in FIG. 3A, the phase adjustment unit 101, the first video processing unit 106a, the first drive signal generation unit 107a, the second video processing unit 108a, the second drive signal generation unit 109a, and the first drive. When the delay unit 110 and the second drive delay unit 111 are dedicated hardware, the processing circuit 100a includes, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, or the like. The combination is applicable. Phase adjustment unit 101, first video processing unit 106a, first drive signal generation unit 107a, second video processing unit 108a, second drive signal generation unit 109a, first drive delay unit 110, and second Each function of each part of the drive delay unit 111 may be realized by a processing circuit, or the function of each part may be realized by a single processing circuit.

As shown in FIG. 3B, the phase adjustment unit 101, the first video processing unit 106a, the first drive signal generation unit 107a, the second video processing unit 108a, the second drive signal generation unit 109a, and the first drive. When the delay unit 110 and the second drive delay unit 111 are the processor 100b, the function of each unit is realized by software, firmware, or a combination of software and firmware. Software or firmware is described as a program and stored in the memory 100c. The processor 100b reads and executes the program stored in the memory 100c, thereby executing the phase adjustment unit 101, the first video processing unit 106a, the first drive signal generation unit 107a, the second video processing unit 108a, and the second video processing unit 108a. The functions of the second drive signal generation unit 109a, the first drive delay unit 110, and the second drive delay unit 111 are realized. That is, the phase adjustment unit 101, the first video processing unit 106a, the first drive signal generation unit 107a, the second video processing unit 108a, the second drive signal generation unit 109a, the first drive delay unit 110, and the first drive delay unit 110 The second drive delay unit 111 includes a memory 100c for storing a program in which each step shown in FIG. 8 to be described later is executed when executed by the processor 100b. These programs include the phase adjustment unit 101, the first video processing unit 106a, the first drive signal generation unit 107a, the second video processing unit 108a, the second drive signal generation unit 109a, and the first drive. It can also be said that the computer executes the procedure or method of the delay unit 110 and the second drive delay unit 111.

The phase adjustment unit 101, the first video processing unit 106a, the first drive signal generation unit 107a, the second video processing unit 108a, the second drive signal generation unit 109a, the first drive delay unit 110, and the first A part of the functions of the two drive delay units 111 may be realized by dedicated hardware, and a part may be realized by software or firmware. As described above, the processing circuit 100a in the image processing apparatus 3 can realize the above-described functions by hardware, software, firmware, or a combination thereof.

Next, the operation of the image processing apparatus 3a will be described.
FIG. 8 is a flowchart showing the operation of the image processing apparatus 3a according to the second embodiment. In FIG. 8, the same steps as those in the flowchart of the first embodiment shown in FIG.
In FIG. 8, the case where two video data and two synchronization signals are input from the first video output device 1 and the second video output device 2 to the image processing device 3a will be described as an example. Note that the flowchart of FIG. 8 can be applied with appropriate modifications according to the number of video output devices connected to the image processing device 3a.

When the first video data and the first synchronization signal are input from the first video output device 1, and the second video data and the second synchronization signal are input from the second video output device 2 (step ST21), The first video processing unit 106a generates first display data from the first video data and the first synchronization signal input in step ST21, and outputs the first display data to the first display device 5 (step ST22). Similarly, as step ST22, the second video processing unit 108a generates second display data from the second video data and the second synchronization signal, and outputs the second display data to the second display device 6.

The first drive signal generation unit 107a generates a first drive signal from the first synchronization signal input in step ST21 (step ST23). Similarly, as step ST23, the second drive signal generation unit 109a generates a second drive signal from the second synchronization signal. On the other hand, the phase adjustment unit 101 is input simultaneously with the first synchronization signal input at step ST21, the second synchronization signal input immediately before the first synchronization signal, or the first synchronization signal. The obtained second synchronization signal is acquired (step ST24). The phase adjustment unit 101 detects the phase difference between the acquired first synchronization signal and the second synchronization signal (step ST3). The phase adjustment unit 101 determines the initial value of the first delay amount and the second value based on the phase difference detected in step ST3 and the delay times set in the first display device 5 and the second display device 6, respectively. An initial value of the delay amount is calculated (step ST4).

The phase adjustment unit 101 determines the drive timing of the first drive signal based on the initial value of the first delay amount calculated in step ST4 and the drive timing of the second drive signal based on the initial value of the second delay amount. Then, it is determined whether or not the distance is longer than a preset time (step ST5). When the distance is longer than the preset time (step ST5; YES), the initial value of the first delay amount calculated in step ST4 is output to the first drive delay unit 110, and the initial value of the second delay amount is set. It outputs to the 2nd drive delay part 111 (step ST6).

On the other hand, when it is determined that the distance is not longer than the preset time (step ST5; NO), the phase adjustment unit 101 sets the initial value of the first delay amount or the initial value of the second delay amount calculated in step ST4. At least one of them is adjusted (step ST7). The phase adjustment unit 101 outputs the first delay amount adjusted in step ST7 to the first drive delay unit 110, and outputs the adjusted second delay amount to the second drive delay unit 111 (step ST8). .

The first drive delay unit 110 uses the first delay amount input in step ST6 or step ST8 as the output timing of the first drive signal generated in step ST23 to the first display device 5. Delay (step ST25). Similarly, as step ST25, the second drive delay unit 111 outputs the output timing of the second drive signal generated at step ST23 to the second display device 6 at step ST6 or step ST8. Delay using a delay amount of 2. The process ends here.

Next, FIG. 9 shows a timing chart showing the drive timing and drive power of the first display device 5 and the second display device 6 when the delay processing by the image processing device 3a is performed.
In FIG. 9, in order from the top, the first horizontal synchronization signal, the first video data, the second horizontal synchronization signal, the second video data, the first drive signal, the first display data, and the second drive. Signal, second display data, delayed first drive signal, first display data, delayed second drive signal, second display data, and drive power of the first and second display devices. A timing chart is illustrated.

As shown in FIG. 9, the timing Pa of the first horizontal synchronization signal and the timing Pb of the second horizontal synchronization signal are the same, and the display timings of the first video data and the second video data are also the same. . Based on the detected phase difference between the first horizontal synchronization signal and the second horizontal synchronization signal, and the delay times of the first display device 5 and the second display device 6, the phase adjustment unit 101 The timing at which the drive signal and the second drive signal are output is estimated. In the example of FIG. 9, the phase adjustment unit 101 does not deviate the timings of the first drive signal and the second drive signal for a predetermined time or more based on the estimated timings of the first drive signal and the second drive signal. Judge. Therefore, the phase adjustment unit 101 adjusts the first delay amount and the second delay amount so that the first drive signal and the second drive signal are separated by a predetermined time or more.

The drive signal whose output timing is delayed by the adjusted first delay amount and the adjusted second delay amount is the delayed first drive signal and the delayed second drive signal shown in FIG. . In the example of FIG. 9, the output timing of the delayed second drive signal is delayed from the drive position Sb to the drive position Sc. As a result, the driving position Sa of the first driving signal and the driving position Sc of the delayed second driving signal are separated, and the peak of the driving power of the first display device 5 becomes the position Ra, and the second display device. The peak of the driving power of 6 is the position Rb. In this way, the peak positions of the driving power of the two display devices are separated, and the peak value of the driving power is suppressed.

As shown in FIG. 9, in the configuration of the image processing apparatus 3a, the output timings of the first display data and the second display data are not delayed. In general, since the drive signal of the display device needs to be output before the next display data is output, the output timing of the drive signal is delayed within the blanking period shown in FIG. Therefore, in the configuration of the second embodiment, the adjustment range of the output timing of the drive signal is limited to the blanking period, but when the blanking period is set sufficiently long as the video data format, Since it is not necessary to provide a processing circuit for delaying the output timing of display data, the circuit scale is reduced.

As described above, according to the second embodiment, the phase of the first synchronization signal input from the first video output device 1 and the second synchronization signal input from the second video output device 2 are changed. Based on the phase, the first delay amount for the output timing of the first drive signal to the first display device 5 and the second delay for the output timing of the second drive signal to the second display device 6 A phase adjustment unit 101 that determines the amount, a first drive delay unit 110 that controls the output timing of the first drive signal based on the determined first delay amount, and a determined second delay amount. Since it comprises the 2nd drive delay part 111 which controls the output timing of a 2nd drive signal, when displaying the some video data output from the some video output apparatus on a some display apparatus Even each display device It is possible to avoid the drive timing from overlapping in. Thereby, the peak value of the drive electric power of a some display apparatus can be reduced.

Further, according to the second embodiment, the first drive signal generation unit 107a that generates the first drive signal when the first synchronization signal is input, and the first drive signal generation unit 107a that generates the first drive signal when the first synchronization signal is input. A second drive signal generation unit 109a that generates a second drive signal, and the first drive delay unit 110 converts the first drive signal generated by the first drive signal generation unit 107a into a first delay amount. The second drive delay unit 111 outputs the second drive signal generated by the second drive signal generation unit 109a based on the second delay amount based on the second delay amount. Since it is configured to output to the display device 6, it is sufficient to provide only a processing circuit for delaying the drive signal, and the circuit scale can be reduced.

In the second embodiment, the image processing device 3a, the control device 4, the first display device 5, the second display device 6, and the power supply circuit 7 constitute a display unit.

In the second embodiment described above, the configuration including the first and second drive

signal generation units

107a and 109a and the first and second

drive delay units

110 and 111 has been described. The second drive

signal generation units

107a and 109a may adjust the output timing in consideration of the delay amount input from the phase adjustment unit 101 when generating the drive signal from the synchronization signal. In this case, the configuration of the first and second

drive delay units

110 and 111 is not necessary.

In the first embodiment and the second embodiment described above, the case where a plurality of video data output from a plurality of video output devices is displayed on a plurality of display devices is described as an example. The present invention can also be applied to a case where a plurality of output video data are displayed on a plurality of image display units (corresponding to the “display unit” of the present invention) of one display device. An example is shown in FIG. In FIG. 10, the four video data output from the four

video output devices

1a, 1b, 1c, and 1d are sent via the image processing device 3 to the first image display unit 5b and the second image display unit 5a. In this case, the image display unit 5c, the third image display unit 5d, and the fourth image display unit 5e are respectively displayed. The first image display unit 5b, the second image display unit 5c, the third image display unit 5d, and the fourth image display unit 5e are each driven by an individual drive signal.

The image processing device 3, the control device 4 (not shown), the display device 5a, and the power supply circuit 7 shown in FIG. 10 constitute a display unit. In FIG. 10, the image processing apparatus 3 shown in the first embodiment can be replaced with the image processing apparatus 3a shown in the second embodiment.

In the first embodiment and the second embodiment described above, the configuration in which the drive signal is generated based on the horizontal synchronization signal has been described. However, the drive is performed based on the data enable signal that indicates the period during which video data input is valid. You may comprise so that a signal may be produced | generated.

In addition to the above, within the scope of the present invention, the present invention can be freely combined with each embodiment, modified any component of each embodiment, or omitted any component in each embodiment. Is possible.

The image processing apparatus according to the present invention can avoid overlapping of the drive timings of the respective display devices even when the plurality of video data output from the plurality of video output devices are displayed on the plurality of display devices. Therefore, it can be applied to a display unit and the like, and cost reduction can be realized.

1 1st video output device, 1a, 1b, 1c, 1d video output device, 2nd video output device, 3 image processing device, 4 control device, 5th display device, 5a display device, 5b 1st Image display unit, 5c second image display unit, 5d third image display unit, 5e fourth image display unit, 6 second display device, 7 power supply circuit, 8 display unit, 101 phase adjustment unit, 102 First video delay unit, 103, first synchronization delay unit, 104, second video delay unit, 105, second synchronization delay unit, 106, 106a, first video processing unit, 107, 107a, first drive

signal generation Unit

108, 108a second video processing unit 109 109a second drive signal generation unit 110 first drive delay unit 111 second drive delay unit.

Claims

First driving for the first display unit based on the phase of the first synchronization signal input from the first video output device and the phase of the second synchronization signal input from the second video output device A phase adjustment unit for determining a first delay amount for the output timing of the signal and a second delay amount for the output timing of the second drive signal for the second display unit;
The output timing of the first drive signal is controlled based on the first delay amount determined by the phase adjustment unit, and the second drive is performed based on the second delay amount determined by the phase adjustment unit. An image processing apparatus comprising: a delay unit that controls signal output timing.
The phase adjustment unit detects a phase difference between the first synchronization signal and the second synchronization signal, and determines the first delay amount and the second delay amount based on the detected phase difference. The image processing apparatus according to claim 1, wherein the determination is performed.
The phase adjustment unit sets a threshold based on a cycle of one of the first synchronization signal and the second synchronization signal, and whether or not the phase difference is equal to or greater than the set threshold. The image processing apparatus according to claim 2, wherein the first delay amount and the second delay amount are determined based on the first delay amount.
When the first display unit and the second display unit are liquid crystal displays,
The phase adjustment unit alternately applies a positive voltage and a negative voltage with an AC application cycle of a positive voltage applied to the liquid crystal display and an AC application cycle of a negative voltage as one AC application cycle. In this case, the first delay amount and the second delay amount are controlled to control the output timing of the first drive signal and the output timing of the second drive signal every even number of the AC application cycles. The image processing apparatus according to claim 1, wherein:
A signal processing unit that generates the first drive signal when the first synchronization signal is input, and generates the second drive signal when the second synchronization signal is input;
The delay unit outputs the first synchronization signal input from the first video output device to the signal processing unit based on the first delay amount, and is input from the second video output device. The image processing apparatus according to claim 1, wherein the second synchronization signal is output to the signal processing unit based on the second delay amount.
A signal processing unit that generates the first drive signal when the first synchronization signal is input, and generates the second drive signal when the second synchronization signal is input;
The delay unit outputs the first driving signal generated by the signal processing unit to the first display unit based on the first delay amount, and the second driving signal generated by the signal processing unit. The image processing apparatus according to claim 1, wherein the image processing apparatus outputs to the second display unit based on the second delay amount.
The screen processing according to claim 1, wherein the first display unit and the second display unit constitute the same display device, or constitute the first display device and the second display device. apparatus.
A display device;
Based on the phase of the first synchronization signal input from the first video output device and the phase of the second synchronization signal input from the second video output device, the first drive signal of the display device A phase adjustment unit for determining a first delay amount for the output timing and a second delay amount for the output timing of the second drive signal to the display device; and the first delay amount determined by the phase adjustment unit. A delay unit that controls the output timing of the first drive signal based on the second delay amount and controls the output timing of the second drive signal based on the second delay amount determined by the phase adjustment unit. A display unit comprising a processing device.