WO2017219430A1 - 一种阵列基板及液晶面板 - Google Patents

一种阵列基板及液晶面板 Download PDF

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Publication number
WO2017219430A1
WO2017219430A1 PCT/CN2016/090782 CN2016090782W WO2017219430A1 WO 2017219430 A1 WO2017219430 A1 WO 2017219430A1 CN 2016090782 W CN2016090782 W CN 2016090782W WO 2017219430 A1 WO2017219430 A1 WO 2017219430A1
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Prior art keywords
tube
switch control
scan
switch
scan line
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Ceased
Application number
PCT/CN2016/090782
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English (en)
French (fr)
Inventor
郭晋波
王金杰
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/128,250 priority Critical patent/US10203575B2/en
Publication of WO2017219430A1 publication Critical patent/WO2017219430A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B30/00—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a liquid crystal panel.
  • VA-TFT-LCD Vertical alignment LCD screen
  • VA-TFT-LCD Vertical alignment LCD screen
  • the color shift phenomenon is more serious when viewed from a large viewing angle, and is more noticeable on a large-sized panel.
  • the pixel design of large-sized panels In order to solve the color shift problem of large viewing angles, the pixel design of large-sized panels generally adopts low color shift (Low).
  • Color shift) pixel design Figure 1), The pixel is divided into a main pixel area and a sub-pixel area. When charging, G1a and G1b are sequentially turned on.
  • one pixel corresponds to two scan lines (gate Line), in order to save cost, reduce the number of gate driving chips, and connect the shared gate signal of adjacent pixels, that is, G1b and the charging gate signal, that is, G2a, so that the number of driving chips in the panel is reduced.
  • the left and right eye signals change according to the signal polarity, and the signal received by the left eye is “+” ⁇ “—” or “—” ⁇ “+”.
  • the low color shift function is normal, and the signal received by the right eye is "+” ⁇ “+” or “—” ⁇ “—”, the low color shift function is abnormal, the pixels are bright, resulting in inconsistent brightness of the left and right eyes, and the image quality is degraded.
  • An object of the present invention is to provide an array substrate and a liquid crystal panel, which can solve the problem of image sticking and the difference in brightness between left and right eyes when a large-sized panel displays a 3D screen, thereby improving the image quality of the 3D screen.
  • a technical solution adopted by the present invention is to provide an array substrate, wherein the array substrate is provided with a plurality of sets of scan lines, and each set of scan lines includes at least a first scan line and a second scan line, and each set of scans
  • a switching unit is disposed, the switching unit alternately applies the input scan signal to the first scan line and the second scan line; wherein the switching unit comprises a first switch tube and a second switch tube, wherein the input of the first switch tube The end is connected to the input end of the second switch tube and is configured to receive the scan signal, and the output end of the first switch tube and the output end of the second switch tube are respectively connected to the first scan line and the second scan line, and the control of the first switch tube
  • the first switch control line is connected to receive the first switch control signal
  • the control end of the second switch tube is connected to the second switch control line and is configured to receive the second switch control signal
  • the first switch control signal and the second switch The control signal is disposed such that the first
  • the first switch tube and the second switch tube are respectively thin film transistors.
  • another technical solution adopted by the present invention is to provide an array substrate on which a plurality of sets of scan lines are disposed, each set of scan lines including at least a first scan line and a second scan line, each group
  • the scan line is correspondingly provided with a switching unit, and the switching unit alternately applies the input scan signals to the first scan line and the second scan line.
  • the switching unit includes a first switching tube and a second switching tube, wherein the input end of the first switching tube is connected to the input end of the second switching tube and is configured to receive a scan signal, and the output end of the first switching tube and the second switch The output end of the tube is respectively connected to the first scan line and the second scan line, the control end of the first switch tube is connected to the first switch control line and is used for receiving the first switch control signal, and the control end of the second switch tube is connected to the second switch
  • the control line is further configured to receive the second switch control signal, wherein the first switch control signal and the second switch control signal are disposed such that the first switch tube and the second switch tube are alternately turned on.
  • the first switch tube and the second switch tube are respectively thin film transistors.
  • the first switch control signal and the second switch control signal are configured to control the first switch tube and the second switch tube to be alternately turned on for the duration of the same scan signal, so that the same scan signal can be respectively applied to the first scan line. And the second scan line.
  • the array substrate is further provided with a gate driver and a switching controller, wherein the gate driver sequentially supplies a scan signal to the switching unit, and the switching controller alternately provides the first switch control to the first switch control line and the second switch control line
  • the signal and the second switch control signal are such that the scan signal is sequentially applied to the first scan line and the second scan line of the plurality of sets of scan lines in a predetermined direction.
  • the array substrate is further provided with a plurality of pixels arranged in a matrix, wherein each row of pixels corresponds to a group of scan lines.
  • the pixel includes a main pixel region on one side of the corresponding one of the scan lines and a sub-pixel region on the other side of the corresponding one of the scan lines, wherein the first scan line is used to control the main pixel region and the sub-pixel region The same data voltage is obtained, and the second scan line is used for voltage adjustment of the sub-pixel region such that the data voltage of the sub-pixel region is different from the main pixel region.
  • the array substrate is further provided with a data line, a common electrode, a first switch control tube, a second switch control tube and a third switch control tube
  • the main pixel area is provided with a main pixel electrode
  • the sub-pixel area is provided with a sub-pixel electrode
  • the main pixel electrode and the common electrode form a first storage capacitor
  • the sub-pixel electrode and the common electrode form a second storage capacitor
  • the control end of the first switch control tube and the control end of the second switch control tube are connected to the first scan line
  • the first switch The input end of the control tube and the input end of the second switch control tube are connected to the data line
  • the output end of the first switch control tube and the output end of the second switch control tube are respectively connected to the main pixel electrode and the sub-pixel electrode, thereby making the first
  • the scan line is applied with the scan signal
  • the data line applies the same data voltage to the main pixel electrode and the sub-pixel electrode via the first switch control tube and the second switch control tube, respectively, and the control end of
  • the input end of the third switch control tube is connected to the sub-pixel electrode, and the output end of the third switch control tube further forms a third with the common electrode Storage capacitance, and further such that when the scanning signal is applied, a second pair of the third storage capacitor storage capacitor discharges at a second scan line.
  • the first switch control tube, the second switch control tube and the third switch control tube are respectively thin film transistors.
  • a liquid crystal panel including the above array substrate, an opposite substrate disposed opposite the array substrate, and a liquid crystal sandwiched therebetween a plurality of sets of scan lines are disposed on the array substrate, each set of scan lines includes at least a first scan line and a second scan line, and each set of scan lines is correspondingly provided with a switching unit, and the switching unit alternately applies the input scan signals to the first A scan line and a second scan line.
  • the switching unit includes a first switching tube and a second switching tube, wherein the input end of the first switching tube is connected to the input end of the second switching tube and is configured to receive a scan signal, and the output end of the first switching tube and the second switch The output end of the tube is respectively connected to the first scan line and the second scan line, the control end of the first switch tube is connected to the first switch control line and is used for receiving the first switch control signal, and the control end of the second switch tube is connected to the second switch
  • the control line is further configured to receive the second switch control signal, wherein the first switch control signal and the second switch control signal are disposed such that the first switch tube and the second switch tube are alternately turned on.
  • the first switch tube and the second switch tube are respectively thin film transistors.
  • the first switch control signal and the second switch control signal are configured to control the first switch tube and the second switch tube to be alternately turned on for the duration of the same scan signal, so that the same scan signal can be respectively applied to the first scan line. And the second scan line.
  • the array substrate is further provided with a gate driver and a switching controller, wherein the gate driver sequentially supplies a scan signal to the switching unit, and the switching controller alternately provides the first switch control to the first switch control line and the second switch control line
  • the signal and the second switch control signal are such that the scan signal is sequentially applied to the first scan line and the second scan line of the plurality of sets of scan lines in a predetermined direction.
  • the array substrate is further provided with a plurality of pixels arranged in a matrix, wherein each row of pixels corresponds to a group of scan lines.
  • the pixel includes a main pixel region on one side of the corresponding one of the scan lines and a sub-pixel region on the other side of the corresponding one of the scan lines, wherein the first scan line is used to control the main pixel region and the sub-pixel region The same data voltage is obtained, and the second scan line is used for voltage adjustment of the sub-pixel region such that the data voltage of the sub-pixel region is different from the main pixel region.
  • the array substrate is further provided with a data line, a common electrode, a first switch control tube, a second switch control tube and a third switch control tube
  • the main pixel area is provided with a main pixel electrode
  • the sub-pixel area is provided with a sub-pixel electrode
  • the main pixel electrode and the common electrode form a first storage capacitor
  • the sub-pixel electrode and the common electrode form a second storage capacitor
  • the control end of the first switch control tube and the control end of the second switch control tube are connected to the first scan line
  • the first switch The input end of the control tube and the input end of the second switch control tube are connected to the data line
  • the output end of the first switch control tube and the output end of the second switch control tube are respectively connected to the main pixel electrode and the sub-pixel electrode, thereby making the first
  • the scan line is applied with the scan signal
  • the data line applies the same data voltage to the main pixel electrode and the sub-pixel electrode via the first switch control tube and the second switch control tube, respectively, and the control end of
  • the input end of the third switch control tube is connected to the sub-pixel electrode, and the output end of the third switch control tube further forms a third with the common electrode Storage capacitance, and further such that when the scanning signal is applied, a second pair of the third storage capacitor storage capacitor discharges at a second scan line.
  • the first switch control tube, the second switch control tube and the third switch control tube are respectively thin film transistors.
  • the invention has the beneficial effects that the array substrate and the liquid crystal panel of the present invention are provided with a plurality of sets of scan lines, and each set of scan lines includes at least a first scan line and a second scan line, and each set of scan lines corresponds to the prior art.
  • a switching unit is provided, and the switching unit alternately applies the input scan signals to the first scan line and the second scan line.
  • the present invention can solve the problem that the image sticking and the brightness of the left and right eyes which are different when the large-sized panel displays the 3D screen are inconsistent, thereby improving the image quality of the 3D screen.
  • FIG. 1 is a schematic structural view of a prior art array substrate
  • 3 is a timing chart of a driving method of double frame inversion
  • FIG. 4 is a schematic structural view of a liquid crystal panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of an embodiment of an array substrate in the liquid crystal panel shown in FIG. 4;
  • FIG. 6 is a specific circuit diagram of each pixel in the array substrate shown in FIG. 5;
  • Fig. 7 is a timing chart showing the operation of the array substrate shown in Fig. 5.
  • the liquid crystal panel includes an array substrate 1, an opposite substrate 2 disposed opposite to the array substrate 1, and a liquid crystal layer 3 sandwiched between the array substrate 1 and the opposite substrate 2.
  • the opposite substrate 2 may be a color filter substrate in the liquid crystal panel.
  • FIG. 5 is a schematic structural view of an embodiment of an array substrate in the liquid crystal panel shown in FIG. 4.
  • the array substrate 1 includes a plurality of sets of scan lines 10, a plurality of switching units 11, a gate driver 12, a switching controller 13, a plurality of pixels 14 arranged in a matrix, and a plurality of data lines 15.
  • Each of the scan lines 10 includes at least a first scan line 101 and a second scan line 102, and each of the switching units 11 corresponds to a set of scan lines 10.
  • the gate driver 12 is connected to each switching unit 11 for sequentially supplying the scanning signal Fanout to each switching unit 11.
  • the gate driver 12 includes a plurality of gate driving chips, each of which provides a scan signal Fanout.
  • the switching unit 11 is connected to the corresponding first scan line 101 and second scan line 102, respectively, for alternately applying the input scan signal Fanout to the first scan line 101 and the second scan line 102.
  • the switching unit 11 includes a first switching transistor 111 and a second switching transistor 112.
  • the first switching transistor 111 and the second switching transistor 112 are respectively thin film transistors.
  • the input end of the first switch tube 111 is connected to the input end of the second switch tube 112 and is configured to receive the scan signal Fanout.
  • the output end of the first switch tube 111 and the output end of the second switch tube 112 are respectively connected to the first scan.
  • the control line of the first switch tube 111 is connected to the first switch control line 103 and is used to receive the first switch control signal L1, and the control end of the second switch tube 112 is connected to the second switch control line 104. And used to receive the second switch control signal L2.
  • the switching controller 13 is connected to the first switch control line 103 and the second switch control line 104, respectively, for alternately providing the first switch control signal L1 and the second switch control to the first switch control line 103 and the second switch control line 104.
  • the signal L2 is such that the scan signal Fanout is sequentially applied to the first scan line 101 and the second scan line 102 of the plurality of sets of scan lines 10 in a predetermined direction.
  • the first switch control signal L1 and the second switch control signal L2 are disposed such that the first switch transistor 111 and the second switch transistor 112 are alternately turned on.
  • the first switch control signal L1 and the second switch control signal L2 are arranged to control the first switch tube 111 and the second switch tube 112 to be alternately turned on for the duration of the same scan signal Fanout, so that the same scan signal Fanout can They are applied to the first scan line 101 and the second scan line 102, respectively.
  • each row of pixels corresponds to a set of scan lines 10, and each column of pixels corresponds to one data line 15.
  • each of the pixels 14 includes a main pixel region 141 on one side of the corresponding one of the scan lines 10 and a sub-pixel region 142 on the other side of the corresponding one of the scan lines 10, wherein the first scan line 101
  • the main pixel region 141 and the sub-pixel region 142 are used to control the same data voltage
  • the second scan line 102 is used to voltage-adjust the sub-pixel region 142 such that the data voltage of the sub-pixel region 142 is different from that of the main pixel region 141.
  • FIG. 6 is a specific circuit diagram of each pixel in the array substrate shown in FIG. 5.
  • the array substrate 1 is further provided with a common electrode Vcom, a first switch control tube T1, a second switch control tube T2, and a third switch control tube T3.
  • the pixel 14 includes a main pixel region 141 and a sub-pixel region 142.
  • the main pixel region 141 is provided with a main pixel electrode 1411
  • the main pixel electrode 1411 and the common electrode Vcom form a first storage capacitor Cst1
  • the sub-pixel region 142 is provided with a sub-pixel electrode 1421
  • the sub-pixel electrode and the common electrode Vcom form a first pixel.
  • the control end of the first switch control tube T1 and the control end of the second switch control tube T2 are connected to the first scan line 101, and the input end of the first switch control tube T1 and the input end of the second switch control tube T2 are connected to the data line 15,
  • the output end of the first switch control tube T1 and the output end of the second switch control tube T2 are respectively connected to the main pixel electrode 1411 and the sub-pixel electrode 1421, so that when the scan signal Fanout is applied to the first scan line 101, the data line 15 passes through
  • the first switch control tube T1 and the second switch control tube T2 apply the same data voltage to the main pixel electrode 1411 and the sub-pixel electrode 1421, respectively.
  • the control end of the third switch control tube T3 is connected to the second scan line 102, the input end of the third switch control tube T3 is connected to the sub-pixel electrode 1421, and the output end of the third switch control tube T3 further forms a third storage capacitor with the common electrode Vcom.
  • Cst3 causes the second storage capacitor Cst2 to discharge the third storage capacitor Cst3 when the scan signal Fanout is applied to the second scan line 102.
  • the first switch control tube T1, the second switch control tube T2, and the third switch control tube T3 are thin film transistors.
  • FIG. 7 is an operation timing diagram of the array substrate shown in FIG. 5.
  • the working timing chart is described by taking two adjacent rows of pixels as an example.
  • the scan signal Fanout outputted by the gate driver 12 to the first row of pixels is recorded as Fanout1
  • the scan signal output from the gate driver 12 to the second row of pixels is Fanout.
  • the signals outputted on the first scan line 101 and the second scan line 12 corresponding to the pixels of the first row are denoted as gate1a and gate1b, respectively
  • the first scan line 101 and the second scan line 12 corresponding to the pixels of the second row are recorded as Fanout2.
  • the output signals are recorded as gate2a and gate2b, respectively.
  • the scan signal Fanout supplied from the gate driver 12 to each switching unit 11 in sequence is a high level signal for two cycles. That is to say, in the T1 and T2 cycles, the scan signal Fanout1 is a high level signal, and the scan signal Fanout2 is a low level signal; in the T3 and T4 cycles, the scan signal Fanout1 is a low level signal, and the scan signal Fanout2 is a high level. signal.
  • the first switch control signal L1 outputted by the switching controller 13 is a high level signal
  • the second switch control signal L2 is a low level signal, so that the first switch tube 111 in each switching unit 11 is turned on.
  • the second switch tube 112 is turned off. Since the scan signal Fanout1 received by the first row of pixels is at a high level, the signal gate1a on the first scan line 101 corresponding to the first row of pixels is at a high level, and the other three signals gate1b, gate2a, and gate2b are low. In the flat state, the data line 15 is simultaneously charged to the main pixel region 141 and the sub-pixel region 142 in the first row of pixels, respectively.
  • the first switch control signal L1 output by the switching controller 13 is a low level signal
  • the second switch control signal L2 is a high level signal, so that the first switch tube 111 in each switching unit 11 is turned off.
  • the second switch tube 112 is turned on. Since the scan signal Fanout1 received by the first row of pixels is at a high level, the signal gate1b on the second scan line 102 corresponding to the first row of pixels is at a high level, and the other three signals gate1a, gate2a, and gate2b are low. Flat, thereby achieving a lower voltage of the sub-pixel region 142 in the first row of pixels.
  • the first switch control signal L1 output by the switching controller 13 is a high level signal
  • the second switch control signal L2 is a low level signal, so that the first switch tube 111 in each switching unit 11 is turned on.
  • the second switch tube 112 is turned off.
  • the scan signal Fanout2 received by the second row of pixels is at a high level, so that the signal gate2a on the first scan line 101 corresponding to the second row of pixels is at a high level, and the other three signals gate1a, gate1b, and gate2b are low.
  • the data line 15 is simultaneously charged to the main pixel region 141 and the sub-pixel region 142 in the second row of pixels, respectively.
  • the first switch control signal L1 outputted by the switching controller 13 is a low level signal
  • the second switch control signal L2 is a high level signal, so that the first switch tube 111 in each switching unit 11 is turned off.
  • the second switch tube 112 is turned on.
  • the scan signal Fanout2 received by the second row of pixels is at a high level, so that the signal gate2b on the second scan line 102 corresponding to the second row of pixels is at a high level, and the other three signals gate1a, gate2a, and gate2a are low. Flat, thereby achieving a voltage lowering of the sub-pixel region 142 in the second row of pixels.
  • the first scan signal that is, the charge gate signal and the second scan signal, that is, the shared gate signal
  • the first scan signal that is, the charge gate signal and the second scan signal, that is, the shared gate signal
  • the pole signal and the charging gate signal are connected to each other, so that the problem of image sticking and inconsistent brightness of the left and right eyes in the prior art does not occur.
  • the invention has the beneficial effects that the array substrate and the liquid crystal panel of the present invention are provided with a plurality of sets of scan lines, and each set of scan lines includes at least a first scan line and a second scan line, and each set of scan lines corresponds to the prior art.
  • a switching unit is provided, and the switching unit alternately applies the input scan signals to the first scan line and the second scan line.
  • the first scanning line that is, the charging gate signal
  • the second scanning line that is, the shared gate signal
  • the problem of inconsistent brightness improves the picture quality of the 3D picture.

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Abstract

一种阵列基板（1）及液晶面板。阵列基板（1）上设置有多组扫描线（10），每组扫描线（10）至少包括第一扫描线（101）和第二扫描线（102），每组扫描线（10）对应设置一切换单元（11），切换单元（11）将输入的扫描信号交替施加于第一扫描线（101）和第二扫描线（102）上。能够解决大尺寸面板在显示3D画面时出现的影像残留和左右眼亮度不一致的问题，进而提升3D画面的画质。

Description

一种阵列基板及液晶面板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶面板。
【背景技术】
垂直排列液晶显示屏(Vertical Alignment Thin Film Transistor Liquid Crystal Display，VA-TFT-LCD)在大视角观察时色偏现象比较严重，在大尺寸面板上更为明显。为了解决大视角的色偏问题，大尺寸面板的像素（pixel）设计普遍采用低色偏（Low color shift）的像素设计(如图一)， pixel分为主像素区和副像素区，充电时G1a和G1b依次打开，当G1a打开G1b关闭时，主像素区和副像素区同时充电，两区电压相同；其后，当G1a关闭G1b打开时，设置于副像素区的电容Cst充电，副像素区电压被拉低，不同的电位使得两个区域的液晶分子转向分布不同，从而具备改善大视角色偏的作用，其中电容Cst的电容值大小决定了副像素区的最终电位及显示亮度，直接影响Low color shift效果。
在如图1所示的低色偏的像素设计中，一个像素对应两条扫描线（gate line），为了节省成本，减少栅极驱动芯片的数量，将相邻像素的共享栅极信号也即G1b和充电栅极信号也即G2a连在一起，这样面板中驱动芯片数量得以减少。
但是，采用上述驱动方式，当大尺寸面板在开启3D功能时，一帧画面给左眼，一帧画面给右眼，当采用单帧也即1帧反转的驱动方式时(如图二) ，“L”/“R”分别为左眼/右眼信号，左眼接收到的信号全部为“+”，右眼接收到的信号全部为“—”，正负信号不可能完全相等，面板显示会出现Image Sticking(影像残留)现象。当采用双帧也即2帧反转的驱动方式时(如图三 )，面板没有Image Sticking，但是左右眼信号由于信号极性变化，左眼接收到的信号为“+” →“—”或“—”→“+”，此时低色偏功能正常，右眼接收到的信号为“+” →“+”或“—” →“—”，低色偏功能异常，画素偏亮，导致左右眼亮度不一致，画质下降。
【发明内容】
本发明的目的在于提供一种阵列基板及液晶面板，能够解决大尺寸面板在显示3D画面时出现的影像残留和左右眼亮度不一致的问题，进而提升3D画面的画质。
为实现上述目的，本发明采用的一个技术方案是：提供一种阵列基板，该阵列基板上设置有多组扫描线，每组扫描线至少包括第一扫描线和第二扫描线，每组扫描线对应设置一切换单元，切换单元将输入的扫描信号交替施加于第一扫描线和第二扫描线上；其中，切换单元包括第一开关管和第二开关管，其中第一开关管的输入端与第二开关管的输入端连接且用于接收扫描信号，第一开关管的输出端与第二开关管的输出端分别连接第一扫描线和第二扫描线，第一开关管的控制端连接第一开关控制线且用于接收第一开关控制信号，第二开关管的控制端连接第二开关控制线且用于接收第二开关控制信号，其中第一开关控制信号和第二开关控制信号设置成使得第一开关管和第二开关管交替导通；其中，阵列基板上进一步设置有按矩阵方式排布的多个像素，其中每行像素对应一组扫描线。
其中，第一开关管与第二开关管分别为薄膜晶体管。
为实现上述目的，本发明采用的另一个技术方案是：提供一种阵列基板，该阵列基板上设置有多组扫描线，每组扫描线至少包括第一扫描线和第二扫描线，每组扫描线对应设置一切换单元，切换单元将输入的扫描信号交替施加于第一扫描线和第二扫描线上。
其中，切换单元包括第一开关管和第二开关管，其中第一开关管的输入端与第二开关管的输入端连接且用于接收扫描信号，第一开关管的输出端与第二开关管的输出端分别连接第一扫描线和第二扫描线，第一开关管的控制端连接第一开关控制线且用于接收第一开关控制信号，第二开关管的控制端连接第二开关控制线且用于接收第二开关控制信号，其中第一开关控制信号和第二开关控制信号设置成使得第一开关管和第二开关管交替导通。
其中，第一开关管与第二开关管分别为薄膜晶体管。
其中，第一开关控制信号和第二开关控制信号设置成在同一扫描信号的持续时间内控制第一开关管和第二开关管交替导通，以使得同一扫描信号能够分别施加到第一扫描线和第二扫描线上。
其中，阵列基板上进一步设置有栅极驱动器以及切换控制器，其中栅极驱动器顺次向切换单元提供扫描信号，切换控制器向第一开关控制线和第二开关控制线交替提供第一开关控制信号和第二开关控制信号，以使得扫描信号沿预定方向顺次施加到多组扫描线的第一扫描线和第二扫描线。
其中，阵列基板上进一步设置有按矩阵方式排布的多个像素，其中每行像素对应一组扫描线。
其中，像素包括位于对应的一组扫描线的一侧的主像素区以及位于对应的一组扫描线的另一侧的副像素区，其中第一扫描线用于控制主像素区和副像素区获取相同的数据电压，第二扫描线用于对副像素区进行电压调整，以使得副像素区的数据电压不同于主像素区。
其中，阵列基板上进一步设置有数据线、公共电极、第一开关控制管、第二开关控制管和第三开关控制管，主像素区设置有主像素电极，副像素区设置有副像素电极，主像素电极与公共电极形成第一存储电容，副像素电极与公共电极形成第二存储电容，第一开关控制管的控制端和第二开关控制管的控制端连接第一扫描线，第一开关控制管的输入端和第二开关控制管的输入端连接数据线，第一开关控制管的输出端和第二开关控制管的输出端分别连接主像素电极和副像素电极，进而使得在第一扫描线施加有扫描信号时，数据线经第一开关控制管和第二开关控制管分别向主像素电极和副像素电极施加相同的数据电压，第三开关控制管的控制端连接第二扫描线，第三开关控制管的输入端连接副像素电极，第三开关控制管的输出端进一步与公共电极形成第三存储电容，进而使得在第二扫描线施加有扫描信号时，第二存储电容对第三存储电容进行放电。
其中，第一开关控制管、第二开关控制管和第三开关控制管分别为薄膜晶体管。
为实现上述目的，本发明采用的再一个技术方案是：提供一种液晶面板，该液晶面板包括了上述的阵列基板、与阵列基板相对设置的对向基板以及夹持于二者之间的液晶层；该阵列基板上设置有多组扫描线，每组扫描线至少包括第一扫描线和第二扫描线，每组扫描线对应设置一切换单元，切换单元将输入的扫描信号交替施加于第一扫描线和第二扫描线上。
其中，切换单元包括第一开关管和第二开关管，其中第一开关管的输入端与第二开关管的输入端连接且用于接收扫描信号，第一开关管的输出端与第二开关管的输出端分别连接第一扫描线和第二扫描线，第一开关管的控制端连接第一开关控制线且用于接收第一开关控制信号，第二开关管的控制端连接第二开关控制线且用于接收第二开关控制信号，其中第一开关控制信号和第二开关控制信号设置成使得第一开关管和第二开关管交替导通。
其中，第一开关管与第二开关管分别为薄膜晶体管。
其中，第一开关控制信号和第二开关控制信号设置成在同一扫描信号的持续时间内控制第一开关管和第二开关管交替导通，以使得同一扫描信号能够分别施加到第一扫描线和第二扫描线上。
其中，阵列基板上进一步设置有栅极驱动器以及切换控制器，其中栅极驱动器顺次向切换单元提供扫描信号，切换控制器向第一开关控制线和第二开关控制线交替提供第一开关控制信号和第二开关控制信号，以使得扫描信号沿预定方向顺次施加到多组扫描线的第一扫描线和第二扫描线。
其中，阵列基板上进一步设置有按矩阵方式排布的多个像素，其中每行像素对应一组扫描线。
其中，像素包括位于对应的一组扫描线的一侧的主像素区以及位于对应的一组扫描线的另一侧的副像素区，其中第一扫描线用于控制主像素区和副像素区获取相同的数据电压，第二扫描线用于对副像素区进行电压调整，以使得副像素区的数据电压不同于主像素区。
其中，阵列基板上进一步设置有数据线、公共电极、第一开关控制管、第二开关控制管和第三开关控制管，主像素区设置有主像素电极，副像素区设置有副像素电极，主像素电极与公共电极形成第一存储电容，副像素电极与公共电极形成第二存储电容，第一开关控制管的控制端和第二开关控制管的控制端连接第一扫描线，第一开关控制管的输入端和第二开关控制管的输入端连接数据线，第一开关控制管的输出端和第二开关控制管的输出端分别连接主像素电极和副像素电极，进而使得在第一扫描线施加有扫描信号时，数据线经第一开关控制管和第二开关控制管分别向主像素电极和副像素电极施加相同的数据电压，第三开关控制管的控制端连接第二扫描线，第三开关控制管的输入端连接副像素电极，第三开关控制管的输出端进一步与公共电极形成第三存储电容，进而使得在第二扫描线施加有扫描信号时，第二存储电容对第三存储电容进行放电。
其中，第一开关控制管、第二开关控制管和第三开关控制管分别为薄膜晶体管。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板及液晶面板设置多组扫描线，每组扫描线至少包括第一扫描线和第二扫描线，每组扫描线对应设置一切换单元，切换单元将输入的扫描信号交替施加于第一扫描线和第二扫描线上。通过上述方式，本发明能够解决大尺寸面板在显示3D画面时出现的影像残留和左右眼亮度不一致的问题，进而提升3D画面的画质。
【附图说明】
图1是现有技术的阵列基板的结构示意图；
图2是单帧反转的驱动方式的时序图；
图3是双帧反转的驱动方式的时序图；
图4是本发明实施例的液晶面板的结构示意图；
图5是图4所示的液晶面板中阵列基板的一实施例的结构示意图；
图6是图5所示的阵列基板中各像素的具体电路图；
图7是图5所示的阵列基板的工作时序图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对发明所提供的一种阵列基板及液晶面板做进一步详细描述。
图4是本发明实施例的液晶面板的结构示意图。如图4所示，液晶面板包括阵列基板1、与阵列基板1相对设置的对向基板2以及夹持于阵列基板1和对向基板2之间的液晶层3。其中，对向基板2可以为液晶面板中的彩色滤光基板。
图5是图4所示的液晶面板中阵列基板的一实施例的结构示意图。如图4所示，阵列基板1包括多组扫描线10、多个切换单元11、栅极驱动器12、切换控制器13、按矩阵方式排布的多个像素14以及多条数据线15。
其中，每组扫描线10至少包括第一扫描线101和第二扫描线102，每个切换单元11对应一组扫描线10。
其中，栅极驱动器12与各切换单元11连接，用于顺次向各切换单元11提供扫描信号Fanout。具体来说，栅极驱动器12包括多个栅极驱动芯片，每个驱动芯片提供一扫描信号Fanout。切换单元11分别与对应的第一扫描线101和第二扫描线102连接，用于将输入的扫描信号Fanout交替施加于第一扫描线101和第二扫描线102上。
具体来说，切换单元11包括第一开关管111和第二开关管112。优选地，第一开关管111和第二开关管112分别为薄膜晶体管。
其中，第一开关管111的输入端与第二开关管112的输入端连接且用于接收扫描信号Fanout，第一开关管111的输出端与第二开关管112的输出端分别连接第一扫描线101和第二扫描线102，第一开关管111的控制端连接第一开关控制线103且用于接收第一开关控制信号L1，第二开关管112的控制端连接第二开关控制线104且用于接收第二开关控制信号L2。
切换控制器13分别与第一开关控制线103和第二开关控制线104连接，用于向第一开关控制线103和第二开关控制线104交替提供第一开关控制信号L1和第二开关控制信号L2，以使得扫描信号Fanout沿预定方向顺次施加到多组扫描线10的第一扫描线101和第二扫描线102。
具体来说，第一开关控制信号L1和第二开关控制信号L2设置成使得第一开关管111和第二开关管112交替导通。优选地，第一开关控制信号L1和第二开关控制信号L2设置成在同一扫描信号Fanout的持续时间内控制第一开关管111和第二开关管112交替导通，以使得同一扫描信号Fanout能够分别施加到第一扫描线101和第二扫描线102上。
每行像素对应一组扫描线10，每列像素对应一条数据线15。具体来说，每个像素14包括位于对应的一组扫描线10的一侧的主像素区141以及位于对应的一组扫描线10的另一侧的副像素区142，其中第一扫描线101用于控制主像素区141和副像素区142获取相同的数据电压，第二扫描线102用于对副像素区142进行电压调整，以使得副像素区142的数据电压不同于主像素区141。
请一并参考图6，图6是图5所示的阵列基板中各像素的具体电路图。如图6所示，阵列基板1上进一步设置有公共电极Vcom、第一开关控制管T1、第二开关控制管T2和第三开关控制管T3。
其中，像素14包括主像素区141和副像素区142。具体来说，主像素区141设置有主像素电极1411，主像素电极1411和公共电极Vcom形成第一存储电容Cst1，副像素区142设置有副像素电极1421，副像素电极和公共电极Vcom形成第二存储电容Cst2。
第一开关控制管T1的控制端和第二开关控制管T2的控制端连接第一扫描线101，第一开关控制管T1的输入端和第二开关控制管T2的输入端连接数据线15，第一开关控制管T1的输出端和第二开关控制管T2的输出端分别连接主像素电极1411和副像素电极1421，进而使得在第一扫描线101施加有扫描信号Fanout时，数据线15经第一开关控制管T1和第二开关控制管T2分别向主像素电极1411和副像素电极1421施加相同的数据电压。第三开关控制管T3的控制端连接第二扫描线102，第三开关控制管T3的输入端连接副像素电极1421，第三开关控制管T3的输出端进一步与公共电极Vcom形成第三存储电容Cst3，进而使得在第二扫描线102施加有扫描信号Fanout时，第二存储电容Cst2对第三存储电容Cst3进行放电。
优选地，第一开关控制管T1、第二开关控制管T2和第三开关控制管T3为薄膜晶体管。
请一并参考图7，图7是图5所示的阵列基板的工作时序图。其中，该工作时序图以相邻的两行像素为例进行描述，栅极驱动器12输出至第一行像素的扫描信号Fanout记为Fanout1、栅极驱动器12输出至第二行像素的扫描信号Fanout记为Fanout2，第一行像素对应的第一扫描线101和第二扫描线12上输出的信号分别记为gate1a和gate1b，第二行像素对应的第一扫描线101和第二扫描线12上输出的信号分别记为gate2a和gate2b。
如图4所示，栅极驱动器12顺次向各切换单元11提供的扫描信号Fanout为持续两个周期的高电平信号。也就是说，在T1和T2周期，扫描信号Fanout1为高电平信号，扫描信号Fanout2为低电平信号；在T3和T4周期，扫描信号Fanout1为低电平信号，扫描信号Fanout2为高电平信号。
在T1周期内，切换控制器13输出的第一开关控制信号L1为高电平信号，第二开关控制信号L2为低电平信号，从而使得各切换单元11中的第一开关管111导通，第二开关管112截止。由于第一行像素接收的扫描信号Fanout1为高电平，进而使得第一行像素对应的第一扫描线101上的信号gate1a为高电平，另外三个信号gate1b、gate2a和gate2b均为低电平，从而实现数据线15分别向第一行像素中的主像素区141和副像素区142同时充电。
在T2周期内，切换控制器13输出的第一开关控制信号L1为低电平信号，第二开关控制信号L2为高电平信号，从而使得各切换单元11中的第一开关管111截止，第二开关管112导通。由于第一行像素接收的扫描信号Fanout1为高电平，进而使得第一行像素对应的第二扫描线102上的信号gate1b为高电平，另外三个信号gate1a、gate2a和gate2b均为低电平，从而实现拉低第一行像素中的副像素区142的电压。
在T3周期内，切换控制器13输出的第一开关控制信号L1为高电平信号，第二开关控制信号L2为低电平信号，从而使得各切换单元11中的第一开关管111导通，第二开关管112截止。由于第二行像素接收的扫描信号Fanout2为高电平，进而使得第二行像素对应的第一扫描线101上的信号gate2a为高电平，另外三个信号gate1a、gate1b和gate2b均为低电平，从而实现数据线15分别向第二行像素中的主像素区141和副像素区142同时充电。
在T4周期内，切换控制器13输出的第一开关控制信号L1为低电平信号，第二开关控制信号L2为高电平信号，从而使得各切换单元11中的第一开关管111截止，第二开关管112导通。由于第二行像素接收的扫描信号Fanout2为高电平，进而使得第二行像素对应的第二扫描线102上的信号gate2b为高电平，另外三个信号gate1a、gate2a和gate2a均为低电平，从而实现拉低第二行像素中的副像素区142的电压。
后续的每行像素依此类推，从而实现像素的逐行扫描。
与现有技术相比，本发明中的第一扫描信号也即充电栅极信号和第二扫描信号也即共享栅极信号是相互独立控制，而不是如现有技术中相邻像素的共享栅极信号和充电栅极信号是相互连接在一起的，从而也就不会出现现有技术中的影像残留和左右眼亮度不一致的问题。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板及液晶面板设置多组扫描线，每组扫描线至少包括第一扫描线和第二扫描线，每组扫描线对应设置一切换单元，切换单元将输入的扫描信号交替施加于第一扫描线和第二扫描线上。通过上述方式，本发明由于第一扫描线也即充电栅极信号和第二扫描线也即共享栅极信号相互独立控制，从而能够解决大尺寸面板在显示3D画面时出现的影像残留和左右眼亮度不一致的问题，进而提升3D画面的画质。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板上设置有多组扫描线，每组扫描线至少包括第一扫描线和第二扫描线，每组扫描线对应设置一切换单元，所述切换单元将输入的扫描信号交替施加于所述第一扫描线和所述第二扫描线上；
    其中，所述切换单元包括第一开关管和第二开关管，其中所述第一开关管的输入端与所述第二开关管的输入端连接且用于接收所述扫描信号，所述第一开关管的输出端与所述第二开关管的输出端分别连接所述第一扫描线和所述第二扫描线，所述第一开关管的控制端连接第一开关控制线且用于接收第一开关控制信号，所述第二开关管的控制端连接第二开关控制线且用于接收第二开关控制信号，其中所述第一开关控制信号和所述第二开关控制信号设置成使得所述第一开关管和所述第二开关管交替导通；
    其中，所述阵列基板上进一步设置有按矩阵方式排布的多个像素，其中每行像素对应一组所述扫描线。
  2. 根据权利要求1所述的阵列基板，其中，所述第一开关管与所述第二开关管分别为薄膜晶体管。
  3. 一种阵列基板，其中，所述阵列基板上设置有多组扫描线，每组扫描线至少包括第一扫描线和第二扫描线，每组扫描线对应设置一切换单元，所述切换单元将输入的扫描信号交替施加于所述第一扫描线和所述第二扫描线上。
  4. 根据权利要求3所述的阵列基板，其中，所述切换单元包括第一开关管和第二开关管，其中所述第一开关管的输入端与所述第二开关管的输入端连接且用于接收所述扫描信号，所述第一开关管的输出端与所述第二开关管的输出端分别连接所述第一扫描线和所述第二扫描线，所述第一开关管的控制端连接第一开关控制线且用于接收第一开关控制信号，所述第二开关管的控制端连接第二开关控制线且用于接收第二开关控制信号，其中所述第一开关控制信号和所述第二开关控制信号设置成使得所述第一开关管和所述第二开关管交替导通。
  5. 根据权利要求4所述的阵列基板，其中，所述第一开关管与所述第二开关管分别为薄膜晶体管。
  6. 根据权利要求5所述的阵列基板，其中，所述第一开关控制信号和所述第二开关控制信号设置成在同一所述扫描信号的持续时间内控制所述第一开关管和所述第二开关管交替导通，以使得同一所述扫描信号能够分别施加到所述第一扫描线和所述第二扫描线上。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板上进一步设置有栅极驱动器以及切换控制器，其中所述栅极驱动器顺次向所述切换单元提供所述扫描信号，所述切换控制器向所述第一开关控制线和所述第二开关控制线交替提供所述第一开关控制信号和所述第二开关控制信号，以使得所述扫描信号沿预定方向顺次施加到所述多组扫描线的所述第一扫描线和所述第二扫描线。
  8. 根据权利要求3所述的阵列基板，其中，所述阵列基板上进一步设置有按矩阵方式排布的多个像素，其中每行像素对应一组所述扫描线。
  9. 根据权利要求3所述的阵列基板，其中，所述像素包括位于对应的一组所述扫描线的一侧的主像素区以及位于对应的一组所述扫描线的另一侧的副像素区，其中所述第一扫描线用于控制所述主像素区和副像素区获取相同的数据电压，所述第二扫描线用于对所述副像素区进行电压调整，以使得所述副像素区的数据电压不同于所述主像素区。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板上进一步设置有数据线、公共电极、第一开关控制管、第二开关控制管和第三开关控制管，所述主像素区设置有主像素电极，所述副像素区设置有副像素电极，所述主像素电极与所述公共电极形成第一存储电容，所述副像素电极与所述公共电极形成第二存储电容，所述第一开关控制管的控制端和所述第二开关控制管的控制端连接所述第一扫描线，所述第一开关控制管的输入端和所述第二开关控制管的输入端连接所述数据线，所述第一开关控制管的输出端和所述第二开关控制管的输出端分别连接所述主像素电极和副像素电极，进而使得在所述第一扫描线施加有扫描信号时，所述数据线经所述第一开关控制管和所述第二开关控制管分别向所述主像素电极和副像素电极施加相同的数据电压，所述第三开关控制管的控制端连接所述第二扫描线，所述第三开关控制管的输入端连接所述副像素电极，所述第三开关控制管的输出端进一步与所述公共电极形成第三存储电容，进而使得在所述第二扫描线施加有扫描信号时，所述第二存储电容对所述第三存储电容进行放电。
  11. 根据权利要求10所述的阵列基板，其中，所述第一开关控制管、第二开关控制管和第三开关控制管分别为薄膜晶体管。
  12. 一种液晶面板，其中，所述液晶面板包括阵列基板、与所述阵列基板相对设置的对向基板以及夹持于二者之间的液晶层；其中，所述阵列基板上设置有多组扫描线，每组扫描线至少包括第一扫描线和第二扫描线，每组扫描线对应设置一切换单元，所述切换单元将输入的扫描信号交替施加于所述第一扫描线和所述第二扫描线上。
  13. 根据权利要求12所述的液晶面板，其中，所述切换单元包括第一开关管和第二开关管，其中所述第一开关管的输入端与所述第二开关管的输入端连接且用于接收所述扫描信号，所述第一开关管的输出端与所述第二开关管的输出端分别连接所述第一扫描线和所述第二扫描线，所述第一开关管的控制端连接第一开关控制线且用于接收第一开关控制信号，所述第二开关管的控制端连接第二开关控制线且用于接收第二开关控制信号，其中所述第一开关控制信号和所述第二开关控制信号设置成使得所述第一开关管和所述第二开关管交替导通。
  14. 根据权利要求13所述的液晶面板，其中，所述第一开关管与所述第二开关管分别为薄膜晶体管。
  15. 根据权利要求14所述的液晶面板，其中，所述第一开关控制信号和所述第二开关控制信号设置成在同一所述扫描信号的持续时间内控制所述第一开关管和所述第二开关管交替导通，以使得同一所述扫描信号能够分别施加到所述第一扫描线和所述第二扫描线上。
  16. 根据权利要求15所述的液晶面板，其中，所述阵列基板上进一步设置有栅极驱动器以及切换控制器，其中所述栅极驱动器顺次向所述切换单元提供所述扫描信号，所述切换控制器向所述第一开关控制线和所述第二开关控制线交替提供所述第一开关控制信号和所述第二开关控制信号，以使得所述扫描信号沿预定方向顺次施加到所述多组扫描线的所述第一扫描线和所述第二扫描线。
  17. 根据权利要求12所述的液晶面板，其中，所述阵列基板上进一步设置有按矩阵方式排布的多个像素，其中每行像素对应一组所述扫描线。
  18. 根据权利要求12所述的液晶面板，其中，所述像素包括位于对应的一组所述扫描线的一侧的主像素区以及位于对应的一组所述扫描线的另一侧的副像素区，其中所述第一扫描线用于控制所述主像素区和副像素区获取相同的数据电压，所述第二扫描线用于对所述副像素区进行电压调整，以使得所述副像素区的数据电压不同于所述主像素区。
  19. 根据权利要求18所述的液晶面板，其中，所述阵列基板上进一步设置有数据线、公共电极、第一开关控制管、第二开关控制管和第三开关控制管，所述主像素区设置有主像素电极，所述副像素区设置有副像素电极，所述主像素电极与所述公共电极形成第一存储电容，所述副像素电极与所述公共电极形成第二存储电容，所述第一开关控制管的控制端和所述第二开关控制管的控制端连接所述第一扫描线，所述第一开关控制管的输入端和所述第二开关控制管的输入端连接所述数据线，所述第一开关控制管的输出端和所述第二开关控制管的输出端分别连接所述主像素电极和副像素电极，进而使得在所述第一扫描线施加有扫描信号时，所述数据线经所述第一开关控制管和所述第二开关控制管分别向所述主像素电极和副像素电极施加相同的数据电压，所述第三开关控制管的控制端连接所述第二扫描线，所述第三开关控制管的输入端连接所述副像素电极，所述第三开关控制管的输出端进一步与所述公共电极形成第三存储电容，进而使得在所述第二扫描线施加有扫描信号时，所述第二存储电容对所述第三存储电容进行放电。
  20. 根据权利要求19所述的液晶面板，其中，所述第一开关控制管、第二开关控制管和第三开关控制管分别为薄膜晶体管。
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