WO2017219420A1 - 高解析度解复用器驱动电路 - Google Patents

高解析度解复用器驱动电路 Download PDF

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WO2017219420A1
WO2017219420A1 PCT/CN2016/090581 CN2016090581W WO2017219420A1 WO 2017219420 A1 WO2017219420 A1 WO 2017219420A1 CN 2016090581 W CN2016090581 W CN 2016090581W WO 2017219420 A1 WO2017219420 A1 WO 2017219420A1
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driving circuit
sub
control signal
resolution
circuit according
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PCT/CN2016/090581
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English (en)
French (fr)
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林建宏
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武汉华星光电技术有限公司
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Priority to US15/119,726 priority Critical patent/US10297214B2/en
Publication of WO2017219420A1 publication Critical patent/WO2017219420A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a high resolution demultiplexer driving circuit.
  • a plurality of array-arranged pixels are respectively included in a flat panel display device such as a liquid crystal display device (LCD) and an organic light emitting diode display device (OLED), and each pixel generally includes sub-pixels of three colors of red, green, and blue.
  • a flat panel display device such as a liquid crystal display device (LCD) and an organic light emitting diode display device (OLED)
  • each pixel generally includes sub-pixels of three colors of red, green, and blue.
  • Each sub-pixel is controlled by one gate line and one data line, the gate line is used to control the opening and closing of the sub-pixel, and the data line causes different sub-pixels to display different gray scales by applying different data voltage signals to the sub-pixels. Thereby realizing the display of the full color picture.
  • FIG. 1 it is a schematic diagram of a conventional 1 push 2 demultiplexer circuit. 1 is based on the existing RGB three primary color display panel to illustrate the 1 push 2 demultiplexer circuit, the circuit of the display panel portion is a conventional design, the row scan lines G1, G2, ... are respectively connected to the sub-pixels of the corresponding row, the data line D1, D2 ...
  • each sub-pixel is electrically connected to the corresponding scan line of the row of the sub-pixel and the data line corresponding to the column of the sub-pixel through the corresponding thin film transistor;
  • the demultiplexer circuit part includes more
  • the multiplexing module 10 includes two thin film transistors, and the gates of the two thin film transistors are electrically connected to the first shunt control signal Demux1 and the second shunt control signal Demux2, respectively.
  • the source is electrically connected to the same data signal Data1(+), that is, the voltage of the same level from the data chip (Data IC) signal, and the drains are electrically connected to a data line D1 and D3, respectively.
  • FIG. 2 is a schematic diagram of a power saving mode signal and a circuit of a conventional 1 push 2 demultiplexer circuit
  • FIG. 3 is a conventional 1 push 2 demultiplexer circuit in a power saving mode.
  • Signal map If the power saving mode is turned on, this means that two pixels (pixel) are regarded as one minimum unit (each pixel in FIG. 2 includes three sub-pixels of RGB), so the resolution in the Y direction will be halved, as shown in FIG. 2
  • the dotted box is a minimum unit, and the level of the R/G/B color is L240/L127/L30.
  • the color scale is an index standard indicating the brightness of the image.
  • the usual 8-bit color RGB space number The image is represented by 256 gradations, red, green and blue. The range of each color is [0, 255].
  • the gradations of red, green and blue in Figure 2 are 240, 127 and 30 respectively.
  • the relevant signal is as shown in FIG. 3, which illustrates G1 (Gate signal), data signals Data1 (+), Data 2 (-) and Data 3 (+), and the first shunt control signal Demux1 and The two-way control signal is Demux2.
  • an object of the present invention is to provide a high-resolution demultiplexer driving circuit that improves power saving efficiency in a power saving mode.
  • the present invention provides a high-resolution demultiplexer driving circuit, which comprises: respectively connecting row scanning lines of sub-pixels of corresponding rows, respectively connecting data lines of sub-pixels of corresponding columns, and multiple complexes
  • Each of the multiplexing modules includes two thin film transistors, and the gates of the two thin film transistors are electrically connected to the first shunt control signal and the second shunt control signal, respectively, and the source is electrically connected to the same data signal.
  • the drains are electrically connected to the data lines of the adjacent two colorimetric sub-pixel columns respectively; by controlling the polarity of each data signal, the polarity distributions of the sub-pixel columns except the head and the tail are alternately arranged in the horizontal direction according to the alternating positive and negative polarity. display.
  • the driving circuit connects and drives the RGB three primary color display panels.
  • the color gradations of the R/G/B sub-pixels are 240, 127 and 30, respectively.
  • the first shunt control signal and the second shunt control signal are different.
  • the first shunt control signal and the second shunt control signal are the same.
  • the multiplexing module is switched once during each gate signal time.
  • the multiplexing module switches twice during each gate signal time.
  • the sub-pixel columns except the head and the tail are displayed in the horizontal direction according to the polar distribution of the positive and negative alternating negative and negative.
  • the sub-pixel columns except the head and the tail are displayed in the horizontal direction in a polarity distribution in which the positive and negative are positive and negative.
  • the polarities of the data signals are distributed in a positive and negative alternating manner.
  • the invention also provides a high-resolution demultiplexer driving circuit, comprising: respectively connecting corresponding Row scan lines of the sub-pixels of the row, respectively connecting the data lines of the sub-pixels of the corresponding column, and a plurality of multiplexing modules; each multiplexing module includes two thin film transistors, and the gates of the two thin film transistors are respectively electrically Connecting the first shunt control signal and the second shunt control signal, the source is electrically connected to the same data signal, and the drain is electrically connected to the data lines of the adjacent two colorimetric sub-pixel columns respectively; by controlling the polarity of each data signal , controlling the sub-pixel columns except the head and the tail to be displayed in the horizontal direction according to the alternating polarity distribution of positive and negative negative;
  • the driving circuit connects and drives the RGB three primary color display panels
  • the polarities of the data signals are distributed in a positive and negative alternating manner.
  • the high-resolution demultiplexer driving circuit of the present invention does not need to convert voltage in the power saving mode, so that the power saving effect can be greatly saved, and the number of control signals can be further eliminated, and the number of control signals can be further reduced.
  • the frequency of the control signal further achieves the effect of power saving.
  • 1 is a schematic diagram of a conventional 1 push 2 demultiplexer circuit
  • FIG. 2 is a schematic diagram of a power saving mode signal and a circuit of a conventional 1 push 2 demultiplexer circuit
  • FIG. 3 is a driving signal diagram of a conventional 1 push 2 demultiplexer circuit in a power saving mode
  • FIG. 4 is a schematic structural diagram of a circuit of a high-resolution demultiplexer driving circuit according to a preferred embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a power saving mode signal and a circuit of the circuit structure of the preferred embodiment
  • FIG. 6 is a first driving signal diagram of the circuit structure of the preferred embodiment in a power saving mode
  • FIG. 7 is a second driving signal diagram of the circuit structure of the preferred embodiment in a power saving mode
  • FIG. 8 is a diagram showing a third driving signal of the circuit structure of the preferred embodiment in a power saving mode.
  • FIG. 4 it is a schematic diagram of a circuit structure of a high-resolution demultiplexer driving circuit according to a preferred embodiment of the present invention.
  • the preferred embodiment of the high-resolution demultiplexer driving circuit mainly includes: row scanning lines G1, G2, . . . respectively connected to the sub-pixels of the corresponding row, respectively connecting the data lines D1, D2 of the sub-pixels of the corresponding column. And a plurality of multiplexing modules 20; each of the multiplexing modules 20 includes two thin film transistors, and the gates of the two thin film transistors are electrically connected to the first shunt control signal Demux1 and the second shunt control signal Demux2, respectively.
  • the source is electrically connected to the same data signal
  • the drain is electrically connected to the data lines of the adjacent two colorimetric sub-pixel columns, respectively, to realize the same data signal.
  • Line 1 pushes 2, and can be set to be floating when no adjacent homochromatic sub-pixel columns can be found for the drain of the multiplexing module in the head and tail position; by controlling the polarity of each data signal Data0, Data1, ..., except for the first and last
  • the sub-pixel columns are displayed in the horizontal direction in a polarity distribution in which the positive and negative are alternated.
  • the display panel formed by the sub-pixel array may be an existing RGB three-primary color display panel, and the circuit of the display panel portion may be a conventional design.
  • the voltage of the same level of the Data IC signal is distributed to the two data lines of the same color adjacent to the display area through the two TFT element switches, and the horizontal direction is ++ ⁇
  • the present invention is in the power saving mode (half the resolution in the Y direction) because the signal demand signals of the same color are Consistent, so you can use the same set of IC signal voltage control, the voltage does not need to be transformed to achieve power saving purposes.
  • FIG. 5 it is a schematic diagram of a power saving mode signal and a circuit of the circuit structure of the preferred embodiment.
  • FIG. 4 it can be found that two adjacent concentric pixels are provided by the same set of IC signals (Data1 ⁇ Data4), so in the power saving mode (the Y direction resolution is halved), as shown in FIG. Shown as a minimum unit, and the color scale of the R/G/B color is L240/L127/L30.
  • FIG. 6 there is shown a first drive signal diagram of the circuit structure of the preferred embodiment in a power saving mode. It can be found that the data signal does not need to change the voltage, and the demultiplexer is in a non-shared manner, consisting of Demux 1 and Demux 2.
  • FIG. 7 there is shown a second drive signal diagram of the circuit structure of the preferred embodiment in a power saving mode.
  • Demux1 is shared with Demux2, which is the same signal, but it is switched twice during each Gate time.
  • FIG. 8 there is shown a third drive signal diagram of the circuit structure of the preferred embodiment in a power saving mode.
  • Demux1 is shared with Demux2 and is also the same signal, but it is only switched once during each Gate time.
  • the new design of the high-resolution demultiplexer driving circuit of the invention has a large power saving benefit in the power saving mode (the Y-direction resolution is halved), and the data signal does not need to be converted.
  • the number of control signals provided by the demultiplexer provided by the IC can be omitted, and FIG. 8 can further reduce the frequency of the demultiplexer control signal, and further achieve the effect of power saving.
  • the high-resolution demultiplexer driving circuit of the present invention does not need to convert voltage in the power saving mode, so that the power saving effect can be greatly saved, and the number of control signals can be further eliminated, and the number of control signals can be further reduced.
  • the frequency of the control signal further achieves the effect of power saving.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种高解析度解复用器驱动电路，该高解析度解复用器驱动电路包括：分别连接对应行的子像素的行扫描线（G1、G2……），分别连接对应列的子像素的数据线（D1、D2……），以及多个复用模块（20）；每个复用模块（20）包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别电性连接第一分路控制信号（Demux1）和第二分路控制信号（Demux2），源极均电性连接同一数据信号（Data0、Data1……），漏极分别电性连接临近的两同色子像素列的数据线（D1、D2……）；通过控制各数据信号（Data0、Data1……）的极性，控制除首尾的各子像素列在水平方向按照正正与负负交替的极性分布进行显示。该高解析度解复用器驱动电路在省电模式下数据信号（Data0、Data1……）不需变换电压，因此可以有很大的省电效益，进一步可以省去控制信号数目，更可以降低控制信号的频率，更进一步达到省电的效果。

Description

高解析度解复用器驱动电路 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种高解析度解复用器驱动电路。
背景技术
在液晶显示装置(LCD)与有机发光二极管显示装置(OLED)等平板显示装置中均包括多个阵列式排布的像素，每个像素通常包括红、绿、蓝三种颜色的子像素，每个子像素均受控于一条栅极线与一条数据线，栅极线用于控制子像素的开启和关闭，数据线通过向子像素施加不同的数据电压信号，使子像素显示不同的灰阶，从而实现全彩画面的显示。
近年来针对高PPI(每英寸像素数)面板上的开发越来越火热，当面板设计为越高的解析度上时相对因为负载变重及频率升高，因此会耗损更多的电力(Power)，而其中占很大的能量耗损会来自于解复用器(Demux)的设计，而当设计为越高解析度时，其解复用器因为充电时间变很短因此会由1推多变成1推2的方式，例如在小尺寸面板，解析度达4K以上时，就可能会用到1推2的解复用器设计，而由于PPI够高所以可以开启一些省电模式，可将Y方向信号线的解析度减半，来降低电力的损耗。
参见图1，其为现有的1推2的解复用器电路示意图。图1基于现有RGB三基色显示面板来说明1推2解复用器电路，显示面板部分的电路为常规设计，行扫描线G1，G2……分别连接对应行的子像素，数据线D1，D2……分别连接对应列的子像素，每一子像素通过相应薄膜晶体管电性连接该子像素所在行对应的扫描线和该子像素所在列对应的数据线；解复用器电路部分包括多个复用模块，以复用模块10为例，复用模块10包括两个薄膜晶体管，该两个薄膜晶体管的栅极分别电性连接第一分路控制信号Demux1和第二分路控制信号Demux2，源极均电性连接同一数据信号Data1(+)，也就是来自数据芯片(Data IC)信号的同一级性的电压，漏极分别电性连接一数据线D1和D3。
参见图2及图3，图2为现有1推2的解复用器电路的省电模式信号及电路示意图，图3为现有1推2的解复用器电路省电模式下的驱动信号图。若开启省电模式，此指将两个像素(pixel)当成一个最小单元(图2中每个像素包括RGB三个子像素)，因此在Y方向的解析度将减半，如图2两 虚线方框为一个最小单元，并点R/G/B各色的色阶(Level)为L240/L127/L30，色阶是表示图像亮度强弱的指数标准，通常的8位色的RGB空间数字图像，分别用256个阶度表示红绿蓝，每个颜色的取值范围都是[0，255]，图2中红绿蓝各色的色阶分别为240，127及30。此时相关信号如图3所示，图示了G1(Gate signal，栅极信号)，数据信号Data1(+)，Data2(-)及Data3(+)，以及第一分路控制信号Demux1和第二分路控制信号Demux2。虽然邻近的同色(以两个pixel为最小单位)其色阶一样，但数据(Data)的信号仍需要有压差的变化，仍会有很大的电力损耗。
发明内容
因此，本发明的目的在于提供一种高解析度解复用器驱动电路，提升省电模式下的省电效益。
为实现上述目的，本发明提供了一种高解析度解复用器驱动电路，包括：分别连接对应行的子像素的行扫描线，分别连接对应列的子像素的数据线，以及多个复用模块；每个复用模块包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别电性连接第一分路控制信号和第二分路控制信号，源极均电性连接同一数据信号，漏极分别电性连接临近的两同色子像素列的数据线；通过控制各数据信号的极性，控制除首尾的各子像素列在水平方向按照正正与负负交替的极性分布进行显示。
其中，该驱动电路连接并驱动RGB三基色显示面板。
其中，当该驱动电路工作于省电模式下时，R/G/B子像素各色的色阶分别为240，127及30。
其中，当该驱动电路工作于省电模式下时，第一分路控制信号和第二分路控制信号不同。
其中，当该驱动电路工作于省电模式下时，第一分路控制信号和第二分路控制信号相同。
其中，每个栅极信号时间内，所述复用模块开关一次。
其中，每个栅极信号时间内，所述复用模块开关两次。
其中，除首尾的所述各子像素列在水平方向按照先正正后负负交替的极性分布进行显示。
其中，除首尾的所述各子像素列在水平方向按照先负负后正正交替的极性分布进行显示。
其中，所述各数据信号的极性按照正负交替的方式分布。
本发明还提供一种高解析度解复用器驱动电路，包括：分别连接对应 行的子像素的行扫描线，分别连接对应列的子像素的数据线，以及多个复用模块；每个复用模块包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别电性连接第一分路控制信号和第二分路控制信号，源极均电性连接同一数据信号，漏极分别电性连接临近的两同色子像素列的数据线；通过控制各数据信号的极性，控制除首尾的各子像素列在水平方向按照正正与负负交替的极性分布进行显示；
其中，该驱动电路连接并驱动RGB三基色显示面板；
其中，所述各数据信号的极性按照正负交替的方式分布。
综上所述，本发明的高解析度解复用器驱动电路在省电模式下数据信号不需变换电压，因此可以有很大的省电效益，进一步可以省去控制信号数目，更可以降低控制信号的频率，更进一步达到省电的效果。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的1推2的解复用器电路示意图；
图2为现有1推2的解复用器电路的省电模式信号及电路示意图；
图3为现有1推2的解复用器电路省电模式下的驱动信号图；
图4为本发明高解析度解复用器驱动电路一较佳实施例的电路结构示意图；
图5为该较佳实施例的电路结构的省电模式信号及电路示意图；
图6为该较佳实施例的电路结构在省电模式下的第一驱动信号图；
图7为该较佳实施例的电路结构在省电模式下的第二驱动信号图；
图8为该较佳实施例的电路结构在省电模式下的第三驱动信号图。
具体实施方式
参见图4，其为本发明高解析度解复用器驱动电路一较佳实施例的电路结构示意图。该高解析度解复用器驱动电路的较佳实施例主要包括：分别连接对应行的子像素的行扫描线G1，G2……，分别连接对应列的子像素的数据线D1，D2……，以及多个复用模块20；每个复用模块20包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别电性连接第一分路控制信号Demux1和第二分路控制信号Demux2，源极均电性连接同一数据信号，漏极分别电性连接临近的两同色子像素列的数据线，实现由同一数据信号进 行1推2，对于处于首尾位置的复用模块的漏极找不到临近的同色子像素列时可以设置为悬空；通过控制各数据信号Data0，Data1……的极性，控制除首尾的各子像素列在水平方向按照正正与负负交替的极性分布进行显示。子像素阵列所构成的显示面板可以为现有RGB三基色显示面板，显示面板部分的电路可以为常规设计。
本发明在1推2的解复用器设计中，Data IC信号同一级性的电压透过两个TFT元件开关分给显示区邻近的两个同色的数据线，并形成水平方向为++――++――……的极性显示方式，并在频率减半显示情况下，其中两组解复用器可为同一个信号，可变成共用，或为分开不同的信号。利用新的解复用器排列方式，将同色且邻近的两个信号线由同一组IC信号来控制，本发明在省电模式下(Y方向解析度减半)，因为同色的信号需求信号是一致的，因此可以用同一组IC信号电压控制，电压不需要做变换，达到省电的目的。
参见图5，其为该较佳实施例的电路结构的省电模式信号及电路示意图。结合图4，可发现其中有两个邻近的同色画素是由同一组IC信号提供(Data1～Data4)，因此在省电模式下(Y方向解析度减半)，如图5中两虚线方框所示为一个最小单元，并点R/G/B各色的色阶为L240/L127/L30。
参见图6，其为该较佳实施例的电路结构在省电模式下的第一驱动信号图。可发现数据信号不需要改变电压，其中解复用器为非共用方式，由Demux 1 and Demux 2组成。
参见图7，其为该较佳实施例的电路结构在省电模式下的第二驱动信号图。图7中Demux1与Demux2共用，为同样的信号，但每个Gate时间内，还是开关两次。
参见图8，其为该较佳实施例的电路结构在省电模式下的第三驱动信号图。图8中Demux1与Demux2共用，也为同样信号，但其每个Gate时间内，只开关一次。
本发明高解析度解复用器驱动电路的新的设计，在省电模式下(Y方向解析度减半)，其Data信号不需变换电压，因此可以有很大的省电效益，而在图7和图8中可以省去IC所提供解复用器的控制信号数目，而且图8更可以降低解复用器控制信号的频率，更进一步达到省电的效果。
综上所述，本发明的高解析度解复用器驱动电路在省电模式下数据信号不需变换电压，因此可以有很大的省电效益，进一步可以省去控制信号数目，更可以降低控制信号的频率，更进一步达到省电的效果。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (18)

  1. 一种高解析度解复用器驱动电路，包括：分别连接对应行的子像素的行扫描线，分别连接对应列的子像素的数据线，以及多个复用模块；每个复用模块包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别电性连接第一分路控制信号和第二分路控制信号，源极均电性连接同一数据信号，漏极分别电性连接临近的两同色子像素列的数据线；通过控制各数据信号的极性，控制除首尾的各子像素列在水平方向按照正正与负负交替的极性分布进行显示。
  2. 如权利要求1所述的高解析度解复用器驱动电路，其中，该驱动电路连接并驱动RGB三基色显示面板。
  3. 如权利要求2所述的高解析度解复用器驱动电路，其中，当该驱动电路工作于省电模式下时，R/G/B子像素各色的色阶分别为240，127及30。
  4. 如权利要求1所述的高解析度解复用器驱动电路，其中，当该驱动电路工作于省电模式下时，第一分路控制信号和第二分路控制信号不同。
  5. 如权利要求1所述的高解析度解复用器驱动电路，其中，当该驱动电路工作于省电模式下时，第一分路控制信号和第二分路控制信号相同。
  6. 如权利要求5所述的高解析度解复用器驱动电路，其中，每个栅极信号时间内，所述复用模块开关一次。
  7. 如权利要求5所述的高解析度解复用器驱动电路，其中，每个栅极信号时间内，所述复用模块开关两次。
  8. 如权利要求1所述的高解析度解复用器驱动电路，其中，除首尾的所述各子像素列在水平方向按照先正正后负负交替的极性分布进行显示。
  9. 如权利要求1所述的高解析度解复用器驱动电路，其中，除首尾的所述各子像素列在水平方向按照先负负后正正交替的极性分布进行显示。
  10. 如权利要求1所述的高解析度解复用器驱动电路，其中，所述各数据信号的极性按照正负交替的方式分布。
  11. 一种高解析度解复用器驱动电路，包括：分别连接对应行的子像素的行扫描线，分别连接对应列的子像素的数据线，以及多个复用模块；每个复用模块包括两个薄膜晶体管，所述两个薄膜晶体管的栅极分别电性连接第一分路控制信号和第二分路控制信号，源极均电性连接同一数据信号，漏极分别电性连接临近的两同色子像素列的数据线；通过控制各数据信号的极性，控制除首尾的各子像素列在水平方向按照正正与负负交替的 极性分布进行显示；
    其中，该驱动电路连接并驱动RGB三基色显示面板；
    其中，所述各数据信号的极性按照正负交替的方式分布。
  12. 如权利要求11所述的高解析度解复用器驱动电路，其中，当该驱动电路工作于省电模式下时，R/G/B子像素各色的色阶分别为240，127及30。
  13. 如权利要求11所述的高解析度解复用器驱动电路，其中，当该驱动电路工作于省电模式下时，第一分路控制信号和第二分路控制信号不同。
  14. 如权利要求11所述的高解析度解复用器驱动电路，其中，当该驱动电路工作于省电模式下时，第一分路控制信号和第二分路控制信号相同。
  15. 如权利要求14所述的高解析度解复用器驱动电路，其中，每个栅极信号时间内，所述复用模块开关一次。
  16. 如权利要求14所述的高解析度解复用器驱动电路，其中，每个栅极信号时间内，所述复用模块开关两次。
  17. 如权利要求11所述的高解析度解复用器驱动电路，其中，除首尾的所述各子像素列在水平方向按照先正正后负负交替的极性分布进行显示。
  18. 如权利要求11所述的高解析度解复用器驱动电路，其中，除首尾的所述各子像素列在水平方向按照先负负后正正交替的极性分布进行显示。
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10311773B2 (en) * 2013-07-26 2019-06-04 Darwin Hu Circuitry for increasing perceived display resolutions from an input image
CN106298851B (zh) * 2016-08-12 2018-06-29 京东方科技集团股份有限公司 一种像素结构、显示面板及其驱动方法
CN206194295U (zh) * 2016-11-15 2017-05-24 京东方科技集团股份有限公司 数据线多路分配器、显示基板、显示面板及显示装置
CN107610658B (zh) * 2017-08-23 2020-06-26 惠科股份有限公司 显示装置的驱动装置及驱动方法
US10797125B2 (en) * 2017-08-30 2020-10-06 Apple Inc. Electronic device having display circuitry with rounded corners
CN108766373B (zh) * 2018-05-08 2020-11-24 昆山龙腾光电股份有限公司 一种检测电路和液晶显示装置
US12099912B2 (en) 2018-06-22 2024-09-24 Samsung Electronics Co., Ltd. Neural processor
US10964235B1 (en) * 2018-06-25 2021-03-30 Apple Inc. Electronic devices with narrow border displays
CN108803174B (zh) * 2018-07-03 2022-04-01 京东方科技集团股份有限公司 一种阵列基板、显示面板及其驱动方法、显示装置
CN108831402B (zh) * 2018-08-24 2021-04-16 南京中电熊猫液晶显示科技有限公司 显示装置及其驱动方法和电压调整方法
CN109637414B (zh) * 2018-12-28 2022-07-22 厦门天马微电子有限公司 一种显示面板驱动电路及其驱动方法、显示装置
CN109584778B (zh) * 2019-01-29 2022-04-26 鄂尔多斯市源盛光电有限责任公司 显示模组、显示装置及该显示模组的驱动方法
WO2020206589A1 (zh) * 2019-04-08 2020-10-15 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
US11671111B2 (en) * 2019-04-17 2023-06-06 Samsung Electronics Co., Ltd. Hardware channel-parallel data compression/decompression
JPWO2020229917A1 (zh) * 2019-05-10 2020-11-19
CN110264970A (zh) * 2019-06-14 2019-09-20 武汉华星光电技术有限公司 显示面板
US11189241B2 (en) * 2020-03-27 2021-11-30 Tcl China Star Optoelectronics Technology Co., Ltd Method for charging pixels and display panel
US11778874B2 (en) 2020-03-30 2023-10-03 Apple Inc. Reducing border width around a hole in display active area
CN111968588B (zh) * 2020-07-31 2022-05-03 南京京东方显示技术有限公司 一种多路复用显示面板
TWI729907B (zh) * 2020-08-14 2021-06-01 凌巨科技股份有限公司 顯示器以及用於顯示器的多工器
CN114743493B (zh) * 2022-04-02 2023-06-30 武汉天马微电子有限公司 一种显示面板和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655219A (zh) * 2003-12-17 2005-08-17 三星电子株式会社 共享缓冲器的显示板的驱动方法和系统
CN1702724A (zh) * 2004-05-25 2005-11-30 三星Sdi株式会社 显示设备和多路分解器
US20140015821A1 (en) * 2012-07-12 2014-01-16 Samsung Display Co., Ltd. Method of driving a display panel and display panel driving apparatus for performing the method
KR20140109697A (ko) * 2013-03-06 2014-09-16 엘지디스플레이 주식회사 액정표시장치
CN104700794A (zh) * 2013-12-05 2015-06-10 群创光电股份有限公司 用于双列反转架构的具有1:2多任务的驱动装置
CN105469765A (zh) * 2016-01-04 2016-04-06 武汉华星光电技术有限公司 多路复用型显示驱动电路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8988334B2 (en) * 2010-11-08 2015-03-24 Apple Inc. Column inversion techniques for improved transmittance
KR102034236B1 (ko) * 2013-01-17 2019-10-21 삼성디스플레이 주식회사 유기전계발광 표시장치
KR102350392B1 (ko) * 2015-04-30 2022-01-17 엘지디스플레이 주식회사 표시장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655219A (zh) * 2003-12-17 2005-08-17 三星电子株式会社 共享缓冲器的显示板的驱动方法和系统
CN1702724A (zh) * 2004-05-25 2005-11-30 三星Sdi株式会社 显示设备和多路分解器
US20140015821A1 (en) * 2012-07-12 2014-01-16 Samsung Display Co., Ltd. Method of driving a display panel and display panel driving apparatus for performing the method
KR20140109697A (ko) * 2013-03-06 2014-09-16 엘지디스플레이 주식회사 액정표시장치
CN104700794A (zh) * 2013-12-05 2015-06-10 群创光电股份有限公司 用于双列反转架构的具有1:2多任务的驱动装置
CN105469765A (zh) * 2016-01-04 2016-04-06 武汉华星光电技术有限公司 多路复用型显示驱动电路

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