WO2017211061A1 - 一种芯片及获取芯片调试数据的方法 - Google Patents

一种芯片及获取芯片调试数据的方法 Download PDF

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Publication number
WO2017211061A1
WO2017211061A1 PCT/CN2016/110086 CN2016110086W WO2017211061A1 WO 2017211061 A1 WO2017211061 A1 WO 2017211061A1 CN 2016110086 W CN2016110086 W CN 2016110086W WO 2017211061 A1 WO2017211061 A1 WO 2017211061A1
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chip
ddr
control module
module
control
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PCT/CN2016/110086
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English (en)
French (fr)
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洪思华
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深圳市中兴微电子技术有限公司
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Publication of WO2017211061A1 publication Critical patent/WO2017211061A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing

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  • the invention relates to a chip debugging technology, in particular to a chip and a method for acquiring chip debugging data.
  • the technician In the process of using the chip, it often encounters an abnormality or a crash. At this time, the technician needs to analyze the problem of the chip that has an abnormality or a crash, find out the cause of the abnormality or crash, and carry out subsequent optimization and adjustment design. And take the corresponding exception or crash avoidance scheme.
  • the technician adds the memory cells for debugging inside the chip, and observes the memory cells through the input/output (IO, Input/Output) interface to obtain debug data.
  • IO Input/Output
  • adding additional memory cells inside the chip requires additional cost, and the memory cell capacity within the chip is too small, and the debug data collected is limited.
  • the technician sets up additional flash memory (Flash) outside the chip to collect the debug data.
  • Flash flash memory
  • the working state data of the chip is stored on the externally set Flash. Since the storage space of the Flash is larger than the storage space in the chip, the data collection amount of the debug data of the mobile phone after the abnormality of the chip or the crash is increased.
  • Flash is usually used to store fixed programs, if you want to store debugging data, you need to increase the storage space, which increases the cost; Accessing debugging information in the process requires consumption of the bandwidth of the Flash interface and the bus bandwidth inside the chip, which affects the performance of the chip.
  • the embodiment of the present invention is expected to provide a chip and a method for acquiring chip debugging data, which can acquire a large amount of debugging data at a low cost and without affecting the working performance of the chip.
  • an embodiment of the present invention provides a method for acquiring chip debug data, where the method is applied to a chip, and the chip is connected to an external double rate synchronous dynamic random access memory DDR memory unit, where the chip includes: a chip master control module, an IO control module, an access command recording module, a DDR control and interface module, and a DDR training parameter saving module; the method includes:
  • the chip master control module determines that the chip is in a dead state, triggering the IO control module to control the DDR memory unit to perform self-refresh by forcibly changing an IO level state of the DDR memory unit;
  • the chip master control module controls the chip to reset according to a preset reset sequence according to the reset request command received by the IO control module;
  • the DDR control and interface module configures an access channel of the DDR storage unit according to the training parameters pre-stored in the DDR training parameter saving module, and sends a stop self-refresh to the IO control module after the configuration is completed.
  • Control instruction ;
  • the chip master control module calls the DDR control and interface module from the main data channel of the chip according to a preset debugging strategy, and triggers the DDR control and the interface module to access the DDR storage unit through the IO control module to obtain storage. Field data within the DDR memory unit.
  • the triggering the IO control module controls the DDR storage unit to perform self-refresh by forcibly changing an IO level state of the DDR storage unit;
  • the chip master control module When the chip master control module confirms that the chip is in a dead state, the chip master control module Transmitting, to the IO control module, a mode control instruction, the IO control module enters a data hold mode after receiving the mode control instruction, and forcibly changes a level state of an IO interface of the DDR storage unit, triggering the DDR The storage unit enters a self-refresh mode;
  • the IO control module forcibly changes the level of the IO interface of the DDR memory unit when the IO control module does not receive the data refresh instruction transmitted by the chip to the DDR memory unit within a preset period of time a state that triggers the DDR memory unit to enter a self-refresh mode.
  • the chip master control module controls the chip to reset according to the preset reset sequence according to the reset request command received by the IO control module, including:
  • the IO control module receives a reset request command, and transmits the reset request command to the chip master control module;
  • the chip master control module controls the chip to be reset according to the preset reset sequence according to the reset request command; wherein the preset reset sequence is used to indicate that the chip master control module follows the chip internal common
  • the system, the system bus, the DDR control and interface module, and the IO control module are sequentially reset in sequence.
  • the chip master control module calls the DDR control and interface module from the main data channel of the chip according to a preset debugging strategy, and triggers the DDR control and the interface module to access the DDR through the IO control module.
  • the storage unit acquires the field data stored in the DDR storage unit, including:
  • the chip master control module enters a debugging state according to its internal state and information of the IO control module;
  • the interface module accesses the DDR storage unit through the IO control module to acquire field data stored in the DDR storage unit.
  • the method further includes: when the chip is in a normal working state, the DDR control and interface module trains the DDR access channel, and pre-stores the training parameter in the normal working state of the chip. DDR training parameters are saved in the module;
  • the access command recording module is configured to monitor a DDR access command of the DDR control and interface module.
  • an embodiment of the present invention provides a chip, where the chip includes: a chip total control module, an IO control module, an access command recording module, a DDR control and interface module, and a DDR training parameter saving module;
  • the chip master control module is configured to trigger the IO control module when the chip is in a dead state
  • the IO control module is configured to control the DDR memory unit to perform self-refresh by forcibly changing an IO level state of the DDR memory unit according to a trigger of the chip master control module;
  • the chip master control module is further configured to control the chip to be reset according to a preset reset sequence according to the reset request command received by the IO control module;
  • the DDR control and interface module is configured to configure an access channel of the DDR storage unit according to the training parameter pre-stored in the DDR training parameter saving module, and send a stop self-refresh to the IO control module after the configuration is completed. Control instruction;
  • the chip master control module is further configured to invoke the DDR control and interface module from a master data channel of the chip according to a preset debugging policy, and trigger the DDR control and the interface module to access the DDR memory through the IO control module. a unit that acquires field data stored in the DDR storage unit.
  • the chip master control module is configured to send a mode control instruction to the IO control module
  • the IO control module is configured to enter a data hold mode after receiving the mode control instruction, and forcibly change a level state of the IO interface of the DDR memory unit, triggering the DDR memory unit to enter a self-refresh mode;
  • the IO control module is configured to forcibly change the IO interface of the DDR storage unit when the data refresh instruction transmitted by the chip to the DDR storage unit is not received within a preset time period.
  • the level state triggers the DDR memory unit to enter a self-refresh mode.
  • the IO control module is configured to receive a reset request command, and transmit the reset request command to the chip master control module;
  • the chip master control module is configured to control the chip to be reset according to the preset reset sequence according to the reset request command; wherein the preset reset sequence is configured to instruct the chip master control module to follow the chip
  • the internal general subsystem, the system bus, the DDR control and interface module, and the IO control module are sequentially reset in sequence.
  • the chip master control module is configured to enter a debugging state according to the internal state of the chip and the information of the IO control module;
  • the DDR control and interface module is configured to train the DDR access channel when the chip is in a normal working state, and pre-store the training parameters in the normal working state of the chip in the DDR training parameter. Save the module;
  • the access command recording module is configured to monitor a DDR access command of the DDR control and interface module in a normal working state of the chip.
  • the embodiment of the invention provides a chip and a method for acquiring chip debugging data.
  • the IO control module is additionally disposed inside the chip, and is configured to monitor the IO of the chip to access the DDR storage unit outside the chip.
  • the IO control module can force the DDR memory cell to self-refresh by transmitting a refresh command to a DDR memory cell external to the chip, or by initiating a self-refresh mode of the DDR memory cell, or forcibly changing the IO level state.
  • FIG. 1 is a schematic flowchart of a method for acquiring chip debugging data according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a chip according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a reset process according to an embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of acquiring field data according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another chip according to an embodiment of the present invention.
  • a Double Rate Synchronous Dynamic Random Access Memory (DDR) storage unit can store a large amount of live information (in gigabit GB) of live information and data, but DDR is non-permanent storage.
  • the storage device whose data retention life is usually on the order of milliseconds. Therefore, in the embodiment of the present invention, an IO control module is additionally disposed inside the chip, and is configured to monitor the IO that the chip accesses the DDR storage unit outside the chip. The IO control module can transmit a refresh command to a DDR memory unit external to the chip.
  • the method can be applied to the chip 20 connected to an external DDR memory unit as shown in FIG. 2 .
  • the chip 20 structure may include: a chip master control module 201, an IO control module 202, an access command recording module 203, a DDR control and interface module 204, and a DDR training parameter saving module 205; the method may include:
  • the trigger IO control module 202 controls the DDR memory unit to perform self-refresh by forcibly changing the IO level state of the DDR memory unit;
  • the watchdog counter is internally set in the chip master control module 201.
  • the watchdog counter starts counting and performs the dog feeding operation; when the watchdog counter exceeds the pre-preview
  • the chip master control module 201 can confirm that the chip 20 is in a dead state.
  • the trigger IO control module 202 controls the DDR storage unit to perform self-refresh by forcibly changing the IO level state of the DDR storage unit, and may include:
  • the chip master control module 201 When the chip master control module 201 confirms that the chip 20 is in a dead state, the chip master control module 201 can send a mode control instruction to the IO control module 202; the IO control module 202 enters the data hold mode after receiving the instruction, and forcibly changes the DDR memory unit.
  • the level state of the IO interface triggers the DDR memory cell to enter the self-refresh mode.
  • the trigger IO control module 202 controls the DDR storage unit to perform self-refresh by forcibly changing the IO level state of the DDR storage unit, and may include:
  • the IO control module 202 When the IO control module 202 does not receive the chip 20 to the DDR memory list within a preset period of time, the IO control module 202 forcibly changes the level state of the IO interface of the DDR memory unit, and triggers the DDR memory unit to enter the self-refresh mode.
  • the DDR memory unit can perform the self-refresh mode according to the level state of the IO interface forced to be changed by the IO control module 202, thereby saving the field data saved by the DDR memory unit itself for describing the running state of the chip.
  • the chip master control module 201 controls the chip 20 to perform reset according to the preset reset sequence according to the reset request command received by the IO control module 202.
  • step S102 may specifically include steps S1021 and S1022:
  • IO control module 202 receives a reset request command, and transmits the reset request command to the chip master control module 201;
  • the chip master control module 201 controls the chip 20 to perform reset according to the preset reset sequence according to the reset request command.
  • the preset reset sequence is used to instruct the chip master control module 201 to reset according to the order of the internal common subsystem of the chip 20, the system bus, the DDR control and interface module 204, and the IO control module 202.
  • the chip master control module 201 controls the chip 20 to perform reset according to a preset reset sequence, which may include:
  • the chip master control module 201 can sequentially send a reset command to the internal common subsystem of the chip 20, the system bus, the DDR control and interface module 204, and the IO control module 202; the internal subsystem of the trigger chip 20, the system bus, the DDR control and the interface module 204 And the IO control module 202 resets in the order in which the reset command is received.
  • the chip 20 crash is likely to cause the access channel of the chip 20 and the DDR memory unit to hang, so that a chip reset is required at this time.
  • the reset process takes a certain amount of time to execute, and many system reset times are also in milliseconds, or at the second level. Therefore, data of the DDR memory cell may be lost during reset.
  • the chip 20 needs Sequence planning for resetting, since the IO control module 202 does not perform the service in the main reset sequence, but has separate service control, in the embodiment of the present invention, it is preferable to perform the IO after the main reset of the chip 20 is completed.
  • the reset of control module 202 Therefore, the reset of the IO control module 202 is placed at the end of the reset sequence. This ensures that the field data information held in the DDR memory unit is not corrupted during the reset phase.
  • the DDR control and interface module 204 configures an access channel of the DDR storage unit according to the training parameters pre-stored in the DDR training parameter saving module 205 after resetting, and sends a stop self-refresh control command to the IO control module 202 after the configuration is completed;
  • the stop self-refresh control command is used to instruct the IO control module 202 to control the DDR memory unit to stop the self-refresh.
  • the DDR memory unit stops self-refresh at this time it can enter the acquisition phase of the debug data, namely:
  • the chip master control module 201 calls the DDR control and interface module 204 from the main data channel of the chip 20 according to a preset debugging strategy to access the DDR memory unit through the IO control module 202, and obtains the field data stored in the DDR memory unit;
  • step S104 may include S1041 to S1043:
  • the chip master control module 201 enters a debugging state according to its internal state and information of the IO control module 202.
  • the IO control module 202 after receiving the stop self-refresh control command transmitted by the DDR control and interface module 204, the IO control module 202 notifies the chip master control module 201; at this time, the chip master control module 201 can be based on its internal state and The information of the IO control module 202 performs state determination; subsequently, the IO control module 202 notifies the outside of the chip 20, and can enter the interactive debugging phase.
  • S1042 The data information of the IO control module 202, the chip master control module 201, the DDR training parameter saving module 205, and the access command recording module 203 are passed through the IO control module 202 to the core.
  • the external output of the slice 20 is obtained, and a preliminary debugging scheme is obtained;
  • step S1042 since the IO control module 202 is configured to perform IO of data with the outside of the chip 20, the external debugger acquires the IO control module 202, the chip master control module 201, the DDR training parameter saving module 205, and The internal data information of the access command recording module 203 must be acquired by the IO control module 202; and the internal data information of the DDR training parameter saving module 205 and the access command recording module 203 need to be collected by the chip master control module 201 after the chip is collected.
  • the IO control module 202 can be externally outputted; therefore, the external debugger obtains the internal data information of the IO control module 202, the chip master control module 201, the DDR training parameter saving module 205, and the access command recording module 203 through the IO control module 202.
  • the initial debugging scheme can be formed by combining the contents of the chip manual.
  • S1043 Calling the DDR control and interface module 204 from the main data channel of the chip 20 according to the initial debugging scheme, accessing the DDR storage unit through the IO control module 202, and acquiring the field data stored in the DDR storage unit.
  • step S1043 the process of acquiring the chip debug data from the DDR memory unit is realized.
  • the embodiment may further include:
  • the DDR control and interface module 204 trains the DDR access channel, and pre-stores the training parameters of the chip 20 in the normal working state in the DDR training parameter saving module 205. It can be understood that since the correct training parameters in the normal working state of the chip 20 are maintained and directly assigned to the DDR control and interface module 204 after resetting, And shortened the training time.
  • the access command recording module 203 is configured to monitor the DDR access command of the DDR control and interface module 204.
  • the access command may include: accessing the user identifier, the type of the read and write operation, and the operation start. Access information such as address and operation data length. These access information are key control information for the chip 20 at work.
  • the embodiment provides a method for acquiring chip debugging data, and an IO control module is additionally disposed inside the chip, and is configured to monitor the IO that the chip accesses the DDR storage unit outside the chip.
  • the IO control module can ensure that the chip is abnormal or by transmitting a refresh command to the DDR memory unit external to the chip, or by starting the self-refresh mode of the DDR memory cell, or forcibly changing the IO level state, forcing the DDR memory cell to self-refresh.
  • the data in the DDR memory unit can be effectively saved, and a large amount of debug data can be obtained at a low cost and without affecting the performance of the chip.
  • the chip 50 may include a chip master control module 501, an IO control module 502, and an access command recording module 503. , DDR control and interface module 504 and DDR training parameter saving module 505; wherein
  • the chip master control module 501 is configured to trigger the IO control module 502 when the chip is in a dead state;
  • the IO control module 502 is configured to control the DDR memory unit to perform self-refresh by forcibly changing an IO level state of the DDR memory unit according to a trigger of the chip master control module 501;
  • the chip master control module 501 is further configured to control the chip to be reset according to a preset reset sequence according to the reset request command received by the IO control module 502;
  • the DDR control and interface module 504 is configured to save according to the DDR training parameter
  • the training parameters pre-stored in the module 505 configure an access channel of the DDR storage unit, and send a stop self-refresh control command to the IO control module 502 after the configuration is completed;
  • the chip master control module 501 is further configured to invoke the DDR control and interface module 504 from the main data channel of the chip according to a preset debugging policy, and access the DDR storage unit through the IO control module 502 to obtain storage. Field data within the DDR memory unit.
  • the chip structure shown in FIG. 5 also needs to include a general-purpose subsystem inside the chip, the number of which is at least one, in this embodiment, three
  • the subsystems are described as an example. It can be understood that since the subsystems inside the chip need to access and interact with the DDR storage unit through the DDR control and interface module 504, the subsystem inside the chip and the DDR control and interface module 504
  • the data is connected through the internal data bus of the chip, as shown by the thick line in FIG. 5; and the transmission of the control command is performed between the other modules. Therefore, the modules described in this embodiment pass through the control bus. Connection, as shown by the thin line in Figure 5.
  • the chip master control module 501 is configured to send a mode control instruction to the IO control module 502;
  • the IO control module 502 is configured to enter a data hold mode after receiving the mode control instruction, and forcibly change a level state of the IO interface of the DDR memory unit, triggering the DDR memory unit to enter a self-refresh mode;
  • the IO control module 502 is configured to forcibly change the IO interface of the DDR storage unit when the data refresh instruction transmitted by the chip to the DDR storage unit is not received within a preset period of time.
  • the level state triggers the DDR memory unit to enter a self-refresh mode.
  • the IO control module 502 is configured to receive a reset request command, and transmit the reset request command to the chip master control module 501;
  • the chip master control module 501 is configured to follow a preset reset according to the reset request command. Serially controlling the chip to perform resetting; wherein the preset reset sequence is used to indicate that the chip master control module 501 follows the chip internal general subsystem, the system bus, the DDR control and interface module 504, and the The order of the IO control module 502 is sequentially reset.
  • the chip total control module 501 is configured to enter a debugging state according to its internal state and the information of the IO control module 502;
  • the data information of the IO control module 502, the chip master control module 501, the DDR training parameter saving module 505, and the access command recording module 503 are output to the outside of the chip through the IO control module 502, and obtained.
  • the DDR control and interface module 504 is called from the main data channel of the chip according to the preliminary debugging scheme to access the DDR storage unit through the IO control module 502, and the field data stored in the DDR storage unit is obtained.
  • the DDR control and interface module 504 is configured to train the DDR access channel when the chip is in a normal working state, and pre-exist the training parameters in the normal working state of the chip in the DDR training.
  • the access command recording module 503 is configured to monitor the DDR access command of the DDR control and interface module 504 under normal working conditions of the chip.
  • the above modules may be implemented by an application specific integrated circuit (ASIC), a logic programmable gate (FPGA) or a complex programmable logic device (CPLD).
  • ASIC application specific integrated circuit
  • FPGA logic programmable gate
  • CPLD complex programmable logic device
  • the embodiment of the invention discloses a chip and a method for acquiring chip debugging data.
  • the IO control module is additionally provided in the chip, and is configured to monitor the IO of the chip to access the DDR storage unit outside the chip.
  • the IO control module can transmit a refresh command to a DDR memory unit external to the chip, or activate a self-refresh mode of the DDR memory cell, or forcibly change the IO level State, forcing the DDR memory cell to self-refresh. It can ensure that the data in the DDR memory unit can be effectively saved in the event of abnormality or crash, and a large amount of debugging data can be obtained at a low cost and without affecting the performance of the chip.

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Abstract

一种芯片及获取芯片调试数据的方法，该方法包括：芯片总控模块确定芯片处于死机状态时，触发IO控制模块通过强制更改DDR存储单元的IO电平状态控制DDR存储单元进行自刷新（S101）；芯片总控模块根据IO控制模块接收到的复位请求命令按照预设的复位序列控制芯片进行复位（S102）；DDR控制及接口模块在复位后根据DDR训练参数保存模块中预存的训练参数对DDR存储单元的访问通道进行配置，并在配置完毕后向IO控制模块发送停止自刷新控制指令（S103）；芯片总控模块按照预设的调试策略从芯片的主数据通道调用DDR控制及接口模块通过IO控制模块访问DDR存储单元，获取存储在DDR存储单元内的现场数据（S104）。

Description

一种芯片及获取芯片调试数据的方法 技术领域
本发明涉及芯片调试技术，尤其涉及一种芯片及获取芯片调试数据的方法。
背景技术
在芯片运用的过程中，经常会碰到异常或死机的时候，此时，技术人员需要对发生异常或死机的芯片进行问题定位分析，找出发生异常或死机的原因，并进行后续优化调整设计，以及采取对应的异常或死机规避方案。
在芯片的设计规模不大的时候，通过采用不同用例对芯片进行测试，观测在不同用例作用下芯片的不同反应，猜测芯片发生异常或死机的原因。但是随着芯片的设计规模及其复杂度不断增大，通过用例对芯片进行试验猜测的方法需要花费大量的时间，加大了芯片的研发成本。
接着，技术人员通过在芯片内部增加用来进行调试的存储单元，通过输入/输出(IO，Input/Output)接口对这些存储单元进行观测，获取调试数据。方便芯片发生异常或死机后定位问题。但是在芯片内部增加存储单元需要额外的增加成本，而且芯片内的存储单元容量太小，收集到的调试数据有限。
为了获取更多更面的调试数据，技术人员在芯片外部设置额外的闪存(Flash)来进行调试数据的收集。当芯片工作的时候，将芯片的工作状态数据存放到外部设置的Flash上。由于Flash的存储空间比芯片内的存储空间大，因此增加了芯片异常或死机后手机的调试数据的数据采集量。
但该方案具有以下两个缺陷：1、Flash通常用于存放固定程序，如果要存放调试数据，需要额外增加存储空间，从而增加了成本；2、在芯片过 程中存取调试信息需要消耗Flash接口带宽及芯片内部的总线带宽，影响芯片的工作性能。
发明内容
为解决上述技术问题，本发明实施例期望提供一种芯片及获取芯片调试数据的方法，能够在较低的成本以及不影响芯片工作性能的前提下，获取大量的调试数据。
本发明的技术方案是这样实现的：
第一方面，本发明实施例提供了一种获取芯片调试数据的方法，所述方法应用于一芯片，所述芯片与外部双倍速率同步动态随机存储器DDR存储单元相连接，所述芯片包括：芯片总控模块，IO控制模块、访问命令记录模块、DDR控制及接口模块和DDR训练参数保存模块；所述方法包括：
所述芯片总控模块确定所述芯片处于死机状态时，触发所述IO控制模块通过强制更改所述DDR存储单元的IO电平状态控制所述DDR存储单元进行自刷新；
所述芯片总控模块根据所述IO控制模块接收到的复位请求命令按照预设的复位序列控制芯片进行复位；
所述DDR控制及接口模块在复位后根据所述DDR训练参数保存模块中预存的训练参数对所述DDR存储单元的访问通道进行配置，并在配置完毕后向所述IO控制模块发送停止自刷新控制指令；
所述芯片总控模块按照预设的调试策略从所述芯片的主数据通道调用所述DDR控制及接口模块，触发DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
在上述方案中，所述触发所述IO控制模块通过强制更改所述DDR存储单元的IO电平状态控制所述DDR存储单元进行自刷新；包括：
当所述芯片总控模块确认所述芯片处于死机状态时，所述芯片总控模 块向所述IO控制模块发送模式控制指令，所述IO控制模块接收到所述模式控制指令后进入数据保持模式，并强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式；
或者，
当所述IO控制模块在预设的时间段内未接收到所述芯片对所述DDR存储单元传输的数据刷新指令时，所述IO控制模块强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式。
在上述方案中，所述芯片总控模块根据所述IO控制模块接收到的复位请求命令按照预设的复位序列控制芯片进行复位，包括：
所述IO控制模块接收复位请求命令，并将所述复位请求命令传输至所述芯片总控模块；
所述芯片总控模块根据所述复位请求命令按照预设的复位序列控制所述芯片进行复位；其中，所述预设的复位序列用于指示所述芯片总控模块按照所述芯片内部通用子系统、系统总线、所述DDR控制及接口模块以及所述IO控制模块的顺序依次进行复位。
在上述方案中，所述芯片总控模块按照预设的调试策略从所述芯片的主数据通道调用所述DDR控制及接口模块，触发DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据，包括：
所述芯片总控模块根据自身内部状态及所述IO控制模块的信息，进入调试状态；
将所述IO控制模块、所述芯片总控模块、所述DDR训练参数保存模块以及所述访问命令记录模块的数据信息通过所述IO控制模块向所述芯片外部输出，获得初步调试方案；
根据所述初步调试方案从所述芯片的主数据通道调用所述DDR控制及 接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
在上述方案中，所述方法还包括：在所述芯片正常工作状态时，所述DDR控制及接口模块对DDR访问通道进行训练，并将所述芯片正常工作状态下的训练参数预存在所述DDR训练参数保存模块中；
以及，在所述芯片正常工作状态下，所述访问命令记录模块配置为监测所述DDR控制及接口模块的DDR访问命令。
第二方面，本发明实施例提供了一种芯片，所述芯片包括：芯片总控模块，IO控制模块、访问命令记录模块、DDR控制及接口模块和DDR训练参数保存模块；其中，
所述芯片总控模块，配置为确定所述芯片处于死机状态时，触发所述IO控制模块；
所述IO控制模块；配置为根据所述芯片总控模块的触发，通过强制更改所述DDR存储单元的IO电平状态控制所述DDR存储单元进行自刷新；
所述芯片总控模块，还配置为根据所述IO控制模块接收到的复位请求命令按照预设的复位序列控制所述芯片进行复位；
所述DDR控制及接口模块，配置为根据所述DDR训练参数保存模块中预存的训练参数对所述DDR存储单元的访问通道进行配置，并在配置完毕后向所述IO控制模块发送停止自刷新控制指令；
所述芯片总控模块，还配置为按照预设的调试策略从所述芯片的主数据通道调用所述DDR控制及接口模块，触发DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
在上述方案中，所述芯片总控模块，配置为向所述IO控制模块发送模式控制指令；
所述IO控制模块，配置为接收到所述模式控制指令后进入数据保持模式，并强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式；
在上述方案中，所述IO控制模块，配置为在预设的时间段内未接收到所述芯片对所述DDR存储单元传输的数据刷新指令时，强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式。
在上述方案中，所述IO控制模块，配置为接收复位请求命令，并将所述复位请求命令传输至所述芯片总控模块；
所述芯片总控模块，配置为根据所述复位请求命令按照预设的复位序列控制所述芯片进行复位；其中，所述预设的复位序列配置为指示所述芯片总控模块按照所述芯片内部通用子系统、系统总线、所述DDR控制及接口模块以及所述IO控制模块的顺序依次进行复位。
在上述方案中，所述芯片总控模块，配置为根据自身内部状态及所述IO控制模块的信息，进入调试状态；以及，
将所述IO控制模块、所述芯片总控模块、所述DDR训练参数保存模块以及所述访问命令记录模块的数据信息通过所述IO控制模块向所述芯片外部输出，获得初步调试方案；以及，
根据所述初步调试方案从所述芯片的主数据通道调用所述DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
在上述方案中，所述DDR控制及接口模块，配置为在所述芯片正常工作状态时，对DDR访问通道进行训练，并将所述芯片正常工作状态下的训练参数预存在所述DDR训练参数保存模块中；
所述访问命令记录模块，配置为在所述芯片正常工作状态下，监测所述DDR控制及接口模块的DDR访问命令。
本发明实施例提供了一种芯片及获取芯片调试数据的方法，在芯片内部额外地设置IO控制模块，配置为监控芯片对芯片外部的DDR存储单元进行访问的IO。IO控制模块可以通过向芯片外部的DDR存储单元传输刷新命令，或者启动DDR存储单元的自刷新模式，或者强制更改IO电平状态，迫使DDR存储单元进行自刷新。
从而能够确保芯片在出现异常或死机的情况下，DDR存储单元中的数据可以得到有效的保存，能够在较低的成本以及不影响芯片工作性能的前提下，获取大量的调试数据。
附图说明
图1为本发明实施例所提供的一种获取芯片调试数据的方法流程示意图；
图2为本发明实施例所提供的一种芯片的结构示意图；
图3为本发明实施例所提供的一种复位过程示意图；
图4为本发明实施例所提供的一种获取现场数据的流程示意图；
图5为本发明实施例所提供的另一种芯片的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
本发明实施例的基本思想是：由于双倍速率同步动态随机存储器(DDR，Double Data Rate SDRAM)存储单元能够存储海量(以吉比特GB为单位)的现场信息和数据，但是DDR属于非永久存储的存储器件，它的数据保持寿命通常是毫秒量级的。因此，本发明实施例在芯片内部额外地设置IO控制模块，配置为监控芯片对芯片外部的DDR存储单元进行访问的IO。IO控制模块可以通过向芯片外部的DDR存储单元传输刷新命令， 或者启动DDR存储单元的自刷新模式，或者强制更改IO电平状态，迫使DDR存储单元进行自刷新，从而能够确保芯片在出现异常或死机的情况下，DDR存储单元中的数据可以得到有效的保存。
实施例一
基于上述基本思想，参见图1，其示出了本发明实施例所提供的一种获取芯片调试数据的方法，该方法可以应用于如图2所示的与外部DDR存储单元相连接的芯片20，该芯片20结构可以包括：芯片总控模块201，IO控制模块202、访问命令记录模块203、DDR控制及接口模块204和DDR训练参数保存模块205；该方法可以包括：
S101：芯片总控模块201确定芯片20处于死机状态时，触发IO控制模块202通过强制更改DDR存储单元的IO电平状态控制DDR存储单元进行自刷新；
需要说明的是，在具体实现过程中，芯片总控模块201内部会设置看门狗计数器，当芯片正常工作时，看门狗计数器会启动计数并执行喂狗操作；当看门狗计数器超出预设的计数门限时，芯片总控模块201就能够确认芯片20处于死机状态。
可选地，在具体实现过程中，所述触发IO控制模块202通过强制更改DDR存储单元的IO电平状态控制DDR存储单元进行自刷新，可以包括：
当芯片总控模块201确认芯片20处于死机状态时，芯片总控模块201可以向IO控制模块202发送模式控制指令；IO控制模块202接收到该指令后进入数据保持模式，并强制更改DDR存储单元的IO接口的电平状态，触发DDR存储单元进入自刷新模式。
可选地，在具体实现过程中，所述触发IO控制模块202通过强制更改DDR存储单元的IO电平状态控制DDR存储单元进行自刷新，可以包括：
当IO控制模块202在预设的时间段内未接收到芯片20对DDR存储单 元传输的数据刷新指令时，IO控制模块202强制更改DDR存储单元的IO接口的电平状态，触发DDR存储单元进入自刷新模式。
可以理解地，DDR存储单元可以根据IO接口由于IO控制模块202强制变更的电平状态，进行自刷新模式，从而将DDR存储单元自身所保存的用于描述芯片运行状态的现场数据进行保存。
S102：芯片总控模块201根据IO控制模块202接收到的复位请求命令按照预设的复位序列控制芯片20进行复位；
示例性地，如图3所示，步骤S102具体可以包括步骤S1021和S1022：
S1021：IO控制模块202接收复位请求命令，并将所述复位请求命令传输至芯片总控模块201；
S1022：芯片总控模块201根据所述复位请求命令按照预设的复位序列控制芯片20进行复位；
其中，所述预设的复位序列用于指示芯片总控模块201按照芯片20内部通用子系统、系统总线、DDR控制及接口模块204以及IO控制模块202的顺序进行复位。
在具体实现过程中，芯片总控模块201按照预设的复位序列控制芯片20进行复位，可以包括：
芯片总控模块201可以依次向芯片20内部通用子系统、系统总线、DDR控制及接口模块204以及IO控制模块202发送复位命令；触发芯片20内部通用子系统、系统总线、DDR控制及接口模块204以及IO控制模块202按照接收到复位命令的顺序进行复位。
需要说明的是，芯片20死机很可能造成芯片20与DDR存储单元的访问通道已经挂死，因此这时需要进行芯片复位。复位的过程需要一定时间来执行，很多系统复位时间也是毫秒级的，或者是秒级别的时候。因此在复位期间DDR存储单元的数据可能发生丢失情况。鉴于此，芯片20需要 对复位进行序列规划，由于IO控制模块202不在主复位序列中进行服务，而是有单独的服务控制，所以，在本发明实施例中，优选地采用了芯片20主复位完成后，再进行IO控制模块202的复位。因此，IO控制模块202的复位放在了复位顺序的最后。从而可以确保DDR存储单元中所保存的现场数据信息不会在复位阶段遭受破坏。
S103：DDR控制及接口模块204在复位后根据DDR训练参数保存模块205中预存的训练参数对DDR存储单元的访问通道进行配置，并在配置完毕后向IO控制模块202发送停止自刷新控制指令；
需要说明的是，自刷新的过程中是无法访问DDR数据的，因此，停止自刷新控制指令用于指示IO控制模块202控制DDR存储单元进行停止自刷新。当DDR存储单元在此时停止自刷新完毕之后，就可以进入了调试数据的获取阶段，即：
S104：芯片总控模块201按照预设的调试策略从芯片20的主数据通道调用DDR控制及接口模块204通过IO控制模块202访问DDR存储单元，获取存储在DDR存储单元内的现场数据；
示例性地，在具体实现过程中，如图4所示，步骤S104可以包括S1041至S1043：
S1041：芯片总控模块201根据自身内部状态及IO控制模块202的信息，进入调试状态；
需要说明的是，IO控制模块202在接收到由DDR控制及接口模块204传输的停止自刷新控制指令后，通知芯片总控模块201；此时，芯片总控模块201就可以根据自身内部状态及IO控制模块202的信息，进行状态判断；随后通过IO控制模块202通知芯片20外部，可以进入交互调试阶段。
S1042：将IO控制模块202、芯片总控模块201、DDR训练参数保存模块205以及访问命令记录模块203的数据信息通过IO控制模块202向芯 片20外部输出，获得初步调试方案；
对于步骤S1042，需要说明的是，由于IO控制模块202配置为与芯片20的外部进行数据的IO，因此，外部调试人员获取IO控制模块202、芯片总控模块201、DDR训练参数保存模块205以及访问命令记录模块203的内部数据信息必须通过IO控制模块202才能进行获取；而在芯片内部，DDR训练参数保存模块205以及访问命令记录模块203的内部数据信息需要通过芯片总控模块201收集之后才能够通过IO控制模块202向外输出；所以，在外部调试人员通过IO控制模块202获取到IO控制模块202、芯片总控模块201、DDR训练参数保存模块205以及访问命令记录模块203的内部数据信息之后，就可以结合芯片手册的内容形成初步调试方案。
S1043：根据初步调试方案从芯片20的主数据通道调用DDR控制及接口模块204通过IO控制模块202访问DDR存储单元，获取存储在DDR存储单元内的现场数据。
可以理解地，根据初步调试方案执行完成步骤S1043之后，就实现了从DDR存储单元中获取芯片调试数据的过程。
需要说明的是，当复位完毕后，DDR访问通道还需要进行训练(training)后才可以进行正确的数据访问操作，而training有各种模式，需要的时间也长短不一，而在training阶段时期，DDR存储单元中的数据是得不到保持的，时间越长，DDR存储单元里面的数据丢失越严重。因此需要缩短traing时间，由于芯片的外部硬件环境不会发生重大变化，所以本实施例优选地，本实施例还可以包括：
在芯片20正常工作状态时，DDR控制及接口模块204会对DDR访问通道进行训练，并将芯片20正常工作状态下的训练参数预存在DDR训练参数保存模块205中。可以理解地，由于将芯片20正常工作状态下的正确训练参数进行保持，并在复位后直接赋值给DDR控制及接口模块204，从 而缩短了训练的时间。
还需要说明的是，在芯片20正常工作状态下，访问命令记录模块203配置为监测DDR控制及接口模块204的DDR访问命令，访问命令可以包括：访问用户标识、读写操作类型、操作起始地址、操作数据长度等访问信息。这些访问信息均是芯片20在工作时的关键控制信息。
本实施例提供了一种获取芯片调试数据的方法，在芯片内部额外地设置IO控制模块，配置为监控芯片对芯片外部的DDR存储单元进行访问的IO。IO控制模块可以通过向芯片外部的DDR存储单元传输刷新命令，或者启动DDR存储单元的自刷新模式，或者强制更改IO电平状态，迫使DDR存储单元进行自刷新，从而能够确保芯片在出现异常或死机的情况下，DDR存储单元中的数据可以得到有效的保存，能够在较低的成本以及不影响芯片工作性能的前提下，获取大量的调试数据。
实施例二
结合上述实施例相同的技术构思，参见图5，其示出了本发明实施例提供的一种芯片50，该芯片50可以包括：芯片总控模块501，IO控制模块502、访问命令记录模块503、DDR控制及接口模块504和DDR训练参数保存模块505；其中，
所述芯片总控模块501，配置为确定所述芯片处于死机状态时，触发所述IO控制模块502；
所述IO控制模块502；配置为根据所述芯片总控模块501的触发，通过强制更改所述DDR存储单元的IO电平状态控制所述DDR存储单元进行自刷新；
所述芯片总控模块501，还配置为根据所述IO控制模块502接收到的复位请求命令按照预设的复位序列控制所述芯片进行复位；
所述DDR控制及接口模块504，配置为根据所述DDR训练参数保存 模块505中预存的训练参数对所述DDR存储单元的访问通道进行配置，并在配置完毕后向所述IO控制模块502发送停止自刷新控制指令；
所述芯片总控模块501，还配置为按照预设的调试策略从所述芯片的主数据通道调用所述DDR控制及接口模块504通过所述IO控制模块502访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
需要说明的是，为了能够清楚地说明本实施例的技术方案，图5所示的芯片结构示意中还需要包括芯片内部的通用子系统，其数量至少为一个，在本实施例中，以三个子系统为例进行说明，可以理解地，由于芯片内部的子系统需要通过DDR控制及接口模块504与DDR存储单元进行数据访问和交互，因此，芯片内部的子系统与DDR控制及接口模块504之间通过芯片内部的数据总线相连接，如图5中的粗线所示；而其余模块之间由于进行的是控制指令的传输，因此，本实施例所述的模块之间的均通过控制总线连接，如图5中细线所示。
在上述方案中，所述芯片总控模块501，配置为向所述IO控制模块502发送模式控制指令；
所述IO控制模块502，配置为接收到所述模式控制指令后进入数据保持模式，并强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式；
在上述方案中，所述IO控制模块502，配置为在预设的时间段内未接收到所述芯片对所述DDR存储单元传输的数据刷新指令时，强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式。
在上述方案中，所述IO控制模块502，配置为接收复位请求命令，并将所述复位请求命令传输至所述芯片总控模块501；
所述芯片总控模块501，配置为根据所述复位请求命令按照预设的复位 序列控制所述芯片进行复位；其中，所述预设的复位序列用于指示所述芯片总控模块501按照所述芯片内部通用子系统、系统总线、所述DDR控制及接口模块504以及所述IO控制模块502的顺序依次进行复位。
在上述方案中，所述芯片总控模块501，配置为根据自身内部状态及所述IO控制模块502的信息，进入调试状态；以及，
将所述IO控制模块502、所述芯片总控模块501、所述DDR训练参数保存模块505以及所述访问命令记录模块503的数据信息通过所述IO控制模块502向所述芯片外部输出，获得初步调试方案；以及，
根据所述初步调试方案从所述芯片的主数据通道调用所述DDR控制及接口模块504通过所述IO控制模块502访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
在上述方案中，所述DDR控制及接口模块504，配置为在所述芯片正常工作状态时，对DDR访问通道进行训练，并将所述芯片正常工作状态下的训练参数预存在所述DDR训练参数保存模块505中；
所述访问命令记录模块503，配置为在所述芯片正常工作状态下，监测所述DDR控制及接口模块504的DDR访问命令。
实际应用中，上述模块可由专用集成电路(ASIC)、逻辑可编程门电路(FPGA)或复杂可编程逻辑器件(CPLD)实现。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例公开了一种芯片及获取芯片调试数据的方法，通过在芯片中额外设置IO控制模块，配置为监控芯片对芯片外部的DDR存储单元进行访问的IO。IO控制模块可以通过向芯片外部的DDR存储单元传输刷新命令，或者启动DDR存储单元的自刷新模式，或者强制更改IO电平状 态，迫使DDR存储单元进行自刷新。能够确保芯片在出现异常或死机的情况下，DDR存储单元中的数据可以得到有效的保存，能够在较低的成本以及不影响芯片工作性能的前提下，获取大量的调试数据。

Claims (11)

  1. 一种获取芯片调试数据的方法；
    所述方法应用于一芯片，所述芯片与外部双倍速率同步动态随机存储器DDR存储单元相连接，所述芯片包括：芯片总控模块，IO控制模块、访问命令记录模块、DDR控制及接口模块和DDR训练参数保存模块；
    所述方法包括：
    所述芯片总控模块确定所述芯片处于死机状态时，触发所述IO控制模块通过强制更改所述DDR存储单元的IO电平状态控制所述DDR存储单元进行自刷新；
    所述芯片总控模块根据所述IO控制模块接收到的复位请求命令按照预设的复位序列控制芯片进行复位；
    所述DDR控制及接口模块在复位后，根据所述DDR训练参数保存模块中预存的训练参数对所述DDR存储单元的访问通道进行配置，并在配置完毕后向所述IO控制模块发送停止自刷新控制指令；
    所述芯片总控模块按照预设的调试策略从所述芯片的主数据通道调用所述DDR控制及接口模块，触发所述DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
  2. 根据权利要求1所述的方法，其中，所述触发所述IO控制模块通过强制更改所述DDR存储单元的IO电平状态控制所述DDR存储单元进行自刷新；包括：
    当所述芯片总控模块确认所述芯片处于死机状态时，所述芯片总控模块向所述IO控制模块发送模式控制指令，所述IO控制模块接收到所述模式控制指令后进入数据保持模式，并强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式；
    或者，
    当所述IO控制模块在预设的时间段内未接收到所述芯片对所述DDR存储单元传输的数据刷新指令时，所述IO控制模块强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式。
  3. 根据权利要求1所述的方法，其中，所述芯片总控模块根据所述IO控制模块接收到的复位请求命令按照预设的复位序列控制芯片进行复位，包括：
    所述IO控制模块接收复位请求命令，并将所述复位请求命令传输至所述芯片总控模块；
    所述芯片总控模块根据所述复位请求命令按照预设的复位序列控制所述芯片进行复位；其中，所述预设的复位序列用于指示所述芯片总控模块按照所述芯片内部通用子系统、系统总线、所述DDR控制及接口模块以及所述IO控制模块的顺序依次进行复位。
  4. 根据权利要求1所述的方法，其中，所述芯片总控模块按照预设的调试策略从所述芯片的主数据通道调用所述DDR控制及接口模块，触发所述DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据，包括：
    所述芯片总控模块根据自身内部状态及所述IO控制模块的信息，进入调试状态；
    将所述IO控制模块、所述芯片总控模块、所述DDR训练参数保存模块以及所述访问命令记录模块的数据信息通过所述IO控制模块向所述芯片外部输出，获得初步调试方案；
    根据所述初步调试方案从所述芯片的主数据通道调用所述DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
  5. 根据权利要求1所述的方法，其中，所述方法还包括：在所述芯片正常工作状态时，所述DDR控制及接口模块对DDR访问通道进行训练，并将所述芯片正常工作状态下的训练参数预存在所述DDR训练参数保存模块中；
    以及，在所述芯片正常工作状态下，所述访问命令记录模块用于监测所述DDR控制及接口模块的DDR访问命令。
  6. 一种芯片，所述芯片包括：芯片总控模块，IO控制模块、访问命令记录模块、双倍速率同步动态随机存储器DDR控制及接口模块和DDR训练参数保存模块；其中，
    所述芯片总控模块，配置为确定所述芯片处于死机状态时，触发所述IO控制模块；
    所述IO控制模块；配置为根据所述芯片总控模块的触发，通过强制更改所述DDR存储单元的IO电平状态控制所述DDR存储单元进行自刷新；
    所述芯片总控模块，还配置为根据所述IO控制模块接收到的复位请求命令按照预设的复位序列控制所述芯片进行复位；
    所述DDR控制及接口模块，配置为根据所述DDR训练参数保存模块中预存的训练参数对所述DDR存储单元的访问通道进行配置，并在配置完毕后向所述IO控制模块发送停止自刷新控制指令；
    所述芯片总控模块，还配置为按照预设的调试策略从所述芯片的主数据通道调用所述DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
  7. 根据权利要求6所述的芯片，其中，所述芯片总控模块，配置为向所述IO控制模块发送模式控制指令；
    所述IO控制模块，配置为接收到所述模式控制指令后进入数据保持模式，并强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR 存储单元进入自刷新模式。
  8. 根据权利要求6所述的芯片，其中，
    所述IO控制模块，配置为在预设的时间段内未接收到所述芯片对所述DDR存储单元传输的数据刷新指令时，强制更改所述DDR存储单元的IO接口的电平状态，触发所述DDR存储单元进入自刷新模式。
  9. 根据权利要求6所述的芯片，其中，
    所述IO控制模块，配置为接收复位请求命令，并将所述复位请求命令传输至所述芯片总控模块；
    所述芯片总控模块，配置为根据所述复位请求命令按照预设的复位序列控制所述芯片进行复位；其中，所述预设的复位序列用于指示所述芯片总控模块按照所述芯片内部通用子系统、系统总线、所述DDR控制及接口模块以及所述IO控制模块的顺序依次进行复位。
  10. 根据权利要求6所述的芯片，其中，
    所述芯片总控模块，配置为根据自身内部状态及所述IO控制模块的信息，进入调试状态；以及，
    将所述IO控制模块、所述芯片总控模块、所述DDR训练参数保存模块以及所述访问命令记录模块的数据信息通过所述IO控制模块向所述芯片外部输出，获得初步调试方案；以及，
    根据所述初步调试方案从所述芯片的主数据通道调用所述DDR控制及接口模块通过所述IO控制模块访问所述DDR存储单元，获取存储在所述DDR存储单元内的现场数据。
  11. 根据权利要求6所述的芯片，其中，所述DDR控制及接口模块，配置为在所述芯片正常工作状态时，对DDR访问通道进行训练，并将所述芯片正常工作状态下的训练参数预存在所述DDR训练参数保存模块中；
    所述访问命令记录模块，配置为在所述芯片正常工作状态下，监测所 述DDR控制及接口模块的DDR访问命令。
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