WO2017204019A1

WO2017204019A1 - Electrolytic copper plating liquid evaluation system, electrolytic copper plating liquid evaluation method, and electrolytic copper plating liquid evaluation chip

Info

Publication number: WO2017204019A1
Application number: PCT/JP2017/018217
Authority: WO
Inventors: 近藤　和夫; ホアン・ヴァン・ハ
Original assignee: 公立大学法人大阪府立大学; 株式会社東設
Priority date: 2016-05-27
Filing date: 2017-05-15
Publication date: 2017-11-30

Abstract

Provided are an electrolytic copper plating liquid evaluation system, an electrolytic copper plating liquid evaluation method, and an electrolytic copper plating liquid evaluation chip that are able to measure a concentration distribution of monovalent copper inside a pore. The electrolytic copper plating liquid evaluation system according to the present invention is provided with: an electrolytic copper plating liquid evaluation chip which has a pore, at least one first electrode formed in the lateral wall within the pore, and a second electrode formed in the lateral wall within the pore; a reference electrode; an anode; and a current/potential settings measurement device to which the first electrode, the second electrode, the anode, and the reference electrode are connected, wherein a copper plating reaction is induced by the second electrode, and measurement of monovalent copper concentration is conducted by the first electrode.

Description

Electrolytic copper plating solution evaluation system, electrolytic copper plating solution evaluation method, and electrolytic copper plating solution evaluation chip

The present invention relates to an electrolytic copper plating solution evaluation system, an electrolytic copper plating solution evaluation method, and an electrolytic copper plating solution evaluation chip.

In recent years, electronic devices such as mobile phones and notebook computers are rapidly becoming smaller and higher performance. Along with this, miniaturization of wiring and multilayering of wiring have been promoted, and copper having excellent conductivity and heat dissipation is used as a wiring material. An electrolytic copper plating process is widely used for forming copper wiring.

For example, in a build-up board in which wiring layers are stacked on the top and bottom of a core material, a via fill plating process is used in which vias for interlayer connection are filled with copper by an electrolytic copper plating process. For copper wiring of LSI chips, a copper damascene process is used in which wiring trenches and interlayer connection vias are filled with copper by an electrolytic copper plating process. In three-dimensional mounting in which a large number of LSI chips are stacked to form a single package, LSI chips are stacked, and LSIs are formed using silicon through electrodes (hereinafter abbreviated as TSV) that serve as vertical wirings penetrating the LSI chips. A circuit connection is made between chips, and a TSV is formed by filling a via penetrating an LSI chip with copper by an electrolytic copper plating process (for example, Patent Document 1).

JP 2003-96596 A

In electrolytic copper plating, the following reaction proceeds.

When copper is filled into a hole such as a via by an electroplating process, the deposition rate at the upper end of the hole is larger than the deposition rate inside the hole, and the inside of the hole may not be completely filled. In order to completely fill the inside of the hole, it is known that Cu ⁺ (hereinafter referred to as monovalent copper) that is an intermediate of the plating reaction needs to be present at the bottom of the hole. For this reason, an inhibitor that adsorbs to the upper end portion of the hole and suppresses plating at the upper end portion of the hole and an accelerator that stabilizes the monovalent copper complex existing inside the hole are usually used as an additive for the plating solution. By fully exhibiting the effects of these inhibitors and accelerators, it becomes possible to completely fill the hole with copper. For this purpose, it is important to monitor the concentration distribution of monovalent copper inside the hole. Conventionally, the rotating ring disk method is known as a method for measuring the concentration of monovalent copper in the plating solution of the plating tank. There is a cyclic voltammetry stripping (CVS) method for managing the plating solution. However, there is no known method for directly measuring the concentration distribution of monovalent copper in the plating solution inside the hole. If the concentration distribution of monovalent copper in the hole can be directly measured, the plating solution can be managed more directly.

Accordingly, an object of the present invention is to provide an electrolytic copper plating solution evaluation system, an electrolytic copper plating solution evaluation method, and an electrolytic copper plating solution evaluation chip capable of measuring the concentration distribution of monovalent copper inside the hole. It was.

In order to solve the above problems, the electrolytic copper plating solution evaluation system of the present invention is:
An electrolytic copper plating solution evaluation chip having a hole, one or more first electrodes formed on the side wall in the hole, and a second electrode formed on the side wall in the hole;
A reference electrode;
An anode,
A current potential setting measuring device connecting the first electrode, the second electrode, the anode, and the reference electrode;
A copper plating reaction is caused by the second electrode, and the concentration of monovalent copper is measured by the first electrode.

An electrolytic copper plating solution evaluation method of the present invention is an electrolytic copper plating solution evaluation method using the electrolytic copper plating solution evaluation system, wherein the electrolytic copper plating solution evaluation chip is immersed in the electrolytic copper plating solution, The divalent copper is reduced with two electrodes, the potential of the first electrode is maintained at a potential capable of oxidizing the monovalent copper, and the concentration of the monovalent copper is measured.

The electrolytic copper plating solution evaluation chip of the present invention includes a hole, one or a plurality of first electrodes formed on the side wall in the hole, and a second electrode formed on the side wall in the hole. It is characterized by having.

The electrolytic copper plating solution evaluation system of the present invention has a hole, one or a plurality of first electrodes formed on the side wall in the hole, and a second electrode formed on the side wall in the hole. By using the electrolytic copper plating solution evaluation chip, the concentration distribution of monovalent copper inside the hole can be directly measured. Since the plating solution inside the via can be regarded as being in the same state as the plating solution inside the hole of the evaluation chip, the plating solution inside the via is appropriately managed by using the measurement result of the evaluation chip described above. And generation of voids during electrolytic copper plating can be prevented. In particular, since the evaluation chip of the present invention can produce a hole having a minute opening diameter on the order of nm by using a semiconductor microfabrication process, the concentration distribution of monovalent copper inside the minute via is reduced. It can be suitably used for measurement. The concentration distribution of monovalent copper in the present invention is the concentration distribution of monovalent copper in the depth direction of the hole, using the concentration of monovalent copper at a depth distance of one point or more from the upper end of the hole. Can be represented.

It is a schematic diagram which shows an example of a structure of the electrolytic copper plating solution evaluation system of this invention. It is a model perspective view which shows an example of the structure of the chip | tip for evaluation used for the electrolytic copper plating liquid evaluation system of this invention. FIG. 3 is a longitudinal sectional view taken along line XX ′ in FIG. 2. FIG. 3 is a schematic diagram illustrating an example of a manufacturing process of the evaluation chip in FIG. 2. FIG. 3 is a schematic diagram illustrating an example of a manufacturing process of the evaluation chip in FIG. 2. FIG. 3 is a schematic diagram illustrating an example of a manufacturing process of the evaluation chip in FIG. 2. It is a model perspective view which shows an example of the structure of the member used for the chip | tip for evaluation of FIG. It is a graph which shows an example of the measurement result of the electrolytic copper plating solution evaluation system of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, an electrolytic copper plating solution evaluation system according to the present invention includes an electrolytic copper plating solution evaluation chip 21, a reference electrode 22, an anode 23, a first electrode, a second electrode, an anode, and a reference electrode. A current potential setting measuring device 24 for connecting the electrode, and an electrolytic copper plating solution evaluation chip 21, a reference electrode 22, and an anode 23 are immersed in a plating solution 26 in a plating tank 25 and used. .

An evaluation chip used in the evaluation system of the present invention includes a hole, one or more first electrodes formed on the side wall in the hole, and a second electrode formed on the side wall in the hole. Have. The hole is preferably formed by bonding a second substrate having a groove on one main surface to the upper surface of the first substrate with the one main surface facing each other via an insulating layer. Preferably, the one or more first electrodes are formed on an upper surface of the first substrate facing the groove, and the second electrode is formed on an inner surface of the groove. In the present invention, the hole may be a bottomless through hole or a bottomed hole.

FIG. 2 is a schematic perspective view showing an example of the structure of the evaluation chip of the present invention, and FIG. 3 is a longitudinal sectional view taken along the line XX ′. The evaluation chip A has a first substrate 1 and a second substrate 7. The second substrate 7 has a groove 8 having one end closed on one main surface and the other end opened. One bottomed hole 9 extending on the first substrate 1 is formed on the upper surface of the first substrate 1 by facing the one main surface of the second substrate 7 and bonding it via the insulating layer 11. is doing. The side wall in the bottomed hole 9 has a first side wall 91 made of the first substrate 1 exposed in the bottomed hole 9 and a second side wall 92 made of the second substrate 7 exposed in the bottomed hole 9. ing. Further, the second side wall 92 includes a groove bottom surface 921 and a groove inner side surface 922 of the groove 8 of the second substrate 7. A plurality of

first electrodes

3 a, 3 b, 3 c, 3 d, 3 e are formed on the first side wall 91 along the depth direction of the bottomed hole 9. A second electrode 10 is formed on the second side wall 92. In addition, side electrodes 101 are formed on the entire four side surfaces of the second substrate 7 and are electrically connected to the second electrode 10. The

first electrodes

3 a, 3 b, 3 c, 3 d, 3 e are drawn out by the wiring 6 and are connected to

electrode pads

2 a, 2 b, 2 c, 2 d, 2 e formed at one end of the first substrate 1. An electrode pad 13 is formed on the side electrode 101 of the second substrate 7. 2 and 3 show examples in which five first electrodes are used. However, the number of first electrodes is not particularly limited as long as it is one or more.

The evaluation chip of the present invention includes, for example, a step of forming one or a plurality of first electrodes on the upper surface of the first substrate, and a groove on one main surface and a second electrode on the inner surface of the groove. Forming a second substrate and bonding the first main surface of the second substrate to the upper surface of the first substrate through an insulating layer so as to oppose the first electrode and the first electrode on the inner surface. And a step of forming a hole having two electrodes.

FIG. 4A, FIG. 4B, FIG. 4C, and FIG. 5 are schematic diagrams showing an example of the manufacturing process of the evaluation chip A, and show an example of manufacturing two evaluation chips.

FIG. 4A shows a first pattern formed by forming a metal film on the entire surface of the first substrate 1 by sputtering or vacuum deposition, and using a photolithography method that performs resist coating, exposure, development, and etching. One electrode, an electrode pad, and wiring for connecting the first electrode and the electrode pad are shown. In the first substrate 1 on the back side of the drawing, the

electrode pads

2a, 2b, 2c, 2d, and 2e are arranged substantially linearly along one end surface of the first substrate 1, and the

first electrodes

3a, 3b, 3c, and 3d are arranged. , 3e are arranged linearly in the direction substantially orthogonal to the one end face near the center of the first substrate 1, and the plurality of wirings 6 are connected to the electrode pads 2a by the

first electrodes

3a, 3b, 3c, 3d, 3e. , 2b, 2c, 2d, 2e. Similarly, in the first substrate 1 in front of the paper surface, the

electrode pads

4a, 4b, 4c, 4d, and 4e are arranged substantially linearly along one end surface of the first substrate 1, and the

first electrodes

5a, 5b, 5c, 5d, and 5e are linearly arranged near the center of the first substrate 1 in a direction substantially orthogonal to the one end face, and the plurality of wirings 6 are formed of the

first electrodes

5a, 5b, 5c, 5d, and 5e. Is drawn out to the

electrode pads

4a, 4b, 4c, 4d and 4e.

Here, FIG. 5 is a schematic perspective view showing the structure of the second substrate 7. The second substrate 7 has a rectangular parallelepiped shape having a pair of opposing main surfaces and four side surfaces connecting the pair of main surfaces, and one main surface has one end closed and the other end opened. The upper surface of the groove 8 is open. A second electrode 10 is formed on the groove bottom surface and the groove inner side wall of the groove 8. In addition, side electrodes 101 are formed on the entire four side surfaces of the second substrate 7 and are electrically connected to the second electrode 10. The second substrate 7 can be produced, for example, by cutting a substrate similar to the substrate 1 into a rectangular parallelepiped shape and forming the grooves 8. The groove 8 has a groove width of 10 cm to 2 nm, preferably 1000 μm to 2 nm, more preferably 10 μm to 2 nm, a groove depth of 1 cm to 10 nm, preferably 100 μm to 10 nm, and a groove length of 20 cm. Is 1 μm, preferably 100 μm to 1 μm. In particular, by using a semiconductor microfabrication process, after forming a resist pattern, forming a groove 8 by etching, forming a second electrode by vapor deposition, etc., and then removing the resist layer, the groove width, groove depth, groove length. However, it is possible to form minute grooves on the order of micrometers or even on the order of nanometers.

FIG. 4B shows a process of bonding the manufactured second substrate 7 to the first substrate 1 on which the first electrode, the electrode pad, and the wiring are formed. An insulating layer 11 is formed on the surface of the first substrate 1 excluding the first electrode and the electrode pad. The second substrate 7 is aligned so that the groove 8 faces the

first electrodes

5a, 5b, 5c, 5d, and 5e, and the one main surface of the second substrate 7 other than the groove 8 is bonded using an adhesive. The first substrate 1 is bonded to the insulating layer 11 by bonding.

Next, the evaluation chip A shown in FIG. 4C can be obtained by dividing the first substrate 1 bonded with the second substrate 7 in the step of FIG. 4B into two parts. A second electrode pad 13 is formed on the side surface of the second substrate 7, and the second electrode pad 13 is drawn out by a second electrode lead 14 and connected to a current potential setting measurement device. The

electrode pads

2a, 2b, 2c, 2d, and 2e are drawn out by the first electrode leads 12a, 12b, 12c, 12d, and 12e, and are connected to the current potential setting measuring device.

According to the manufacturing method of the present invention, a semiconductor substrate microfabrication process is used to produce a second substrate having a minute groove having a groove width, groove depth, and groove length on the order of micrometers, and further on the order of nanometers. By bonding the second substrate and the first substrate through an insulating layer, a minute hole having a minute opening diameter on the order of micrometers or even nanometers can be easily produced.

Although FIGS. 4A, 4B, and 4C show an example in which two evaluation chips are manufactured, a larger number of evaluation chips can be manufactured using the same first substrate.

As the first substrate and the second substrate used in the present invention, a silicon substrate, a quartz substrate, an alumina substrate, a resin substrate, or the like can be used. A silicon substrate is preferable from the viewpoint of productivity. When a silicon substrate is used, a SiO ₂ film can be used for the insulating layer 10. The SiO ₂ film can be produced by, for example, plasma CVD.

Further, the shape and size of the hole 9 can be set by the shape and size of the groove formed in the second substrate. The opening area of the holes is 10 cm ² to 20 nm ² , preferably 10 ⁵ μm ² to 20 nm ² , more preferably 10 ² μm ² to 20 nm ² . The depth of the hole is 20 cm to 1 μm, preferably 500 μm to 1 μm, more preferably 100 μm to 1 μm. Moreover, the cross-sectional shape of the hole is circular or rectangular.

Moreover, noble metals, such as gold | metal | money, platinum, and ruthenium, can be used for a 1st electrode. Gold or platinum is preferable. The thickness of the first electrode is 10 μm to 0.01 nm, preferably 1 μm to 1 nm. The surface area of the first electrode is 25 cm ² to 1 × 10 ⁻¹⁶ cm ² , preferably 100 to 1 μm ² . Here, the surface area of the first electrode refers to the area of the upper surface of the first electrode. In addition, various shapes such as a rectangle, a circle, and an indefinite shape can be used for the first electrode. The number of first electrodes is one or more, and in the case of a plurality of first electrodes, it is preferable to arrange them along the depth direction of the hole. Further, the first electrode can be formed by a sputtering method and a photolithography method as described above.

The second electrode can be made of a metal material to be plated, such as copper, or a base metal such as nickel, but is preferably copper. The 2nd electrode should just be formed in a part of groove | channel bottom of a groove | channel, and the area is not specifically limited. A copper layer can be used as the second electrode. The thickness of the copper layer is 100 to 0.01 μm, preferably 1 to 0.01 μm. Moreover, a vacuum evaporation method can be used for formation of a copper layer.

Also, noble metals such as gold, platinum and ruthenium can be used for the electrode pads and wiring. Gold or platinum is preferable. The size of the electrode pad can be set as appropriate.

Also, in order to protect the electrode pads and wiring from the electrolytic copper plating solution, it can be covered with an insulating protective film as necessary. As the protective film, a resin film such as a polyimide resin film, a metal oxide film, or a metal nitride film can be used.

Further, copper or platinum electrodes, which are metal materials to be plated, can be used for the anode used in the evaluation system of the present invention. Further, a silver / silver chloride electrode or a saturated caramel electrode can be used as the reference electrode.

Further, the current potential setting measurement device used in the evaluation system of the present invention connects the first electrode, the second electrode, the anode and the reference electrode, and independently controls the potential of the first electrode and the potential of the second electrode, In addition, it is a device capable of measuring a current based on a reaction occurring between the first electrode and the second electrode, and examples thereof include a dual potentio galvanostat or two potentio galvanostats.

Next, a method for evaluating an electrolytic copper plating solution using the evaluation system of the present invention will be described.
The evaluation chip of the present invention is immersed in an electrolytic copper plating solution in a plating tank, and an anode and a reference electrode are also arranged in the plating tank. By connecting the leads from the first electrode and the second electrode to a dual potentiostat, the potentials of the first electrode and the second electrode can be independently controlled with respect to a single reference electrode. Here, the plurality of first electrodes are electrically connected to the dual potentiostat through the switching device. The switching device connects the specific first electrode to the dual potentiostat based on a predetermined switching signal. A plating reaction is caused on the second electrode by setting the potential of the second electrode to a potential at which Cu ²⁺ (bivalent copper) can be reduced. On the other hand, the potential of the first electrode is set to a potential capable of oxidizing monovalent copper. Since the monovalent copper produced on the second electrode diffuses to the first electrode and is oxidized, the concentration of monovalent copper at the position where the first electrode is disposed in the hole is measured by measuring the oxidation current. Can be detected. As shown in FIG. 3, since the plurality of first electrodes are arranged along the depth direction of the hole, by connecting each first electrode to a dual potentiostat using a switching device, The concentration of monovalent copper in the depth direction of the hole can be calculated. That is, by using the evaluation apparatus of the present invention, not only the concentration of monovalent copper in the hole, but also the concentration distribution of monovalent copper in the depth direction in the hole can be monitored on the spot. Using this monitoring result, it is possible to manage the plating solution inside the via that can be regarded as the plating solution inside the hole of the evaluation chip, for example, by controlling the additive.

The potential of the second electrode is, for example, −2800 mV to +240 mV, preferably −560 to +230 mV with respect to a saturated calomel electrode in order to reduce divalent copper. The potential of the first electrode is a potential capable of oxidizing monovalent copper, and is, for example, +3050 mV to +40 mV, preferably +650 to +50 mV, based on a saturated calomel electrode. These potentials are values at 25 ° C.

By controlling the concentration distribution of monovalent copper in the obtained hole to a desired range set in advance, the hole can be completely filled. Specific examples include a method of changing the replenishment amount of the inhibitor and / or accelerator to the plating solution and bubbling oxygen gas or nitrogen gas.

Moreover, the electrolytic copper plating solution which is the object of the present invention contains a divalent copper salt, an acid, and an electrically conductive salt as basic components, and contains an inhibitor, an accelerator, a smoothing agent, and the like as additives. Examples of the basic component divalent copper salt include copper sulfate. The concentration of copper sulfate (pentahydrate) is 2 to 300 g / L. Examples of the basic component acid include sulfuric acid. The concentration is 1 to 300 g / L of sulfuric acid. Moreover, as an electroconductive salt of a basic component, sodium chloride can be mentioned, for example. The concentration is 1 to 1000 mg / L of chloride ion.

Moreover, a polyether compound can be used as the inhibitor. Polyethylene glycol (molecular weight 200 to 10000) or a copolymer of polyethylene glycol and polypropylene glycol (molecular weight 400 to 10000) is preferable. The amount added is 10 to 1000 mg / L. Moreover, SPS can be used as an accelerator. The addition amount is 0.01 to 50 mg / L.

Hereinafter, the present invention will be described in more detail with reference to examples.

Example 1
(Production of evaluation chip)
The first electrode, the electrode pad, and the wiring formed in the pattern shown in FIG. 2 were formed by performing platinum sputtering on the entire surface of the silicon substrate and using a photolithography method in which resist coating, exposure, development, and etching were performed. The size of the first electrode was 5 × 5 μm, and the distance between the first electrodes was 5 μm. The size of the electrode pad was 5 × 5 mm, and the interval was 5 mm. The wiring width was 3 to 5 μm. In addition, a SiO ₂ layer was formed on the substrate excluding the first electrode and the electrode pad by using plasma CVD.

As the second substrate, a silicon substrate cut into an 8-inch rectangular parallelepiped shape was used. After forming the resist pattern, a groove having one end closed by etching and the other end opened was formed. After forming a copper layer by vacuum deposition on the groove bottom surface and groove side surface, the resist layer was removed. The size of the groove is 10 μm wide, 50 μm long, and 10 μm deep. The opening area of the hole formed by bonding to the substrate is 10 μm × 10 μm and 100 μm ² . The formed copper layer has a thickness of 0.1 μm.

An evaluation chip was fabricated by bonding the second substrate having the groove formed thereon to the substrate using an adhesive. The evaluation chip has a size of 20 × 20 mm and a thickness of 2 mm.

(Evaluation methods)
For electrochemical measurement, an electrochemical measurement system HZ-7000 manufactured by Hokuto Denko was used. As the working electrode, the prepared evaluation chip (size: 20 × 20 mm, thickness: 2 mm) was used. Further, a copper electrode was used as the counter electrode, and a saturated calomel electrode (hereinafter abbreviated as SCE) was used as the reference electrode. An evaluation chip, a counter electrode, and a reference electrode were immersed in a plating tank containing a plating solution, and measurement was performed while stirring the plating solution using a magnetic rotor. The temperature of the plating solution was kept at 25 ° C.

The composition of the plating solution used is as follows.
_{_{CuSO 4 · 5H 2 O: 200g}} / L
H ₂ SO ₄ : 25 g / L
Cl ⁻ : 70 mg / L
SPS (bis- (sulfopropyl) disulfide): 2 mg / L

The five first electrodes of the evaluation chip were connected to the switching device. The switching device was connected to the ring electrode terminal of HZ-7000, and the potential of the first electrode was set to 500 mV (SCE standard). The second electrode of the evaluation chip was connected to a disk electrode terminal of HZ-7000. The potential of the second electrode was maintained at −50 mV (SCE standard) for 30 seconds to precipitate copper, and then maintained at 100 mV (SCE standard) for 45 milliseconds to dissolve the copper. By switching the five first electrodes with the switching device, the oxidation current of monovalent copper was measured using each first electrode.

(result)
FIG. 6 shows oxidation current values of monovalent copper (hereinafter also referred to as oxidation current values) measured at three different first electrodes. “1”, “2”, and “3” in FIG. 6 correspond to the measured currents at the

first electrodes

3e, 3c, and 3a in FIG. 3, respectively, and oxidation at the bottom, middle, and inlet portions of the holes, respectively. Indicates the current value. The oxidation current value is given by the peak value indicated by the arrow in FIG. 6, and the scale is over at the place of “1”, and the oxidation current value increases from the entrance to the bottom of the hole, that is, monovalent copper. The concentration is high. This indicates that it is possible to monitor the concentration distribution of monovalent copper in a hole such as a via by using the evaluation chip of the present invention.

By using the electrolytic copper plating solution evaluation system of the present invention, it becomes possible to monitor the concentration distribution of monovalent copper in holes such as vias. Therefore, such as via fill plating process, copper damascene process, TSV plating process, etc. Management of the plating solution is facilitated and occurrence of defects can be suppressed.

1

Substrate

2a, 2b, 2c, 2d, 2e

First electrode pad

3a, 3b, 3c, 3d, 3e

First electrode

4a, 4b, 4c, 4d, 4e

First electrode pad

5a, 5b, 5c, 5d, 5e First electrode 6 Wiring 7 Second substrate 8 Groove 81 Groove bottom 82 Groove side 9 Bottomed hole 91 First side wall 92 Second side wall 921 Groove bottom 922 Groove side 10 Second electrode 101 Side electrode 11

Insulating layer

12a, 12b, 12c, 12d, 12e Second electrode lead 13 First electrode pad 14 First electrode lead 21 Chip for electrolytic copper plating solution 22 Reference electrode 23 Anode 24 Current potential setting measuring device 25 Plating tank 26 Plating solution

Claims

An electrolytic copper plating solution evaluation chip having a hole, one or more first electrodes formed on the side wall in the hole, and a second electrode formed on the side wall in the hole;
A reference electrode;
An anode,
A current potential setting measuring device connecting the first electrode, the second electrode, the anode, and the reference electrode;
An electrolytic copper plating solution evaluation system in which a copper plating reaction is caused by the second electrode and the concentration of monovalent copper is measured by the first electrode.
An electrolytic copper plating solution evaluation method using the electrolytic copper plating solution evaluation system according to claim 1,
Immerse the tip for electrolytic copper plating solution in electrolytic copper plating solution,
Divalent copper is reduced at the second electrode,
The evaluation method of measuring the concentration of monovalent copper while maintaining the potential of the first electrode at a potential capable of oxidizing monovalent copper.
An electrolytic copper plating solution evaluation chip having a hole, one or more first electrodes formed on the side wall in the hole, and a second electrode formed on the side wall in the hole.
4. The evaluation chip according to claim 3, wherein the surface area of one of the first electrodes is 25 cm 2 to 1 × 10 −16 cm 2 .
The evaluation chip according to claim 3 or 4, wherein the first electrode is made of a noble metal.
The evaluation chip according to any one of claims 3 to 5, wherein the second electrode is made of copper.
The hole is formed by joining a second substrate having a groove on one main surface to an upper surface of the first substrate with the one main surface facing each other via an insulating layer. 7. The evaluation chip according to any one of 6 above.
8. The evaluation chip according to claim 7, wherein the one or more first electrodes are formed on an upper surface of the first substrate facing the groove, and the second electrode is formed on an inner surface of the groove.