KR100803004B1 - Method for filling through hole - Google Patents

Abstract

A method for filling through holes is provided to prevent inlets of the through holes from be excessively coated, perform filling of a filling material into the through holes more compactly, and enhance adhesion of the filling material with inner walls of the through holes. As a method for filling a conductor in through holes formed in a substrate, the method for filling the through holes comprises: (a) a seed layer forming step(S100) of depositing conductive metal onto portions of inner wall surfaces of the through holes to form a seed layer; (b) a plugging step(S200) of performing an electroplating operation to fill portions of the through holes with a conductor; and (c) a growing step(S300) of performing the electroplating operation to fill residual portions of the through holes with the conductor. The step(a) is carried out by depositing conductive metal onto one face of the substrate. The step(a) comprises controlling deposition thickness of the conductive metal deposited onto the one face of the substrate to control depth of the seed layer formed on the inner wall surfaces of the through holes. The step(b) is conducted by controlling a current density applied to both faces of the substrate.

Description

Through Hole Filling Method {Method for filling through hole}

1 is a view showing a through hole filling method according to the prior art.

Figure 2 is a schematic diagram showing a through hole filling method according to an embodiment of the present invention.

Figure 3 is a state diagram showing a through electrode formed by the plugging step and the drawing step according to an embodiment of the present invention.

4 is a cross-sectional view of a substrate on which a seed layer according to a first embodiment of the present invention is formed.

5 is a view showing an electroplating apparatus according to a first preferred embodiment of the present invention.

6 shows a plug formed by a plugging step according to a first preferred embodiment of the invention;

7 is a view for explaining an increase amount of the depth of the plug according to the first embodiment of the present invention.

8A and 8B illustrate plug states according to charge amounts during a plugging step according to a first embodiment of the present invention.

9 is a view showing a state of filling by the drawing step from the plug (maximum current density 6mA / cm ² ) formed in the bottom of the through-hole according to the first embodiment of the present invention.

10 is a view showing a state of filling by the drawing step from the plug (maximum current density 4mA / cm ² ) formed in the bottom of the through-hole according to the first embodiment of the present invention.

11 is a view showing a state of filling by the drawing step from the plug (maximum current density 6mA / cm ² ) formed in the center of the through-hole according to the first embodiment of the present invention.

12 is a view showing a state of filling by the drawing step from the plug formed on the top of the through-hole according to the first embodiment of the present invention.

13 is a view showing the formation state of the seed layer according to a second embodiment of the present invention.

14A and 14B show a plug formed by a plugging step according to a second preferred embodiment of the present invention.

FIG. 15 is a view illustrating a filled state of a through hole according to a third exemplary embodiment of the present invention. FIG.

16 is a flow chart showing a through-hole filling method according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

2 substrate 4 through hole

6: seed layer 8: through electrode

10: silicon wafer 12a, 12b, 12c: plug

14a, 14b: copper plate 16: plating solution

18a, 18b: anode 20: cathode

22a, 22b: rectifier 24: void

The present invention relates to a through-hole filling method by electroplating.

With the development of the electronics industry, portable electronic products such as mobile phones and DMB (Digital Multimedia Broadcasting) are becoming smaller and more functional. Accordingly, electronic components are also required to be miniaturized, highly integrated, multifunctional, and high performance. One of the key technologies that enables this product development goal is package assembly technology.

Chip-scale package as a package assembly technology is a new type of package that has been recently developed and proposed, and has the advantage of greatly reducing the size of a package compared to a typical plastic package.

Chip-scale packages are mainly used in products requiring miniaturization and mobility, such as digital camcorders, mobile phones, notebook computers, memory cards, and so on, and include digital signal processors (DSPs), application specific integrated circuits (ASICs), and microcontrollers (microcontrollers). Semiconductor devices such as controllers are mounted in chip-scale packages. In addition, the use of chip-scale packages in which memory devices such as dynamic random access memory (DRAM), flash memory, and the like are mounted is increasingly being used.

However, while the chip scale package has an absolute advantage in terms of size, it is difficult to secure reliability and additional manufacturing equipment is required for the manufacture of the chip scale package. There is a downside to falling.

In order to solve this problem, chip-scale packages are emerging at the wafer level. In a typical wafer fabrication process, when a semiconductor wafer is manufactured, individual chips are separated from the wafer and subjected to a package assembly process. This package assembly process is completely separate from the wafer fabrication process and requires different equipment and raw materials. However, it is possible to produce a package as a complete product at the wafer level, i.e. without separating individual chips from the wafer. Therefore, the existing wafer manufacturing equipment and processes can be used as it is in the manufacturing equipment or manufacturing process used to manufacture the package. This also means that it is possible to minimize the additional raw materials required to manufacture the package. In addition, a stack package in which a chip scale package manufactured at the wafer level is stacked in three dimensions is also emerging.

In order to stack the chip scale packages manufactured at the wafer level in three dimensions, electrical connections are required between the chip scale packages arranged up and down. For this purpose, it is necessary to form a hole penetrating the semiconductor wafer and to form a through electrode in the hole. As described above, the through hole required for stacking the chip scale package in three dimensions at the wafer level has a large aspect ratio compared to the printed circuit board (PCB) due to the high integration and density of electronic components. It is very difficult to fill through electrodes without voids or cracks in the through holes.

1 is a view showing a through hole filling method according to the prior art. Referring to FIG. 1, a substrate 102, a through hole 104, a blind via 106, a metal plate 110, a conductive adhesive 112, and a through electrode 114 are illustrated.

Referring to FIG. 1, a conventional method of filling a through electrode 114 in a through hole 104 by electroplating is described. According to a method of forming a seed layer in the through hole 104, a through hole ( In the step of forming 104, the through-hole 104 is not completely drilled, an unthrough hole (hereinafter referred to as a "blind via hole") is formed, and a seed layer is formed on the inner surface of the unthrough hole, and the through hole is electroplated. After the bottom surface of 104 is filled with a conductor, a method of forming a through electrode by removing the substrate 102 that has not been penetrated by an etching process or chemical mechanical polishing (CMP) (FIG. a)), and the metal plate 110 or the foil is directly attached to one side of the substrate 102 on which the through hole 104 is formed and used as a seed layer, or one side of the substrate 102 is used as a seed layer. Apply, or apply conductive adhesive, tape, etc. 110 and the air pad portion of the metal foil there is a method of filling a conductor by the through holes 104 by using as a seed layer for electroplating ((b) in Fig. 1). In another method, a photoresistor is applied to one surface of the substrate 102 to cover the entire surface of one side of the substrate 102, and then a metal thin film is formed through sputtering or evaporation, and then an ashing process is performed. After removing the photosensitive agent exposed from the through-hole 104 through, the electroplating is performed using a seed layer to fill the entire through-hole 104 with a conductive metal (Fig. 1 (c)) and the like have.

When the conductive metal is filled in the entire through hole 104, the seed layer and the overplating portion formed on one surface of the substrate 102 are removed to complete the through electrode.

The filling method of the through hole 104 by electroplating according to the prior art is to perform electroplating with a seed layer. In the filling direction, plating is performed from the surface of the substrate 102 on which the seed layer is formed so that the seed layer is not formed. It is filled in one direction toward the substrate 102 surface.

However, the through-hole filling method according to the prior art is filled in one direction, so the process is simple and there is little possibility of voids or cracks, but the first method described above is an aspect ratio. ), It is difficult to apply, and the seed layer must be formed on the entire surface of the via via hole. If a defect occurs in forming the seed layer, defects may occur in electrode filling. In the second method, the seed layer metal layer is applied to the substrate 102. When the conductive adhesive 112 for adhering the metal layer is introduced into the through hole 104 by the capillary phenomenon, defects may occur in the adhesion between the wall of the through hole 104 and the through electrode 114. There is concern. In addition, in the third method, since a seed layer is formed on one surface of the substrate 102 and filling of the through hole 104 is made therefrom, there is little possibility that voids or gaps occur, but the surface of the substrate 102 may be formed. The seed layer and the plating layer due to the electroplating are formed thick, and there is a problem that a defect occurs in adhesion between the inner wall of the through hole 104 and the filler.

In addition, the through-hole filling method according to the prior art causes an unnecessary increase in the copper plating layer on the pattern, and the increase in the plating layer causes the warpage of the wafer to cause a change in the aperture size of the through-hole after the CMP process. There was a problem that the through-hole of can be formed.

The present invention forms a seed layer on part or all of the inner wall surface of the through-hole, and varies the current density between one side and the other side of the substrate during electroplating, and also performs plating by dividing the electroplating process into two steps. It is to provide a through-hole filling method that can prevent excessive plating concentration on the through hole and make the filling of the through hole more tightly, and improve the adhesion between the inner wall of the through hole and the filling material.

According to an aspect of the present invention, a method of filling a through hole formed in a substrate with a conductor, the method comprising: (a) forming a seed layer on the inner wall surface of the through hole; There is provided a through hole filling method including a plugging step of filling a part of a hole with a conductor and a growing step of filling the remaining part of the through hole with a conductor by performing a plating step (c).

Step (a) may be performed such that the seed layer is formed on a part of the inner wall surface of the through hole. In addition, step (a) may be performed by depositing a conductive metal on one surface of the substrate, and may control the depth of the seed layer formed on the inner wall surface of the through hole by adjusting the deposition thickness of the conductive metal.

The conductive metal may include at least one of copper (Cu), chromium (Cr), nickel (Ni), silver (Ag), gold (Au), and aluminum (Al).

Step (b) may be performed by adjusting the current density applied to both sides of the substrate.

The substrate may include at least one of a silicon wafer, a high resistance silicon wafer, polycrystalline silicon, glass, and a ceramic substrate.

The conductor may include at least one of copper (Cu), chromium (Cr), nickel (Ni), silver (Ag), gold (Au), and aluminum (Al).

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

Hereinafter, preferred embodiments of the through-hole filling method according to the present invention will be described in detail with reference to the accompanying drawings, in the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and Duplicate explanations will be omitted.

Figure 2 is a schematic diagram showing a through-hole filling method by electroplating according to an embodiment of the present invention. Referring to FIG. 2, a substrate 2, a through hole 4, a seed layer 6, a plug 12b, and a through electrode 8 are illustrated.

According to the present invention, the seed layer 6 is formed on one surface of the substrate 2 and part or all of the inner wall surface of the through-hole connected to one surface thereof, and then the current density applied to one surface and the other surface of the substrate 2 during electroplating. In addition, the electroplating process is divided into two stages of a plugging step and a plugging step to perform plating to reduce the overplating layer, and there are no gaps and gaps in the filler. It is to provide a through-hole filling method that can improve the adhesion between the through-hole inner wall and the filling body.

As the substrate 2 used in the present embodiment, not only silicon wafers, high resistance silicon wafers, polycrystalline silicon, glass, ceramics, etc. used in the manufacture of semiconductor devices, but also PCB substrates can be used.

The through holes formed in the substrate 2 may be processed using a CNC (Computer Numerical Control) drill or a laser, or the substrate 2 which may be etched by a reactive ion etching (RIE) forms fine through holes by dry etching. In this case, the diameter of the applicable through hole may be several to several hundred μm.

In the present invention, the seed layer 6 means a layer which becomes an electrode for electroplating in a subsequent electroplating process.

The seed layer 6 is formed by depositing a metal thin film (for example, a conductive metal such as Cu, Cr, Ni, Ag, Au, Al, etc.) through a sputtering process, an evaporation process, or the like.

In the present embodiment, the seed layer 6 is formed on one side of the substrate 2 and part or all of the inner wall surface of the through-hole connected to the one side of the substrate 2, and then the current density of both sides of the substrate 2 is adjusted in the plugging step. You can adjust the position. In this case, when the depth of the seed layer 6 formed on the inner wall surface of the through hole is changed, the filling property by plating of the through hole in the electroplating process is changed.

The seed layer 6 is formed on one surface of the substrate 2 and through holes connected to the one surface of the substrate 2 by sputtering and evaporating on one surface of the substrate 2 on which the through holes are formed. The depth of the seed layer formed on the inner wall surface of the through hole on one surface of the substrate 2 may be controlled by adjusting the deposition height of the seed layer formed on one surface of the substrate 2.

When the seed layer 6 is formed, primary electroplating is performed with the electrode, which is referred to as a plugging step in the present invention. The plugging step is a process of forming a plug which becomes a reference for forming the through electrode 8 by completely filling the through holes. The position of the plug may be formed at the top, center, or bottom of the through hole by adjusting the current density of one surface and the other surface of the substrate 2 in the electroplating bath.

When the plug is formed in the through hole, secondary electroplating is performed, which is referred to as a growing step in the present invention. In the drawing step, the plating is grown based on the plug formed in the plugging step to fill the through holes to form the through electrodes 8. The through hole is filled by adjusting the current densities of one surface and the other surface of the substrate 2 according to the position of the plug formed in the through hole. In the filling direction according to the present invention, the filling is made in one or two directions based on the plug, unlike the filling in one direction.

When the conductive metal is filled in the entire through hole, the seed layer and the overplating portion formed on one surface of the substrate 2 are removed to complete the through electrode 8.

3 is a state diagram showing a through electrode formed by a plugging step and a drawing step according to a preferred embodiment of the present invention. Referring to FIG. 3, a silicon wafer 10, plugs 12a, 12b, 12c, and through electrode 8 are shown.

In this embodiment, a copper electroplating method using a copper (Cu) to fill the through hole is used.

FIG. 3A illustrates a state in which a through hole is filled by a drawing step after the plug 12a is formed in one direction of the substrate (upper through hole in the drawing) by the plugging step. b) shows the state in which the through hole is filled by the drawing step after the plug 12b is formed in the center of the through hole by the plugging step, and FIG. 4C shows the lower portion of the through hole by the plugging step (c). After the plug 12c is formed in a direction opposite to one surface of the substrate on which the seed layer is formed, the through hole is filled by the drawing step.

As such, by dividing the electroplating process into a plugging step and a drawing step, it is possible to prevent excessive plating concentration at the entrance of the through hole, to make the filling of the through hole more tight, and to adhere to the inner wall of the through hole and the through electrode 8. To increase.

The plugging step is performed by placing a substrate to be filled with through holes in the electroplating bath and then changing current densities on both sides of the substrate.

4 is a cross-sectional view of a substrate on which a seed layer according to a first embodiment of the present invention is formed. Referring to FIG. 4, a silicon wafer 10, seed layer 6 is shown.

In this embodiment, titanium (Ti) is deposited to 500 Å (1Å = 10 ^-10 m = 10 ^-1 nm) on one surface of a substrate having a through hole having a diameter (d) of 80 μm and a depth of 300 μm. In the case of depositing gold (Au) at 2000 μs, the seed layer 6 formed on one surface of the substrate and the inner wall surface of the through hole is formed. In this case, the seed layer 6 is formed up to about half of the depth of the through hole. As the substrate used in the present embodiment, a 4 inch silicon wafer 10 (P type) used for manufacturing a semiconductor device was used.

When the depth of the through-hole divided by the diameter of the through-hole is called an aspect ratio, it can be seen that the aspect-ratio of this embodiment is about 3.75, which is a through-hole having a very high aspect ratio.

The seed layer 6 is formed on one surface of the substrate and through holes connected to one surface of the substrate by sputtering and evaporating on one surface of the substrate on which the through holes are formed. To form on the wall.

The depth at which the seed layer 6 is formed on the inner wall of the through hole depends on the deposition height of the seed layer 6 on one surface of the substrate. For example, the diameter (d) is 80 μm and the depth (l) is 300 μm. On one surface of the substrate with phosphorus through-holes, titanium (Ti) was deposited to a thickness of 50010 (1Å = 10 ^-10 m = 10 ^-1 nm), and gold (Au) was deposited to 7000Å and over the entire depth of the through-hole. Layer 6 is formed.

5 is a view showing an electroplating apparatus according to a first embodiment of the present invention. Referring to FIG. 5, the silicon wafer 10, the copper plates 14a and 14b, the plating solution 16, the anodes 18a and 18b, the cathode 20, and the rectifiers 22a and 22b are illustrated.

In this embodiment, since the copper electroplating method is used, the electroplating baths are placed by placing (14a, 14b) at both ends of the electroplating bath containing copper salts, and placing the silicon wafer 10 to be plated at the center of the electroplating bath. do.

The copper plate 14a disposed on the left side of the figure is used as an anode 18a, and the seed layer formed on the substrate is connected to one rectifier 22a using a cathode 20 as a cathode. The current density on both sides of the electroplating bath divided by the substrate is controlled by connecting the copper plate 14b disposed as the anode 18b and the seed layer as the cathode 20 to another rectifier 22b. Can be.

The plugging step may form a plug by electroplating at the top, the center, or the bottom of the through hole by adjusting the current density in the electroplating bath divided into two surfaces of the substrate in the above-described electroplating bath. This will be described in detail with reference to FIGS. 6 and 7 below.

In the drawing step, when a plug is formed in the through-hole, a different current density is applied to fill the remaining portion of the through-hole. This will be described in detail with reference to FIG. 9 below.

6 is a view showing a plug formed by the plugging step according to the first embodiment of the present invention, Figure 7 is a view for explaining the increase in the depth of the plug according to a preferred embodiment of the present invention. 6 and 7, a silicon wafer 10, plugs 12a, 12b, 12c are shown.

The substrate used in this embodiment is a 4 inch silicon wafer 10 (P type) having a through hole having a diameter (d) of 80 µm and a depth (l) of 300 µm. When gold (Au) is deposited on one side of the wafer at 2000 microseconds, the seed layer is formed to approximately half the depth of one side of the silicon wafer 10 and the depth of the through hole. In this case, the aspect ratio of the through hole is about 3.75, which has a very high aspect ratio.

The plating solution used for electroplating was 250 g / L for copper sulfate (CuSO ₄ · 5H ₂ O), 30 g / L for sulfuric acid (H ₂ SO ₄ ), 40 ppm of hydrochloric acid (HCL), and Ebara Co..LTD as an additive. Inc. was added.

The electroplating conditions of the present embodiment is a copper plate containing phosphorus (P) as an anode, the experimental temperature is 25 ℃, 10 liters of air per minute (Air 10 LPM (Liter Per) to stir the plating solution Minute)).

In the present invention, the current density applied from the electroplating bath in one surface direction of the silicon wafer 10 on which the seed layer is formed is called the first current density, and is applied to the other surface direction of the silicon wafer 10 on which the seed layer is not formed. The current density is referred to as a second current density, and the ratio of the first current density to the second current density is referred to as a current density ratio. In addition, for convenience of description, the 'top (or top) of the through hole' refers to a portion of the through hole in one direction of the substrate on which the seed layer is formed, and 'the bottom (or bottom) of the through hole' does not form the seed layer. It means a through-hole portion in the other surface direction of the substrate.

The plugging step may form the plugs 12a, 12b, and 12c by electroplating at the top, center, or bottom of the through hole by adjusting the current density ratio.

In Figure 6 (a '), (b ') and (c ') line of a case where the maximum current density to be applied to Article electrolytic plating, respectively above, respectively ^{8mA / cm 2, 6mA / cm} 2 and 4mA / cm ² In Fig. 6, columns (a), (b) and (c) indicate that the ratio of the first current density and the second current density is 0.5: 1, 2: 1, and 4: 1, respectively, according to the maximum current density. The plug 12a, 12b, 12c formed in the through-hole in the case is shown. For example, the drawings located in rows (a ') and (a) of FIG. 6 show the first current density as 4 mA / cm ² and the second current density as 8 mA / cm ² , the maximum current density applied to the electroplating bath. When applied, the state of the plugs 12a, 12b, and 12c formed in the through-holes is shown, and the diagrams located in rows (c ') and (c) of FIG. 6 show a first current density of 4 mA / cm ² . , The state of the plugs 12a, 12b, 12c formed in the through-holes when the second current density is applied at 1 mA / cm ² according to the current density ratio 4: 1.

As shown in FIG. 6, when the maximum current density to be applied is 6 mA / cm ² , the plugs 12a, 12b, and the top, center, and bottom of the through-holes have current density ratios of 0.5: 1, 2: 1, and 4: 1. 12c) is formed. In addition, when the maximum current density applied is 8mA / cm ² , the plug 12c is formed in the lower portion of the through hole at a current density ratio of 0.5: 1, even if the maximum current density is 6mA / cm ² , the current density ratio is 0.5: At 1, a plug 12c is formed at the bottom of the through hole.

7 shows the position and thickness (y-axis of FIG. 7) at which the plugs 12a, 12b, and 12c are formed in the through-holes according to the change of the current density ratio (x-axis of FIG. 7).

6 the current density ratio is 0.5 (in FIG. 6 (a) columns) 1 and (a) of the figure of the case of applying the maximum current density to ^{8mA / cm 2, 6mA / cm} 2 and 4mA / cm ² (Fig. 6 As shown in the columns (a '), (b') and (c ')) and FIG. 7, the second current density is 8 mA / cm ² and 6 mA / cm when the current density ratio is 0.5: 1. ^As it decreases to ² , 4 mA / cm ² , the plugs 12a, 12b, and 12c are formed from the bottom of the through-hole to the center and the top.

8A and 8B illustrate plug states according to charge amounts during a plugging step according to a first embodiment of the present invention. Referring to FIG. 8, a silicon wafer 10, plugs 12a, 12b, 12c are shown.

(A1), (a2) and (a3) of FIG. 8A show that when the maximum current density applied is 6 mA / cm ² and the ratio of the first current density and the second current density is 0.5: 1, the amount of charge is 4 A.Hr, In the case of 5 A.Hr and 6 A.Hr, the states of the plugs 12a, 12b, and 12c are shown. In Figs. 8A (b1), (b2) and (b3), the maximum current density to be applied is 6 mA / In the case where cm ² and the ratio of the first current density to the second current density are 4: 1, the states of the plugs 12a, 12b, and 12c are shown when the charge amounts are 4 AHr, 5 AHr, and 6 AHr, respectively. Doing.

As shown in FIGS. 8A and 8B, as the supply time of the applied current becomes longer, the amount of charge in the electroplating bath increases, and thus the plug 12c formed from the bottom of the through hole when the current density ratio is 0.5: 1. When the thickness is increased and the current density ratio is 4: 1, the plug 12a is thinly formed on the top of the through hole, and a plating layer is formed along the seed layer, so as to form a blind via hole having a sharp end. These pointed areas are difficult to fill completely by the growing step. In this case, however, it is possible to apply a substrate that requires only conduction of the upper and lower surfaces of the substrate without requiring full filling. In particular, when the current density ratio is 4: 1, the filling by plating is performed on the inner wall of the through hole where the seed layer is not formed.

FIG. 9 is a view showing a state of filling by a drawing step from a plug (maximum current density of 6 mA / cm ² ) formed under the through hole according to the first embodiment of the present invention. Referring to FIG. 9, a silicon wafer 10, through electrodes 8, and voids 24 are shown.

During the plugging step, the drawing step is performed to fill the rest of the through holes based on the plugs formed at the bottom of the through holes.

FIG. 9 (a) shows that the maximum current density applied during the plugging step described above is 6 mA / cm ^2, and the ratio of the first current density to the second current density is 0.5: 1 and the charge amount is 4 A · Hr. The plug 12c formed in the lower end of the hole is shown. When the plug 12c is formed as described above, the through electrode is formed by filling the remaining portion of the through hole by the drawing step based on the plug 12c.

FIG. 9 (b) shows that the current density of the electroplating bath is 3 mA / cm ² , and a charge amount of 2 A · Hr is introduced, and the drawing step is performed while spraying 5 liters of air per minute (5 LPM) for stirring the plating solution. The filling state of the through-holes in the case of performing the above is shown, and FIG. 9 (c) shows a charge amount of 2 A · Hr with a current density of 3 mA / cm ² and injects 10 liters of air per minute to stir the plating solution. (10 LPM) shows the filling state of the through-holes when the drawing step is performed. In addition, Fig. 9 (d) shows the filling of the through-holes in the case where the drawing step was performed while the charge amount of 1.5 A · Hr was injected with the current density as ² mA / cm ² and 5 LPM of air was injected per minute (5 LPM). It shows the state.

Referring to (b), (c) and (d) of FIG. 9, the stirring of the plating liquid in the range of 5 to 10 LPM has no effect on the filling, and when the current density is applied at 3 mA / cm ² , the voids in the filling body ( void, 24) is formed, and the void 24 does not occur when a current density of ² mA / cm ² is applied. However, the current application time is somewhat increased for complete filling.

10 is a view showing a state of filling by the drawing step from the plug (maximum current density 4mA / cm ² ) formed in the bottom of the through-hole according to an embodiment of the present invention. Referring to FIG. 10, a silicon wafer 10, a plug 12c, and a through electrode 8 are shown.

(A), (b) and (c) of FIG. 10 show that when the maximum current density applied in the plugging step is 4 mA / cm ² and the ratio of the first current density and the second current density is 0.5: 1, the amount of charge is 2, respectively. The plug 12c formed of the through hole when A · Hr, 3A · Hr, and 4A · Hr is shown, and FIGS. 10 (d) and 10 (e) show the upper direction of the through hole (the direction in which the seed layer is formed). The current density is 5 mA / cm ² , and the filling state of the through-holes is shown in the drawing step when the charge amounts are 1 A.Hr and 2 A.Hr, respectively. As shown in FIG. 10, although there is no void in the through electrode 8, a plating layer may be formed on one surface of the silicon wafer 10 to improve the phenomenon of concentration of additives in the plating solution. The thickness of the plating layer can be lowered.

FIG. 11 is a view showing a filling state by a drawing step from a plug (maximum current density of 6 mA / cm ² ) formed in the center of a through hole according to a first embodiment of the present invention. Referring to FIG. 11, a silicon wafer 10, a plug 12b, and a void 24 are shown.

11 (a) and 11 (b) show that when the maximum current density applied in the plugging step is 6 mA / cm ² and the ratio of the first current density and the second current density is 2: 1, the amount of charge is 4 A.Hr and In the case of 5 Ar, the plug 12b formed of the through hole is shown, and Figs. 11C and 11D show the filling state of the through hole by the drawing step when the charge amount is 2A · Hr, respectively.

When the plug 12b is formed in the center of the through-hole, it is difficult to completely fill the remaining part of the through-hole by the drawing step, so the reproducibility is low. In this case, it is possible to apply a substrate that requires only conduction of the upper and lower surfaces of the substrate without requiring full filling.

12 is a view showing a state of filling by the drawing step from the plug formed on the top of the through-hole according to the first embodiment of the present invention. Referring to FIG. 12, a silicon wafer 10, a plug 12a, a through electrode 8, and a void 24 are shown.

FIG. 12A shows the state of the plug 12a formed on the upper portion of the through hole by the above plugging step. As shown in (a) of FIG. 12, the plug 12a is thinly formed on the top of the through hole, and a plating layer is formed along the seed layer, as if a blind via hole having a sharp tip is formed. It is difficult to form the through electrode 8 by completely filling the pointed portion by the drawing step. In this case, it is possible to apply a substrate that requires only conduction of the upper and lower surfaces of the substrate without requiring full filling.

FIG. 13 is a view showing a formation state of a seed layer according to a second embodiment of the present invention. FIG. Referring to FIG. 13, a silicon wafer 10, seed layer 6 is shown.

In the present embodiment, the components other than the forming process and the plugging step of the seed layer 6 are as described in the first embodiment, and the description thereof will be omitted in the present embodiment.

In this embodiment, the thickness of titanium (Ti) is 500Å (1 m = 10 ^-10 m = 10 ^-1 nm) on one surface of the silicon wafer 10 having a through hole having a diameter d of 80 μm and a depth of 300 μm. When the gold (Au) is deposited at 7000 Å, the seed layer 6 formed on one surface of the silicon wafer 10 and the inner wall surface of the through hole is formed. In this case, the seed layer 6 is formed over the entire length of the through hole.

When the depth of the through-hole divided by the diameter of the through-hole is called an aspect ratio, the aspect-ratio is about 3.75, indicating that the through-hole has a very high aspect ratio.

The seed layer 6 is formed on one surface of the substrate and through holes connected to one surface of the substrate by sputtering and evaporating on one surface of the substrate on which the through holes are formed. To form on the wall.

The depth at which the seed layer 6 is formed on the inner wall surface of the through-hole depends on the deposition height of one surface of the substrate. For example, a substrate having a through-hole having a diameter d of 80 μm and a depth l of 300 μm is formed. In one side, when titanium (Ti) is deposited to a thickness of 500 kW (1Å = 10 ^-10 m = 10 ^-1 nm) and gold (Au) is deposited to 2000 mW, it is formed to about half of the depth of the through hole.

14A and 14B show plugs formed by a plugging step according to a second preferred embodiment of the present invention. 14A and 14B, a silicon wafer 10, plugs 12a, 12b, 12c are shown.

The substrate used in this embodiment is a 4 inch silicon wafer 10 (P type) having a through hole having a diameter (d) of 80 µm and a depth (l) of 300 µm. When gold (Au) is deposited on one side of the wafer at 7000 Å, the seed layer is formed over one side of the wafer and the entire depth of the through hole. In this case, the aspect ratio of the through hole is about 3.75, which has a very high aspect ratio.

The plating solution used for electroplating was 250 g / L for copper sulfate (CuSO ₄ · 5H ₂ O), 30 g / L for sulfuric acid (H ₂ SO ₄ ), 40 ppm of hydrochloric acid (HCL), and Ebara Co..LTD as an additive. Inc. was added.

The electroplating conditions of the present embodiment is a copper plate containing phosphorus (P) as an anode, the experimental temperature is 25 ℃, 10 liters of air per minute (Air 10 LPM (Liter Per) to stir the plating solution Minute)).

The plugging step may form the plugs 12a, 12b, and 12c by electroplating at the top, center, or bottom of the through hole by adjusting the current density ratio.

In Fig. 14A, the lines (a '), (b') and (c ') represent the cases where the maximum current densities applied to the electroplating bath described above are 6 mA / cm ² , 5 mA / cm ^2, and 4 mA / cm ² , respectively. In FIG. 14A, columns (a), (b), (c), (d) and (e) have a ratio of first current density and second current density of 0.5: 1 and 1: depending on the maximum current density. The plugs 12a, 12b and 12c formed in the through holes in the case of 1, 2: 1, 3: 1 and 4: 1 are shown. For example, the drawings located in rows (a ') and (a) show that the first current density is 3 mA / cm ² and the second current density is 6 mA / cm ² , the maximum current density applied to the electroplating bath. The state of the plugs 12a, 12b, and 12c formed in the through-holes is shown. The figures located in rows (c ') and (e) of FIG. 14 show a first current density of 4 mA / cm ² and a second. The state of the plugs 12a, 12b, and 12c formed in the through-holes when the current density is applied at 1 mA / cm ² according to the current density ratio 4: 1 is shown.

FIG. 14B is a view showing the state in which the plugs 12a, 12b, and 12c are preferably formed at the top, the center, and the bottom of the through hole among plugs formed by various maximum current densities and current density ratios, as shown in FIG. It is shown.

14B (a) shows a case where the maximum current density is 4 mA / cm ² and the ratio of the first current density and the second current density is 0.5: 1, that is, the first current density is ² mA / cm ² , and 2 shows a state in which the plug 12c is formed when electroplating is performed by applying a current density of 4 mA / cm ² , and FIG. 14B (b) shows a maximum current density of 6 mA / cm ² and a first current. The plug 12b in the case where the ratio of the density and the second current density is 1: 1, that is, electroplating is performed by applying the first current density at 6 mA / cm ² and the second current density at 6 mA / cm ² . FIG. 14B (c) shows a case where the maximum current density is 6 mA / cm ² and the ratio of the first current density and the second current density is 4: 1, that is, the first current density. a shows the formation state of the plug (12a) in the case of performing electrolytic plating is applied to 6mA / cm ^2, to the second current density 1.5mA / cm ^2.

Looking at (a), (b) and (c) of Figure 14b, it can be seen that the plug 12c is formed in the upper direction from the bottom of the through hole. Therefore, as the second current density decreases, the position where the plug is formed is formed from the lower end of the through hole to the upper end.

FIG. 15 is a view illustrating a filled state of a through hole according to a third exemplary embodiment of the present invention. Referring to FIG. 15, a silicon wafer 10 and a through electrode 8 are shown.

The substrate used in this embodiment is a 4 inch silicon wafer 10 (P type, 100) having a through-hole having a diameter (d) of 50 μm and a depth (l) of 300 μm. After deposition, gold (Au) was deposited on one side of the wafer at 2000Å to form a seed layer on one side of the wafer and a part of the inner wall of the through hole. In this case, the aspect ratio of the through-hole is 6 and has a very high aspect ratio.

In the plugging step, the maximum current density applied to the electroplating bath is ² mA / cm ² , and the ratio of the first current density to the second current density is 0.5: 1, that is, the first current density is 1 mA / cm ² , The electroplating was performed by applying a second current density of 2 mA / cm ² , and the amount of charge was 3 A.Hr. The drawing step was performed by applying a current density of 1 mA / cm ² and the amount of charge by 1 A.Hr. Was performed. As described above, when the seed layer, the plugging step, and the drawing step are performed, the through hole is filled in the through electrode 8 of the through hole without gaps or cracks as shown in FIG. 15.

16 is a flowchart illustrating a through hole filling method according to an exemplary embodiment of the present invention. Referring to FIG. 16, in step S100, a seed layer is formed on part or all of the inner wall surface of the through hole formed in the substrate. The seed layer may be formed on one side of the substrate and part or all of the inner wall surface of the through hole connected to the one side of the substrate, and then the position of the plug may be adjusted by controlling the current density of both sides of the substrate in the subsequent plugging step. In this case, when the depth of the seed layer formed on the inner wall surface of the through hole is changed, the filling property by the plating of the through hole in the electroplating process is changed.

The seed layer is formed on one surface of the substrate and through holes connected to one surface of the substrate so that the metal thin film is formed on the inner wall surface of the through hole by sputtering and evaporating on one surface of the substrate where the through holes are formed. By controlling the deposition height of the seed layer, the depth of the seed layer formed on the inner wall surface of the through hole on one surface of the substrate may be controlled.

In step S200, when the seed layer is formed, primary electroplating is performed on the electrode to fill a portion of the through hole with a conductor. This is referred to as a plugging step in the present invention.

The plugging step is a process of forming a plug which becomes a reference for forming a through electrode by completely filling the through hole. The position of the plug may be formed at the top, center, or bottom of the through hole by adjusting the current density of one surface and the other surface of the substrate in the electroplating bath.

In step S300, when a plug is formed in the through hole, secondary electroplating is performed to fill the remaining part of the through hole with a conductor. This is referred to as a growing step in the present invention.

The drawing step is a step of forming a through electrode by growing a plating based on the plug formed in the plugging step to fill a through hole with a conductor. The filling characteristics of the through holes vary according to the positions of the plugs formed in the through holes.

Then, when the conductive metal is filled in the entire through hole, the through electrode is completed by removing the seed layer and the overplating portion formed on one surface of the substrate.

Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

As described above, according to the preferred embodiment of the present invention, it is possible to prevent excessive plating concentration at the inlet of the through hole, to make the filling of the through hole more tight, and to increase the adhesion between the inner wall of the through hole and the filling material.

In addition, the unnecessary copper plating layer on the pattern can be suppressed to a minimum, and the process lead time and cost can be reduced during the chemical mechanical polishing (CMP) process after the plating process to utilize the package.

In addition, by using a general dipping equipment instead of using a separate wafer plating facility or a commutation method such as a complicated pulse, DC power is used as a main control element, which reduces the process cost and changes in the pattern. Easy to optimize process conditions

Claims (8)

As a method of filling a through hole formed in a substrate with a conductor, (a) forming a seed layer by depositing a conductive metal on a portion of the inner wall surface of the through hole; (b) a plugging step of filling a part of the through hole with a conductor by performing electroplating; And (C) a through-hole filling method comprising a growing step of performing electroplating to fill the remaining portion of the through-hole with a conductor. delete The method of claim 1, Step (a) is, Through-hole filling method, characterized in that carried out by depositing a conductive metal on one surface of the substrate. The method of claim 3, Step (a) is, And a depth of the seed layer formed on the inner wall surface of the through hole by adjusting a deposition thickness of the conductive metal deposited on one surface of the substrate. The method of claim 3, The conductive metal filling method comprises at least one of copper (Cu), chromium (Cr), nickel (Ni), silver (Ag), gold (Au) and aluminum (Al). The method of claim 1, Step (b) is, Through-hole filling method, characterized in that performed by adjusting the current density applied to both sides of the substrate. The method of claim 1, The substrate is a through-hole filling method comprising at least one of a silicon wafer, a high resistance silicon wafer, polycrystalline silicon, glass, a ceramic substrate. The method of claim 1, The conductor, A through-hole filling method comprising at least one of copper (Cu), chromium (Cr), nickel (Ni), silver (Ag), gold (Au), and aluminum (Al).

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