JP6216522B2 - A method for manufacturing an interposer substrate. - Google Patents

Description

  The present invention relates to a method for manufacturing an interposer substrate. In particular, the present invention relates to a method for manufacturing an interposer substrate that is used for a three-dimensional mounting device that penetrates a semiconductor chip and leads an electrode to the back surface, an extraction electrode of a Si interposer, or a MEMS device.

  In recent years, electronic devices have been increased in density and size, and LSI chips have been reduced to the same extent as semiconductor packages. Densification only by arranging LSI chips two-dimensionally is reaching its limit. Therefore, in order to increase the packaging density, it is necessary to divide LSI chips and stack them three-dimensionally. Further, in order to operate the entire semiconductor package in which LSI chips are stacked at high speed, it is necessary to bring the stacked circuits closer together and to shorten the wiring distance between the stacked circuits.

  Therefore, in order to meet the above requirements, Patent Document 1 discloses a technique for manufacturing a through electrode substrate having a conducting portion that conducts the front and back of the substrate as an interposer between LSI chips. According to the example of Patent Document 1, the through electrode substrate is formed by filling copper into the through hole provided in the substrate without voids by an electrolytic plating method using a plating solution containing copper sulfate.

JP 2006-147971 A

  In general, when the thickness of the substrate is increased, there is a problem that the time for electrolytic plating required to fill the through hole with the conductive material is increased. Such a problem may also occur in a bottomed hole (hereinafter sometimes referred to as a bottomed hole) where the hole does not penetrate. In addition, an additive may be added to the electrolytic plating solution to shorten the time. However, additives are generally expensive and result in increased costs.

  Therefore, the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique for improving the deposition property of a metal material in a hole formed in a substrate.

  As one embodiment of the present invention, it has a first surface and a second surface, and a through hole penetrating the first surface and the second surface or a bottomed hole in the second surface. Preparing the formed substrate, disposing a seed layer on the substrate, and performing an electroplating method of supplying power to the seed layer in a state in which the substrate on which the seed layer is formed is in contact with a plating solution, Provided is a method for manufacturing an interposer substrate, comprising filling a metal material into a through-hole or the bottomed hole, wherein the plating solution contains ions of a metal to be deposited and tin ions. .

  According to this method for manufacturing an interposer substrate, it is possible to improve the depositability of the metal material into the holes formed in the substrate. As a result, the metal material can be filled into the holes at high speed.

  The metal ions may be copper ions.

  Thereby, the manufacturing cost of wiring etc. can be reduced.

  The tin ions may be obtained by dissolving tin chloride.

  Thereby, a stable electrolytic plating method can be performed.

  The plating solution may further contain a carboxylic acid.

  Thereby, a stable electrolytic plating method can be performed.

  The plating solution may have a temperature of 30 ° C. or higher.

  Thereby, the time which uses an electrolytic plating method can be shortened.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which improves the precipitation property of the metal material in the hole formed in the board | substrate can be provided.

It is a figure explaining the composition of the interposer substrate concerning one embodiment of the present invention. It is process sectional drawing explaining the manufacturing method of the interposer substrate which concerns on one Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the interposer substrate which concerns on one Embodiment of this invention. It is a figure which shows the electrochemical characteristic of the plating solution which concerns on an Example and a comparative example. It is a figure which shows the temperature dependence of the electrochemical characteristic in the plating solution which concerns on an Example. It is a cross-sectional enlarged photograph of the interposer board | substrate which concerns on an Example and a comparative example. It is a figure which shows the value of the crystal grain map and crystal average particle diameter of the metal material of the conduction | electrical_connection part which concerns on the interposer board | substrate which concerns on an Example and a comparative example. It is a figure which shows the compositional analysis result by TOF-SIMS of the conduction | electrical_connection part which concerns on an Example.

  The present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes and should not be construed as being limited to the description of the embodiments described below. Note that in the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference numerals, and repeated description thereof may be omitted. Also, it should be noted that for convenience of explanation, the scale is changed as compared with the actual explanation.

<Configuration of interposer board>
FIG. 1 is a diagram illustrating the configuration of an interposer substrate according to an embodiment of the present invention. FIG. 1 shows a cross section of an interposer substrate. The interposer substrate 100 has a through hole 104 that penetrates the front surface and the back surface of the substrate 102. The through hole 104 includes a conduction portion 106. The conductive portion 106 is filled with a metal material. Moreover, you may provide the insulating layer 108 formed in the surface of the front and back of the board | substrate 102, and the through-hole 104 as needed.

  The material for the substrate 102 is not particularly limited. Examples of the material of the substrate 102 include a composite material including a semiconductor material, a glass material, a resin material, or the like, or an arbitrary combination of these materials. Typically, silicon is used as the material of the substrate 102. The thickness of the substrate 102 is not particularly limited. Accordingly, the thickness of the substrate 102 can be set in consideration of material strength, handling suitability, and the like. The thickness of the board | substrate 102 can be suitably selected, for example in the range of 100 micrometers or more and 1 mm or less.

  One or a plurality of through holes 104 are arranged in the substrate 102. When a plurality of through holes 104 are arranged on the substrate 102, the arrangement can be arbitrary. Therefore, the arrangement of the plurality of through holes 104 can be appropriately selected according to the use of the product. The hole diameter (diameter) of the through hole is not particularly limited. The diameter of the through hole can be appropriately selected within a range of, for example, 1 μm or more and 100 μm or less. As an example suitable as an interposer substrate, the aspect ratio of the through hole 104 may be 3 or more and 100 or less, more preferably 5 or more and 50 or less. Note that the aspect ratio is the depth of the through-hole 104 (the height of the substrate 102 (the thickness of the insulating layer 108 on the front surface and the back surface of the substrate 102 may be added if necessary)). The value is divided by the hole diameter (if necessary, the thickness of the insulating layer 108 on the inner wall of the through hole 104 may be subtracted).

  The conductive portion 106 includes a metal material. The metal material typically includes, for example, copper (Cu). By using copper, the manufacturing cost of the interposer substrate can be reduced while ensuring high conductivity. The conductive portion 106 is preferably filled with a metal material without voids. However, there may be minute voids that do not interfere with the use of the interposer substrate.

  The material of the insulating layer 108 is not particularly limited as long as a desired insulating property can be exhibited. Examples of the material of the insulating layer 108 include silicon oxide, silicon nitride, silicon oxynitride, or a composite material made of any combination of these materials. In FIG. 1, the insulating layer 108 is illustrated as one layer for convenience. Without being limited thereto, a multilayer structure of two or more layers may be used as the structure of the insulating layer 108. The thickness of the insulating layer 108 is not particularly limited. The thickness of the insulating layer 108 can be appropriately selected within a range of, for example, 0.1 μm or more and less than 5.0 μm.

<Method of manufacturing interposer substrate>
Below, the manufacturing method of an interposer board | substrate is demonstrated.
(First embodiment)
As a first embodiment, a manufacturing method of an interposer substrate manufactured by filling a through hole with a metal material will be described.
(1) Preparation of substrate 102 and drilling of through-hole 104 (FIG. 2A)
A substrate 102 is prepared. The substrate 102 is, for example, a silicon substrate. The thickness of the substrate 102 is, for example, not less than 300 μm and not more than 800 μm. First, a mask (not shown) selected from a photoresist, silicon oxide, silicon nitride, metal, or the like is formed on the substrate 102, and then the substrate 102 is etched through the mask until it penetrates in the thickness direction. Thereby, a through-hole 104 penetrating the first surface 102a and the second surface 102b of the substrate 102 is formed. As the etching method, for example, an RIE (Reactive Ion Etching) method, a DRIE (Deep Reactive Ion Etching) method, or the like can be used. Note that the through-hole 104 may be formed only by etching, or after forming the bottomed hole in the substrate 102, the through-hole 104 may be formed by polishing and opening.

  Note that when the first surface 102 a of the substrate 102 is the back surface of the substrate 102, the second surface 102 b of the substrate 102 is the surface of the substrate 102. Further, when the first surface 102 a of the substrate 102 is a front surface of the substrate 102, the second surface 102 b of the substrate 102 is the back surface of the substrate 102. Therefore, any correspondence can be used between the first surface 102 a and the second surface 102 b of the substrate 102 and the front and back surfaces of the substrate 102.

(2) Formation of the insulating layer 108 (FIG. 2B)
An insulating layer 108 is formed on the first surface 102 a, the second surface 102 b, and the inner wall of the through hole 104 of the substrate 102. The insulating layer 108 has, for example, a multilayer structure including a silicon oxide film and a silicon nitride film from the substrate 102 side. After a silicon oxide film is formed on the substrate 102 by a thermal oxidation method, a silicon nitride film is formed by a PE-CVD (Plasma Enhance Chemical Vapor Deposition) method. The thickness of the insulating layer is not particularly limited as long as desired insulating properties can be obtained. Therefore, the thickness of the insulating layer can be appropriately selected within a range of 0.1 μm or more and less than 5.0 μm, for example.

(3) Formation of seed layer (FIG. 2C)
A seed layer 110 is formed on the first surface 102 a side of the substrate 102. The seed layer 110 includes a metal film to be deposited in the through hole 104. The seed layer 110 may be configured as a multilayer structure by providing a film of Cr, Ti, or the like on the first surface 102a side of the substrate 102 for adhesion. The seed layer 110 can be formed by a film formation method such as sputtering or physical vapor deposition. The seed layer 110 serves as a power feeding unit for forming the conductive unit 106 by electrolytic plating. Note that the seed layer 110 is not limited to the one having an opening corresponding to the through hole 104 on the first surface 102 a side of the substrate 102. For example, a support substrate with a metal foil can be bonded to the substrate 102, and this metal foil can be used as a seed layer.

(4) Formation of conductive portion 106 (FIG. 2D)
The substrate 102 on which the seed layer 110 is formed is placed in a plating tank supplied with a plating solution. As a result, the substrate 102 can be brought into contact with the plating solution. The seed layer 110 is connected to the positive electrode side. By performing an electrolytic plating method in which power is supplied to the seed layer 110 in a state where the substrate 102 is in contact with the plating solution, metal deposition starts from the first surface 102a side and proceeds toward the second surface 102b side. Is deposited to fill the through hole 104 with a metal material. The current supplied in the electrolytic plating method may be any of direct current, pulse, and pulse reverse.

  The plating solution contains metal ions to be deposited and tin (Sn) ions. The ions of the metal to be deposited can be obtained by dissolving the metal salt to be deposited to form a plating solution. Further, tin (Sn) ions can be obtained by dissolving a water-soluble salt of tin (Sn) to form a plating solution. In one embodiment of the present invention, it is preferable that tin (Sn) does not precipitate by electrolytic plating. In order to prevent the precipitation of tin (Sn), for example, in the plating solution used for the electrolytic plating method, the activity of ions of tin (Sn) is 30% or less of the activity of ions of the metal to be deposited. , Preferably 5% or less, more preferably 2% or less. Thus, precipitation of tin (Sn) can be suppressed by making the activity of the ion of tin (Sn) smaller than the activity of the metal ion to be deposited.

More specifically, in consideration of the equilibrium potential in the plating solution, it is preferable to differentiate the deposition potential of the metal to be deposited by electrolytic plating, tin (Sn), and the deposition potential. That is, Nernst's formula when the metal and metal ion in the plating solution are in an equilibrium state (E = E ⁰ + RT / nFln [M ^{n +} ] where E ⁰ is the standard electrode potential, F is the Faraday constant, and R is The equilibrium potential of the metal ion is determined by the gas constant, T is the absolute temperature, and [M ^{n +} ] is the activity of the metal ion). Therefore, in consideration of the activity of metal ions and tin (Sn) ions to be deposited by electrolytic plating, the amount of each component contained in the plating solution is adjusted. That is, the deposition potential of the metal to be deposited by electrolytic plating, tin (Sn), and the deposition potential are differentiated. Thereby, the metal which should be deposited by electrolytic plating can be performed by the conditions which precipitation of tin (Sn) does not generate | occur | produce substantially.

  Conventionally, an organic additive has been used as an accelerator for promoting metal deposition in electrolytic plating. However, organic additives have a risk of decomposing and are difficult to use stably. In particular, when the temperature of the plating solution is increased, there is a high possibility that the organic additive is decomposed.

  In the method of manufacturing an interposer substrate in one embodiment of the present invention, one of the reasons for using a water-soluble tin salt is to promote precipitation. The water-soluble salt of tin is ionized in the plating solution, thereby promoting the deposition of the metal to be deposited. This eliminates the need to add organic additives to the plating solution. Further, since there is no risk of decomposition of the organic additive, the electroplating method can be carried out with the temperature of the plating solution being higher than before. For example, the temperature of the plating solution can be 30 ° C. or higher, preferably 50 ° C. or higher.

It is known that a metal having a large exchange current density (specifically, 10 ⁻³ mA / cm ⁻² or more and 10 mA / cm ⁻² or less) is likely to precipitate, and as a metal having a large exchange current density, tin, Lead (Pb), indium (In), silver (Ag), and the like can be given. Accordingly, it is considered that metal is easily deposited because tin promotes the nucleus growth of metal at the initial stage of electrolytic plating. As the water-soluble salt of tin, for example, tin chloride, tin sulfate or the like can be used.

Examples of the metal to be filled in the through hole 104, that is, the metal to be deposited by electrolytic plating, include copper (Cu), gold (Au), silver (Ag), and the like. Typically, copper is used as the metal to be deposited. By using copper, the manufacturing cost of the interposer substrate can be reduced while ensuring high conductivity. In the method for producing an interposer substrate according to an embodiment of the present invention, when copper is deposited, for example, a plating solution containing copper ions and tin ions produced using copper sulfate, sulfuric acid, and tin chloride is used. Can do. The amount of each component to be contained in the plating solution, ~1.2mol / dm ³ or less, for example 0.1 mol / dm ³ or more for copper sulfate, ~1.0mol / dm ³ for sulfuric example 0.5 mol / dm ³ or more for the tin chloride, for example it may be appropriately adjusted within the range of 0.01 mol / dm ³ or more ~0.2mol / dm ^3.

  In addition, carboxylic acid may be mix | blended with the plating solution. As the carboxylic acid, for example, citric acid or the like can be used. In addition to carboxylic acid, boric acid and the like can also be used. By adding carboxylic acid, especially citric acid, metal deposition can be stabilized. One reason for this is thought to be that carboxylic acid or the like functions as a pH buffer. Examples of carboxylic acids other than citric acid that can be added include glycine, succinic acid, malonic acid, malic acid, tartaric acid, and oxalic acid.

(5) Removal of unnecessary parts (FIG. 2E)
Unnecessary portions of the seed layer 110 and the conductive portion 106 present on the first surface 102a of the substrate 102 are removed by etching or CMP (Chemical Mechanical Polishing).

  Through the above process, the interposer substrate 100 according to an embodiment of the present invention can be manufactured.

(Second Embodiment)
Another example of the method for manufacturing an interposer substrate according to an embodiment of the present invention will be described. That is, as a second embodiment, a method for manufacturing an interposer substrate manufactured by filling a bottomed hole with a metal material will be described.
The description of the same configuration and processing as those described in the first embodiment may be omitted.

(1) Preparation of substrate 110 and formation of bottomed hole (FIG. 3A)
A substrate 110 is prepared. As the substrate 110, for example, a silicon substrate is prepared. First, a mask (not shown) selected from a photoresist, silicon oxide, silicon nitride, metal, or the like is formed on the substrate 110, and then etched so as not to penetrate the substrate 102 in the thickness direction through the mask. . As a result, a bottomed hole 112 that does not open on the first surface 112a of the substrate 110 but opens on the second surface 112b is formed. As in the first embodiment, any correspondence can be used between the first surface 112a and the second surface 112b of the substrate 110 and the front and back surfaces of the substrate 112.

(2) Formation of insulating layer 118 (FIG. 3B)
An insulating layer 118 is formed on the second surface 112 b of the substrate 110, the inner wall and the bottom wall of the bottomed hole 112. For example, the insulating layer 118 has a multilayer structure including a silicon oxide film and a silicon nitride film from the substrate 110 side. After a silicon oxide film is formed on the substrate 112 by a thermal oxidation method, a silicon nitride film is formed by a PE-CVD (Plasma Enhance Chemical Vapor Deposition) method. The thickness of the insulating layer is not particularly limited as long as desired insulating properties can be obtained. Therefore, the thickness of the insulating layer can be appropriately selected within a range of 0.1 μm or more and less than 5.0 μm, for example.

(3) Formation of seed layer 114 (FIG. 3C)
A seed layer 114 is formed on the second surface 112b side of the substrate 110 on which the insulating layer 118 is formed. The seed layer 114 includes a metal film to be deposited in the through hole 112. The seed layer 114 may be formed as a multilayer structure by providing a film such as Cr or Ti on the first surface 102b side of the substrate 110 for adhesion. The seed layer 114 can be formed by a film formation method such as sputtering or physical vapor deposition. The seed layer 114 serves as a power feeding part for forming the conduction part 116 by electrolytic plating.

(4) Formation of conductive portion 116 (FIG. 3D)
The substrate 110 on which the seed layer 114 is formed is placed in a plating tank supplied with a plating solution. As a result, the substrate 110 can be brought into contact with the plating solution. The seed layer 120 is connected to the positive electrode side. The bottomed hole 112 is filled with a metal material by performing an electrolytic plating method in which power is supplied to the seed layer 114 while the substrate 110 is in contact with the plating solution.

(5) Removal of unnecessary portions (FIG. 3E)
Unnecessary portions of the seed layer 114 and the conductive portion 116 are removed. Further, the surface of the substrate 110 is polished on the first surface 102a side and polished until the surface of the conductive portion 116 is exposed. Thereby, the conduction | electrical_connection part 116 is formed as shown in FIG.3 (E). Through the above process, the interposer substrate 120 according to the embodiment of the present invention can be manufactured.

  Hereinafter, it demonstrates in detail using an Example.

1. Electrochemical evaluation First, copper plating solutions A to D having the compositions shown in Table 1 were prepared.

  In Table 1, “JGB” is Yanas Green B, and “Accelerator” and “Inhibitor” are commercial accelerators and inhibitors for plating, respectively. n / a indicates that the substance or additive in the row is not contained in the plating solution. Each of the copper plating solution A and the copper plating solution B is a copper plating solution according to an embodiment of the present invention. The copper plating solution A is prepared from copper sulfate, sulfuric acid, chlorine, and tin chloride. The copper plating solution B is prepared by adding citric acid to the copper plating solution A. The copper plating solution C and the copper plating solution D are comparative plating solutions. The copper plating solution C is adjusted by adding JGB which is an organic additive to copper sulfate, sulfuric acid and chlorine, and the copper plating solution D is adjusted by adding an accelerator and an inhibitor to copper sulfate, sulfuric acid and chlorine.

  The electrochemical characteristics were evaluated using copper plating solutions A to D. The electrochemical characteristics were evaluated by measuring a current / potential curve using a potentiostat (HZ-5000, manufactured by Hokuto Denko). A platinum disk electrode of φ5 mm was used as the working electrode, a Ti—Pt mesh electrode of φ100 mm was used as the counter electrode, and a calomel electrode was used as the reference electrode. Electrochemical measurement was performed by the LSV (Linear Sweep Voltammetry) method.

FIG. 4 is a diagram showing electrochemical characteristics of plating solutions according to Examples and Comparative Examples. As shown in FIG. 4, the copper plating solution A bath formulated with tin chloride, the results of the electrochemical measurement of the copper plating solution C bath and D bath not blended tin chloride, 9 mA / cm ² or more 100 mA / cm ² In the following current density regions, the current value of the copper plating solution A bath was larger than the others, and it was confirmed that the copper precipitation of the copper plating solution A was good.

  Next, by adding citric acid to the copper plating solution A to increase the stability of the solution, and using the copper plating solution B bath, the copper plating solution C bath and the D bath at solution temperatures of 25 ° C., 35 ° C. and 50 ° C. The electrochemical measurements were evaluated. FIG. 5 is a diagram showing the temperature dependence of electrochemical characteristics in the plating solution. It was confirmed that as the bath temperature increased, the current value increased and the copper precipitation improved.

  From the above, it was confirmed that the precipitation of copper was improved by adding tin chloride as a water-soluble salt of tin to the copper plating solution. Furthermore, it was confirmed that the precipitation of copper is improved by increasing the temperature of the plating solution. It is considered that the high-quality filling of the conductive material into the through-hole can be achieved by improving the copper precipitation.

2. Evaluation of Filling Plating A silicon substrate having a thickness of 725 μm was prepared, a photoresist was applied to the substrate by spin coating, and exposure was performed through a photomask to form a mask having a plurality of openings of φ50 μm. Using this mask as an etching, a bottomed hole was formed by DRIE. Thereafter, the surface opposite to the etching start surface was polished to form a through hole penetrating the first surface and the second surface of the substrate having a thickness of 400 μm.

  A silicon oxide film was formed on this substrate by thermal oxidation. Further, a silicon nitride film was formed on the silicon oxide film by PE-CVD, and an insulating layer having a stacked structure of the silicon nitride film and the silicon oxide film was formed.

A copper seed layer was formed on one side of the substrate by physical vapor deposition. The substrate on which the seed layer is formed is immersed in a copper plating tank supplied with the copper plating solution shown in Table 1 below and brought into contact with the copper plating solution, and the seed layer is connected to the anode to bottom up the copper in the through hole. Filled the formula. The electrolytic plating process at this time was performed for about 18 hours with a direct current density of 0.85 A / cm ² . In Example 1, an interposer substrate in which copper was filled in the through holes using the copper plating solution A was manufactured, and in Comparative Example 1, an interposer in which copper was filled in the through holes using the copper plating solution D was used. A poser substrate was manufactured.

  The interposer substrates of Example 1 and Comparative Example 1 were cut with FIB (Focus Ion Beam), and the cross section was observed with a scanning electron microscope. FIG. 6 is an enlarged cross-sectional photograph of the interposer substrate according to the example (FIG. 6A) and the comparative example (FIG. 6B). In both Example 1 and Comparative Example 1, it was confirmed that the through hole was filled with copper without voids. Therefore, in Example 1, it was shown that it does not lead to generation | occurrence | production of a void, when the precipitation property of copper improves with tin chloride.

3. Crystallinity evaluation The crystallinity of the metal material filled in the through holes was evaluated. In Example 1 and Comparative Example 1, the measurement of the crystal grain size of the metal material was performed by an EBSD (Electron backscatter diffraction pattern) method. The analyzer used for the measurement is JEM-7000 FEBSD TSL (OIM Software Ver. 4.6) manufactured by SEM JEOL, and the observation conditions include an acceleration voltage of 25 kV, a sample tilt angle of 70 °, and a measurement step of 0.3 μm. did.

  FIG. 7 is a diagram showing the crystal grain map and the average crystal grain size value of the metal material of the conductive portion related to the interposer substrate according to the example and the comparative example, and FIG. 7A is a crystal grain map. is there. The crystal grain map shown on the left side of FIG. 7A relates to the example, and the right side relates to the comparative example. FIG. 7B shows the average crystal grain size at each depth position in FIG. Note that the upper end side of the crystal map in FIG. 7A is the first surface 102a side, and the lower end side is the second surface 102b side. In addition, the crystal grain sizes at the measurement positions [1] to [5] in FIG. 7B were measured at respective positions in the section obtained by dividing the thickness of the interposer substrate by 5 from the first surface 102a side. Is.

  7A and 7B, it can be seen that in Example 1, the crystal grain size of the metal grown from the first surface 102a to the second surface 102b side is gradually increased. In Example 1, a value of 6.1 μm was observed in the latter half of the filling (measurement position [5]), which was nearly three times the crystal grain size of Comparative Example 1. Thus, it was found that the crystal grain size of the metal to be filled can be increased by including tin ions in the copper plating solution. Since a metal material having a large crystal grain size has a small crystal grain size, it has excellent electrical characteristics when used as an interposer substrate.

  Moreover, since the copper plating solution used in Example 1 does not contain additives such as JGB, the plating cost can be reduced.

4). Composition analysis The composition of the metal material filled in the through holes in the examples was analyzed. FIG. 8: is a figure which shows the compositional analysis result by TOF-SIMS (Time-of-flight secondary ion mass spectrometer) of the conduction | electrical_connection part which concerns on an Example. Tin was detected in the first half of the filling (side closer to the first surface) and the second half of the filling (side closer to the second surface). In any case, tin was hardly observed, and it was confirmed that tin was not taken into the metal material filled in the through holes.

5. High-speed filling property evaluation Filling plating was performed using the copper plating solution A and the copper plating solution D. When the copper plating solution A was used, it was confirmed that the filling was 1.5 times faster than when the copper plating solution D was used, and an increase of 50% was recognized as an effect of speeding up the filling plating. .

Claims (11)

Preparing a substrate having a first surface and a second surface and having a bottomed hole formed in the second surface;
Forming an insulating layer on the second surface of the substrate, the inner wall and the bottom wall of the bottomed hole;
Forming a seed layer on the second side of the substrate;
Filling the bottomed hole with a metal material by performing an electroplating method for supplying power to the seed layer in a state where the substrate on which the seed layer is formed is in contact with a plating solution,
Carrying out a polishing treatment from the first surface side of the substrate until the metal material filled in the bottomed hole is exposed,
The method for producing an interposer substrate, wherein the plating solution contains ions of metal to be deposited and ions of tin.   2. The method of manufacturing an interposer substrate according to claim 1, wherein the metal ions are copper ions.   The method for producing an interposer substrate according to claim 1 or 2, wherein the tin ions are obtained by dissolving tin chloride.   The method for manufacturing an interposer substrate according to any one of claims 1 to 3, wherein the plating solution further contains a carboxylic acid.   The method of manufacturing an interposer substrate according to any one of claims 1 to 4, wherein a temperature of the plating solution is 30 ° C or higher. The method for manufacturing an interposer substrate according to claim 1, wherein unnecessary portions of the seed layer and the metal material are removed .   The method of manufacturing an interposer substrate according to any one of claims 1 to 6, wherein the substrate is a semiconductor material.   The method for manufacturing an interposer substrate according to any one of claims 1 to 7, wherein the insulating layer is formed by a thermal oxidation treatment. The manufacturing method of the interposer substrate according to any one of claims 1 to 7, wherein the insulating layer includes a silicon oxide film formed by a thermal oxidation process and a silicon nitride film formed by a PE-CVD method. Method.   The method for manufacturing an interposer substrate according to any one of claims 1 to 6, wherein the substrate is made of a glass material. As the insulating layer, silicon oxide, silicon nitride, and a single layer or a stacked layer selected from a silicon oxynitride, claims 1-7, according to any one of 10, a method of manufacturing an interposer substrate.