WO2017201781A1 - 薄膜晶体管、薄膜晶体管的制备方法及cmos器件 - Google Patents

薄膜晶体管、薄膜晶体管的制备方法及cmos器件 Download PDF

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WO2017201781A1
WO2017201781A1 PCT/CN2016/086639 CN2016086639W WO2017201781A1 WO 2017201781 A1 WO2017201781 A1 WO 2017201781A1 CN 2016086639 W CN2016086639 W CN 2016086639W WO 2017201781 A1 WO2017201781 A1 WO 2017201781A1
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doped region
low temperature
layer
temperature polysilicon
heavily doped
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French (fr)
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赵芬利
谢应涛
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/112,638 priority Critical patent/US20180108746A1/en
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Definitions

  • the present invention claims the priority of the prior application entitled “Thin-film transistor, method of fabricating a thin-film transistor, and CMOS device", which is incorporated by reference in its entirety. In this article.
  • the present invention relates to the field of display, and in particular, to a thin film transistor, a method of fabricating a thin film transistor, and a CMOS device.
  • a display device such as a liquid crystal display (LCD) is a commonly used electronic device that is favored by users because of its low power consumption, small size, and light weight.
  • LCD liquid crystal display
  • Amorphous silicon has a low electron mobility
  • Ploy-silicon can be fabricated at low temperatures and has a higher carrier mobility than amorphous silicon.
  • CMOS devices fabricated from low temperature polysilicon can be applied to make liquid crystal displays have higher resolution and lower power consumption. Therefore, low temperature polysilicon has been widely used and studied. Higher carrier mobility is prone to hot carrier effects, resulting in threshold voltage (Vth) drift, Kink effect, etc.
  • low temperature polysilicon thin film transistors used in low temperature polysilicon.
  • ion implantation is generally used to form shallow doped transition regions, such as LDD (Light Doped Drain) and GOLDD (Gate On LDD).
  • the formation of the shallow doped transition region is typically formed by a mask process or by a gate self-alignment process (Gate Self Alignment).
  • GATE Self Alignment The disadvantages of these methods are that there are many mask processes required, and the formed low-temperature polysilicon thin film transistor is prone to doping deviation or offset between the gate and the LDD region, resulting in poor device characteristics of the low-temperature polysilicon thin film transistor.
  • the invention provides a thin film transistor, the thin film transistor comprising:
  • a low temperature polysilicon layer disposed adjacent to the substrate
  • the first lightly doped region and the second lightly doped region are disposed in the same layer as the low temperature polysilicon layer, and are disposed at opposite ends of the low temperature polysilicon layer, the first lightly doped region and the second The doped concentration of the lightly doped region with respect to the symmetric portion of the low temperature polysilicon layer is equal;
  • the first heavily doped region and the second heavily doped region are disposed in the same layer as the low temperature polysilicon layer, and the first heavily doped region is disposed at an end of the first lightly doped region away from the low temperature polysilicon layer a doping concentration of the first heavily doped region and the second heavily doped region with respect to a symmetric portion of the low temperature polysilicon layer, the second heavily doped region being disposed in the second lightly doped region Far from the end of the low temperature polysilicon layer, the doping types of the first lightly doped region, the second lightly doped region, the first heavily doped region, and the second heavily doped region are the same;
  • a first insulating layer including a first portion and a second portion, the first portion covering the low temperature polysilicon layer, the first lightly doped region, the second lightly doped region, and the first heavily doped region And the second heavily doped region, the second portion is disposed at a middle portion of the surface of the first portion away from the low temperature polysilicon layer, and the second portion and the first portion form a "convex" word;
  • a gate is disposed on the second portion and the gate intersects the second portion and the plane of the opposite end faces is equal to the midpoint of the low temperature polysilicon layer.
  • the plane in which the end face of the first lightly doped region in contact with the low temperature polysilicon layer is located is a first plane
  • the plane in which the end face of the second lightly doped region is in contact with the low temperature polysilicon layer is second.
  • a second doped region is disposed at an end of the second lightly doped region away from the low temperature polysilicon layer
  • the second portion includes a first end face and a second end face that are oppositely disposed, and the first The end surface and the second end surface respectively intersect the surface of the first portion adjacent to the second portion, the plane of the first end surface is coplanar with the first plane, and the second end surface and the second end surface The plane is coplanar.
  • the first portion is provided with a first through hole corresponding to the first heavily doped region and a second through hole corresponding to the second heavily doped region, and the thin film transistor further includes:
  • the second insulating layer covering the gate, the second insulating layer is provided with a third through hole and a fourth through hole, and the third through hole is in communication with the first through hole, the fourth through hole Communicating with the second through hole;
  • a source and a drain are disposed on the second insulating layer, and a source is connected to the first heavily doped region through the first through hole and the third through hole, and the drain passes through The second through hole and the fourth through hole are connected to the second heavily doped region;
  • the flat layer is provided with a fifth through hole, the fifth through hole is disposed corresponding to the drain, the thin film transistor further includes a pixel electrode, and the pixel electrode is disposed on the flat layer and passes through the A fifth via connects the drain.
  • the doping type of the first lightly doped region, the second lightly doped region, the first heavily doped region, and the second heavily doped region is N-type ion doped or P Type ion doping.
  • the invention also provides a method for preparing a thin film transistor, the method for preparing the thin film transistor comprises:
  • the first photoresist layer to retain a first photoresist pattern corresponding to the low temperature polysilicon pattern, the first photoresist pattern including oppositely disposed first surface and second surface, and the first The surface and the second surface both intersect the surface of the first metal layer adjacent to the first photoresist layer, and the planes where the first surface and the second surface are located are located on the low temperature polysilicon pattern and the substrate Between the planes where the two surfaces intersect and are oppositely disposed;
  • the pole insulating layer is partially etched to retain a first insulating layer corresponding to the low temperature polysilicon pattern, the first insulating layer includes a first portion, a second portion, the first portion covers the low temperature polysilicon pattern, and the second portion a portion is disposed at a middle portion of the surface of the first portion away from the low temperature polysilicon pattern, the second portion and the first portion form a "convex" word, and the opposite end faces of the second portion are respectively associated with the first portion a surface and the second surface are coplanar;
  • the low temperature polysilicon pattern corresponding to the first photoresist pattern forms a low temperature polysilicon layer, the low temperature covered only by the first portion and the second portion and not covered by the first photoresist pattern Forming the first lightly doped region and the second lightly doped region by the polysilicon pattern, and forming the first heavily doped region and the second heavily doped region only by the low temperature polysilicon pattern covered by the first portion;
  • the first photoresist pattern is stripped.
  • the method for preparing the thin film transistor further includes:
  • a planar layer is deposited on the source and the drain.
  • the ion doping is N-type ion doping or P-type ion doping.
  • the low temperature polysilicon pattern is ion doped with the first photoresist pattern and the first insulating layer as a mask, corresponding to the first portion, the second portion, and the first photoresist
  • the patterned doped ions have equal ion concentrations and the same doping time.
  • the present invention also provides a CMOS device comprising the thin film transistor of any of the foregoing embodiments.
  • the first photoresist layer and the first insulating layer are used as a mask, and the thickness of the first portion and the second portion itself is used to achieve final doping to a low temperature.
  • the difference in ion concentration of each portion of the polysilicon pattern That is, the low temperature polysilicon pattern corresponding to the first photoresist pattern is a low temperature polysilicon layer, and the low temperature polysilicon pattern formed only by the first portion and the second portion and not covered by the first photoresist pattern is formed.
  • the first lightly doped region and the second lightly doped region are formed by the low temperature polysilicon pattern covered by the first portion to form a first heavily doped region and The second heavily doped region.
  • the mask process is not required in this step, which simplifies the manufacturing process of the thin film transistor.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a CMOS device in accordance with a preferred embodiment of the present invention.
  • FIG 3 is a schematic cross-sectional view of a CMOS according to a preferred embodiment of the present invention.
  • FIG. 4 is a flow chart of a method of fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 14 are schematic structural views corresponding to respective steps of a method for fabricating a thin film transistor of the present invention.
  • FIG. 1 is a cross-sectional structural diagram of a thin film transistor according to a preferred embodiment of the present invention.
  • the thin film transistor 10 includes a substrate 110, a low temperature polysilicon layer 130, a first lightly doped region 140a, a second lightly doped region 140b, a first heavily doped region 150a, a second heavily doped region 150b, and a first insulating layer. 160 and gate 170.
  • the low temperature polysilicon layer 130 is disposed adjacent to the substrate 110. It can be understood that the low temperature polysilicon layer 130 may be directly disposed on the surface of the substrate 110 or may be disposed on the substrate 110 through a buffer layer.
  • the first lightly doped region 140a and the second lightly doped region 140b are disposed in the same layer as the low temperature polysilicon layer 130, and are disposed at opposite ends of the low temperature polysilicon layer 130, the first lightly doped
  • the doping concentration of the symmetrical portion of the low temperature polysilicon layer 130 is equal to that of the second lightly doped region 140a.
  • the first heavily doped region 150a and the second heavily doped region 150b are disposed in the same layer as the low temperature polysilicon layer 130, and the first heavily doped region 150a is disposed at the first The lightly doped region 140a is away from one end of the low temperature polysilicon layer 130, and the second heavily doped region 150b is disposed at an end of the second lightly doped region 140b away from the low temperature polysilicon layer 130, the first heavily doped
  • the doping concentration of the region 150a and the second heavily doped region 150b with respect to the symmetrical portion of the low temperature polysilicon layer 130 is equal.
  • the doping types of the first lightly doped region 140a, the second lightly doped region 140b, the first heavily doped region 150a, and the second heavily doped region 150b are the same.
  • the first insulating layer 160 includes a first portion 160a and a second portion 160b.
  • the first portion 160a covers the low temperature polysilicon layer 130, the first lightly doped region 140a, the second lightly doped region 140b, the first heavily doped region 150a, and the second heavily doped region Zone 150b.
  • the second portion 160b is disposed at a middle portion of the surface of the first portion 160a away from the low temperature polysilicon layer 130, and the second portion 160b and the first portion 160a form a "convex" word.
  • the gate 170 is disposed on the second portion 160b and the gate 170 intersects the second portion 160b and the distance between the plane of the opposite end faces is equal to the midpoint of the low temperature polysilicon layer.
  • the material of the substrate 110 includes any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • the low temperature polysilicon layer 130, the first lightly doped region 140a, the second lightly doped region 140b, the first heavily doped region 150a, the second heavily doped region 150b, the first An insulating layer 160 and the gate 170 are disposed on the same side of the substrate 110. It can be understood that the first lightly doped region 140a, the second lightly doped region 140b, the first heavily doped region 150a, the second heavily doped region 150b, and the first insulating layer 160 and the gate 170 may be disposed directly or indirectly on the same side of the substrate 110.
  • the first lightly doped region 140a, the second lightly doped region 140b, the first heavily doped region 150a, the second heavily doped region 150b, the first An insulating layer 160 and the gate electrode 170 are disposed on the same side of the substrate 110 through a buffer layer.
  • the buffer layer can reduce damage to the substrate 110 during the preparation of the thin film transistor 10.
  • a plane in which the end surface of the first lightly doped region 140a in contact with the low temperature polysilicon layer 130 is located is a first plane 141, and a plane in which the end surface of the second lightly doped region 140b is in contact with the low temperature polysilicon layer 130 is located It is the second plane 142.
  • a plane in which the side of the first heavily doped region 150a in contact with the first lightly doped region 140a is located is a third plane 143.
  • the second heavily doped region 150b is disposed at one end of the second lightly doped region 150a away from the low temperature polysilicon layer 130, and the second heavily doped region
  • the plane in which the side of the region 150b in contact with the second lightly doped region 140b is located is the fourth plane 144.
  • the second portion 160b includes a first end surface 161 and a second end surface 162 that are oppositely disposed.
  • the first end surface 161 and the second end surface 162 respectively intersect the surface of the first portion 160a adjacent to the second portion 160b, and the plane of the first end surface 161 is coplanar with the first plane 141.
  • the second end surface 162 is coplanar with the second plane 142.
  • the first portion 160a defines a first through hole 163 corresponding to the first heavily doped region 150a and a second through hole 164 corresponding to the second heavily doped region 150b.
  • the thin film transistor further includes a second insulating layer 180, a source 190a, a drain 190b, and a flat layer 190c.
  • the second insulating layer 180 covers the gate 170, and the second insulating layer 180 defines a third through hole 181 and a fourth through hole 182.
  • the third through hole 181 is in communication with the first through hole 163
  • the fourth through hole 182 is in communication with the second through hole 164 .
  • the source 190a and the drain 190b are disposed on the second insulating layer 180, and the source 190a passes through the first through hole 163 and the third through hole 181 and the first weight
  • the doped regions 150a are connected.
  • the drain 190b is connected to the second heavily doped region 150b through the second through hole 164 and the fourth through hole 182.
  • the flat layer 190c covers the source 190a and the drain 190b.
  • the flat layer 190c is provided with a fifth through hole 191, and the fifth through hole 191 is disposed corresponding to the drain 190b.
  • the thin film transistor 10 further includes a pixel electrode 190d disposed on the flat layer 190c and connected to the drain 190b through the fifth through hole 191.
  • the first lightly doped region 140a, the second lightly doped region 140b, the first heavily doped region 150a, and the second heavily doped region 150b have the same doping type, for example, the same N
  • the type ion is doped or the same as the P type ion doping.
  • the N-type ion doped ions may be, but are not limited to, phosphorus (P) ions, arsenic (AS) ions, and the like.
  • the P-type ion doped ions may be, but are not limited to, boron (B) ions or the like.
  • the doping concentration of the first heavily doped region 150a is greater than the doping concentration of the first lightly doped region 140a.
  • the doping concentration of the second heavily doped region 150b is greater than the doping concentration of the second lightly doped region 140b.
  • the doping concentration of the first heavily doped region 150a in the present embodiment is greater than the doping concentration of the first lightly doped region 140a, and the doping concentration of the second heavily doped region 150b is greater than the first
  • the doping concentration of a lightly doped region 140b can reduce the contact resistance between the source 190a and the low temperature polysilicon layer 130, and reduce the contact resistance between the drain 190b and the low temperature polysilicon layer 130. Again The leakage current of the thin film transistor 10 can be reduced.
  • the first insulating layer 160 includes, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx) materials, and the like.
  • the material of the gate 170 includes, but is not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi.
  • the gate 170 has a thickness of 1500 to 6000 angstroms.
  • the second insulating layer 180 includes, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx) materials, and the like.
  • the materials of the source 190a and the drain 190b include, but are not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi.
  • the pixel electrode 190d may include, but is not limited to, one or more of the following materials: a ZnO-based transparent oxide semiconductor material, a SnO 2 -based transparent oxide semiconductor material, an In 2 O 3 -based transparent oxide semiconductor material, or the like.
  • the transparent oxide semiconductor film layer may be Indium Gallium Zinc Oxide (IGZO).
  • the first lightly doped region 140a and the second lightly doped region 140b in the thin film transistor 10 of the present invention are disposed in the same layer as the low temperature polysilicon layer 130, and are disposed at opposite ends of the low temperature polysilicon layer 130,
  • the doping concentration of the first lightly doped region 140a and the second lightly doped region 140b with respect to the symmetric portion of the low temperature polysilicon layer 130 is equal;
  • the first heavily doped region 150a and the second heavily doped region 150b are The low temperature polysilicon layer 130 is disposed in the same layer, and the first heavily doped region 150a is disposed at an end of the first lightly doped region 140a away from the low temperature polysilicon layer 130, and the first heavily doped region 150a is
  • the second heavily doped region 150b is equal in doping concentration with respect to the symmetric portion of the low temperature polysilicon layer 130, the first lightly doped region 140a, the second lightly doped region 140b, and the first heavily doped region
  • the present invention also provides a CMOS (Complementary Metal Oxide Semiconductor) device 1, please refer to FIG. 2 and FIG. 3 together.
  • 2 is a schematic circuit diagram of a CMOS device according to a preferred embodiment of the present invention
  • FIG. 3 is a cross-sectional structural view of a CMOS according to a preferred embodiment of the present invention.
  • the CMOS device 1 includes a first thin film transistor Q1 and a second thin film transistor Q2, wherein when the first thin film transistor Q1 is an N-type thin film transistor, the second thin film transistor Q2 is a P-type thin film transistor. When the first thin film transistor Q1 is a P-type thin film transistor, the second thin film transistor Q2 is an N-type thin film transistor.
  • a gate of the first thin film transistor Q1 is electrically connected to a gate of the second thin film transistor Q2, and a drain of the first thin film transistor Q1 is connected to a source of the second thin film transistor.
  • the first thin film transistor Q1 in the CMOS device of the present embodiment may be the thin film transistor 10 described above, or the second thin film transistor Q2 of the CMOS device is the thin film transistor 10 described above, and details are not described herein again.
  • FIG. 4 is a flow chart of a method for fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • the method of preparing the thin film transistor includes, but is not limited to, the following steps.
  • the substrate 110 is provided.
  • the material of the substrate 110 includes any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • Step S102 forming a polysilicon material layer on the surface of the substrate 110 and patterning the polysilicon material layer to form a low temperature polysilicon pattern 211.
  • an amorphous silicon material layer may be formed on the surface of the substrate 110, and the amorphous silicon material layer may be subjected to excimer laser annealing or other methods to make the amorphous silicon material layer.
  • the amorphous silicon in the polysilicon becomes polycrystalline silicon.
  • step S103 the gate insulating material layer 22, the first metal layer 23 and the first photoresist layer 24 are sequentially disposed on the surface of the low temperature polysilicon pattern 211 away from the substrate 110. Please refer to Figure 6 together.
  • Step S104 patterning the first photoresist layer 24 to retain a first photoresist pattern 241 corresponding to the low temperature polysilicon pattern 211, the first photoresist pattern 241 including a first surface 241a and a first surface disposed opposite to each other Two surfaces 241b, and the first surface 241a and the second surface 241b are both
  • the first metal layer 23 is adjacent to the surface of the first photoresist layer 241, and the planes where the first surface 241a and the second surface 241b are located are located at the low temperature polysilicon pattern 211 and the substrate 110 intersects and are oppositely disposed. The plane between the two surfaces lies. Please refer to Figure 7 together.
  • Step S105 patterning the first metal layer 23 to remove the first metal layer 23 not covered by the first photoresist pattern 241, and retaining the first metal covered by the first photoresist pattern 241 a layer 23, and partially etching the gate insulating layer 22 to retain a first insulating layer 160 corresponding to the low temperature polysilicon pattern 211, the first insulating layer 160 including a first portion 160a and a second portion 160b
  • the first portion 160a covers the low temperature polysilicon pattern 211
  • the second portion 160b is disposed at a middle portion of the surface of the first portion 160a away from the low temperature polysilicon pattern 211, and the second portion 160b and the first portion 160a are formed.
  • the word "convex" and the opposite end faces of the second portion 160b are coplanar with the first surface 241a and the second surface 241b, respectively. Please refer to Figure 8 together.
  • step S106 both ends of the first photoresist pattern 241 are ashed.
  • the areas where the two ends of the first photoresist pattern 241 are grayed out correspond to the first lightly doped region 140a and the second lightly doped region 140b in the thin film transistor 10, respectively.
  • Step S107 etching the first metal layer 23 to remove both ends of the first metal layer 23 corresponding to the ashing region of the first photoresist pattern 241, and retaining the first metal layer 230 to form the gate 170, see FIG.
  • the low temperature polysilicon pattern 211 is ion doped with the first photoresist pattern 241 and the first insulating layer 160 as a mask, and the low temperature polysilicon pattern 211 corresponding to the first photoresist pattern 241 is formed.
  • the low temperature polysilicon layer 130, the low temperature polysilicon pattern 211 covered only by the first portion 160a and the second portion 160b and not covered by the first photoresist pattern 241 forms the first lightly doped region 140a and
  • the second lightly doped region 140b, the low temperature polysilicon pattern 211 covered only by the first portion 160a forms a first heavily doped region 150a and a second heavily doped region 150b.
  • the low temperature polysilicon pattern 211 when the low temperature polysilicon pattern 211 is ion doped with the first photoresist pattern 241 and the first insulating layer 160 as a mask, the first portion 160a and the second portion are corresponding.
  • the portion 160b and the first photoresist pattern 241 have the same ion concentration and the same doping time. Please refer to Figure 11 together.
  • the first photoresist pattern 241 and the first The insulating layer 160 is a mask, and the difference in ion concentration of each portion finally doped to the low-temperature polysilicon pattern 211 is achieved by the thickness of the first portion 160a and the second portion 160b itself. That is, the low temperature polysilicon pattern 211 corresponding to the first photoresist pattern 241 is the low temperature polysilicon layer 130, and is covered only by the first portion 160a and the second portion 160b and not covered by the first photoresist pattern 241.
  • the low temperature polysilicon pattern 211 forms the first lightly doped region 140a and the second lightly doped region 140b, and only the low temperature polysilicon pattern 211 covered by the first portion 160a forms the first heavily doped region 150a and the second Heavy doped region 150b.
  • the mask process is not required in this step, which simplifies the manufacturing process of the thin film transistor.
  • Step S109 etching the first insulating layer 160 to remove a portion of the second portion 160b that is not covered by the gate 170. Please refer to Figure 12.
  • step S110 the first photoresist pattern 241 is peeled off. Please refer to Figure 13.
  • the method for preparing the thin film transistor further includes the following steps.
  • Step S111 depositing a second insulating layer 180 on the gate 170 and the first insulating layer 160.
  • Step S112 a through hole is formed in the second insulating layer 180 and the first insulating layer 160 corresponding to the first heavily doped region 150a and the second heavily doped region 150b to be in the first insulating layer 160.
  • the third through hole 181 is connected to the through hole 163 and the fourth through hole 182 is connected to the second through hole 164.
  • Step S113 depositing a second metal layer 25 on the second insulating layer 180, and patterning the second metal layer 25 to form through the first through hole 163 and the third through hole 181 a source 190a connected to the first heavily doped region 150a, and a drain 190b connected to the second heavily doped region 150b through the second through hole 164 and the fourth through hole 182.
  • Step S114 depositing a flat layer 190c on the source 190a and the drain 190b.
  • the method for preparing the thin film transistor further includes the following steps.
  • step S115 a fifth through hole 191 is defined in the flat layer 190c corresponding to the drain 190b.
  • Step S116 depositing a transparent conductive layer on the flat layer 190c, and patterning the transparent conductive layer to form a pixel electrode 190d connected to the drain 190b through the fifth through hole 191. Please refer to FIG. 14 together with steps S109 to S116.

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Abstract

一种薄膜晶体管、薄膜晶体管的制备方法及CMOS器件。薄膜晶体管（10）包括：基板（110）；邻近基板设置的低温多晶硅层（130）；与低温多晶硅层同层且设置在低温多晶硅层相对两端的第一、第二轻掺杂区（140a、140b），与低温多晶硅层同层设置的第一、第二重掺杂区（150a、150b），第一重掺杂区设置在第一轻掺杂区远离低温多晶硅层的一端，第二重掺杂区设置在第二轻掺杂区远离低温多晶硅层的一端，第一、第二轻掺杂区及第一、第二重掺杂区掺杂类型相同；第一绝缘层（160），包括第一、第二部分（160a、160b），第一部分覆盖低温多晶硅层、第一、第二轻掺杂区及第一、第二重掺杂区，第二部分设置在第一部分的表面中部，第一、第二部分形成"凸"字；栅极（170），设置在第二部分上。

Description

薄膜晶体管、薄膜晶体管的制备方法及CMOS器件
本发明要求2016年5月26日递交的发明名称为“薄膜晶体管、薄膜晶体管的制备方法及CMOS器件”的申请号201610363860.0的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管、薄膜晶体管的制备方法及CMOS器件。
背景技术
显示设备，比如液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。随着平面显示技术的发展，具有高分辨率、低能耗的液晶显示器的需求被提出。非晶硅的电子迁移率较低，而低温多晶硅(Low Temperature Ploy-silicon)可以在低温下制作，且拥有比非晶硅更高的载流子迁移率。其次，低温多晶硅制作的CMOS器件可应用于使液晶显示器具有更高的分辨率和低能耗。因此，低温多晶硅得到了广泛地应用和研究。较高的载流子迁移率容易产生热载流子效应，导致低温多晶硅所应用的低温多晶硅薄膜晶体管的阈值电压(Vth)漂移，Kink效应等。为了避免热载流子效应一般采用离子注入形成浅掺杂过渡区，如LDD(Light Doped Drain)和GOLDD(Gate On LDD)等。浅掺杂过渡区的形成一般通过光罩(mask)工艺或者通过栅极自对准工艺(Gate Self Alignment)掺杂形成。这些方法的缺点是需要的光罩工序较多，且形成的低温多晶硅薄膜晶体管容易出现掺杂偏差或者栅极与LDD区域偏移，从而导致低温多晶硅薄膜晶体管的器件特性不良。
发明内容
本发明提供一种薄膜晶体管，所述薄膜晶体管包括：
基板；
低温多晶硅层，邻近所述基板设置；
第一轻掺杂区及第二轻掺杂区，与所述低温多晶硅层同层设置，且设置在所述低温多晶硅层相对的两端，所述第一轻掺杂区与所述第二轻掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相等；
第一重掺杂区及第二重掺杂区，与所述低温多晶硅层同层设置，所述第一重掺杂区设置在所述第一轻掺杂区远离所述低温多晶硅层的一端，所述第一重掺杂区与所述第二重掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相等，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型相同；
第一绝缘层，包括第一部分及第二部分，所述第一部分覆盖所述低温多晶硅层、所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区，所述第二部分设置在所述第一部分远离所述低温多晶硅层的表面的中部，所述第二部分及所述第一部分形成“凸”字；
栅极，设置在第二部分上且所述栅极与所述第二部分相交且相对设置的两端面所在的平面到所述低温多晶硅层的中点的距离相等。
其中，所述第一轻掺杂区与所述低温多晶硅层接触的端面所在的平面为第一平面，所述第二轻掺杂区与所述低温多晶硅层接触的端面所在的平面为第二平面，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，述第二部分包括相对设置的第一端面及第二端面，且所述第一端面及所述第二端面分别与所述第一部分邻近所述第二部分的表面相交，所述第一端面所在的平面与所述第一平面共面，所述第二端面与所述第二平面共面。
其中，所述第一部分开设有对应所述第一重掺杂区的第一贯孔及对应所述第二重掺杂区的第二贯孔，所述薄膜晶体管还包括：
第二绝缘层，覆盖所述栅极，所述第二绝缘层开设有第三贯孔及第四贯孔，所述第三贯孔与所述第一贯孔连通，所述第四贯孔与所述第二贯孔连通；
源极和漏极，设置在所述第二绝缘层上，且源极通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区相连，所述漏极通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区相连；
平坦层，覆盖所述源极和所述漏极。
其中，所述平坦层开设有第五贯孔，所述第五贯孔对应所述漏极设置，所述薄膜晶体管还包括像素电极，所述像素电极设置在所述平坦层上且通过所述第五贯孔连接所述漏极。
其中，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型为N型离子掺杂或者为P型离子掺杂。
本发明还提供了一种薄膜晶体管的制备方法，所述薄膜晶体管的制备方法包括：
提供基板；
在所述基板的表面上形成多晶硅材料层并图案化所述多晶硅材料层，以形成低温多晶硅图案；
在所述低温多晶硅图案远离所述基板的表面依次设置栅极绝缘材料层、第一金属层及第一光阻层；
对所述第一光阻层进行图案化以保留对应所述低温多晶硅图案的第一光阻图案，所述第一光阻图案包括相对设置的第一表面及第二表面，且所述第一表面与所述第二表面均与所述第一金属层邻近所述第一光阻层的表面相交，所述第一表面及所述第二表面所在的平面均位于所述低温多晶硅图案与基板相交且相对设置的两表面所在的平面之间；
对所述第一金属层进行图案化，移除未被所述第一光阻图案覆盖的第一金属层，保留被所述第一光阻图案覆盖的第一金属层，且对所述栅极绝缘层进行部分蚀刻，以保留对应所述低温多晶硅图案的第一绝缘层，所述第一绝缘层包括第一部分、第二部分，所述第一部分覆盖所述低温多晶硅图案，所述第二部分设置在所述第一部分远离所述低温多晶硅图案的表面的中部，所述第二部分及所述第一部分形成“凸”字，且所述第二部分相对的两个端面分别与所述第一表面及所述第二表面共面；
对所述第一光阻图案的两端进行灰化；
对所述第一金属层进行蚀刻，以移除所述第一金属层的对应所述第一光阻图案灰化区域的两端，保留下来的所述第一金属层以形成栅极；
以所述第一光阻图案及所述第一绝缘层为掩膜对所述低温多晶硅图案进 行离子掺杂，所述第一光阻图案对应的低温多晶硅图案形成低温多晶硅层，仅被所述第一部分及所述第二部分覆盖且未被所述第一光阻图案覆盖的所述低温多晶硅图案形成所述第一轻掺杂区及所述第二轻掺杂区，仅被所述第一部分覆盖的低温多晶硅图案形成第一重掺杂区及第二重掺杂区；
对所述第一绝缘层进行蚀刻，以移除所述第二部分中未被所述栅极覆盖的部分；
剥离所述第一光阻图案。
其中，所述薄膜晶体管的制备方法还包括：
在所述栅极及所述第一绝缘层上沉积第二绝缘层；
在所述第二绝缘层及所述第一绝缘层对应所述第一重掺杂区及第二重掺杂区开设贯孔，以在所述第一绝缘层上形成对应第一重掺杂区的第一贯孔及对应所述第二重掺杂区的第二贯孔，以及在所述第二绝缘层上形成与所述第一贯孔连通的第三贯孔以及与所述第二贯孔连通的第四贯孔；
在所述第二绝缘层上沉积第二金属层，对所述第二金属层进行图案化，以形成通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区连接的源极，以及通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区连接的漏极；
在所述源极和所述漏极上沉积平坦层。
其中，所述离子掺杂为N型离子掺杂或者为P型离子掺杂。
其中，以所述第一光阻图案及所述第一绝缘层为掩膜对所述低温多晶硅图案进行离子掺杂时，对应所述第一部分、所述第二部分及所述第一光阻图案的掺杂的离子浓度相等，掺杂时间相同。
本发明还提供了一种CMOS器件，所述CMOS器件包括前述任意一实施方式所述的薄膜晶体管。
本发明的薄膜晶体管的制备方法中以所述第一光阻图案及所述第一绝缘层为掩膜，利用所述第一部分及所述第二部分自身的厚度，来实现最终掺杂到低温多晶硅图案的各部分的离子浓度的不同。即，对应第一光阻图案对应的低温多晶硅图案为低温多晶硅层，仅被所述第一部分及所述第二部分覆盖且未被所述第一光阻图案覆盖的所述低温多晶硅图案形成所述第一轻掺杂区及所述第二轻掺杂区，仅被所述第一部分覆盖的低温多晶硅图案形成第一重掺杂区及 第二重掺杂区。此步骤中不需要使用光罩工艺，从而简化了薄膜晶体管的制程工序。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。
图2为本发明的一较佳实施方式的CMOS器件的电路示意图。
图3为本发明一较佳实施方式的CMOS的剖面结构示意图。
图4为本发明一较佳实施方式的薄膜晶体管的制备方法的流程图。
图5至图14为本发明薄膜晶体管的制备方法各步骤对应的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。所述薄膜晶体管10包括基板110、低温多晶硅层130、第一轻掺杂区140a、第二轻掺杂区140b、第一重掺杂区150a、第二重掺杂区150b、第一绝缘层160及栅极170。所述低温多晶硅层130邻近所述基板110设置，可以理解地，所述低温多晶硅层130可以直接设置在所述基板110的表面，也可以通过缓冲层设置在所述基板110上。所述第一轻掺杂区140a及所述第二轻掺杂区140b与所述低温多晶硅层130同层设置，且设置在所述低温多晶硅层130相对的两端，所述第一轻掺杂区140a与所述第二轻掺杂区140b关于所述低温多晶硅层130对称部分的掺杂浓度相等。所述第一重掺杂区150a与所述第二重掺杂区150b与所述低温多晶硅层130同层设置，所述第一重掺杂区150a设置在所述第一 轻掺杂区140a远离所述低温多晶硅层130的一端，所述第二重掺杂区150b设置在第二轻掺杂区140b远离所述低温多晶硅层130的一端，所述第一重掺杂区150a与所述第二重掺杂区150b关于所述低温多晶硅层130对称部分的掺杂浓度相等。所述第一轻掺杂区140a、所述第二轻掺杂区140b、所述第一重掺杂区150a及所述第二重掺杂区150b的掺杂类型相同。所述第一绝缘层160包括第一部分160a及第二部分160b。所述第一部分160a覆盖所述低温多晶硅层130、所述第一轻掺杂区140a、所述第二轻掺杂区140b、所述第一重掺杂区150a及所述第二重掺杂区150b。所述第二部分160b设置在所述第一部分160a远离所述低温多晶硅层130的表面的中部，所述第二部分160b及所述第一部分160a形成“凸”字。所述栅极170，设置在第二部分160b上且所述栅极170与所述第二部分160b相交且相对设置的两端面所在的平面到所述低温多晶硅层的中点的距离相等。
所述基板110的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板110为绝缘层衬底能够减小所述基板110的高频损耗。
所述低温多晶硅层130、所述第一轻掺杂区140a、所述第二轻掺杂区140b、所述第一重掺杂区150a、所述第二重掺杂区150b、所述第一绝缘层160及所述栅极170设置在所述基板110的同侧。可以理解地，所述第一轻掺杂区140a、所述第二轻掺杂区140b、所述第一重掺杂区150a、所述第二重掺杂区150b、所述第一绝缘层160及所述栅极170可以直接或者间接设置在所述基板110的同侧。在另一实施方式中，所述第一轻掺杂区140a、所述第二轻掺杂区140b、所述第一重掺杂区150a、所述第二重掺杂区150b、所述第一绝缘层160及所述栅极170通过一缓冲层设置在所述基板110的同侧。所述缓冲层可以减小在所述薄膜晶体管10的制备过程中对所述基板110的损伤。
所述第一轻掺杂区140a与所述低温多晶硅层130接触的端面所在的平面为第一平面141，所述第二轻掺杂区140b与所述低温多晶硅层130接触的端面所在的平面为第二平面142。所述第一重掺杂区150a与所述第一轻掺杂区140a接触的一面所在的平面为第三平面143。所述第二重掺杂区150b设置在所述第二轻掺杂区150a远离所述低温多晶硅层130的一端，所述第二重掺杂 区150b与所述第二轻掺杂区140b接触的一面所在的平面为第四平面144。所述第二部分160b包括相对设置的第一端面161及第二端面162。所述第一端面161及所述第二端面162分别与所述第一部分160a邻近所述第二部分160b的表面相交，所述第一端面161所在的平面与所述第一平面141共面，所述第二端面162与所述第二平面142共面。
所述第一部分160a开设有对应所述第一重掺杂区150a的第一贯孔163及对应所述第二重掺杂区150b的第二贯孔164。相应地，所述薄膜晶体管还包括第二绝缘层180、源极190a、漏极190b及平坦层190c。所述第二绝缘层180覆盖所述栅极170，所述第二绝缘层180开设有第三贯孔181及第四贯孔182。所述第三贯孔181与所述第一贯孔163连通，所述第四贯孔182与所述第二贯孔164连通。所述源极190a和所述漏极190b设置在所述第二绝缘层180上，且所述源极190a通过所述第一贯孔163及所述第三贯孔181与所述第一重掺杂区150a相连。所述漏极190b通过所述第二贯孔164及所述第四贯孔182与所述第二重掺杂区150b相连。所述平坦层190c覆盖所述源极190a和所述漏极190b。
所述平坦层190c开设有第五贯孔191，所述第五贯孔191对应所述漏极190b设置。所述薄膜晶体管10还包括像素电极190d，所述像素电极190d设置在所述平坦层190c上且通过所述第五贯孔191连接所述漏极190b。
所述第一轻掺杂区140a、所述第二轻掺杂区140b、所述第一重掺杂区150a及所述第二重掺杂区150b的掺杂类型相同，比如，同为N型离子掺杂或者同为P型离子掺杂。所述N型离子掺杂的离子可以为但不仅限于为磷(P)离子、砷(AS)离子等。所述P型离子掺杂的离子可以为但不仅限于为硼(B)离子等。
所述第一重掺杂区150a的掺杂浓度大于所述第一轻掺杂区140a的掺杂浓度。所述第二重掺杂区150b的掺杂浓度大于所述第二轻掺杂区140b的掺杂浓度。本实施方式中的所述第一重掺杂区150a的掺杂浓度大于所述第一轻掺杂区140a的掺杂浓度，所述第二重掺杂区150b的掺杂浓度大于所述第一轻掺杂区140b的掺杂浓度既能够降低所述源极190a与所述低温多晶硅层130之间的接触电阻，降低所述漏极190b与所述低温多晶硅层130之间的接触电阻，又 能够减小所述薄膜晶体管10的泄露电流。
所述第一绝缘层160包括但不仅限于氮化硅(SiNx)、氧化硅(SiOx)材料等。
所述栅极170的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。所述栅极170的厚度为1500～6000埃。
所述第二绝缘层180包括但不仅限于氮化硅(SiNx)、氧化硅(SiOx)材料等。
所述源极190a和所述漏极190b的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
所述像素电极190d可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。举例而言，所述透明氧化物半导体膜层可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
本发明的薄膜晶体管10中的第一轻掺杂区140a及第二轻掺杂区140b与所述低温多晶硅层130同层设置，且设置在所述低温多晶硅层130相对的两端，所述第一轻掺杂区140a与所述第二轻掺杂区140b关于所述低温多晶硅层130对称部分的掺杂浓度相等；第一重掺杂区150a及第二重掺杂区150b与所述低温多晶硅层130同层设置，所述第一重掺杂区150a设置在所述第一轻掺杂区140a远离所述低温多晶硅层130的一端，所述第一重掺杂区150a与所述第二重掺杂区150b关于所述低温多晶硅层130对称部分的掺杂浓度相等，所述第一轻掺杂区140a、所述第二轻掺杂区140b、所述第一重掺杂区150a及所述第二重掺杂区150b的掺杂类型相同；第一绝缘层160包括第一部分160a及第二部分160b，所述第一部分160a覆盖所述低温多晶硅层130、所述第一轻掺杂区140a、所述第二轻掺杂区140b、所述第一重掺杂区150a及所述第二重掺杂区150b，所述第二部分160b设置在所述第一部分160a远离所述低温多晶硅层130的表面的中部，所述第二部分160b及所述第一部分160a形成“凸”字；栅极170，设置在第二部分160b上且所述栅极170与所述第二部分160b相交且相对设置的两端面所在的平面到所述低温多晶硅层130的中点的距离相等， 从而使得所述薄膜晶体管10的阈值电压较为稳定，使得所述薄膜晶体管10的电学特性得到提高。
本发明还提供了一种CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)器件1，请一并参阅图2和图3。图2为本发明的一较佳实施方式的CMOS器件的电路示意图；图3为本发明一较佳实施方式的CMOS的剖面结构示意图。所述CMOS器件1包括第一薄膜晶体管Q1和第二薄膜晶体管Q2，其中，当所述第一薄膜晶体管Q1为N型薄膜晶体管时，所述第二薄膜晶体管Q2为P型薄膜晶体管，当所述第一薄膜晶体管Q1为P型薄膜晶体管时，所述第二薄膜晶体管Q2为N型薄膜晶体管。所述第一薄膜晶体管Q1的栅极电连接所述第二薄膜晶体管Q2的栅极，所述第一薄膜晶体管Q1的漏极连接所述第二薄膜晶体管的源极。本实施方式中的CMOS器件中的第一薄膜晶体管Q1可以为前述介绍的薄膜晶体管10，或者所述CMOS器件中的第二薄膜晶体管Q2为前述介绍的薄膜晶体管10，在此不再赘述。
下面结合图1及对薄膜晶体管10的描述，对本发明薄膜晶体管的制备方法进行介绍。请参阅图4，图4为本发明一较佳实施方式的薄膜晶体管的制备方法的流程图。所述薄膜晶体管的制备方法包括但不仅限于以下步骤。
步骤S101，提供基板110。所述基板110的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板110为绝缘层衬底能够减小所述基板110的高频损耗。
步骤S102，在所述基板110的表面上形成多晶硅材料层并图案化所述多晶硅材料层，以形成低温多晶硅图案211。请一并参阅图5。在其他实施方式中，也可以在所述基板110的表面形成非晶硅材料层，再将所述非晶硅材料层进行准分子激光退火或者其他方法处理，以使所述非晶硅材料层中的非晶硅变为多晶硅。
步骤S103，在所述低温多晶硅图案211远离所述基板110的表面依次设置栅极绝缘材料层22、第一金属层23及第一光阻层24。请一并参阅图6。
步骤S104，对所述第一光阻层24进行图案化以保留对应所述低温多晶硅图案211的第一光阻图案241，所述第一光阻图案241包括相对设置的第一表面241a及第二表面241b，且所述第一表面241a与所述第二表面241b均与所 述第一金属层23邻近所述第一光阻层241的表面相交，所述第一表面241a及所述第二表面241b所在的平面均位于所述低温多晶硅图案211与基板110相交且相对设置的两表面所在的平面之间。请一并参阅图7。
步骤S105，对所述第一金属层23进行图案化，移除未被所述第一光阻图案241覆盖的第一金属层23，保留被所述第一光阻图案241覆盖的第一金属层23，且对所述栅极绝缘层22进行部分蚀刻，以保留对应所述低温多晶硅图案211的第一绝缘层160，所述第一绝缘层160包括第一部分160a、第二部分160b，所述第一部分160a覆盖所述低温多晶硅图案211，所述第二部分160b设置在所述第一部分160a远离所述低温多晶硅图案211的表面的中部，所述第二部分160b及所述第一部分160a形成“凸”字，且所述第二部分160b相对的两个端面分别与所述第一表面241a及所述第二表面241b共面。请一并参阅图8。
步骤S106，对所述第一光阻图案241的两端进行灰化。在本实施方式中，所述第一光阻图案241两端灰化的区域分别对应所述薄膜晶体管10中的第一轻掺杂区140a及所述第二轻掺杂区140b，请参阅图9。
步骤S107，对所述第一金属层23进行蚀刻，以移除所述第一金属层23的对应所述第一光阻图案241灰化区域的两端，保留下来的所述第一金属层230以形成栅极170，请参阅图10。
步骤S108，以所述第一光阻图案241及所述第一绝缘层160为掩膜对所述低温多晶硅图案211进行离子掺杂，所述第一光阻图案241对应的低温多晶硅图案211形成低温多晶硅层130，仅被所述第一部分160a及所述第二部分160b覆盖且未被所述第一光阻图案241覆盖的所述低温多晶硅图案211形成所述第一轻掺杂区140a及所述第二轻掺杂区140b，仅被所述第一部分160a覆盖的低温多晶硅图案211形成第一重掺杂区150a及第二重掺杂区150b。在本实施方式中，以所述第一光阻图案241及所述第一绝缘层160为掩膜对所述低温多晶硅图案211进行离子掺杂时，对应所述第一部分160a、所述第二部分160b及所述第一光阻图案241的掺杂的离子浓度相等，掺杂时间相同。请一并参阅图11。
本发明的薄膜晶体管的制备方法中以所述第一光阻图案241及所述第一 绝缘层160为掩膜，利用所述第一部分160a及所述第二部分160b自身的厚度，来实现最终掺杂到低温多晶硅图案211的各部分的离子浓度的不同。即，对应第一光阻图案241对应的低温多晶硅图案211为低温多晶硅层130，仅被所述第一部分160a及所述第二部分160b覆盖且未被所述第一光阻图案241覆盖的所述低温多晶硅图案211形成所述第一轻掺杂区140a及所述第二轻掺杂区140b，仅被所述第一部分160a覆盖的低温多晶硅图案211形成第一重掺杂区150a及第二重掺杂区150b。此步骤中不需要使用光罩工艺，从而简化了薄膜晶体管的制程工序。
步骤S109，对所述第一绝缘层160进行蚀刻，以移除所述第二部分160b中未被所述栅极170覆盖的部分。请参阅图12。
步骤S110，剥离所述第一光阻图案241。请参阅图13。
所述薄膜晶体管的制备方法还包括如下步骤。
步骤S111，在所述栅极170及所述第一绝缘层160上沉积第二绝缘层180。
步骤S112，在所述第二绝缘层180及所述第一绝缘层160对应所述第一重掺杂区150a及第二重掺杂区150b开设贯孔，以在所述第一绝缘层160上形成对应第一重掺杂区150a的第一贯孔163及对应所述第二重掺杂区150b的第二贯孔164，以及在所述第二绝缘层180上形成与所述第一贯孔163连通的第三贯孔181以及与所述第二贯孔164连通的第四贯孔182。
步骤S113，在所述第二绝缘层180上沉积第二金属层25，对所述第二金属层25进行图案化，以形成通过所述第一贯孔163及所述第三贯孔181与所述第一重掺杂区150a连接的源极190a，以及通过所述第二贯孔164及所述第四贯孔182与所述第二重掺杂区150b连接的漏极190b。
步骤S114，在所述源极190a和所述漏极190b上沉积平坦层190c。
在一实施方式中，所述薄膜晶体管的制备方法还包括如下步骤。
步骤S115，在所述平坦层190c上对应所述漏极190b开设第五贯孔191。
步骤S116，在所述平坦层190c上沉积透明导电层，并对所述透明导电层进行图案化，以形成通过所述第五贯孔191与所述漏极190b连接的像素电极190d。步骤S109至步骤S116请一并参阅图14。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发 明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (14)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    基板；
    低温多晶硅层，邻近所述基板设置；
    第一轻掺杂区及第二轻掺杂区，与所述低温多晶硅层同层设置，且设置在所述低温多晶硅层相对的两端，所述第一轻掺杂区与所述第二轻掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相等；
    第一重掺杂区及第二重掺杂区，与所述低温多晶硅层同层设置，所述第一重掺杂区设置在所述第一轻掺杂区远离所述低温多晶硅层的一端，所述第一重掺杂区与所述第二重掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相等，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型相同；
    第一绝缘层，包括第一部分及第二部分，所述第一部分覆盖所述低温多晶硅层、所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区，所述第二部分设置在所述第一部分远离所述低温多晶硅层的表面的中部，所述第二部分及所述第一部分形成“凸”字；
    栅极，设置在第二部分上且所述栅极与所述第二部分相交且相对设置的两端面所在的平面到所述低温多晶硅层的中点的距离相等。
  2. 如权利要求1所述的薄膜晶体管，其中，所述第一轻掺杂区与所述低温多晶硅层接触的端面所在的平面为第一平面，所述第二轻掺杂区与所述低温多晶硅层接触的端面所在的平面为第二平面，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，所述第二部分包括相对设置的第一端面及第二端面，且所述第一端面及所述第二端面分别与所述第一部分邻近所述第二部分的表面相交，所述第一端面所在的平面与所述第一平面共面，所述第二端面与所述第二平面共面。
  3. 如权利要求1所述的薄膜晶体管，其中，所述第一部分开设有对应所述第一重掺杂区的第一贯孔及对应所述第二重掺杂区的第二贯孔，所述薄膜晶体管还包括：
    第二绝缘层，覆盖所述栅极，所述第二绝缘层开设有第三贯孔及第四贯孔，所述第三贯孔与所述第一贯孔连通，所述第四贯孔与所述第二贯孔连通；
    源极和漏极，设置在所述第二绝缘层上，且源极通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区相连，所述漏极通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区相连；
    平坦层，覆盖所述源极和所述漏极。
  4. 如权利要求3所述的薄膜晶体管，其中，所述平坦层开设有第五贯孔，所述第五贯孔对应所述漏极设置，所述薄膜晶体管还包括像素电极，所述像素电极设置在所述平坦层上且通过所述第五贯孔连接所述漏极。
  5. 如权利要求1所述的薄膜晶体管，其中，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型为N型离子掺杂或者为P型离子掺杂。
  6. 一种薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法包括：
    提供基板；
    在所述基板的表面上形成多晶硅材料层并图案化所述多晶硅材料层，以形成低温多晶硅图案；
    在所述低温多晶硅图案远离所述基板的表面依次设置栅极绝缘材料层、第一金属层及第一光阻层；
    对所述第一光阻层进行图案化以保留对应所述低温多晶硅图案的第一光阻图案，所述第一光阻图案包括相对设置的第一表面及第二表面，且所述第一表面与所述第二表面均与所述第一金属层邻近所述第一光阻层的表面相交，所述第一表面及所述第二表面所在的平面均位于所述低温多晶硅图案与基板相交且相对设置的两表面所在的平面之间；
    对所述第一金属层进行图案化，移除未被所述第一光阻图案覆盖的第一金属层，保留被所述第一光阻图案覆盖的第一金属层，且对所述栅极绝缘层进行部分蚀刻，以保留对应所述低温多晶硅图案的第一绝缘层，所述第一绝缘层包括第一部分、第二部分，所述第一部分覆盖所述低温多晶硅图案，所述第二部分设置在所述第一部分远离所述低温多晶硅图案的表面的中部，所述第二部分及所述第一部分形成“凸”字，且所述第二部分相对的两个端面分别与所述第一表面及所述第二表面共面；
    对所述第一光阻图案的两端进行灰化；
    对所述第一金属层进行蚀刻，以移除所述第一金属层的对应所述第一光阻图案灰化区域的两端，保留下来的所述第一金属层以形成栅极；
    以所述第一光阻图案及所述第一绝缘层为掩膜对所述低温多晶硅图案进行离子掺杂，所述第一光阻图案对应的低温多晶硅图案形成低温多晶硅层，仅被所述第一部分及所述第二部分覆盖且未被所述第一光阻图案覆盖的所述低温多晶硅图案形成所述第一轻掺杂区及所述第二轻掺杂区，仅被所述第一部分覆盖的低温多晶硅图案形成第一重掺杂区及第二重掺杂区；
    对所述第一绝缘层进行蚀刻，以移除所述第二部分中未被所述栅极覆盖的部分；
    剥离所述第一光阻图案。
  7. 如权利要求6所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括：
    在所述栅极及所述第一绝缘层上沉积第二绝缘层；
    在所述第二绝缘层及所述第一绝缘层对应所述第一重掺杂区及第二重掺杂区开设贯孔，以在所述第一绝缘层上形成对应第一重掺杂区的第一贯孔及对应所述第二重掺杂区的第二贯孔，以及在所述第二绝缘层上形成与所述第一贯孔连通的第三贯孔以及与所述第二贯孔连通的第四贯孔；
    在所述第二绝缘层上沉积第二金属层，对所述第二金属层进行图案化，以形成通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区连接的源极，以及通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区连接的漏极；
    在所述源极和所述漏极上沉积平坦层。
  8. 如权利要求6所述的薄膜晶体管的制备方法，其中，所述离子掺杂为N型离子掺杂或者为P型离子掺杂。
  9. 如权利要求6所述的薄膜晶体管的制备方法，其中，以所述第一光阻图案及所述第一绝缘层为掩膜对所述低温多晶硅图案进行离子掺杂时，对应所述第一部分、所述第二部分及所述第一光阻图案的掺杂的离子浓度相等，掺杂时间相同。
  10. 一种CMOS器件，其中，所述CMOS器件薄膜晶体管，所述薄膜晶体管包括：
    基板；
    低温多晶硅层，邻近所述基板设置；
    第一轻掺杂区及第二轻掺杂区，与所述低温多晶硅层同层设置，且设置在所述低温多晶硅层相对的两端，所述第一轻掺杂区与所述第二轻掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相等；
    第一重掺杂区及第二重掺杂区，与所述低温多晶硅层同层设置，所述第一重掺杂区设置在所述第一轻掺杂区远离所述低温多晶硅层的一端，所述第一重掺杂区与所述第二重掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相等，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型相同；
    第一绝缘层，包括第一部分及第二部分，所述第一部分覆盖所述低温多晶硅层、所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区，所述第二部分设置在所述第一部分远离所述低温多晶硅层的表面的中部，所述第二部分及所述第一部分形成“凸”字；
    栅极，设置在第二部分上且所述栅极与所述第二部分相交且相对设置的两端面所在的平面到所述低温多晶硅层的中点的距离相等。
  11. 如权利要求10所述的CMOS器件，其中，所述第一轻掺杂区与所述低温多晶硅层接触的端面所在的平面为第一平面，所述第二轻掺杂区与所述低温多晶硅层接触的端面所在的平面为第二平面，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，所述第二部分包括相对设置的第一端面及第二端面，且所述第一端面及所述第二端面分别与所述第一部分邻近所述第二部分的表面相交，所述第一端面所在的平面与所述第一平面共面，所述第二端面与所述第二平面共面。
  12. 如权利要求10所述的CMOS器件，其中，所述第一部分开设有对应所述第一重掺杂区的第一贯孔及对应所述第二重掺杂区的第二贯孔，所述薄膜晶体管还包括：
    第二绝缘层，覆盖所述栅极，所述第二绝缘层开设有第三贯孔及第四贯孔，所述第三贯孔与所述第一贯孔连通，所述第四贯孔与所述第二贯孔连通；
    源极和漏极，设置在所述第二绝缘层上，且源极通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区相连，所述漏极通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区相连；
    平坦层，覆盖所述源极和所述漏极。
  13. 如权利要求12所述的CMOS器件，其中，所述平坦层开设有第五贯孔，所述第五贯孔对应所述漏极设置，所述薄膜晶体管还包括像素电极，所述像素电极设置在所述平坦层上且通过所述第五贯孔连接所述漏极。
  14. 如权利要求10所述的CMOS器件，其中，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型为N型离子掺杂或者为P型离子掺杂。
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