WO2017201727A1 - 一种异步fifo电路及时延确定方法 - Google Patents

一种异步fifo电路及时延确定方法 Download PDF

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Publication number
WO2017201727A1
WO2017201727A1 PCT/CN2016/083616 CN2016083616W WO2017201727A1 WO 2017201727 A1 WO2017201727 A1 WO 2017201727A1 CN 2016083616 W CN2016083616 W CN 2016083616W WO 2017201727 A1 WO2017201727 A1 WO 2017201727A1
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Prior art keywords
address
read
delay
write
circuit
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PCT/CN2016/083616
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English (en)
French (fr)
Inventor
夏山春
张志伟
陈默
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华为技术有限公司
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Priority to CN201680086087.6A priority Critical patent/CN109155798B/zh
Priority to PCT/CN2016/083616 priority patent/WO2017201727A1/zh
Publication of WO2017201727A1 publication Critical patent/WO2017201727A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming

Definitions

  • Embodiments of the present invention relate to the field of wireless communications, and in particular, to a method for determining a time delay of an asynchronous FIFO (First In First Out First Queue) circuit.
  • asynchronous FIFO First In First Out First Queue
  • a plurality of communication devices are often included, the clock domains of the plurality of communication devices are basically independent, and the clock domains of the plurality of modules included in the same communication device are basically independent, and therefore, Data transmission between any two communication devices or data transmission between any two modules in a plurality of modules is basically a data transmission between different clock domains.
  • the data transmission between the Common Public Radio Interface (CPRI) of any two communication devices is data transmission in different clock domains, and the numbers in the Radio Radio Unit (RRU) in the same communication device.
  • Data transmission between modules on the Digital Front End (DFE) is also a data transmission in different clock domains.
  • CPRI Common Public Radio Interface
  • RRU Radio Radio Unit
  • asynchronous FIFO circuits of communication devices are often used for data transmission.
  • the normal operation of many services in a wireless communication system requires precise timing synchronization, and the asynchronous FIFO circuit often has a certain delay.
  • the introduction of the delay of the asynchronous FIFO circuit makes it impossible for the communication device to accurately determine the data transmission and reception time.
  • the timing synchronization accuracy of the communication device is affected. Therefore, when data is transmitted through the asynchronous FIFO circuit, in order to improve the timing synchronization accuracy of the communication device, it is necessary to determine the delay of the asynchronous FIFO circuit.
  • the asynchronous FIFO circuit includes: a write clock generation circuit 1, a read clock generation circuit 2, a write address generation circuit 3, a read address generation circuit 4, and a random access memory 5.
  • the synchronous logic circuit 6 and the address comparison logic circuit 7. Referring to FIG. 1, the output terminal 1a of the write clock generating circuit 1 is connected to the input terminal 3a of the write address generating circuit 3, and the first output terminal 3b of the write address generating circuit 3 is connected to the first input terminal 5a of the random access memory 5, and is written.
  • the second output terminal 3c of the address generation circuit 3 is connected to the first input terminal 6a of the synchronization logic circuit 6, and the output terminal 6b of the synchronization logic circuit 6 is connected to the first input terminal 7a of the address comparison logic circuit 7, the synchronization logic circuit 6
  • the second input terminal 6c and the second input terminal 7b of the address comparison logic circuit 7 are respectively connected to the output terminal 2a of the read clock generating circuit 2; the output terminal 2a of the read clock generating circuit 2 is also connected to the read address generating circuit
  • the input terminal 4a of 4 is connected, and the output terminal 4b of the read address generating circuit 4 is connected to the second input terminal 5b of the random access memory 5 and the third input terminal 7c of the address comparison logic circuit 7, respectively, and the output terminal of the address comparison logic circuit 7 7d is connected to the set terminal 4c of the read address generating circuit 4.
  • the data transmission between the communication devices of any two different clock domains in the wireless communication processing system is taken as an example.
  • the first communication device needs to transmit the target data to be transmitted to the second communication device, at this time, the first communication The device can perform write operations and read operations on the random access memory in the FIFO circuit itself.
  • the write address generation circuit may generate a write address signal on the rising edge of the write clock signal generated by the write clock generation circuit, the write address signal carrying the write address, the first communication device The target data can be written to a location in the random access memory corresponding to the write address.
  • the read address generating circuit may generate a read address signal on the rising edge of the read clock signal generated by the read clock generating circuit, the read address signal carrying the read address, the first communication The device can read the data stored at the location corresponding to the read address from the random access memory and transmit the read data to the second communication device.
  • the first communication device may further determine a product of the specified read/write address difference and the clock cycle as a delay of the asynchronous FIFO circuit, and specify a read/write address difference.
  • the address difference between the write address and the read address set in advance, the clock period is the period of the read clock signal or the write clock signal, and the read clock signal is equal to the period of the write clock signal.
  • the real delay of the asynchronous FIFO circuit includes two parts: fractional delay and integer delay.
  • the fractional delay is introduced by the phase difference between the read clock signal and the write clock signal.
  • the integer delay is written to the random access memory at the same time.
  • the difference between the address of the write address and the read address of the read operation is introduced.
  • the fractional delay is not determined, only the integer delay is determined, and the integer delay is directly determined as the delay of the asynchronous FIFO circuit, which causes the asynchronous FIFO circuit delay determination result to be inaccurate.
  • the present invention provides an asynchronous FIFO circuit delay determination method.
  • the technical solution is as follows:
  • a FIFO circuit comprising: a write clock generation circuit, a read clock generation circuit, a write address generation circuit, a read address generation circuit, a random access memory, a delay line circuit, a synchronization logic circuit, Address comparison logic circuit and processor;
  • An output of the write clock generating circuit is coupled to an input of the write address generating circuit, a first output of the write address generation circuit is coupled to the first input of the random access memory, and a second output of the write address generation circuit is coupled to the first input of the delay line circuit, the delay line a second input of the circuit is coupled to the first output of the processor, an output of the delay line circuit is coupled to a first input of the synchronous logic circuit, an output of the synchronous logic circuit is a first input end of the address comparison logic circuit is connected, and a second input end of the synchronous logic circuit and a second input end of the address comparison logic circuit are respectively connected to an output end of the read clock generation circuit;
  • An output of the read clock generating circuit is further connected to an input end of the read address generating circuit, and an output end of the read address generating circuit is connected to a second input end of the random access memory, the read address generating circuit
  • the output is also coupled to a third input of the address comparison logic, and the first output of the address comparison logic is coupled to an input of the processor.
  • the write clock generation circuit is configured to generate a write clock signal; the read clock generation circuit is configured to generate a read clock signal; the write address generation circuit is configured to generate a plurality of write address signals and a write indication signal, each write address signal carrying a write address
  • the write indication signal is generated based on at least two write addresses generated by the write address generation circuit, and the write indication signal is changed from the first logic level to the second logic level when the write address generation circuit generates the designated write address,
  • the write address generation circuit can send the generated multiple write address signals to the random access memory through the first output end of the same, and can send the generated write indication signal to the delay line circuit through the second output end thereof;
  • the address generating circuit is configured to generate a plurality of read address signals, each read address signal carrying a read address, wherein the read address generating circuit can send the generated multiple read address signals to the random access memory and the address comparison through the output terminal thereof.
  • the synchronization logic circuit is configured to receive the write indication signal on the rising edge of the read clock signal generated by the read clock generation circuit, and receive the received write indication The signal is sent to the address comparison logic circuit; the address comparison logic circuit is configured to determine a read/write address difference based on the write indication signal and the read address signal, wherein the read/write address difference is a write address and a read operation of the current write operation to the random access memory The address difference between the read addresses; the processor is configured to determine the fractional delay based on the read/write address difference determined by the address comparison logic circuit, and determine the delay of the asynchronous FIFO circuit based on the fractional delay, wherein the fractional delay is The delay introduced by the phase difference between the read clock signal and the write clock signal.
  • the write clock generation circuit, the read clock generation circuit, the write address generation circuit, the read address generation circuit, the random access memory, the delay line circuit, and the synchronous logic circuit can be implemented in hardware in practical applications, and the address comparison logic circuit And the processor can be in software form in practical applications. The embodiment of the present invention does not specifically limit this.
  • the asynchronous FIFO circuit includes a write clock generation circuit, a read clock generation circuit, a write address generation circuit, a read address generation circuit, a random access memory, a delay line circuit, a synchronization logic circuit, an address comparison logic circuit, and a processor.
  • the read address generating circuit can send the generated multiple read address signals to the address comparison logic circuit
  • the write address generating circuit can send the generated write indication signal to the delay line circuit
  • the delay line circuit can delay the write indication signal.
  • the synchronous logic circuit sends the address comparison logic circuit, and the address comparison logic circuit can determine the read/write address difference based on the write indication signal and the read address signal, and the processor can determine the decimal point based on the read/write address difference determined by the address comparison logic circuit.
  • the delay and based on the fractional delay, determines the delay of the asynchronous FIFO circuit, and therefore, the accurate determination of the delay of the asynchronous FIFO circuit can be achieved.
  • the second output of the address comparison logic circuit is coupled to the set terminal of the read address generation circuit.
  • the address comparison logic circuit is configured to reset the read address currently generated by the read address generation circuit when detecting that the write indication signal transitions from the first logic level to the second logic level.
  • the address comparison logic circuit can reset the read address currently generated by the read address, thereby ensuring the address difference between the write address of the write operation of the random access memory and the read address of the read operation at the same time.
  • the integer delay of the asynchronous FIFO circuit is fixed.
  • the second output end of the processor and the reset of the write address generating circuit The terminal is connected, and the third output of the processor is connected to the reset end of the read address generating circuit.
  • the processor is configured to set the write address power-on reset value to the third address and the read address power-on reset value to the fourth address when the reset setting instruction is received, and the address difference between the third address and the fourth address is Specify the read/write address difference.
  • the write address power-on reset value is the initial write address generated by the write address generation circuit at power-on.
  • the read address power-on reset value is the initial read address generated by the read address generation circuit at power-on.
  • the reset setting command is used to set the write address power-on reset value and the read address power-on reset value.
  • the write address power-on reset value may be set to a third address
  • the read address power-on reset value is set to a fourth address
  • the address difference between the third address and the fourth address is a specified read-write address.
  • the delay line circuit includes: N-1 a delay section and N taps, the N being a natural number greater than one;
  • the N-1 delay sections are connected in series, and one end of the ith delay section of the N-1 delay sections is connected to an i-th tap of the N taps, and the N-1 delay sections are the first The other end of the i delay sections is connected to the i+1th tap of the N taps, the i being greater than or equal to 1 and less than or equal to N-1.
  • each of the N-1 delay sections is used to delay the write indication signal input to the delay section.
  • N taps correspond to N preset delays one by one. Therefore, for each of the N taps, when the delay line circuit detects the write indication signal, the write indication signal may be delayed by the tap to a preset delay corresponding to the tap and then sent to the synchronization logic circuit.
  • the delay line circuit is further configured to delay the write indication signal by a second delay and then send the signal to the synchronous logic circuit.
  • the second delay is a delay that can eliminate the metastable state of the synchronous logic circuit.
  • the delay line circuit delays the write indication signal by a second delay and then sends it to the synchronous logic circuit to avoid the metastable state of the synchronous logic circuit, thereby ensuring that the synchronous logic circuit can receive a stable write indication signal.
  • the N taps in the delay line circuit are in one-to-one correspondence with the N preset delays, and the delay line circuit can sequentially delay the write indication signal by N preset delays through the N taps.
  • the synchronous logic circuit sends the address comparison logic circuit, so that the address comparison logic circuit can sequentially determine N read/write address differences corresponding to the N preset delays one by one, thereby ensuring that the subsequent processor can be based on the N read/write addresses. Poor, to achieve accurate determination of fractional delay.
  • the synchronization logic circuit includes multiple triggers in series Each of the plurality of series-connected flip-flops is configured to receive a write indication signal on a rising edge of a read clock signal generated by the read clock generating circuit.
  • the first stage trigger of the plurality of flip-flops included in the synchronous logic circuit receives the write indication signal on the rising edge of the read clock signal, and sends the write indication signal to the second-stage flip-flop, and the second-stage flip-flop is in the read clock.
  • Receiving the write indication signal by the rising edge of the signal, and transmitting the write indication signal to the third stage flip-flop, such that until the write indication signal is sent to the m-th level flip-flop included in the synchronization logic circuit receives the write indication signal on a rising edge of the read clock signal, and sends the write indication signal to the address comparison logic circuit, where m is a natural number and m is greater than or equal to two.
  • the first to mth flip-flops of the plurality of flip-flops are determined according to the serial sequence of the plurality of flip-flops, that is, the flip-flops that can be connected to the delay line circuit Determined as the first-level trigger, the trigger after the first-level trigger is sequentially determined as the second-level trigger, the third-level trigger, the m-th level trigger.
  • the synchronous logic circuit may send the write indication signal to the synchronous logic circuit through a plurality of flip-flops, wherein each of the plurality of series-connected flip-flops is a read clock signal generated by the read clock generating circuit.
  • the rising edge receives the write indication signal and transmits. Therefore, the signal of the write indication signal and the read address signal can be synchronized, thereby facilitating the subsequent address comparison logic circuit to determine the read/write address difference based on the write indication signal and the read address signal.
  • the read address generating circuit is configured to send the generated multiple read address signals to the address Comparison logic circuit
  • the write address generation circuit is configured to send the generated write indication signal to the delay line circuit, the write indication signal is generated based on at least two write addresses generated by the write address generation circuit, and the write indication The signal transitions from the first logic level to the second logic level when the write address generation circuit generates the designated write address;
  • the processor configured to, by the read address generation circuit, the delay line circuit, the synchronization logic circuit, and the address comparison logic circuit, based on the write indication signal, the plurality of read address signals, and Reading the read clock signal generated by the clock generating circuit to obtain N read/write address differences, and the N read/write address differences are in one-to-one correspondence with N preset delays in the delay line circuit;
  • the processor is further configured to determine a fractional delay based on the N read and write address differences and a wiring delay, and determine a delay of the asynchronous FIFO circuit based on the fractional delay, the wiring delay a delay introduced by the wiring between the write address generation circuit and the synchronous logic circuit, the fractional delay being a phase between the read clock signal and a write clock signal generated by the write clock generation circuit The delay introduced by the difference.
  • the processor may generate a read clock signal generated by the write indication signal, the plurality of read address signals, and the read clock generation circuit by using the read address generation circuit, the delay line circuit, the synchronization logic circuit, and the address comparison logic circuit. Obtaining N read/write address differences, and determining a fractional delay based on the N read/write address differences and the wiring delay, and determining the time of the asynchronous FIFO circuit based on the fractional delay Deferred, an accurate determination of the asynchronous FIFO circuit is achieved.
  • the delay line circuit is configured to: when the write indication signal is detected, The indication signal is delayed by a preset delay corresponding to the ith tap of the N taps, and sent to the address comparison logic circuit by the synchronization logic circuit, the N taps and the N preset delays One correspondence
  • the address comparison logic circuit configured to acquire the currently received one when the write indication signal is detected to be the second logic level by the rising edge of the read clock signal Reading a read address carried in the address signal, and determining a read/write address difference corresponding to the i-th tap based on the specified write address and the acquired read address, and sending the read/write address difference corresponding to the i-th tap Giving the processor;
  • the preset delay corresponding to the i-th tap of the taps is sent to the address comparison logic circuit through the synchronization logic circuit.
  • the processor can set the tap currently used by the delay line circuit, that is, the processor can set the preset delay currently used by the delay line circuit, thereby ensuring that the delay line circuit can be traversed in sequence.
  • the N taps sequentially delay the write indication signal by the N preset delays.
  • a loop operation can be performed by the cooperation of the delay line circuit, the synchronous logic circuit, the address comparison logic circuit and the processor, thereby ensuring that the read/write address difference corresponding to each tap of the N taps can be obtained. That is, it is ensured that the read/write address difference corresponding to each preset delay in the N preset delays is obtained, thereby ensuring the accuracy of the delay when the subsequent processor determines the decimal based on the N read/write address differences. .
  • the second aspect provides a method for determining a delay, which is applied to the asynchronous FIFO circuit according to any one of the foregoing possible implementation manners of the first aspect to the first aspect, the method includes :
  • the read address generation circuit transmits a plurality of generated read address signals to the address comparison logic circuit, and the write address generation circuit generates the write An indication signal is sent to the delay line circuit, the write indication signal is based on the At least two write addresses generated by the write address generation circuit are generated, and the write indication signal is changed from the first logic level to the second logic level when the write address generation circuit generates the designated write address;
  • the processor based on the read address generation circuit, the delay line circuit, the synchronization logic circuit, and the address comparison logic circuit, based on the write indication signal, the plurality of read address signals, and the read clock Generating a read clock signal generated by the circuit to obtain N read/write address differences, wherein the N read/write address differences are in one-to-one correspondence with N preset delays in the delay line circuit, and the N is a natural number greater than 1. ;
  • the processor determines a fractional delay based on the N read and write address differences and a wiring delay, and the wiring delay is a delay introduced by a wiring between the write address generation circuit and the synchronous logic circuit
  • the fractional delay is a delay introduced by a phase difference between the read clock signal and a write clock signal generated by the write clock generation circuit
  • the processor determines a delay of the asynchronous FIFO circuit based on the fractional delay.
  • the read address generating circuit in the process of performing a read operation on the random access memory, each time the read address generating circuit detects a rising edge of the read clock signal, a read address signal is generated, and the read address signal carries the read address, that is, The read address generating circuit can generate a read address signal every cycle of the read clock signal. Meanwhile, in the process of writing to the random access memory, the write address generating circuit can generate a write indication signal and a plurality of write address signals, each of the write address signals carrying a write address, and when the write address generation circuit detects the generated When the write address is the designated write address, the write indication signal can be changed from the first logic level to the second logic level.
  • the state of the first logic level is opposite to the state of the second logic level, such as when the first logic level is 0, the second logic level may be 1; when the first logic level is 1, when the first logic level is 1, The second logic level may be 0, which is not specifically limited in this embodiment of the present invention.
  • the write address generation circuit may further change the write indication signal from the second logic level to the first logic level when detecting that the generated write address is any write address other than the specified write address.
  • the embodiment of the invention is not specifically limited thereto.
  • the processor may generate a read clock signal generated by the write indication signal, the plurality of read address signals, and the read clock generation circuit by using the read address generation circuit, the delay line circuit, the synchronization logic circuit, and the address comparison logic circuit. Obtaining N read/write address differences, and determining a fractional delay based on the N read/write address differences and routing delays, and determining a delay of the asynchronous FIFO circuit based on the fractional delay to achieve accurateness of the asynchronous FIFO circuit determine.
  • the delay line The circuit includes N-1 delay sections and N taps, and the N taps are in one-to-one correspondence with the N preset delays;
  • the processor based on the read address generation circuit, the delay line circuit, the synchronization logic circuit, and the address comparison logic circuit, based on the write indication signal, the plurality of read address signals, and the read clock Generate a read clock signal generated by the circuit to obtain N read/write address differences, including:
  • the delay line circuit detects the write indication signal, delaying the write indication signal by a preset delay corresponding to an ith tap of the N taps, and sending the address to the address by using the synchronization logic circuit. Comparing logic circuits, said i being greater than or equal to 1 and less than or equal to N-1;
  • the address comparison logic detects that the write indication signal changes from the first logic level to the second logic level on a rising edge of the read clock signal, acquiring a currently received read address signal Determining a read/write address difference corresponding to the i-th tap based on the specified write address and the acquired read address, and transmitting the read/write address difference corresponding to the i-th tap to the processor;
  • each of the N-1 delay sections is used to delay the write indication signal input to the delay section.
  • N taps correspond to N preset delays one by one.
  • the processor can set the tap currently used by the delay line circuit, that is, the processor can set the preset delay currently used by the delay line circuit, thereby ensuring that the delay line circuit can sequentially traverse the N. Taps to delay the write indication signal by the N preset delays.
  • a loop operation can be performed by the cooperation of the delay line circuit, the synchronous logic circuit, the address comparison logic circuit and the processor, thereby ensuring that the read/write address difference corresponding to each tap of the N taps can be obtained. That is, it is ensured that the read/write address difference corresponding to each preset delay in the N preset delays is obtained, thereby ensuring the accuracy of the delay when the subsequent processor determines the decimal based on the N read/write address differences. .
  • the address comparison logic circuit determines, according to the specified write address and the acquired read address, The read/write address difference corresponding to the i-th tap includes:
  • the address comparison logic circuit determines an address difference between the specified write address and the acquired read address
  • the address comparison logic circuit decrements the number of flip-flops included in the synchronous logic circuit to obtain a first value
  • the address comparison logic circuit adds the determined address difference and the first value to obtain a read/write address difference corresponding to the ith tap.
  • the write indication signal is changed from the first logic level to the second logic level when the write address generation circuit generates the designated write address, and the write indication signal is delayed by the synchronization logic circuit.
  • a value clock cycle is sent to the address comparison logic circuit. Therefore, when the address comparison logic detects that the write indication signal changes from the first logic level to the second logic level, the write address generation circuit generates the specified write. After the address, the first value of the write address is generated again, so the address difference between the write address currently writing to the random access memory and the specified write address is the first value.
  • the address comparison logic circuit is used to determine the address difference between the write address of the write operation of the random access memory and the read address of the read operation at the same time, and the read address signal currently received by the address comparison logic circuit is directly sent to The address comparison logic circuit does not perform a delay. Therefore, when the address comparison logic circuit determines the read/write address difference corresponding to the i-th tap based on the specified write address and the acquired read address, the determined address difference and the A value is added to obtain the read/write address difference corresponding to the i-th tap, and the accurate determination of the read/write address difference corresponding to the i-th tap is realized.
  • the processor is based on the N reading and writing Address differences and routing delays, before determining the fractional delay, also include:
  • the processor acquires a maximum delay and a minimum delay introduced by the wiring between the write address generation circuit and the synchronization logic circuit from a stored back-end wiring report, the back-end wiring report is used for recording The delay introduced by all the wirings included in the asynchronous FIFO circuit;
  • the processor determines an average of the maximum delay and the minimum delay as the wiring delay.
  • the position of the write address generating circuit and the synchronous logic circuit affects the wiring delay
  • the position of the write address generating circuit and the synchronous logic circuit can be constrained when the asynchronous FIFO circuit is wired.
  • the routing delay determined by the minimum delay is as small and stable as possible, thereby ensuring that the processor determines the accuracy of the delay based on the routing delay based on the routing delay.
  • the processor is based on the N reading and writing Address differences and routing delays to determine fractional delays, including:
  • the processor determines a sum of the first delay and the wiring delay as the fractional delay.
  • the processor may determine the first delay from the N preset delays based on the N read/write address differences, and determine the sum of the first delay and the wiring delay as a decimal Delay, thus achieving an accurate determination of the fractional delay.
  • the processor based on the N read/write address differences, from the N preset times Yanzhong determines the first delay, including:
  • the processor sorts the N read/write address differences based on the N preset delays to obtain an order of the N read/write address differences
  • the processor acquires a first read/write address difference from the N read/write address differences based on the sequence of the N read/write address differences, where the first read/write address difference is based on the N read/write addresses
  • the read/write address difference of the jump in the address difference is determined, and the read/write address difference of the jump is a read/write address difference different from the previous read/write address difference;
  • the processor determines a preset delay corresponding to the first read/write address difference as the first time delay.
  • the processor may select the N read/write addresses according to the N preset delays.
  • the difference is sorted.
  • the N read/write address differences may be sorted according to the order of the N preset delays, which is not specifically limited in this embodiment of the present invention.
  • the processor obtains the first read/write address difference from the N read/write address differences based on the sequence of the N read/write address differences: when the sequence of the N read/write address differences is When the N preset delays are sorted from small to large, the processor obtains the read and write address difference of the first jump from the N read/write address differences, and determines the read and write address difference obtained as the first read.
  • Write address difference when the order of N read/write address differences is obtained by sorting the N preset delays from large to small, the processor determines the last hop read and write from the N read/write address differences. Address difference and read and write the last transition The difference between the previous bit read/write address of the address difference is determined as the first read/write address difference.
  • the processor is based on the N Write address difference and routing delay. After determining the fractional delay, it also includes:
  • the processor resets a read address generated by the read address generation circuit by the address comparison logic circuit based on the first delay and the second delay.
  • the processor since the second delay is a delay capable of canceling the metastable state of the synchronous logic circuit, the processor reads the address through the address comparison logic circuit based on the first delay and the second delay. During the process of resetting the read address generated by the circuit, the metastable state of the synchronous logic circuit can be avoided, thereby ensuring that the synchronous logic circuit can receive a stable write indication signal, thereby ensuring the read/write address difference determined by the address comparison logic circuit. Accuracy ensures that the address comparison logic circuit correctly resets the read address generated by the read address generation circuit.
  • the determining, by the processor, the second time delay based on the first time delay includes:
  • the processor determines a sum of the first delay and the first preset delay as the second delay, where the first preset The delay is greater than the signal stabilization time and is less than the third delay.
  • the signal stabilization time is the sum of the setup time and the hold time of the first-stage flip-flop, and the first-stage flip-flop is included in the synchronous logic circuit.
  • the third delay is a difference between a clock period and the signal stabilization time, and the clock period is the read clock signal or the Writing a period of a clock signal, the read clock signal being equal to a period of the write clock signal, the signal settling time being less than the third time delay;
  • the processor subtracts the first delay from the first delay to obtain the second delay.
  • the second preset delay is greater than the signal stabilization time and less than or equal to the fractional delay; or
  • the processor subtracts the first time delay from the first time delay to obtain the second time delay.
  • first preset delay and the second preset delay may be preset, and the first preset delay may be any delay within a range greater than the signal stabilization time and less than the third delay.
  • Second The preset delay may be any delay in the range of the signal stabilization time and less than or equal to the fractional delay, which is not specifically limited in the embodiment of the present invention.
  • the setup time and the hold time of the first-level trigger may be obtained from the back-end routing report, and the sum of the setup time and the hold time is determined as the signal stabilization time.
  • the signal stabilization time can also be obtained in other manners, which is not specifically limited in this embodiment of the present invention.
  • the delay line circuit delays the write indication signal to the synchronous logic circuit after delaying the first delay, the rising edge of the read clock signal is exactly at the jump point of the write indication signal, and therefore,
  • the metastable state of the synchronous logic circuit ensures that the write indication signal received by the synchronous logic circuit is relatively stable, and the second delay may be determined based on the first delay, and the delay line circuit may delay the write indication signal by the second delay and then send
  • the synchronous logic circuit is provided to ensure that the rising edge of the read clock signal is at a stable point of the write indication signal, thereby ensuring that the synchronous logic circuit can receive a stable write indication signal on the rising edge of the read clock signal.
  • the processor is based on the first time Extending the second delay, resetting the read address generated by the read address generating circuit by using the address comparison logic circuit, including:
  • the processor sends the first delay to the address comparison logic circuit
  • the processor sets a delay of the delay line circuit to the second time delay
  • the address comparison logic detects that the write indication signal changes from the first logic level to the second logic level on a rising edge of the read clock signal, acquiring the currently received read address signal Reading a address, determining, according to the specified write address and the acquired read address, a second read/write address difference, where the second read/write address difference is a read/write address difference corresponding to the second delay;
  • the N read/write address differences do not include the read/write address difference corresponding to the second delay, so The read/write address difference corresponding to the two delays is determined; and when the N preset delays include the second time delay, in order to ensure the determination The accuracy of the second read/write address difference may also be determined again for the read/write address difference corresponding to the second delay. Therefore, regardless of whether the second preset delay includes the second delay, after the processor sets the delay of the delay line circuit to the second delay, the address comparison logic circuit can pass the delay line circuit and the synchronous logic circuit. And the read address generating circuit determines the read/write address difference corresponding to the second delay, that is, determines the second read/write address difference.
  • the write indication signal may be delayed by the second delay and then sent to the address comparison logic. Circuit. Since the second delay is a delay that can eliminate the metastable state of the synchronous logic circuit, the synchronous logic circuit can receive the stable write indication signal and send the write indication signal to the address comparison logic circuit, thereby ensuring The address comparison logic circuit determines, based on the accuracy of the second read/write address difference determined by the write indication signal, that the address comparison logic circuit can correctly reset the read address generated by the read address generation circuit based on the second read/write address difference.
  • the processor is based on the first time Extending the second delay, resetting the read address generated by the read address generating circuit by the address comparison logic circuit, including:
  • the processor acquires a second read/write address difference from the N read/write address differences, and the second read/write address difference a read/write address difference corresponding to the second delay;
  • the processor sends the first delay and the second read/write address difference to the address comparison logic circuit
  • the processor sets a delay of the delay line circuit to the second time delay
  • the address comparison logic detects that the write indication signal is changed from the first logic level to the second logic level and receives the first delay on a rising edge of the read clock signal And the second read/write address difference, based on the specified write address, the first delay, the second read/write address difference, and the specified read/write address difference, currently generated by the read address generation circuit Read the address to reset.
  • the N read/write address differences include a read/write address difference corresponding to the second delay
  • the processor can Read from the N
  • the write address difference directly obtains the read/write address difference corresponding to the second delay, and sends the read/write address difference corresponding to the second delay to the address comparison logic circuit, and the address comparison logic circuit does not need to pass the delay line circuit and synchronize
  • the logic circuit and the read address generating circuit determine the read/write address difference corresponding to the second delay again, thereby saving processing resources in the asynchronous FIFO circuit.
  • the address comparison logic circuit is based on the specified The write address, the first delay, the second read/write address difference, and the designated read/write address difference are used to reset the read address currently generated by the read address generation circuit, including:
  • the address comparison logic circuit is based on the specified write An address and a number of flip-flops included in the synchronization logic circuit, determining a first address, and setting a read address currently generated by the read address generation circuit to the first address; or
  • the address comparison logic circuit is based on the specified write address and the synchronization logic when the first delay is greater than the signal stabilization time and the second read/write address difference is not equal to the specified read/write address difference.
  • the number of flip-flops included in the circuit determines a second address and sets a read address currently generated by the read address generation circuit to the second address.
  • the address comparison logic circuit may determine the first address or the second address based on the different conditions of the first delay and the second read/write address difference, and further read the read based on the first address or the second address.
  • the read address currently generated by the address generation circuit is reset, thereby achieving a correct reset of the read address currently generated by the read address generation circuit.
  • the processor is based on the fractional delay Determining the delay of the asynchronous FIFO circuit, including:
  • the processor obtains an integer delay, which is a delay introduced by an address difference between a write address of a write operation of the random access memory and a read address of a read operation at the same time;
  • the processor determines the sum of the fractional delay and the integer delay as the delay of the asynchronous FIFO circuit.
  • the processor when the processor obtains an integer delay, the product of the specified read/write address difference and the clock period may be determined as an integer delay.
  • the processor may also obtain an integer delay by other means. The embodiment does not specifically limit this.
  • the delay of the asynchronous FIFO circuit usually includes an integer delay And the fractional delay, therefore, the sum of the fractional delay and the integer delay can be determined as the delay of the asynchronous FIFO circuit, thereby achieving an accurate determination of the delay of the asynchronous FIFO circuit.
  • the method further includes:
  • the processor When the processor receives the reset setting instruction, setting the write address power-on reset value to the third address, and setting the read address power-on reset value to the fourth address, the third address and the fourth address
  • the address difference is a specified read/write address difference
  • the write address power-on reset value is an initial write address generated by the write address generation circuit when the power is turned on, and the read address power-on reset value is generated when the power-on reset value is powered on.
  • the reset setting command is used to set the write address power-on reset value and the read address power-on reset value.
  • the write address power-on reset value is set to the third address
  • the read address power-on reset value is set to the fourth address
  • the address difference between the third address and the fourth address is the specified read-write address difference.
  • the asynchronous FIFO circuit can ensure that the address difference between the write address of the write operation of the random access memory and the read address of the read operation is the specified read/write address difference at the beginning of power-on operation, thereby ensuring that the asynchronous FIFO circuit is The delays are the same throughout the working process, ensuring the accuracy of the delay of the determined asynchronous FIFO circuit.
  • the asynchronous FIFO circuit includes a write clock generation circuit, a read clock generation circuit, a write address generation circuit, a read address generation circuit, a random access memory, a delay line circuit, Synchronous logic, address comparison logic, and processor.
  • the read address generating circuit can send the generated multiple read address signals to the address comparison logic circuit, and the write address generating circuit can send the generated write indication signal to the delay line circuit, because the delay line circuit includes N presets.
  • the delay line circuit can sequentially delay the write indication signal by N preset delays and then send the same to the address comparison logic circuit through the synchronization logic circuit, and the address comparison logic circuit can determine the same according to the write indication signal and the read address signal.
  • FIG. 1 is a schematic structural diagram of an asynchronous FIFO circuit provided by the related art
  • FIG. 2 is a schematic structural diagram of an asynchronous FIFO circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another asynchronous FIFO circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another asynchronous FIFO circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a delay line circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a synchronous logic circuit according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for determining a delay according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a first write indication signal according to an embodiment of the present invention.
  • FIG. 9(a) is a schematic diagram of a second write indication signal according to an embodiment of the present invention.
  • FIG. 9(b) is a schematic diagram of a third write indication signal according to an embodiment of the present invention.
  • FIG. 10(a) is a schematic diagram of a fourth write indication signal according to an embodiment of the present invention.
  • FIG. 10(b) is a schematic diagram of a fifth write indication signal according to an embodiment of the present invention.
  • FIG. 10(c) is a schematic diagram of a sixth write indication signal according to an embodiment of the present invention.
  • 1 write clock generation circuit
  • 1a output of the write clock generation circuit
  • 2 a read clock generating circuit
  • 2a an output terminal of the read clock generating circuit
  • 3 write address generation circuit
  • 3a write address generation circuit input
  • 3b write address generation circuit first output
  • 3c write address generation circuit second output
  • 4 read address generation circuit; 4a: the input end of the read address generation circuit; 4b: the output end of the read address generation circuit; 4c: the set end of the read address generation circuit;
  • 5 random access memory
  • 5a random access memory first input
  • 5b random access memory second input
  • 6 a synchronous logic circuit
  • 6a a first input terminal of the synchronous logic circuit
  • 6b an output terminal of the synchronous logic circuit
  • 6c a second input terminal of the synchronous logic circuit
  • 7 address comparison logic circuit
  • 7a first input terminal of the address comparison logic circuit
  • 7b second input terminal of the address comparison logic circuit
  • 7c third input terminal of the address comparison logic circuit
  • 7d address comparison logic circuit Output.
  • 8 write clock generation circuit
  • 8a write the output end of the clock generation circuit
  • 9 a read clock generating circuit
  • 9a an output of the read clock generating circuit
  • 10 write address generation circuit
  • 10a write address generation circuit input terminal
  • 10b write address generation circuit first output terminal
  • 10c write address generation circuit second output terminal
  • 10d write address generation circuit reset terminal ;
  • 11 read address generation circuit; 11a: the input end of the read address generation circuit; 11b: the output end of the read address generation circuit; 11c: the set end of the read address generation circuit; 11d: the reset end of the read address generation circuit;
  • 12 random access memory
  • 12a random access memory first input
  • 12b random access memory second input
  • 13 a delay line circuit
  • 13a a first input terminal of the delay line circuit
  • 13b an output terminal of the delay line circuit
  • 13c a second input terminal of the delay line circuit
  • 14 a synchronous logic circuit
  • 14a a first input of the synchronous logic circuit
  • 14b an output of the synchronous logic circuit
  • 14c a second input of the synchronous logic circuit
  • 15 address comparison logic circuit
  • 15a first input terminal of the address comparison logic circuit
  • 15b second input terminal of the address comparison logic circuit
  • 15c third input terminal of the address comparison logic circuit
  • 15d address comparison logic circuit a first output
  • 15e a second output of the address comparison logic circuit
  • 16 processor; 16a: first output of the processor; 16b: input of the processor; 16c: second output of the processor; 16d: third output of the processor 16;
  • D delay section
  • T tap
  • P trigger
  • FIG. 2 is a schematic structural diagram of an asynchronous FIFO circuit according to an embodiment of the present invention.
  • the asynchronous FIFO circuit includes: a write clock generating circuit 8, a read clock generating circuit 9, a write address generating circuit 10, a read address generating circuit 11, a random access memory 12, a delay line circuit 13, a synchronous logic circuit 14, and an address. Comparing logic circuit 15 and processor 16;
  • the output terminal 8a of the write clock generating circuit 8 is connected to the input terminal 10a of the write address generating circuit 10, the first output terminal 10b of the write address generating circuit 10 and the first input terminal 12a of the random access memory 12
  • the second output terminal 10c of the connection, address generation circuit 10 is connected to the first input terminal 13a of the delay line circuit 13, and the second input terminal 13c of the delay line circuit 13 is connected to the first output terminal 16a of the processor 16, the delay line.
  • the output 13b of the circuit 13 is connected to the first input 14a of the synchronous logic circuit 14, the output 14b of the synchronous logic circuit 14 is connected to the first input 15a of the address comparison logic circuit 15, and the second input of the synchronous logic circuit 14 14c and the second input terminal 15b of the address comparison logic circuit 15 are respectively connected to the output terminal 9a of the read clock generating circuit 9; the output terminal 9a of the read clock generating circuit 9 is also connected to the input terminal 11a of the read address generating circuit 11, the read address The output terminal 11b of the generating circuit 11 is connected to the second input terminal 12b of the random access memory 12, and the output terminal 11b of the read address generating circuit 11 is also connected to the third input terminal 15c of the address comparison logic circuit 15, the address comparison logic circuit 15 The first output 15d is coupled to the input 16b of the processor 16.
  • the write clock generating circuit 8 can transmit the generated write clock signal to the write address generating circuit 10, and the write address generating circuit 10 can be at the write clock signal.
  • the rising edge generates a write address signal, and the write address signal carries a write address.
  • the communication device where the asynchronous FIFO circuit is located can write the data to be transmitted to the position corresponding to the write address in the random access memory 12.
  • the read clock generating circuit 9 can transmit the generated read clock signal to the read address generating circuit 11, and the read address generating circuit 11 can be at the read clock signal.
  • the rising edge generates a read address signal, and the read address signal carries a read address.
  • the communication device in which the asynchronous FIFO circuit is located can read the data stored at the position corresponding to the read address from the random access memory 12.
  • the write address generation circuit 10 can send the generated plurality of write address signals to the random access memory 12 through the first output terminal 10b, and can send the generated write indication signal to the second output terminal 10c to a delay line circuit 13;
  • the read address generation circuit 11 is configured to generate a plurality of read address signals, each of which carries a read address, wherein the read address generation circuit 11 can transmit the generated plurality of read address signals through the output terminal 11b.
  • Random access memory 12 and address comparison logic 15 random access memory 12 for storing data; delay line circuit 13 for input delay Write instruction signal delay circuit 13, and the delayed write means
  • the display signal is sent to the synchronous logic circuit 14;
  • the synchronous logic circuit 14 is configured to receive the write indication signal on the rising edge of the read clock signal generated by the read clock generating circuit 9, and send the received write indication signal to the address comparison logic circuit 15;
  • the comparison logic circuit 15 is configured to determine a read/write address difference based on the write indication signal and the read address signal, the read/write address difference being an address between a write address currently performing a write operation to the random access memory 12 and a read address performing a read operation
  • the processor 16 is configured to acquire N reading and writing by the read address generating circuit 11, the delay line circuit 13, the synchronous logic circuit 14, and the address comparison logic circuit 15 based on the write indication signal, the plurality of read address signals, and the read clock signal.
  • An address difference wherein the N read/write address differences are in one-to-one correspondence with N preset delays in the delay line circuit 13, the N being a natural number greater than 1; and the processor 16 is further configured to read and write based on the N
  • the address difference and the wiring delay determine the fractional delay, and determine the delay of the asynchronous FIFO circuit based on the fractional delay, wherein the wiring delay is a write address generation circuit and a synchronous logic circuit Wiring delay introduced between decimal read clock signal delay of a phase difference between the write clock signal delay introduced.
  • the specified write address and the N preset delays may be preset, which is not specifically limited in this embodiment of the present invention.
  • the state of the first logic level is opposite to the state of the second logic level, such as when the first logic level is 0, the second logic level is 1; when the first logic level is 1, the second The logic level is 0, which is not specifically limited in this embodiment of the present invention.
  • the write address generation circuit 10 can also jump from the second logic level to the first logic level when detecting that the generated write address is any write address other than the specified write address. This embodiment of the present invention does not specifically limit this.
  • the write clock generating circuit 8, the read clock generating circuit 9, the write address generating circuit 10, the read address generating circuit 11, the random access memory 12, the delay line circuit 13, and the synchronous logic circuit 14 can be used in practical applications.
  • the hardware form or the software form is implemented, for example, the write clock generating circuit 8 and the read clock generating circuit 9 are implemented by an oscillator, and further, the oscillator can be implemented by combining a phase locked loop, the write address generating circuit 10 and the read address generating circuit.
  • 11 can be implemented by a hardware programming device, such as an FPGA (Field Programmable Gate Array), the synchronous logic circuit 14 can be implemented by a flip-flop, and the functions of the address comparison logic circuit 15 and the processor 16 are actually applied.
  • FPGA Field Programmable Gate Array
  • the implementation may be implemented in the form of software or hardware, such as by a hardware coding device, which is not specifically limited in this embodiment of the present invention.
  • the foregoing circuit and the processor are implemented by software, they may be integrated on one hardware entity, or may be distributed on multiple hardware entities in a distributed manner or in a partial combination, which is not limited herein.
  • the function of the address comparison logic circuit 15 described above may also be performed by the processor.
  • the implementation of the processor 16 is implemented in the address comparison logic circuit 15 or the address comparison logic circuit 15 and the processor 16 are not integrated, which is not limited herein.
  • the second output terminal 15e of the address comparison logic circuit 15 is connected to the set terminal 11c of the read address generation circuit 11.
  • the address comparison logic circuit 15 is configured to reset the read address currently generated by the read address generation circuit 11 when detecting that the write indication signal transitions from the first logic level to the second logic level.
  • the second output terminal 16c of the processor 16 is connected to the reset terminal 10d of the write address generating circuit 10, and the third output terminal 16d of the processor 16 and the reset terminal 11d of the read address generating circuit 11 connection.
  • the processor 16 is configured to: when the reset setting instruction is received, set the write address power-on reset value to the third address, and set the read address power-on reset value to the fourth address, the address of the third address and the fourth address.
  • the difference is the specified read/write address difference
  • the write address power-on reset value is the initial write address generated by the write address generation circuit 10 at power-on
  • the read address power-on reset value is the initial read address generated by the read address generation circuit 11 at power-on.
  • the reset setting command is used to set the write address power-on reset value and the read address power-on reset value.
  • the specified read/write address difference may be set in advance, and the specified read/write address difference may be 7, 8 or the like, which is not specifically limited in the embodiment of the present invention.
  • the write address power-on reset value is set to the third address
  • the read address power-on reset value is set to the fourth address
  • the address difference between the third address and the fourth address is the designated read.
  • the write address difference can ensure that the address difference between the write address of the write operation of the random access memory 12 and the read address of the read operation is the specified read/write address difference when the asynchronous FIFO circuit first starts operating, thereby ensuring the The asynchronous FIFO circuit has the same delay throughout the entire working process.
  • the delay line circuit 13 includes: N-1 delay sections D and N taps T, N being a natural number greater than one;
  • N-1 delay sections are connected in series, one end of the ith delay section of the N-1 delay sections is connected with the i-th tap of the N taps, and the other end of the i-th delay section of the N-1 delay sections is The i+1th tap of the N taps is connected, i is greater than or equal to 1 and less than or equal to N-1.
  • the delay line circuit 13 is configured to delay the write indication signal by a predetermined delay corresponding to the i-th tap of the N taps, and then send the same to the address comparison logic circuit 15 through the synchronization logic circuit 14 when the write indication signal is detected.
  • the N taps are in one-to-one correspondence with the N preset delays;
  • the address comparison logic circuit 15 For acquiring the read address carried in the currently received read address signal when detecting that the write indication signal changes from the first logic level to the second logic level on the rising edge of the read clock signal, and based on the specified write address and acquisition
  • the read address determines the read/write address difference corresponding to the i-th tap, and sends the read/write address difference corresponding to the i-th tap to the processor 16;
  • each of the N-1 delay sections is used to delay the write indication signal input to the delay section.
  • N taps correspond to N preset delays one by one.
  • the processor 16 can set the tap currently used by the delay line circuit 13, that is, the processor 16 can set the preset delay currently used by the delay line circuit 13 to ensure the delay line circuit 13
  • the N taps may be traversed in sequence to sequentially delay the write indication signal by the N preset delays.
  • the above loop operation can be performed by the cooperation of the delay line circuit 13, the synchronization logic circuit 14, the address comparison logic circuit 15, and the processor 16, thereby ensuring that each of the N taps can be obtained.
  • the read/write address difference corresponding to the taps that is, the read/write address difference corresponding to each preset delay in the N preset delays can be obtained, thereby ensuring that the subsequent processor 16 reads and writes based on the N
  • the address difference determines the accuracy of the delay when the decimal is determined.
  • the synchronous logic circuit 14 includes a plurality of flip-flops P connected in series, and each of the plurality of flip-flops P connected in series is used to receive a write instructing signal on a rising edge of the read clock signal generated by the read clock generating circuit 9.
  • the first stage trigger of the plurality of flip-flops included in the synchronous logic circuit 14 receives the write indication signal on the rising edge of the read clock signal, and sends the write indication signal to the second-level flip-flop, and the second-level flip-flop is reading.
  • the rising edge of the clock signal receives the write indication signal and transmits the write indication signal to the third stage flip-flop, such that until the write indication signal is sent to the m-th stage flip-flop included in the synchronous logic circuit 14, the m-th stage
  • the flip-flop receives the write indication signal on the rising edge of the read clock signal, and sends the write indication signal to the address comparison logic circuit 15, m is a natural number, and m is greater than or equal to two.
  • the first to mth triggers of the plurality of triggers are according to the The serial sequence of the plurality of flip-flops is determined, that is, the trigger connected to the delay line circuit 13 can be determined as the first-stage flip-flop, and the trigger after the first-stage flip-flop is sequentially determined as the second-level trigger. , third-level trigger... the m-th level trigger.
  • the asynchronous FIFO circuit includes a write clock generation circuit, a read clock generation circuit, a write address generation circuit, a read address generation circuit, a random access memory, a delay line circuit, a synchronization logic circuit, an address comparison logic circuit, and a processor.
  • the read address generating circuit can send the generated multiple read address signals to the address comparison logic circuit
  • the write address generating circuit can send the generated write indication signal to the delay line circuit, because the delay line circuit includes N presets. Therefore, the delay line circuit can sequentially delay the write indication signal by N preset delays and then send the same to the address comparison logic circuit through the synchronization logic circuit, and the address comparison logic circuit can determine the same according to the write indication signal and the read address signal.
  • N preset read/write address differences corresponding to N preset delays and sending the N read/write address differences to the processor, after which the processor can determine based on the N read/write address differences and the wiring delay Fractional delay, and based on the fractional delay, determines the delay of the asynchronous FIFO circuit, thereby achieving accurate determination of the delay of the asynchronous FIFO circuit.
  • FIG. 7 is a flowchart of a method for determining a delay according to an embodiment of the present invention.
  • the method may be applied to the asynchronous FIFO circuit shown in any of the foregoing FIG. 2-6. It can be understood that the method can also be applied to Unlike the asynchronous FIFO circuit shown in any of FIGS. 2-6, when the asynchronous FIFO circuit shown in any of FIGS. 2-6 is changed to a portion or connection whose key portion of the method implementation is changed, the method is changed. It can still be applied to the changed circuit. For example, when the setting function and connection of the address comparison logic circuit are implemented by other modules such as a processor, the method should still be applicable. Referring to Figure 7, the method includes:
  • Step 701 in the process of performing a read operation and a write operation on the random access memory, the read address generating circuit sends the generated multiple read address signals to the address comparison logic circuit, and the write address generation circuit sends the generated write indication signal to the delay.
  • the write indication signal is generated based on at least two write addresses generated by the write address generation circuit, and the write indication signal is changed from the first logic level to the second logic power when the write address generation circuit generates the designated write address level.
  • the read address generating circuit in the process of performing a read operation on the random access memory, each time the read address generating circuit detects a rising edge of the read clock signal, a read address signal is generated, and the read address signal carries the read address, that is, The read address generating circuit can generate a read address signal every cycle of the read clock signal. Meanwhile, in the process of writing to the random access memory, the write address generating circuit can generate a write indication signal and a plurality of write address signals, each of the write address signals carrying a write address, and When the write address generation circuit detects that the generated write address is the designated write address, the write indication signal can be changed from the first logic level to the second logic level.
  • the specified write address may be set in advance, and the specified write address may be 7, 8, 9, etc., which is not specifically limited in this embodiment of the present invention.
  • the state of the first logic level is opposite to the state of the second logic level, such as when the first logic level is 0, the second logic level may be 1; when the first logic level is 1, when the first logic level is 1, The second logic level may be 0, which is not specifically limited in this embodiment of the present invention.
  • the write address generation circuit may further change the write indication signal from the second logic level to the first logic level when detecting that the generated write address is any write address other than the specified write address.
  • the embodiment of the invention is not specifically limited thereto.
  • the random access memory is used for storing data; the read address generating circuit is configured to generate a plurality of read address signals, each read address signal carries a read address; and the write address generating circuit is configured to generate a plurality of write address signals and write An indication signal, each write address signal carries a write address, the write indication signal is generated based on at least two write addresses generated by the write address generation circuit, and the write indication signal is first by the write address generation circuit to generate the specified write address
  • the logic level jumps to a second logic level; the address comparison logic circuit is configured to determine a read/write address difference based on the write indication signal and the read address signal, the read/write address difference being a write address currently writing to the random access memory The address difference from the read address at which the read operation is performed; the delay line circuit is used to delay the write indication signal of the input delay line circuit.
  • Step 702 The processor acquires N based on the read instruction signal, the plurality of read address signals, and the read clock signal generated by the read clock generation circuit by using the read address generation circuit, the delay line circuit, the synchronization logic circuit, and the address comparison logic circuit.
  • the read/write address difference, the N read/write address differences are in one-to-one correspondence with N preset delays in the delay line circuit, and the N is a natural number greater than 1.
  • the N preset delays may be preset, which is not specifically limited in this embodiment of the present invention.
  • the fractional delay is a delay introduced by a phase difference between the read clock signal and the write clock signal, and the fractional delay is less than one clock cycle, in order to ensure that the subsequent N presets can be based on The delay is determined by the decimal delay.
  • the minimum preset delay of the N preset delays may be 0, and the maximum preset delay of the N preset delays may be greater than or equal to one clock period.
  • the clock period is a period of the read clock signal or the write clock signal, and the read clock signal is equal to the period of the write clock signal.
  • the delay line circuit includes N-1 delay sections and N taps, and the N taps are in one-to-one correspondence with N preset delays
  • the processor passes the read address generation circuit, the delay line circuit, the synchronization logic circuit, and
  • the address comparison logic circuit based on the write indication signal, the plurality of read address signals, and the read clock signal generated by the read clock generation circuit, the operation of acquiring N read/write address differences may include the following steps (1)-(3):
  • i is greater than or Equal to 1 and less than or equal to N-1.
  • each of the N-1 delay sections is used to delay the write indication signal input to the delay section.
  • the operation of the delay line circuit delaying the write indication signal by the preset delay corresponding to the ith tap of the N taps and then sending the same to the address comparison logic circuit through the synchronization logic circuit may be: the delay line circuit passes through the N taps. The ith tap delays the write indication signal by a preset delay corresponding to the ith tap, and then sends the write instruction signal to the synchronization logic circuit; when the synchronization logic circuit receives the write indication signal, the write indication signal is delayed by the first value. It is sent to the address comparison logic circuit after the clock cycle.
  • the first value is a value obtained by subtracting 1 from the number of flip-flops included in the synchronous logic circuit.
  • the delay line circuit can delay the write indication signal by the ith tap of the N taps to delay the preset delay corresponding to the ith tap, and then send the signal to the synchronization logic circuit.
  • the synchronous logic circuit includes a plurality of flip-flops connected in series.
  • the operation of sending the write indication signal to the address comparison logic circuit after delaying the first numerical clock cycle may be: synchronization
  • the first stage of the plurality of flip-flops included in the logic circuit receives the write indication signal on a rising edge of the read clock signal, and sends the write indication signal to the second stage flip-flop, the second stage flip-flop is in the read clock signal
  • the rising edge receives the write indication signal and sends the write indication signal to the third stage flip-flop, such that until the write indication signal is sent to the m-th stage flip-flop included in the synchronous logic circuit, the m-th stage flip-flop is at the read clock
  • the rising edge of the signal receives the write indication signal and sends the write indication signal to the address comparison logic circuit, where m is a natural number and m is greater than or equal to two.
  • the first to mth triggers of the plurality of triggers are determined according to the serial order of the multiple triggers, that is, the delays of the multiple triggers may be delayed.
  • the trigger of the line circuit connection is determined as the first stage trigger, and the trigger after the first stage trigger is sequentially determined as the second level trigger, the third level trigger, the mth level trigger.
  • each of the plurality of flip-flops included in the synchronous logic circuit receives the write indication signal on the rising edge of the read clock signal and transmits the write indication signal to the next flip-flop, when the write indication signal is When the trigger is sent to the next trigger and is sent again by the next trigger, the write indication signal is delayed by one clock cycle, so the synchronization logic can delay the write indication signal by a first number of clock cycles.
  • the operation of the address comparison logic circuit to determine the read/write address difference corresponding to the i-th tap based on the specified write address and the acquired read address may be: the address comparison logic circuit determines the address difference between the specified write address and the acquired read address. The address comparison logic circuit decrements the number of flip-flops included in the synchronous logic circuit by one to obtain a first value; the address comparison logic circuit adds the determined address difference and the first value to obtain a read/write address corresponding to the i-th tap difference.
  • the write indication signal is changed from the first logic level to the second logic level when the write address generation circuit generates the designated write address, and the write indication signal is sent by the synchronization logic circuit after being delayed by the first number of clock cycles. Giving an address comparison logic circuit, therefore, when the address comparison logic circuit detects that the write indication signal transitions from the first logic level to the second logic level, the write address generation circuit generates the first one after generating the specified write address
  • the value is a write address, so the address difference between the write address currently writing to the random access memory and the specified write address is the first value.
  • the address comparison logic circuit is used to determine the address difference between the write address of the write operation of the random access memory and the read address of the read operation at the same time, and the read address signal currently received by the address comparison logic circuit is directly sent to The address comparison logic circuit does not perform a delay. Therefore, when the address comparison logic circuit determines the read/write address difference corresponding to the i-th tap based on the specified write address and the acquired read address, the specified write address and the acquisition need to be obtained. The address difference between the read addresses is added to the first value.
  • the address comparison logic determines that the address difference between the specified write address and the acquired read address is 6, and the number of flip-flops included in the synchronous logic circuit is three, and the number of flip-flops included in the synchronous logic circuit is three. Subtract 1 to get the first value of 2, and add the determined address difference 6 to the first value 2.
  • the read/write address difference corresponding to the i-th tap is 8.
  • the operation of the address comparison logic circuit determining the address difference between the specified write address and the acquired read address may be: when the specified write address is greater than the obtained read address, the specified write address is subtracted from the obtained read address. a second value, the second value is determined as an address difference between the specified write address and the acquired read address; when the specified write address is smaller than the acquired read address, the obtained read address is subtracted from the specified write address to obtain the first
  • the three values, the total number of addresses included in the random access memory is subtracted from the third value to obtain a fourth value, and the fourth value is determined as the address difference between the specified write address and the acquired read address; when the specified write address is specified
  • the read address is equal to the read address, if the write count of the specified write address is the same as the read count of the acquired read address, the address difference between the specified write address and the acquired read address is determined to be 0, if the specified write address is The number of writes is different from the read count of the acquired read address, and the total number of addresses included in the random access memory is
  • the address of the address and the number of writes of the address may be marked on each of the plurality of addresses included in the random access memory, where the number of writes is the number of times the address is written, and the number of reads is read.
  • the number of times of the data is not specifically limited in the embodiment of the present invention.
  • the specified write address is 8, and the acquired read address is 7. Since 8 is greater than 7, the specified write address 8 is subtracted from the acquired read address 7, and the second value is 1, and the second value is determined. The address difference between the specified write address and the acquired read address.
  • the designated write address is 2, and the acquired read address is 7. Since 2 is less than 7, the acquired read address is subtracted from the specified write address, and the third value is 5, and the random access memory includes the total address. If the number is 10, the total number of addresses included in the random access memory is 10 minus the third value 5, and the fourth value is 5, and the fourth value 5 is determined as the specified write address and the acquired read address. The address difference.
  • the designated write address is 7, and the acquired read address is 7. Since the specified write address is equal to the acquired read address, the number of writes of the specified write address and the read count of the read address can be determined, assuming the designation The number of writes of the write address is 2, and the number of reads of the read address obtained is 1, determining that the number of writes of the specified write address is different from the number of times of reading the read address, and the total number of addresses included in the random access memory is 10, Then, the total number of addresses included in the random access memory can be determined as the address difference between the specified write address and the acquired read address.
  • the address comparison logic circuit determines between the specified write address and the acquired read address.
  • the address difference reference may also be made to the related art, which is not described in detail in the embodiment of the present invention.
  • the step of the preset delay is sent to the address comparison logic circuit through the synchronous logic circuit.
  • the round-trip operation can ensure that the read/write address difference corresponding to each tap of the N taps is obtained, that is, each of the N preset delays can be guaranteed to be obtained.
  • the read/write address difference corresponding to the delay is set, thereby ensuring the accuracy of the delay when the subsequent processor determines the decimal based on the N read/write address differences.
  • Step 703 The processor determines the fractional delay based on the N read/write address differences and the wiring delay, and the wiring delay is a delay introduced by the wiring between the write address generating circuit and the synchronous logic circuit, and the fractional delay is read. The delay introduced by the phase difference between the clock signal and the write clock signal.
  • the processor is further configured to obtain a wiring between the write address generation circuit and the synchronous logic circuit from the stored backend wiring report before determining the fractional delay based on the N read/write address differences and the wiring delay.
  • the maximum delay and minimum delay are introduced, and the average of the maximum delay and the minimum delay is determined as the wiring delay, and the back-end wiring report is used to record the delay introduced by all the wirings included in the asynchronous FIFO circuit.
  • the maximum delay introduced by the processor between the write address generation circuit and the synchronous logic circuit obtained from the back-end routing report is 0.6 ns (nanoseconds) with a minimum delay of 0.2 ns
  • the processor can The average delay of 0.6 ns and the average delay of 0.2 ns with a minimum delay of 0.2 ns is determined as the wiring delay.
  • the embodiment of the present invention may constrain the write address generating circuit and the synchronous logic circuit when performing the wiring of the asynchronous FIFO circuit. Positions as close as possible to minimize variations in maximum delay and minimum delay introduced by the routing between the write address generation circuitry and the synchronous logic circuitry to determine routing delays based on the maximum delay and the minimum delay As small and stable as possible, to ensure that the processor determines the accuracy of the delay based on the routing delay.
  • the processor determines a decimal delay based on the N read/write address differences and the routing delay, and the processor may determine the first delay from the N preset delays based on the N read/write address differences. And determine the sum of the first delay and the wiring delay as a fractional delay.
  • the determining, by the processor, the first delay from the N preset delays may be: the processor is based on the N preset delays, and the N read and write addresses are based on the N read/write address differences. Sorting the difference to obtain the order of the N read-write address differences; the processor is based on the order of the N read-write address differences, Obtaining a first read/write address difference from the N read/write address differences, where the first read/write address difference is determined based on a read/write address difference of the jump in the N read/write address differences, and the read/write address of the jump The difference is a read/write address difference different from the previous one of the read/write address difference; the processor determines the preset delay corresponding to the first read/write address difference as the first delay.
  • the processor may read and write the N read/write according to the N preset delays.
  • the address difference is sorted.
  • the N read/write address differences may be sorted according to the order of the N preset delays, which is not specifically limited in this embodiment of the present invention.
  • the N preset delays are 5 ns, 1 ns, 2 ns, 4 ns, 3 ns
  • the N read and write address differences are 6, 7, 7, 6, and 7, wherein the read and write address difference corresponding to 5 ns is 6.
  • the read/write address difference corresponding to 1 ns is 7, 2 ns corresponding to the read/write address difference is 7, 4 ns corresponding to the read and write address difference is 6, 3 ns corresponding to the read and write address difference is 7, the processor can follow the N presets
  • the sequence of delays from small to large, the N read/write address differences are sorted, and the order of the N read/write address differences is 7, 7, 7, 6, and 6.
  • the N preset delays are 5 ns, 1 ns, 2 ns, 4 ns, 3 ns
  • the N read/write address differences are 6, 7, 7, 6, and 7, wherein the read and write address difference corresponding to 5 ns is 6.
  • the read/write address difference corresponding to 1 ns is 7, the read/write address difference corresponding to 7 and 2 ns is 7, the read/write address difference corresponding to 4 ns is 6, and the read/write address difference corresponding to 3 ns is 7, the processor can follow the N pre-
  • the N read/write address differences are sorted in descending order, and the order of the N read/write address differences is 6, 6, 7, 7, and 7.
  • the operation of obtaining the first read/write address difference from the N read/write address differences based on the sequence of the N read/write address differences may be: when the N read/write address differences are in the order according to the N When the preset delays are sorted from small to large, the processor obtains the read and write address difference of the first transition from the N read/write address differences, and determines the obtained read/write address difference as the first read/write address. Poor; when the order of N read/write address differences is obtained by sorting the N preset delays from large to small, the processor determines the read/write address difference of the last transition from the N read/write address differences. And determining the difference between the previous read/write address of the last read and write address difference as the first read/write address difference.
  • the order of the N read-write address differences is 7, 7, 7, 6, and 6, and the order of the N read-write address differences is obtained by sorting the N preset delays from small to large. Then, the processor can obtain the read/write address difference of the first jump from the N read/write address differences to be 6, and determine 6 as the first read/write address difference.
  • the order of the N read/write address differences is 6, 6, 7, 7, and 7, and the order of the N read/write address differences is ordered according to the order of the N preset delays.
  • the processor can determine the read and write address difference of the last transition from the N read/write address differences is 7, and the last transition The previous bit read/write address difference 6 of the read/write address difference is determined as the first read/write address difference.
  • the processor determines the first delay from the N preset delays based on the N read/write address differences, and determines the sum of the first delay and the wiring delay as the fractional delay.
  • FIG. 8 is a schematic diagram of delaying a write indication signal by a delay line circuit according to an embodiment of the present invention.
  • the fractional delay is a delay introduced by a phase difference between the write clock signal and the read clock signal;
  • the write address generation circuit generates a write indication signal, and the write indication signal is at the rising edge a of the write clock signal by the first
  • the logic level 0 jumps to the second logic level 1;
  • the N preset delays in the delay line circuit are the preset delay 1, the preset delay 2... the preset delay f-1, the preset time Delay f...Preset delay n, and preset delay 1 ⁇ preset delay 2 ⁇ ... ⁇ preset delay f-1 ⁇ preset delay f ⁇ ... ⁇ preset delay n.
  • the delay line circuit delays the write indication signal by a preset delay 1, a preset delay 2, a preset delay of f-1, and then sends it to the synchronous logic circuit
  • the rising edge of the read clock signal c is located at a second logic level 1 of the write indication signal.
  • the delay line circuit delays the write indication signal by a predetermined delay f and then sends it to the synchronous logic circuit
  • the rising edge c of the read clock signal is located at the first logic level 0 of the write indication signal and jumps to the second logic level 1 Change the jump point.
  • the wiring between the write address generation circuit and the synchronous logic circuit introduces a wiring delay, when the rising edge c of the read clock signal is at the first logic level 0 of the write indication signal, it jumps to the second logic level 1.
  • the write indication signal is delayed by the delay line circuit by the preset delay f, and the wiring between the write address generation circuit and the synchronous logic circuit is delayed by the wiring delay.
  • the jump point at which the first logic level 0 of the write indication signal jumps to the second logic level 1 is at the rise of the write clock signal.
  • the write indication signal is delayed by the preset delay f and the wiring delay
  • the jump point of the first logic level 0 of the write indication signal to the second logic level 1 is at the rise of the read clock signal Along c. Since the fractional delay is introduced by the phase difference between the write clock signal and the read clock signal, that is, the fractional delay is between the rising edge a of the write clock signal and the rising edge c of the read clock signal in FIG. Therefore, the sum of the preset delay f and the wiring delay can be determined as the fractional delay.
  • the delay line circuit delays the write indication signal by the preset delay 1, the preset delay 2, the preset delay f-1, and then sends it to the synchronous logic circuit, the rising edge c of the read clock signal is in the write indication signal.
  • the second logic level is 1, and since the synchronous logic circuit only receives the write indication signal at the rising edge of the read clock signal, as shown in FIG. 9(a), when the delay line circuit delays the write indication signal by a preset Delay 1, preset delay 2...
  • the preset delay f-1 is sent to the synchronous logic circuit, the synchronous logic circuit can It is detected at the rising edge c of the read clock signal that the write indication signal transitions from the first logic level 0 to the second logic level 1.
  • the address comparison logic circuit can detect that the write indication signal is first by the rising edge e of the read clock signal.
  • the logic level 0 transitions to the second logic level 1
  • the read address obtained by the address compare logic circuit is the read address received at the rising edge e of the read clock signal.
  • the preset delay is 1.
  • Preset delay 2 is equal.
  • the preset time is Delay 1
  • preset delay 2 is E.
  • the delay line circuit delays the write indication signal by a predetermined delay f and then sends it to the synchronous logic circuit, the rising edge c of the read clock signal is just at the first logic level 0 of the write indication signal and jumps to the second logic level 1 The trip point, the rising edge d after the rising edge c of the read clock signal is at the second logic level 1 of the write indication signal, and since the synchronous logic circuit receives the write indication signal only on the rising edge of the read clock signal, As shown in FIG. 9(b), when the delay line circuit delays the write indication signal by a predetermined delay f and sends it to the synchronous logic circuit, the synchronous logic circuit can detect that the write indication signal is first by the rising edge d of the read clock signal.
  • the logic level 0 transitions to the second logic level 1.
  • the synchronous logic circuit includes three flip-flops, that is, the synchronous logic circuit can delay the write indication signal by two clock cycles, then the address comparison logic circuit can detect the write on the rising edge f after the rising edge e of the read clock signal.
  • the indication signal transitions from a first logic level 0 to a second logic level 1, and the read address acquired by the address comparison logic is the read address received at the rising edge f of the read clock signal.
  • the read/write address difference corresponding to the preset delay f It will change to the preset delay 1, the preset delay 2, the address difference obtained by subtracting 1 from the address difference corresponding to any preset delay in the preset delay f-1, for example, as shown in Table 1 below.
  • the read/write address difference corresponding to the preset delay f jumps to E-1.
  • the preset delay f is the first one of the N read/write address differences.
  • the preset delay corresponding to the read/write address difference, that is, the preset delay f is the first delay.
  • the previous one of the N read/write address differences is the read/write address difference of the previous one.
  • the bit read/write address difference is the same as the read/write address difference of the first transition described above. Therefore, when the order of the N read/write address differences is obtained by sorting the N preset delays from large to small, the preset delay f is the last one of the N read/write address differences.
  • the preset delay corresponding to the previous read/write address difference of the read/write address difference, that is, the preset delay f is the first delay.
  • the processor determines the delay of the decimal based on the N read/write address differences and the routing delay, and may determine the first delay from the N preset delays based on the N read/write address differences, and The sum of the first delay and the wiring delay is determined as a fractional delay.
  • the processor may further determine the second delay based on the first delay, and the second delay is to cancel the synchronous logic circuit.
  • the metastable delay the processor resets the read address generated by the read address generation circuit by the address comparison logic circuit based on the first delay and the second delay.
  • the determining, by the processor, the second delay may be: when the first delay is less than or equal to the signal stabilization time, determining a sum of the first delay and the first preset delay as the first The second preset delay is greater than the signal stabilization time and less than the third delay.
  • the signal stabilization time is the sum of the setup time and the hold time of the first-stage flip-flop.
  • the first-stage flip-flop is included in the synchronous logic circuit.
  • the third delay is the difference between the clock period and the signal stabilization time, the signal stabilization time is less than the third delay; or, when the first delay is greater than the signal stability The time is less than the third time delay, the second time delay is subtracted from the first time delay to obtain a second time delay, and the second preset time delay is greater than the signal stabilization time and less than or equal to the decimal time delay; or, when The first delay is greater than or equal to the third time delay, and the first time delay is subtracted from the first time delay to obtain a second time delay.
  • first preset delay and the second preset delay may be preset, and the first preset delay may be any delay within a range greater than the signal stabilization time and less than the third delay.
  • the second preset delay may be any one of a range greater than a signal stabilization time and less than or equal to a fractional delay.
  • the time delay is not specifically limited in the embodiment of the present invention.
  • the setup time and the hold time of the first-level trigger may be obtained from the back-end routing report, and the sum of the setup time and the hold time is determined as the signal stabilization time.
  • the signal stabilization time can also be obtained in other manners, which is not specifically limited in this embodiment of the present invention.
  • the write indication signal should be stable for a first specified time before the rising edge of the read clock signal arrives, and is stable for a second specified time after the rising edge of the read clock signal arrives, otherwise the first stage The write indication signal received by the flip-flop is unstable, resulting in a metastable state of the synchronous logic circuit.
  • first specified time may be greater than or equal to the setup time of the first-level trigger
  • second specified time may be greater than or equal to the hold time of the first-level trigger.
  • the second delay may be determined based on the first delay, and the delay line circuit may delay the write indication signal by a second delay and then send the signal to the synchronous logic circuit to ensure The rising edge of the read clock signal is at a stable point of the write indication signal, thereby ensuring that the synchronous logic circuit can receive a stable write indication signal on the rising edge of the read clock signal.
  • the signal stabilization time is t.
  • the first delay is less than or equal to the signal stabilization time
  • the sum of the first delay and the first preset delay may be determined as the second delay.
  • the delay line circuit delays the write indication signal by the second delay and then sends it to the synchronous logic circuit
  • the rising edge c of the read clock signal is located exactly in the stable region A of the write indication signal, thereby ensuring that the synchronous logic circuit is reading the clock signal.
  • the rising edge can receive a stable write indication signal, avoiding the occurrence of metastability.
  • the signal stabilization time is t.
  • the first delay may be subtracted from the first delay to obtain the second delay.
  • Delay at this time, when the delay line circuit delays the write indication signal by the second delay and then sends it to the synchronous logic circuit, the rising edge c of the read clock signal is located exactly in the stable region B of the write indication signal, thereby ensuring that the synchronous logic circuit is reading.
  • the rising edge of the clock signal can receive a stable write indication signal, avoiding the occurrence of metastability.
  • the signal stabilization time is t, and when the first delay is greater than or equal to the third time delay, The first delay may be subtracted from the first delay to obtain a second delay.
  • the delay line circuit delays the write indication signal by the second delay and then sends the rising edge of the read clock signal to the synchronous logic circuit.
  • c is located just in the stable region B of the write indication signal, thereby ensuring that the synchronous logic circuit can receive a stable write indication signal on the rising edge of the read clock signal, avoiding the occurrence of metastability.
  • the processor may reset the read address generated by the read address generating circuit by using the address comparison logic circuit based on the first delay and the second delay, and may include the following two methods:
  • the first mode the processor sends the first delay to the address comparison logic circuit, and sets the delay of the delay line circuit to the second delay; when the delay line circuit detects the write indication signal, the write indication signal Sending to the address comparison logic circuit through the synchronization logic circuit; when the address comparison logic circuit detects that the write indication signal changes from the first logic level to the second logic level on the rising edge of the read clock signal, acquiring the currently received read address
  • the read address carried in the signal determines the second read/write address difference based on the specified write address and the acquired read address, and the second read/write address difference is the read/write address difference corresponding to the second delay; when the address comparison logic circuit receives The first time delay, based on the specified write address, the first delay, the second read/write address difference, and the specified read/write address difference, resets the read address currently generated by the read address generation circuit.
  • the specified read/write address difference may be preset, for example, the specified read/write address difference may be 7, 8 or the like, which is not specifically limited in this embodiment of the present invention.
  • the delay of the asynchronous FIFO circuit includes integer delay and fractional delay
  • the fractional delay is the delay introduced by the phase difference between the read clock signal and the write clock signal
  • the fractional delay of the same asynchronous FIFO circuit is stable.
  • it is necessary to ensure that the address difference between the write address of the write operation of the random access memory and the read address of the read operation at the same time is the specified read/write address difference, thereby ensuring the same asynchronous FIFO circuit.
  • the integer delay is fixed. However, due to some unmeasured factors, the read address generated by the read address generation circuit may be incorrect.
  • the address difference between the write address of the random access memory and the read address of the read operation at the same time is not specified, resulting in an error in the asynchronous FIFO circuit determined based on the specified read/write address difference at this time. Therefore, during the operation of the asynchronous FIFO circuit, the address difference between the write address currently performing the write operation to the random access memory and the read address of the read operation can be determined in real time, and when the address difference is detected, the read/write is not specified.
  • the read address generated by the read address generating circuit is reset by the address comparison logic circuit to ensure that the address difference between the write address for the write operation of the random access memory and the read address for the read operation at the same time is specified.
  • the read/write address difference is read to ensure the accuracy of the delay of the asynchronous FIFO circuit determined based on the specified read/write address difference.
  • the read address signal sent by the address generating circuit determines the read/write address difference between the write address currently performing the write operation to the random access memory and the read address of the read operation, and when the read/write address difference is not equal to the specified read/write address difference
  • the read address generated by the read address generation circuit is reset.
  • the write indication signal received by the synchronous logic circuit may be inaccurate, thereby affecting the accuracy of the read/write address difference determined by the address comparison logic circuit, thereby causing the address comparison logic circuit to read the address generation circuit.
  • the resulting read address was reset incorrectly.
  • the processor can set the delay of the delay line circuit to the second delay, and the synchronous logic circuit can receive the stable write indication signal, thereby The accuracy of the read/write address difference determined by the address comparison logic circuit can be ensured, thereby ensuring that the address comparison logic circuit can correctly reset the read address generated by the read address generation circuit.
  • the purpose of resetting the read address generated by the address comparison logic circuit to the read address generation circuit is to make the address difference between the write address currently performing the write operation to the random access memory and the read address of the read operation a designated read/write address. difference. Therefore, after the processor sets the delay line circuit to the second delay, when the delay line circuit detects the write indication signal, the write indication signal can be sent to the address comparison logic circuit through the synchronization logic circuit, so that the address comparison logic circuit
  • the read address may be generated based on the specified write address, the first delay, the second read/write address difference, and the specified read/write address difference when detecting that the write indication signal changes from the first logic level to the second logic level.
  • the read address currently generated by the circuit is reset.
  • the N preset delays do not include the second time delay
  • the N read/write address differences do not include the read/write address difference corresponding to the second delay, so The read/write address difference corresponding to the two delays is determined; and when the N preset delays include the second time delay, in order to ensure the accuracy of the determined second read/write address difference, the second delay may also be used.
  • the corresponding read/write address difference is determined again. Therefore, regardless of whether the second preset delay includes the second delay, after the processor sets the delay of the delay line circuit to the second delay, the address comparison logic circuit can pass the delay line circuit and the synchronous logic circuit. And the read address generating circuit determines the read/write address difference corresponding to the second delay, that is, determines the second read/write address difference.
  • the address comparison logic detects that the write indication signal changes from the first logic level to the second logic level on the rising edge of the read clock signal, the read address carried in the currently received read address signal is acquired, based on the designation.
  • the operation of determining the second read/write address difference is similar to the operation of the step (2) in the above step 702, and the details are not described herein again.
  • the N read/write address differences include a read/write address difference corresponding to the second delay
  • the processor can The read/write address difference corresponding to the second delay is directly obtained from the N read/write address differences, and the read/write address difference corresponding to the second delay is sent to the address comparison logic circuit, and the address comparison logic circuit does not need to pass the delay line.
  • the circuit, the synchronous logic circuit and the read address generating circuit determine the read/write address difference corresponding to the second delay again, thereby saving processing resources in the asynchronous FIFO circuit.
  • the address comparison logic circuit In the first mode and the second mode, the address comparison logic circuit generates the current read address generation circuit based on the specified write address, the first time delay, the second read/write address difference, and the specified read/write address difference.
  • the operation of reading the address for resetting may include one of the following modes (1) and (2):
  • the address comparison logic circuit includes the specified write address and the synchronization logic circuit.
  • the number of flip-flops determines the first address and sets the read address currently generated by the read address generation circuit to the first address.
  • the delay line circuit delays the write indication signal by a second delay and then sends the rising edge c of the read clock signal to the synchronous logic circuit.
  • the stable region A of the first logic level 0 of the write indication signal, the rising edge d after the rising edge c of the read clock signal is located at the stable region B of the second logic level 1 of the write indication signal. Since the synchronous logic circuit receives the write indication signal only on the rising edge of the read clock signal, the synchronous logic circuit can detect that the write indication signal changes from the first logic power 0 to the second logic level on the rising edge d of the read clock signal. 1. As shown in FIG.
  • the address comparison logic circuit can detect the write indication signal from the first logic level at the rising edge f after the rising edge e of the read clock signal.
  • the 0 hop changes to the second logic level 1, and the read address acquired by the address comparison logic circuit at this time is the read address received at the rising edge f of the read clock signal.
  • the read/write address difference determined by the address comparison logic circuit based on the read address received at the rising edge e of the read clock signal should be the specified read/write address difference, since the read address generation circuit is at the read clock.
  • the address difference between the read address generated by the rising edge f of the signal and the read address generated at the rising edge e of the read clock signal is 1, therefore, the delay comparison circuit delays the write indication signal by a second time delay, the address comparison logic circuit
  • the second read/write address difference determined based on the read address received at the rising edge f of the read clock signal is one less than the specified read/write address difference.
  • the address comparison logic circuit can determine the first address based on the specified write address and the number of flip-flops included in the synchronous logic circuit, and set the read address currently generated by the read address generating circuit to the first address.
  • the address comparison logic circuit determines, according to the specified write address and the number of flip-flops included in the synchronous logic circuit, the operation of determining the first address may be: the address comparison logic circuit is based on the specified write address and the number of triggers included in the synchronous logic circuit. Determining a write address currently performing a write operation to the random access memory, determining a first address based on the write address and the specified read/write address difference, and the address difference between the write address and the first address is a specified read/write address difference.
  • the address comparison logic circuit determines, according to the specified write address and the number of flip-flops included in the synchronous logic circuit, the operation of the write address of the current random access memory write operation may be: the address comparison logic circuit triggers the synchronization logic circuit The number of the device is decreased by 1 to obtain a first value, and the first value is incremented by 1 to obtain a fifth value. Based on the specified write address and the fifth value, the address difference between the address and the specified write address is determined to be the fifth value. The determined address is determined as the write address currently being written to the random access memory.
  • the write indication signal generated by the write address generation circuit is changed from the first logic level 0 to the first edge of the write clock signal.
  • the delay line circuit delays the write indication signal by a second delay, and the synchronous logic circuit detects that the write indication signal changes from the first logic level 0 to the second logic power on the rising edge d of the read clock signal.
  • Flat 1 Since the rising edge d of the read clock signal is after the rising edge b of the write clock signal, the rising edge b of the write clock is after the rising edge a of the write clock, therefore, the jump from the write indication signal on the rising edge a of the write clock signal occurs.
  • the write address generation circuit can generate a write address on the rising edge b of the write clock signal during the period in which the synchronous logic circuit detects the transition of the write indication signal at the rising edge d of the read clock signal. And in the process of the synchronous logic circuit sending the write indication signal to the address comparison logic circuit, due to the synchronization logic The circuit delays the write indication signal by a first number of clock cycles, so the write address generation circuit generates a first value of the write address during the process. That is, when the address comparison logic detects that the write indication signal transitions from the first logic level 0 to the second logic level 1, the write address generation circuit generates the first value plus one after generating the specified write address. The address is written, and the fifth value is determined by adding the first value to the first value. Therefore, the address difference between the write address currently writing to the random access memory and the specified write address is the fifth value, so The address whose address difference from the specified write address is the fifth value is determined as the write address currently writing to the random access memory.
  • the specified read/write address difference is 8
  • the specified write address is 9, and the number of flip-flops included in the synchronous logic circuit is 3, the number of flip-flops included in the synchronous logic circuit is decreased by 1 to obtain the first value of 2
  • the first value is incremented by one to obtain a fifth value of 3
  • the write address currently writing to the random access memory is the write address 12 whose address difference from the specified write address 9 is the fifth value 3. Since the specified read/write address difference is 8, the first address can be determined to be 4 based on the write address 12 and the specified read/write address difference 8, and then the address comparison logic circuit can set the read address currently generated by the read address generation circuit. Is the first address 4.
  • the address comparison logic circuit determines the number of the triggers included in the synchronous logic circuit based on the specified write address The second address sets the read address currently generated by the read address generation circuit to the second address.
  • the delay line circuit delays the write indication signal by a second delay and then sends the signal to the synchronous logic circuit.
  • the rising edge c is located in the stable region B of the second logic level 1 of the write indication signal. Since the synchronous logic circuit receives the write indication signal only on the rising edge of the read clock signal, the synchronous logic circuit can detect that the write indication signal changes from the first logic power 0 to the second logic level on the rising edge c of the read clock signal. 1. As shown in FIG.
  • the address comparison logic circuit can detect that the write indication signal is changed from the first logic level 0 to the first on the rising edge e of the read clock signal.
  • the second logic level 1 the read address obtained by the address comparison logic circuit is the read address received at the rising edge e of the read clock signal.
  • the address comparison logic circuit is based on the rise of the read clock signal when the address difference between the write address currently writing to the random access memory and the read address performing the read operation is the specified read/write address difference.
  • the read/write address difference determined by the read address received along e should be the specified read/write address difference. Therefore, when the first delay is greater than the signal stabilization time and the second read/write address difference is not equal to the specified read/write address difference, it can be determined.
  • the address difference between the current write address to the random access memory write address and the read address to which the read operation is performed is not the specified read/write address difference.
  • the address comparison logic circuit can determine the second address based on the specified write address and the number of flip-flops included in the synchronous logic circuit, and set the read address currently generated by the read address generating circuit to the second address.
  • the address comparison logic circuit determines that the operation of the second address is based on the specified write address and the number of flip-flops included in the synchronous logic circuit, and the address comparison logic circuit is based on the specified write address and the number of triggers included in the synchronous logic circuit. Determining a write address currently performing a write operation to the random access memory, determining a second address based on the write address and the specified read/write address difference, and the address difference between the write address and the second address is a specified read/write address difference.
  • the address comparison logic circuit determines, according to the specified write address and the number of flip-flops included in the synchronous logic circuit, the operation of the write address of the current random access memory write operation may be: the address comparison logic circuit triggers the synchronization logic circuit The number of the device is decremented by 1, and the first value is obtained. Based on the specified write address, the address difference between the address and the specified write address is determined to be the address of the first value, and the determined address is determined as the current write operation to the random access memory. address.
  • the write indication signal generated by the write address generation circuit is changed from the first logic level 0 to the second logic on the rising edge a of the write clock signal.
  • Level 1 after the delay line circuit delays the write indication signal by a second delay, the synchronous logic circuit detects that the write indication signal changes from the first logic level 0 to the second logic level 1 at the rising edge c of the read clock signal. . Since the rising edge c of the read clock signal is after the rising edge a of the write clock signal, the jump from the write indication signal on the rising edge a of the write clock signal to the synchronous logic circuit detects the write on the rising edge c of the read clock signal.
  • the write address generation circuit does not generate a write address during the period of the transition of the indication signal.
  • the write address generation circuit since the synchronous logic circuit delays the write indication signal by the first number of clock cycles, the write address generation circuit generates the first one in the process.
  • the value is a write address. That is, when the address comparison logic detects that the write indication signal transitions from the first logic level 0 to the second logic level 1, the write address generation circuit generates the first value write after generating the specified write address.
  • the address difference between the write address currently writing to the random access memory and the specified write address is the first value, and therefore, the address with the address difference between the specified write address and the specified write address can be determined as The current write address for a write to the random access memory.
  • the specified read/write address difference is 8
  • the write address is specified to be 9
  • the number of flip-flops included in the synchronous logic circuit is 3, and the number of flip-flops included in the synchronous logic circuit is decreased by one to obtain a first value of 2.
  • the write address currently writing to the random access memory is the write address 11 whose address difference from the specified write address 9 is the first value 2, and since the specified read/write address difference is 8, the write address 11 can be based on the write address 11 And specifying the read/write address difference of 8, determining that the second address is 3, after which the address comparison logic circuit can set the read address currently generated by the read address generation circuit to the second address 3.
  • Step 704 The processor determines the delay of the asynchronous FIFO circuit based on the fractional delay.
  • the processor obtains an integer delay and determines the sum of the fractional delay and the integer delay as the delay of the asynchronous FIFO circuit, and the integer delay is the write address and the read operation of the write operation to the random access memory at the same time.
  • the processor can obtain the integer delay when the integer is obtained, and the processor can also obtain the integer delay by using the method. This is not specifically limited.
  • the processor can multiply the specified read/write address difference 8 by the clock period by 10 ns to obtain an integer delay of 80 ns.
  • the write address power-on reset value is set to a third address
  • the read address power-on reset value is set to a fourth address
  • the address difference between the third address and the fourth address is Specify the read/write address difference.
  • the write address power-on reset value is the initial write address generated by the write address generation circuit at power-on.
  • the read address power-on reset value is the initial read address generated by the read address generation circuit at power-on.
  • the reset setting command is used to set the write address power-on reset value and the read address power-on reset value.
  • the write address power-on reset value is set to the third address
  • the read address power-on reset value is set to the fourth address
  • the address difference between the third address and the fourth address is designated to read and write.
  • the address difference can ensure that the asynchronous FIFO circuit starts to work at the beginning of power-on, the address difference between the write address of the write operation to the random access memory and the read address of the read operation is the specified read/write address difference, thereby ensuring the asynchronous FIFO.
  • the delay of the circuit is the same throughout the working process, ensuring the accuracy of the delay of the determined asynchronous FIFO circuit.
  • the asynchronous FIFO circuit with the determined delay is applied to a digital signal transceiver of a base station in a wireless communication system, for example, can be applied to a MIMO (Multi-Input Multi-Output) or a massive MIMO multi-antenna of a base station.
  • MIMO Multi-Input Multi-Output
  • massive MIMO multi-antenna of a base station.
  • the asynchronous FIFO circuit that determines the delay can also be applied to the synchronous transmission network. For example, it can be applied to an Ethernet using the IEEE-1588 protocol to ensure accurate transmission of the timestamp in the IEEE-1588 protocol. Improve clock synchronization accuracy between network nodes.
  • the read address generating circuit sends the generated multiple read address signals to the address comparison logic circuit, and the write address generation circuit generates a write instruction.
  • the signal is sent to the delay line circuit, and the processor reads the address generation circuit, the delay line circuit, the synchronization logic circuit and the address comparison logic circuit, based on the write indication signal, the plurality of read address signals, and the read clock signal generated by the read clock generation circuit Obtaining N read/write address differences corresponding to N preset delays in the delay line circuit, and then determining, by the processor, the fractional delay based on the N read/write address differences and the wiring delay, and based on the The fractional delay determines the delay of the asynchronous FIFO circuit, thereby achieving an accurate determination of the delay of the asynchronous FIFO circuit.
  • the processor may further determine the second delay based on the first delay, and perform reading on the read address generating circuit by the address comparison logic circuit based on the first delay and the second delay.
  • the address is reset, and since the second delay can eliminate the metastability of the synchronous logic circuit, it can be ensured that the address comparison logic circuit correctly resets the read address generated by the read address generating circuit.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

本发明实施例提供了一种异步FIFO电路及时延确定方法，涉及无线通信领域领域。所述异步FIFO电路包括：写时钟产生电路、读时钟产生电路、写地址产生电路、读地址产生电路、随机访问存储器、延迟线电路、同步逻辑电路、地址比较逻辑电路和处理器；写地址产生电路的第二输出端与延迟线电路的第一输入端连接，延迟线电路的第二输入端与处理器的第一输出端连接，延迟线电路的输出端与同步逻辑电路的第一输入端连接，同步逻辑电路的输出端与地址比较逻辑电路的第一输入端连接，读地址产生电路的输出端与地址比较逻辑电路的第三输入端连接，地址比较逻辑电路的第一输出端与处理器的输入端连接。本发明可以实现对异步FIFO电路的时延的准确确定。

Description

一种异步FIFO电路及时延确定方法 技术领域
本发明实施例涉及无线通信领域，特别涉及一种异步FIFO(First Input First Output，先入先出队列)电路及时延确定方法。
背景技术
在无线通信系统中，往往会包括多个通信设备，该多个通信设备的时钟域基本都是独立的，并且同一通信设备包括的多个模块的时钟域基本也是独立的，因此，在该多个通信设备中任意两个通信设备之间的数据传输或者在多个模块中任意两个模块之间的数据传输基本都是不同时钟域之间的数据传输。例如，任意两个通信设备的通用公共无线接口(Common Public Radio Interface，CPRI)之间的数据传输是不同时钟域的数据传输，同一通信设备中射频拉远单元(Remote Radio Unit，RRU)内数字射频前端(Digital Front End，DFE)上各个模块之间的数据传输也是不同时钟域的数据传输。为了保证数据在不同时钟域之间传输的完整性，往往使用通信设备的异步FIFO电路来进行数据传输。另外，在无线通信系统中许多业务的正常运行都要求精确的定时同步，而异步FIFO电路往往存在一定的时延，该异步FIFO电路时延的引入使得通信设备不能准确确定数据的收发时间，对通信设备的定时同步精度造成影响，因此，通过异步FIFO电路进行数据传输时，为了提高通信设备的定时同步精度，需要确定该异步FIFO电路的时延。
目前，提供了一种异步FIFO电路，如图1所示，该异步FIFO电路包括：写时钟产生电路1、读时钟产生电路2、写地址产生电路3、读地址产生电路4、随机访问存储器5、同步逻辑电路6和地址比较逻辑电路7。参见图1，写时钟产生电路1的输出端1a与写地址产生电路3的输入端3a连接，写地址产生电路3的第一输出端3b与随机访问存储器5的第一输入端5a连接，写地址产生电路3的第二输出端3c与同步逻辑电路6的第一输入端6a连接，同步逻辑电路6的输出端6b与地址比较逻辑电路7的第一输入端7a连接，同步逻辑电路6的第二输入端6c和地址比较逻辑电路7的第二输入端7b分别与读时钟产生电路2的输出端2a连接；读时钟产生电路2的输出端2a还与读地址产生电路 4的输入端4a连接，读地址产生电路4的输出端4b分别与随机访问存储器5的第二输入端5b和地址比较逻辑电路7的第三输入端7c连接，地址比较逻辑电路7的输出端7d与读地址产生电路4的置位端4c连接。
其中，以无线通信处理系统中任意两个不同时钟域的通信设备之间的数据传输为例，假如第一通信设备需要将待传输的目标数据传输给第二通信设备，此时，第一通信设备可以对自身包括的FIFO电路中的随机访问存储器进行写操作和读操作。当第一通信设备对随机访问存储器进行写操作时，写地址产生电路可以在写时钟产生电路产生的写时钟信号的上升沿产生写地址信号，该写地址信号中携带写地址，第一通信设备可以将目标数据写入随机访问存储器中该写地址所对应的位置上。同时，当第一通信设备对随机访问存储器进行读操作时，读地址产生电路可以在读时钟产生电路产生的读时钟信号的上升沿产生读地址信号，该读地址信号中携带读地址，第一通信设备可以从随机访问存储器中读取该读地址所对应位置上存储的数据，并将读取的数据传输给第二通信设备。其中，在第一通信设备和第二通信设备传输数据的过程中，第一通信设备还可以将指定读写地址差与时钟周期的乘积确定为该异步FIFO电路的时延，指定读写地址差为预先设置的写地址与读地址之间的地址差，时钟周期为读时钟信号或者写时钟信号的周期，且读时钟信号与写时钟信号的周期相等。
在实现本发明的过程中，发明人发现现有技术至少存在以下问题：
异步FIFO电路的真实时延包括小数时延和整数时延两部分，小数时延由读时钟信号与写时钟信号之间的相位差所引入，整数时延由同一时刻对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差所引入。现有技术中未对小数时延进行确定，只确定了整数时延，且将该整数时延直接确定为异步FIFO电路的时延，造成异步FIFO电路时延确定结果不准确。
发明内容
为了解决相关技术的问题，本发明提供了一种异步FIFO电路及时延确定方法。所述技术方案如下：
第一方面，提供了一种FIFO电路，所述异步FIFO电路包括：写时钟产生电路、读时钟产生电路、写地址产生电路、读地址产生电路、随机访问存储器、延迟线电路、同步逻辑电路、地址比较逻辑电路和处理器；
所述写时钟产生电路的输出端与所述写地址产生电路的输入端连接，所述 写地址产生电路的第一输出端与所述随机访问存储器的第一输入端连接，所述写地址产生电路的第二输出端与所述延迟线电路的第一输入端连接，所述延迟线电路的第二输入端与所述处理器的第一输出端连接，所述延迟线电路的输出端与所述同步逻辑电路的第一输入端连接，所述同步逻辑电路的输出端与所述地址比较逻辑电路的第一输入端连接，所述同步逻辑电路的第二输入端和所述地址比较逻辑电路的第二输入端分别与所述读时钟产生电路的输出端连接；
所述读时钟产生电路的输出端还与所述读地址产生电路的输入端连接，所述读地址产生电路的输出端与所述随机访问存储器的第二输入端连接，所述读地址产生电路的输出端还与所述地址比较逻辑电路的第三输入端连接，所述地址比较逻辑电路的第一输出端与所述处理器的输入端连接。
其中，写时钟产生电路用于产生写时钟信号；读时钟产生电路用于产生读时钟信号；写地址产生电路用于产生多个写地址信号和写指示信号，每个写地址信号中携带写地址，该写指示信号是基于写地址产生电路产生的至少两个写地址产生，且该写指示信号在写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平，其中，写地址产生电路可以通过自身的第一输出端将产生的多个写地址信号发送给随机访问存储器，且可以通过自身的第二输出端将产生的写指示信号发送给延迟线电路；读地址产生电路用于产生多个读地址信号，每个读地址信号中携带读地址，其中，读地址产生电路可以通过自身的输出端将产生的多个读地址信号发送给随机访问存储器和地址比较逻辑电路；随机访问存储器用于存储数据；延迟线电路用于对输入该延迟线电路的写指示信号进行延迟，并将延迟后的写指示信号发送给同步逻辑电路；同步逻辑电路用于在读时钟产生电路产生的读时钟信号的上升沿接收写指示信号，并将所接收的写指示信号发送给地址比较逻辑电路；地址比较逻辑电路用于基于写指示信号和读地址信号，确定读写地址差，该读写地址差为当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差；处理器用于基于地址比较逻辑电路确定的读写地址差，确定小数时延，并基于该小数时延，确定异步FIFO电路的时延，其中，小数时延为读时钟信号与写时钟信号之间的相位差所引入的时延。
需要说明的是，写时钟产生电路、读时钟产生电路、写地址产生电路、读地址产生电路、随机访问存储器、延迟线电路和同步逻辑电路在实际应用中可以以硬件形式实现，地址比较逻辑电路和处理器在实际应用中可以以软件形式 实现，本发明实施例对此不做具体限定。
在本发明实施例中，异步FIFO电路包括写时钟产生电路、读时钟产生电路、写地址产生电路、读地址产生电路、随机访问存储器、延迟线电路、同步逻辑电路、地址比较逻辑电路和处理器。其中，读地址产生电路可以将产生的多个读地址信号发送给地址比较逻辑电路，写地址产生电路可以将产生的写指示信号发送给延迟线电路，该延迟线电路可以将写指示信号延迟后通过同步逻辑电路发送给地址比较逻辑电路，地址比较逻辑电路可以基于写指示信号和读地址信号，确定读写地址差，由于处理器可以基于地址比较逻辑电路确定的读写地址差，确定小数时延，并基于该小数时延，确定异步FIFO电路的时延，因此，可以实现对异步FIFO电路的时延的准确确定。
结合第一方面，在上述第一方面的第一种可能的实现方式中，所述地址比较逻辑电路的第二输出端与所述读地址产生电路的置位端连接。
其中，地址比较逻辑电路用于在检测到写指示信号由第一逻辑电平跳变到第二逻辑电平时，对读地址产生电路当前产生的读地址进行重置。
在本发明实施例中，地址比较逻辑电路可以对读地址当前产生的读地址进行重置，从而保证同一时刻对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差为某一固定的读写地址差，保证异步FIFO电路的整数时延固定。
结合第一方面或第一方面的第一种可能的实现方式，在上述第一方面的第二种可能的实现方式中，所述处理器的第二输出端与所述写地址产生电路的复位端连接，所述处理器的第三输出端与所述读地址产生电路的复位端连接。
其中，处理器用于在接收到复位设置指令时，将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，第三地址与第四地址的地址差为指定读写地址差，写地址上电复位值为上电时写地址产生电路产生的初始写地址，读地址上电复位值为上电时读地址产生电路产生的初始读地址。
需要说明的是，复位设置指令用于对写地址上电复位值和读地址上电复位值进行设置。
在本发明实施例中，可以将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，且第三地址与第四地址的地址差为指定读写地址差，从而保证异步FIFO电路在上电刚开始工作时，对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差为指定读写地址差，从而保 证该异步FIFO电路在整个工作过程中的时延均相同。
结合第一方面至第一方面的第二种可能的实现方式中任一可能的实现方式，在上述第一方面的第三种可能的实现方式中，所述延迟线电路包括：N-1个延迟节和N个抽头，所述N为大于1的自然数；
所述N-1个延迟节串联连接，所述N-1个延迟节中第i个延迟节的一端与所述N个抽头中第i个抽头连接，所述N-1个延迟节中第i个延迟节的另一端与所述N个抽头中第i+1个抽头连接，所述i大于或等于1且小于或等于N-1。
需要说明的是，N-1个延迟节中的每个延迟节用于对输入该延迟节的写指示信号进行延迟。
另外，由于N个抽头中各个抽头与写地址产生电路之间的延迟节的个数是固定的，且每个延迟节可以将输入该延迟节的写指示信号进行固定时间的延迟，所以，该N个抽头与N个预设时延一一对应。因此，对于该N个抽头中的每个抽头，当延迟线电路检测到写指示信号时，可以通过该抽头将写指示信号延迟该抽头对应的预设时延后发送给同步逻辑电路。
再者，延迟线电路还用于将写指示信号延迟第二时延后发送给同步逻辑电路。其中，第二时延为能够消除同步逻辑电路的亚稳态的时延。延迟线电路将写指示信号延迟第二时延后发送给同步逻辑电路，可以避免同步逻辑电路发生亚稳态，从而保证同步逻辑电路可以接收到稳定的写指示信号。
在本发明实施例中，延迟线电路中的N个抽头与N个预设时延一一对应，延迟线电路可以依次通过该N个抽头，将写指示信号依次延迟N个预设时延后通过同步逻辑电路发送给地址比较逻辑电路，以便地址比较逻辑电路可以依次确定与该N个预设延迟一一对应的N个读写地址差，进而保证后续处理器可以基于该N个读写地址差，实现对小数时延的准确确定。
结合第一方面至第一方面的第三种可能的实现方式中任一可能的实现方式，在上述第一方面的第四种可能的实现方式中，所述同步逻辑电路包括多个串联的触发器，所述多个串联的触发器中每个触发器用于在所述读时钟产生电路产生的读时钟信号的上升沿接收写指示信号。
其中，同步逻辑电路包括的多个触发器中的第一级触发器在读时钟信号的上升沿接收写指示信号，并将该写指示信号发送给第二级触发器，第二级触发器在读时钟信号的上升沿接收该写指示信号，并将该写指示信号发送给第三级触发器，如此，直至将该写指示信号发送给同步逻辑电路包括的第m级触发器， 第m级触发器在读时钟信号的上升沿接收该写指示信号，并将该写指示信号发送给地址比较逻辑电路，m为自然数，且m大于等于2。
需要说明的是，该多个触发器中的第一级触发器至第m级触发器是按照该多个触发器的串联顺序确定得到，也即是，可以将与延迟线电路连接的触发器确定为第一级触发器，将第一级触发器之后的触发器依次确定为第二级触发器、第三级触发器……第m级触发器。
在本发明实施例中，同步逻辑电路可以通过多个触发器将写指示信号发送给同步逻辑电路，由于该多个串联的触发器中每个触发器是在读时钟产生电路产生的读时钟信号的上升沿接收写指示信号并进行发送的，因此，可以实现写指示信号与读地址信号的信号同步，进而便于后续地址比较逻辑电路基于写指示信号和读地址信号，确定读写地址差。
结合第一方面的第三种可能的实现方式，在上述第一方面的第五种可能的实现方式中，所述读地址产生电路，用于将产生的多个读地址信号发送给所述地址比较逻辑电路；
所述写地址产生电路，用于将产生的写指示信号发送给所述延迟线电路，所述写指示信号是基于所述写地址产生电路产生的至少两个写地址产生，且所述写指示信号在所述写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平；
所述处理器，用于通过所述读地址产生电路、所述延迟线电路、所述同步逻辑电路和所述地址比较逻辑电路，基于所述写指示信号、所述多个读地址信号和所述读时钟产生电路产生的读时钟信号，获取N个读写地址差，所述N个读写地址差与所述延迟线电路中的N个预设时延一一对应；
所述处理器，还用于基于所述N个读写地址差和布线时延，确定小数时延，并基于所述小数时延，确定所述异步FIFO电路的时延，所述布线时延为所述写地址产生电路与所述同步逻辑电路之间的布线所引入的时延，所述小数时延为所述读时钟信号与所述写时钟产生电路产生的写时钟信号之间的相位差所引入的时延。
在本发明实施例中，处理器可以通过读地址产生电路、延迟线电路、同步逻辑电路和地址比较逻辑电路，基于写指示信号、多个读地址信号和读时钟产生电路产生的读时钟信号，获取N个读写地址差，并基于该N个读写地址差和布线时延，确定小数时延，进而基于该小数时延，确定异步FIFO电路的时 延，实现对该异步FIFO电路的准确确定。
结合第一方面的第五种可能的实现方式，在上述第一方面的第六种可能的实现方式中，所述延迟线电路，用于当检测到所述写指示信号时，将所述写指示信号延迟所述N个抽头中第i个抽头对应的预设时延后通过所述同步逻辑电路发送给所述地址比较逻辑电路，所述N个抽头与所述N个预设时延一一对应；
所述地址比较逻辑电路，用于当在所述读时钟信号的上升沿检测到所述写指示信号由所述第一逻辑电平跳变为所述第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，并基于所述指定写地址和获取的读地址，确定所述第i个抽头对应的读写地址差，将所述第i个抽头对应的读写地址差发送给所述处理器；
所述处理器，用于当接收到所述第i个抽头对应的读写地址差时，令所述i＝i+1，重新通过所述延迟线电路将所述写指示信号延迟所述N个抽头中第i个抽头对应的预设时延后通过所述同步逻辑电路发送给所述地址比较逻辑电路。
需要说明的是，处理器可以对延迟线电路当前所使用的抽头进行设置，也即是，处理器可以对延迟线电路当前所使用的预设时延进行设置，从而保证延迟线电路可以依次遍历该N个抽头，以将写指示信号依次延迟该N个预设时延。
本发明实施例中，可以通过延迟线电路、同步逻辑电路、地址比较逻辑电路和处理器的配合来执行一个循环操作，从而保证可以获取到N个抽头中每个抽头对应的读写地址差，也即是，可以保证获取到N个预设时延中每个预设时延对应的读写地址差，进而可以保证后续处理器基于该N个读写地址差确定小数时延时的准确性。
第二方面，提供了一种时延确定方法，应用于上述第一方面至第一方面的第六种可能的实现方式中任一可能的实现方式所述的异步FIFO电路中，所述方法包括：
在对所述随机访问存储器进行读操作和写操作的过程中，所述读地址产生电路将产生的多个读地址信号发送给所述地址比较逻辑电路，所述写地址产生电路将产生的写指示信号发送给所述延迟线电路，所述写指示信号是基于所述 写地址产生电路产生的至少两个写地址产生，且所述写指示信号在所述写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平；
所述处理器通过所述读地址产生电路、所述延迟线电路、所述同步逻辑电路和所述地址比较逻辑电路，基于所述写指示信号、所述多个读地址信号和所述读时钟产生电路产生的读时钟信号，获取N个读写地址差，所述N个读写地址差与所述延迟线电路中的N个预设时延一一对应，所述N为大于1的自然数；
所述处理器基于所述N个读写地址差和布线时延，确定小数时延，所述布线时延为所述写地址产生电路与所述同步逻辑电路之间的布线所引入的时延，所述小数时延为所述读时钟信号与所述写时钟产生电路产生的写时钟信号之间的相位差所引入的时延；
所述处理器基于所述小数时延，确定所述异步FIFO电路的时延。
其中，在对随机访问存储器进行读操作的过程中，每当读地址产生电路检测到读时钟信号的一个上升沿时，产生一个读地址信号，该读地址信号中携带读地址，也即是，读地址产生电路可以在读时钟信号的每个周期内产生一个读地址信号。同时，在对随机访问存储器进行写操作的过程中，写地址产生电路可以产生写指示信号和多个写地址信号，每个写地址信号中携带写地址，且当写地址产生电路检测到产生的写地址为指定写地址时，可以将该写指示信号从第一逻辑电平跳变为第二逻辑电平。
另外，第一逻辑电平的状态与第二逻辑电平的状态相反，如当第一逻辑电平为0时，第二逻辑电平可以为1；当第一逻辑电平为1时，第二逻辑电平可以为0，本发明实施例对此不做具体限定。
再者，写地址产生电路还可以在检测到产生的写地址为指定写地址之外的任一写地址时，将该写指示信号从第二逻辑电平跳变为第一逻辑电平，本发明实施例对此不做具体限定。
在本发明实施例中，处理器可以通过读地址产生电路、延迟线电路、同步逻辑电路和地址比较逻辑电路，基于写指示信号、多个读地址信号和读时钟产生电路产生的读时钟信号，获取N个读写地址差，并基于该N个读写地址差和布线时延，确定小数时延，进而基于该小数时延，确定异步FIFO电路的时延，实现对该异步FIFO电路的准确确定。
结合第二方面，在上述第二方面的第一种可能的实现方式中，所述延迟线 电路包括N-1个延迟节和N个抽头，所述N个抽头与所述N个预设时延一一对应；
所述处理器通过所述读地址产生电路、所述延迟线电路、所述同步逻辑电路和所述地址比较逻辑电路，基于所述写指示信号、所述多个读地址信号和所述读时钟产生电路产生的读时钟信号，获取N个读写地址差，包括：
当所述延迟线电路检测到所述写指示信号时，将所述写指示信号延迟所述N个抽头中第i个抽头对应的预设时延后通过所述同步逻辑电路发送给所述地址比较逻辑电路，所述i大于或等于1且小于或等于N-1；
当所述地址比较逻辑电路在所述读时钟信号的上升沿检测到所述写指示信号由所述第一逻辑电平跳变为所述第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，基于所述指定写地址和获取的读地址，确定所述第i个抽头对应的读写地址差，并将所述第i个抽头对应的读写地址差发送给所述处理器；
当所述处理器接收到所述第i个抽头对应的读写地址差时，令所述i＝i+1，返回所述将所述写指示信号延迟所述N个抽头中第i个抽头对应的预设时延后通过所述同步逻辑电路发送给所述地址比较逻辑电路的步骤。
需要说明的是，N-1个延迟节中的每个延迟节用于对输入该延迟节的写指示信号进行延迟。
另外，由于N个抽头中各个抽头与写地址产生电路之间的延迟节的个数是固定的，且每个延迟节可以将输入该延迟节的写指示信号进行固定时间的延迟，所以，该N个抽头与N个预设时延一一对应。
再者，处理器可以对延迟线电路当前所使用的抽头进行设置，也即是，处理器可以对延迟线电路当前所使用的预设时延进行设置，从而保证延迟线电路可以依次遍历该N个抽头，以将写指示信号依次延迟该N个预设时延。
本发明实施例中，可以通过延迟线电路、同步逻辑电路、地址比较逻辑电路和处理器的配合来执行一个循环操作，从而保证可以获取到N个抽头中每个抽头对应的读写地址差，也即是，可以保证获取到N个预设时延中每个预设时延对应的读写地址差，进而可以保证后续处理器基于该N个读写地址差确定小数时延时的准确性。
结合第二方面的第一种可能的实现方式，在上述第二方面的第二种可能的实现方式中，所述地址比较逻辑电路基于指定写地址和获取的读地址，确定所 述第i个抽头对应的读写地址差，包括：
所述地址比较逻辑电路确定所述指定写地址与获取的读地址之间的地址差；
所述地址比较逻辑电路将所述同步逻辑电路包括的触发器的个数减1，得到第一数值；
所述地址比较逻辑电路将确定的地址差和所述第一数值相加，得到所述第i个抽头对应的读写地址差。
在本发明实施例中，由于写指示信号是在写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平的，且该写指示信号是被同步逻辑电路延迟第一数值个时钟周期后发送给地址比较逻辑电路，因此，在地址比较逻辑电路检测到该写指示信号由第一逻辑电平跳变为第二逻辑电平时，写地址产生电路在产生该指定写地址后又产生了第一数值个写地址，所以当前对随机访问存储器进行写操作的写地址与指定写地址之间的地址差为第一数值。又由于地址比较逻辑电路用于确定同一时刻对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差，且地址比较逻辑电路当前接收到的读地址信号是直接发送给地址比较逻辑电路的，并没有进行延迟，因此，当地址比较逻辑电路基于该指定写地址和获取的读地址，确定第i个抽头对应的读写地址差时，可以将确定的地址差和第一数值相加，以得到第i个抽头对应的读写地址差，实现了对第i个抽头对应的读写地址差的准确确定。
结合第二方面至第二方面的第二种可能的实现方式中任一可能的实现方式，在上述第二方面的第三种可能的实现方式中，所述处理器基于所述N个读写地址差和布线时延，确定小数时延之前，还包括：
所述处理器从存储的后端布线报告中获取所述写地址产生电路与所述同步逻辑电路之间的布线所引入的最大时延和最小时延，所述后端布线报告用于记录所述异步FIFO电路包括的所有布线所引入的时延；
所述处理器将所述最大时延与所述最小时延的平均值确定为所述布线时延。
在本发明实施例中，由于写地址产生电路与同步逻辑电路的位置会对布线时延造成影响，因此，可以在进行该异步FIFO电路的布线时，约束写地址产生电路与同步逻辑电路的位置尽可能接近，以使写地址产生电路与同步逻辑电路之间的布线所引入的最大时延和最小时延的变化最小，以便基于该最大时延 和该最小时延确定的布线时延尽可能的小而稳定，从而保证处理器基于该布线时延确定小数时延时的准确性。
结合第二方面至第二方面的第三种可能的实现方式中任一可能的实现方式，在上述第二方面的第四种可能的实现方式中，所述处理器基于所述N个读写地址差和布线时延，确定小数时延，包括：
所述处理器基于所述N个读写地址差，从所述N个预设时延中确定第一时延；
所述处理器将所述第一时延与所述布线时延之和确定为所述小数时延。
在本发明实施例中，处理器可以基于N个读写地址差，从该N个预设时延中确定第一时延，并将该第一时延与布线时延之和确定为小数时延，从而实现了对小数时延的准确确定。
结合第二方面的第四种可能的实现方式，在上述第二方面的第五种可能的实现方式中，所述处理器基于所述N个读写地址差，从所述N个预设时延中确定第一时延，包括：
所述处理器基于所述N个预设时延，对所述N个读写地址差进行排序，得到所述N个读写地址差的顺序；
所述处理器基于所述N个读写地址差的顺序，从所述N个读写地址差中获取第一读写地址差，所述第一读写地址差为基于所述N个读写地址差中跳变的读写地址差确定得到，所述跳变的读写地址差为与前一位读写地址差不同的读写地址差；
所述处理器将所述第一读写地址差对应的预设时延确定为所述第一时延。
可选地，处理器基于该N个预设时延，对该N个读写地址差进行排序时，可以按照该N个预设时延由小到大的顺序，对该N个读写地址差进行排序，当然，也可以按照该N个预设时延由大到小的顺序，对该N个读写地址差进行排序，本发明实施例对此不做具体限定。
可选地，处理器基于该N个读写地址差的顺序，从该N个读写地址差中获取第一读写地址差的操作可以为：当该N个读写地址差的顺序为按照该N个预设时延由小到大的顺序排序得到时，处理器从N个读写地址差中获取首个跳变的读写地址差，将获取的读写地址差确定为第一读写地址差；当N个读写地址差的顺序为按照该N个预设时延由大到小的顺序排序得到时，处理器从N个读写地址差中确定最后一个跳变的读写地址差，并将该最后一个跳变的读写 地址差的前一位读写地址差确定为第一读写地址差。
结合第二方面的第四种可能的实现方式或者第二方面的第五种可能的实现方式，在上述第二方面的第六种可能的实现方式中，所述处理器基于所述N个读写地址差和布线时延，确定小数时延之后，还包括：
所述处理器基于所述第一时延，确定第二时延，所述第二时延为能够消除所述同步逻辑电路的亚稳态的时延；
所述处理器基于所述第一时延和所述第二时延，通过所述地址比较逻辑电路对所述读地址产生电路产生的读地址进行重置。
在本发明实施例中，由于第二时延为能够消除同步逻辑电路的亚稳态的时延，因此，在处理器基于第一时延和第二时延，通过地址比较逻辑电路对读地址产生电路产生的读地址进行重置的过程中，可以避免同步逻辑电路发生亚稳态，从而保证同步逻辑电路可以接收到稳定的写指示信号，进而保证地址比较逻辑电路确定的读写地址差的准确性，保证地址比较逻辑电路对读地址产生电路产生的读地址的正确重置。
结合第二方面的第六种可能的实现方式，在上述第二方面的第七种可能的实现方式中，所述处理器基于所述第一时延，确定第二时延，包括：
当所述第一时延小于或等于信号稳定时间时，所述处理器将所述第一时延与第一预设时延之和确定为所述第二时延，所述第一预设时延大于所述信号稳定时间且小于第三时延，所述信号稳定时间为第一级触发器的建立时间与保持时间之和，所述第一级触发器为所述同步逻辑电路包括的多个触发器中与所述延迟线电路连接的触发器，所述第三时延为时钟周期与所述信号稳定时间之间的差值，所述时钟周期为所述读时钟信号或者所述写时钟信号的周期，所述读时钟信号与所述写时钟信号的周期相等，所述信号稳定时间小于所述第三时延；或者，
当所述第一时延大于所述信号稳定时间且小于所述第三时延时，所述处理器将所述第一时延减去第二预设时延，得到所述第二时延，所述第二预设时延大于所述信号稳定时间且小于或等于所述小数时延；或者，
当所述第一时延大于或等于所述第三时延时，所述处理器将所述第一时延减去所述第一预设时延，得到所述第二时延。
需要说明的是，第一预设时延和第二预设时延均可以预先设置，且第一预设时延可以为在大于信号稳定时间且小于第三时延的范围内的任一时延，第二 预设时延可以为在大于信号稳定时间且小于或等于小数时延的范围内的任一时延，本发明实施例对此不做具体限定。
另外，在本发明实施例中，可以从后端布线报告中获取第一级触发器的建立时间与保持时间，将该建立时间与保持时间之和确定为信号稳定时间，当然，实际应用中，也可以以其它方式获取信号稳定时间，本发明实施例对此不做具体限定。
在本发明实施例中，由于当延迟线电路将写指示信号延迟第一时延后发送给同步逻辑电路时，读时钟信号的上升沿会正好位于写指示信号的跳变点，因此，为了消除同步逻辑电路的亚稳态，保证同步逻辑电路接收到的写指示信号比较稳定，可以基于第一时延，确定第二时延，进而延迟线电路可以将写指示信号延迟第二时延后发送给同步逻辑电路，以保证读时钟信号的上升沿位于写指示信号的稳定点，进而保证同步逻辑电路在读时钟信号的上升沿可以接收到稳定的写指示信号。
结合第二方面的第六种可能的实现方式或者第二方面的第七种可能的实现方式，在上述第二方面的第八种可能的实现方式中，所述处理器基于所述第一时延和所述第二时延，通过所述地址比较逻辑电路对所述读地址产生电路产生的读地址进行重置，包括：
所述处理器将所述第一时延发送给所述地址比较逻辑电路；
所述处理器将所述延迟线电路的时延设置为所述第二时延；
当所述延迟线电路检测到所述写指示信号时，将所述写指示信号通过所述同步逻辑电路发送给所述地址比较逻辑电路；
当所述地址比较逻辑电路在读时钟信号的上升沿检测到所述写指示信号由所述第一逻辑电平跳变为所述第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，基于所述指定写地址和获取的读地址，确定第二读写地址差，所述第二读写地址差为所述第二时延对应的读写地址差；
当所述地址比较逻辑电路接收到所述第一时延时，基于所述指定写地址、所述第一时延、所述第二读写地址差和指定读写地址差，对所述读地址产生电路当前产生的读地址进行重置。
需要说明的是，当该N个预设时延中不包括第二时延时，此时该N个读写地址差中不包括第二时延对应的读写地址差，所以，需要对第二时延对应的读写地址差进行确定；而当该N个预设时延中包括第二时延时，为了保证确定 的第二读写地址差的准确性，也可以对第二时延对应的读写地址差再次进行确定。因此，无论该N个预设时延中是否包括第二时延，在处理器将延迟线电路的时延设置为第二时延后，地址比较逻辑电路都可以通过延迟线电路、同步逻辑电路和读地址产生电路，确定第二时延对应的读写地址差，也即是，确定第二读写地址差。
在本发明实施例中，在处理器将延迟线电路设置为第二时延后，当延迟线电路检测到写指示信号时，可以将该写指示信号延迟第二时延后发送给地址比较逻辑电路。由于第二时延为能够消除同步逻辑电路的亚稳态的时延，因此，此时同步逻辑电路可以接收到稳定的写指示信号，并将该写指示信号发送给地址比较逻辑电路，从而保证地址比较逻辑电路基于该写指示信号确定的第二读写地址差的准确性，保证地址比较逻辑电路可以基于该第二读写地址差对读地址产生电路产生的读地址的正确重置。
结合第二方面的第六种可能的实现方式或者第二方面的第七种可能的实现方式，在上述第二方面的第九种可能的实现方式中，所述处理器基于所述第一时延和所述第二时延，通过地址比较逻辑电路对所述读地址产生电路产生的读地址进行重置，包括：
当所述N个预设时延中包括所述第二时延时，所述处理器从所述N个读写地址差中，获取第二读写地址差，所述第二读写地址差为所述第二时延对应的读写地址差；
所述处理器将所述第一时延和所述第二读写地址差发送给所述地址比较逻辑电路；
所述处理器将所述延迟线电路的时延设置为所述第二时延；
当所述延迟线电路检测到所述写指示信号时，将所述写指示信号通过所述同步逻辑电路发送给所述地址比较逻辑电路；
当所述地址比较逻辑电路在所述读时钟信号的上升沿检测到所述写指示信号由所述第一逻辑电平跳变为所述第二逻辑电平且接收到所述第一时延和所述第二读写地址差时，基于所述指定写地址、所述第一时延、所述第二读写地址差和指定读写地址差，对所述读地址产生电路当前产生的读地址进行重置。
在本发明实施例中，当该N个预设时延中包括第二时延时，此时该N个读写地址差中包括第二时延对应的读写地址差，因此，处理器可以从该N个读 写地址差中直接获取第二时延对应的读写地址差，并将该第二时延对应的读写地址差发送给地址比较逻辑电路，此时地址比较逻辑电路无需通过延迟线电路、同步逻辑电路和读地址产生电路对第二时延对应的读写地址差进行再一次确定，从而节省了异步FIFO电路中的处理资源。
结合第二方面的第八种可能的实现方式或者第二方面的第九种可能的实现方式，在上述第二方面的第十种可能的实现方式中，所述地址比较逻辑电路基于所述指定写地址、所述第一时延、所述第二读写地址差和指定读写地址差，对所述读地址产生电路当前产生的读地址进行重置，包括：
当所述第一时延小于或等于信号稳定时间且所述第二读写地址差加1所得的地址差不等于所述指定读写地址差时，所述地址比较逻辑电路基于所述指定写地址和所述同步逻辑电路包括的触发器的个数，确定第一地址，并将所述读地址产生电路当前产生的读地址设置为所述第一地址；或者，
当所述第一时延大于所述信号稳定时间且所述第二读写地址差不等于所述指定读写地址差时，所述地址比较逻辑电路基于所述指定写地址和所述同步逻辑电路包括的触发器的个数，确定第二地址，并将所述读地址产生电路当前产生的读地址设置为所述第二地址。
在本发明实施例中，地址比较逻辑电路可以基于第一时延和第二读写地址差的不同情况，确定第一地址或者第二地址，进而基于该第一地址或者第二地址，对读地址产生电路当前产生的读地址进行重置，从而实现了对读地址产生电路当前产生的读地址的正确重置。
结合第二方面至第二方面的第十种可能的实现方式中任一可能的实现方式，在上述第二方面的第十一种可能的实现方式中，所述处理器基于所述小数时延，确定所述异步FIFO电路的时延，包括：
所述处理器获取整数时延，所述整数时延为同一时刻对所述随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差所引入的时延；
所述处理器将所述小数时延和所述整数时延之和确定为所述异步FIFO电路的时延。
可选地，处理器获取整数时延时，可以将指定读写地址差与时钟周期的乘积确定为整数时延，当然，实际应用中，处理器也可以通过其它方式获取整数时延，本发明实施例对此不做具体限定。
在本发明实施例中，由于通常情况下异步FIFO电路的时延包括整数时延 和小数时延，因此，可以将小数时延和整数时延之和确定为异步FIFO电路的时延，从而实现对该异步FIFO电路的时延的准确确定。
结合第二方面至第二方面的第十一种可能的实现方式中任一可能的实现方式，在上述第二方面的第十二种可能的实现方式中，所述方法还包括：
当所述处理器接收到复位设置指令时，将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，所述第三地址与所述第四地址的地址差为指定读写地址差，所述写地址上电复位值为上电时所述写地址产生电路产生的初始写地址，所述读地址上电复位值为上电时所述读地址产生电路产生的初始读地址。
需要说明的是，复位设置指令用于对写地址上电复位值和读地址上电复位值进行设置。
在本发明实施例中，将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，且第三地址与第四地址的地址差为指定读写地址差，可以保证异步FIFO电路在上电刚开始工作时，对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差为指定读写地址差，从而保证该异步FIFO电路在整个工作过程中的时延均相同，保证确定的异步FIFO电路的时延的准确性。
本发明提供的技术方案的有益效果是：在本发明实施例中，异步FIFO电路包括写时钟产生电路、读时钟产生电路、写地址产生电路、读地址产生电路、随机访问存储器、延迟线电路、同步逻辑电路、地址比较逻辑电路和处理器。其中，读地址产生电路可以将产生的多个读地址信号发送给地址比较逻辑电路，写地址产生电路可以将产生的写指示信号发送给延迟线电路，由于延迟线电路中包括N个预设时延，因此，该延迟线电路可以将写指示信号依次延迟N个预设时延后通过同步逻辑电路发送给地址比较逻辑电路，地址比较逻辑电路可以基于写指示信号和读地址信号，确定与该N个预设时延一一对应的N个读写地址差，并将该N个读写地址差发送给处理器，之后，处理器可以基于该N个读写地址差和布线时延，确定小数时延，并基于该小数时延，确定异步FIFO电路的时延，从而实现对异步FIFO电路的时延的准确确定。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1是相关技术提供的一种异步FIFO电路的结构示意图；
图2是本发明实施例提供的一种异步FIFO电路的结构示意图；
图3是本发明实施例提供的另一种异步FIFO电路的结构示意图；
图4是本发明实施例提供的又一种异步FIFO电路的结构示意图；
图5是本发明实施例提供的一种延迟线电路的结构示意图；
图6是本发明实施例提供的一种同步逻辑电路的结构示意图；
图7是本发明实施例提供的一种时延确定方法的流程图；
图8是本发明实施例提供的第一种写指示信号的示意图；
图9(a)是本发明实施例提供的第二种写指示信号的示意图；
图9(b)是本发明实施例提供的第三种写指示信号的示意图；
图10(a)是本发明实施例提供的第四种写指示信号的示意图；
图10(b)是本发明实施例提供的第五种写指示信号的示意图；
图10(c)是本发明实施例提供的第六种写指示信号的示意图。
附图标记：
相关技术：
1：写时钟产生电路；1a：写时钟产生电路的输出端；
2：读时钟产生电路；2a：读时钟产生电路的输出端；
3：写地址产生电路；3a：写地址产生电路的输入端；3b：写地址产生电路的第一输出端；3c：写地址产生电路的第二输出端；
4：读地址产生电路；4a：读地址产生电路的输入端；4b：读地址产生电路的输出端；4c：读地址产生电路的置位端；
5：随机访问存储器；5a：随机访问存储器的第一输入端；5b：随机访问存储器的第二输入端；
6：同步逻辑电路；6a：同步逻辑电路的第一输入端；6b：同步逻辑电路的输出端；6c：同步逻辑电路的第二输入端；
7：地址比较逻辑电路；7a：地址比较逻辑电路的第一输入端；7b：地址比较逻辑电路的第二输入端，7c：地址比较逻辑电路的第三输入端；7d：地址比较逻辑电路的输出端。
本发明实施例：
8：写时钟产生电路；8a：写时钟产生电路的输出端；
9：读时钟产生电路；9a：读时钟产生电路的输出端；
10：写地址产生电路；10a：写地址产生电路的输入端；10b：写地址产生电路的第一输出端；10c：写地址产生电路的第二输出端；10d：写地址产生电路的复位端；
11：读地址产生电路；11a：读地址产生电路的输入端；11b：读地址产生电路的输出端；11c：读地址产生电路的置位端；11d：读地址产生电路的复位端；
12：随机访问存储器；12a：随机访问存储器的第一输入端；12b：随机访问存储器的第二输入端；
13：延迟线电路；13a：延迟线电路的第一输入端；13b：延迟线电路的输出端；13c：延迟线电路的第二输入端；
14：同步逻辑电路；14a：同步逻辑电路的第一输入端；14b：同步逻辑电路的输出端；14c：同步逻辑电路的第二输入端；
15：地址比较逻辑电路；15a：地址比较逻辑电路的第一输入端；15b：地址比较逻辑电路的第二输入端，15c：地址比较逻辑电路的第三输入端；15d：地址比较逻辑电路的第一输出端；15e：地址比较逻辑电路的第二输出端；
16：处理器；16a：处理器的第一输出端；16b：处理器的输入端；16c：处理器的第二输出端；16d：处理器16的第三输出端；
D：延迟节；T：抽头；P：触发器。
具体实施方式
下面将结合附图对本发明实施方式作进一步地详细描述。
图2是本发明实施例提供的一种异步FIFO电路的结构示意图。参见图2，该异步FIFO电路包括：写时钟产生电路8、读时钟产生电路9、写地址产生电路10、读地址产生电路11、随机访问存储器12、延迟线电路13、同步逻辑电路14、地址比较逻辑电路15和处理器16；
写时钟产生电路8的输出端8a与写地址产生电路10的输入端10a连接，写地址产生电路10的第一输出端10b与随机访问存储器12的第一输入端12a 连接，写地址产生电路10的第二输出端10c与延迟线电路13的第一输入端13a连接，延迟线电路13的第二输入端13c与处理器16的第一输出端16a连接，延迟线电路13的输出端13b与同步逻辑电路14的第一输入端14a连接，同步逻辑电路14的输出端14b与地址比较逻辑电路15的第一输入端15a连接，同步逻辑电路14的第二输入端14c和地址比较逻辑电路15的第二输入端15b分别与读时钟产生电路9的输出端9a连接；读时钟产生电路9的输出端9a还与读地址产生电路11的输入端11a连接，读地址产生电路11的输出端11b与随机访问存储器12的第二输入端12b连接，读地址产生电路11的输出端11b还与地址比较逻辑电路15的第三输入端15c连接，地址比较逻辑电路15的第一输出端15d与处理器16的输入端16b连接。
其中，当通过该异步FIFO电路对随机访问存储器12进行写操作时，写时钟产生电路8可以将产生的写时钟信号发送给写地址产生电路10，写地址产生电路10可以在该写时钟信号的上升沿产生写地址信号，该写地址信号中携带写地址，此时该异步FIFO电路所在的通信设备可以将待传输的数据写入随机访问存储器12中该写地址所对应的位置上。同时，当通过该异步FIFO电路对随机访问存储器12进行读操作时，读时钟产生电路9可以将产生的读时钟信号发送给读地址产生电路11，读地址产生电路11可以在该读时钟信号的上升沿产生读地址信号，该读地址信号中携带读地址，此时该异步FIFO电路所在的通信设备可以从随机访问存储器12中读取该读地址所对应的位置上存储的数据。
其中，写时钟产生电路8用于产生写时钟信号；读时钟产生电路9用于产生读时钟信号；写地址产生电路10用于产生多个写地址信号和写指示信号，每个写地址信号中携带写地址，该写指示信号是基于写地址产生电路10产生的至少两个写地址产生，且该写指示信号在写地址产生电路10产生指定写地址时由第一逻辑电平跳变为第二逻辑电平，其中，写地址产生电路10可以通过第一输出端10b将产生的多个写地址信号发送给随机访问存储器12，且可以通过第二输出端10c将产生的写指示信号发送给延迟线电路13；读地址产生电路11用于产生多个读地址信号，每个读地址信号中携带读地址，其中，读地址产生电路11可以通过输出端11b将产生的多个读地址信号发送给随机访问存储器12和地址比较逻辑电路15；随机访问存储器12用于存储数据；延迟线电路13用于对输入延迟线电路13的写指示信号进行延迟，并将延迟后的写指 示信号发送给同步逻辑电路14；同步逻辑电路14用于在读时钟产生电路9产生的读时钟信号的上升沿接收写指示信号，并将所接收的写指示信号发送给地址比较逻辑电路15；地址比较逻辑电路15用于基于写指示信号和读地址信号，确定读写地址差，该读写地址差为当前对随机访问存储器12进行写操作的写地址与进行读操作的读地址之间的地址差；处理器16用于通过读地址产生电路11、延迟线电路13、同步逻辑电路14和地址比较逻辑电路15，基于写指示信号、多个读地址信号和读时钟信号，获取N个读写地址差，其中，该N个读写地址差与延迟线电路13中的N个预设时延一一对应，该N为大于1的自然数；且处理器16还用于基于该N个读写地址差和布线时延，确定小数时延，并基于小数时延，确定异步FIFO电路的时延，其中，布线时延为写地址产生电路与同步逻辑电路之间的布线所引入的时延，小数时延为读时钟信号与写时钟信号之间的相位差所引入的时延。
需要说明的是，指定写地址和N个预设时延均可以预先设置，本发明实施例对此不做具体限定。
另外，第一逻辑电平的状态与第二逻辑电平的状态相反，如当第一逻辑电平为0时，第二逻辑电平为1；当第一逻辑电平为1时，第二逻辑电平为0，本发明实施例对此不做具体限定。
再者，写地址产生电路10还可以在检测到产生的写地址为指定写地址之外的任一写地址时，将该写指示信号从第二逻辑电平跳变为第一逻辑电平，本发明实施例对此不做具体限定。
还需要说明的是，写时钟产生电路8、读时钟产生电路9、写地址产生电路10、读地址产生电路11、随机访问存储器12、延迟线电路13和同步逻辑电路14在实际应用中可以以硬件形式或软件形式实现，比如，写时钟产生电路8和读时钟产生电路9由振荡器来实现，进一步，还可以由振荡器结合锁相环来实现，写地址产生电路10和读地址产生电路11可以由硬件编程器件，如FPGA(Field Programmable Gate Array，现场可编程逻辑门阵列)来实现，同步逻辑电路14可以由触发器来实现，地址比较逻辑电路15和处理器16的功能在实际应用中可以以软件或硬件的形式实现，比如由硬件编码器件实现，本发明实施例对此不做具体限定。可选的，当以上电路和处理器由软件实现时，可以集成在一个硬件实体上，也可以各自分散或部分组合地分布在多个硬件实体上，在此不予限定。比如，上述地址比较逻辑电路15的功能也可以由所述处理器 16来实现，或者，处理器16的功能嵌入在所述地址比较逻辑电路15中来实现，或者，地址比较逻辑电路15和处理器16不予集成，在此不予限定。
参见图3，该异步FIFO电路中，地址比较逻辑电路15的第二输出端15e与读地址产生电路11的置位端11c连接。
其中，地址比较逻辑电路15用于在检测到写指示信号由第一逻辑电平跳变到第二逻辑电平时，对读地址产生电路11当前产生的读地址进行重置。
参见图4，该异步FIFO电路中，处理器16的第二输出端16c与写地址产生电路10的复位端10d连接，处理器16的第三输出端16d与读地址产生电路11的复位端11d连接。
其中，处理器16用于在接收到复位设置指令时，将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，第三地址与第四地址的地址差为指定读写地址差，写地址上电复位值为上电时写地址产生电路10产生的初始写地址，读地址上电复位值为上电时读地址产生电路11产生的初始读地址。
需要说明的是，复位设置指令用于对写地址上电复位值和读地址上电复位值进行设置。
另外，指定读写地址差可以预先设置，如该指定读写地址差可以为7、8等，本发明实施例对此不做具体限定。
再者，在本发明实施例中，将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，且第三地址与第四地址的地址差为指定读写地址差，可以保证异步FIFO电路在上电刚开始工作时，对随机访问存储器12进行写操作的写地址与进行读操作的读地址之间的地址差为指定读写地址差，从而保证该异步FIFO电路在整个工作过程中的时延均相同。
参见图5，延迟线电路13包括：N-1个延迟节D和N个抽头T，N为大于1的自然数；
N-1个延迟节串联连接，N-1个延迟节中第i个延迟节的一端与N个抽头中第i个抽头连接，N-1个延迟节中第i个延迟节的另一端与N个抽头中第i+1个抽头连接，i大于或等于1且小于或等于N-1。
其中，延迟线电路13用于当检测到写指示信号时，将写指示信号延迟该N个抽头中第i个抽头对应的预设时延后通过同步逻辑电路14发送给地址比较逻辑电路15，该N个抽头与该N个预设时延一一对应；地址比较逻辑电路15 用于当在读时钟信号的上升沿检测到写指示信号由第一逻辑电平跳变为第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，并基于指定写地址和获取的读地址，确定第i个抽头对应的读写地址差，将第i个抽头对应的读写地址差发送给处理器16；处理器16用于当接收到第i个抽头对应的读写地址差时，令i＝i+1，重新通过延迟线电路13将写指示信号延迟该N个抽头中第i个抽头对应的预设时延后通过同步逻辑电路14发送给地址比较逻辑电路15。
需要说明的是，N-1个延迟节中的每个延迟节用于对输入该延迟节的写指示信号进行延迟。
另外，由于N个抽头中各个抽头与写地址产生电路之间的延迟节的个数是固定的，且每个延迟节可以将输入该延迟节的写指示信号进行固定时间的延迟，所以，该N个抽头与N个预设时延一一对应。
再者，处理器16可以对延迟线电路13当前所使用的抽头进行设置，也即是，处理器16可以对延迟线电路13当前所使用的预设时延进行设置，从而保证延迟线电路13可以依次遍历该N个抽头，以将写指示信号依次延迟该N个预设时延。
还需要说明的是，本发明实施例中可以通过延迟线电路13、同步逻辑电路14、地址比较逻辑电路15和处理器16的配合来执行上述循环操作，从而保证可以获取到N个抽头中每个抽头对应的读写地址差，也即是，可以保证获取到N个预设时延中每个预设时延对应的读写地址差，进而可以保证后续处理器16基于该N个读写地址差确定小数时延时的准确性。
参见图6，同步逻辑电路14包括多个串联的触发器P，多个串联的触发器P中每个触发器用于在读时钟产生电路9产生的读时钟信号的上升沿接收写指示信号。
其中，同步逻辑电路14包括的多个触发器中的第一级触发器在读时钟信号的上升沿接收写指示信号，并将该写指示信号发送给第二级触发器，第二级触发器在读时钟信号的上升沿接收该写指示信号，并将该写指示信号发送给第三级触发器，如此，直至将该写指示信号发送给同步逻辑电路14包括的第m级触发器，第m级触发器在读时钟信号的上升沿接收该写指示信号，并将该写指示信号发送给地址比较逻辑电路15，m为自然数，且m大于等于2。
需要说明的是，该多个触发器中的第一级触发器至第m级触发器是按照该 多个触发器的串联顺序确定得到，也即是，可以将与延迟线电路13连接的触发器确定为第一级触发器，将第一级触发器之后的触发器依次确定为第二级触发器、第三级触发器……第m级触发器。
在本发明实施例中，异步FIFO电路包括写时钟产生电路、读时钟产生电路、写地址产生电路、读地址产生电路、随机访问存储器、延迟线电路、同步逻辑电路、地址比较逻辑电路和处理器。其中，读地址产生电路可以将产生的多个读地址信号发送给地址比较逻辑电路，写地址产生电路可以将产生的写指示信号发送给延迟线电路，由于延迟线电路中包括N个预设时延，因此，该延迟线电路可以将写指示信号依次延迟N个预设时延后通过同步逻辑电路发送给地址比较逻辑电路，地址比较逻辑电路可以基于写指示信号和读地址信号，确定与该N个预设时延一一对应的N个读写地址差，并将该N个读写地址差发送给处理器，之后，处理器可以基于该N个读写地址差和布线时延，确定小数时延，并基于该小数时延，确定异步FIFO电路的时延，从而实现对异步FIFO电路的时延的准确确定。
图7是本发明实施例提供的一种时延确定方法的流程图，该方法可以应用于上述图2-6任一所示的异步FIFO电路中，可以理解的是，本方法也可以应用于不同于图2-6任一所示的异步FIFO电路中，当图2-6任一所示的异步FIFO电路与本方法实现的关键部分关联性较小的部分或连接被改变时，本方法仍可适用于改变后的电路，比如，地址比较逻辑电路的置位功能及连接由其他模块如处理器来实现时，本方法应仍适用。参见图7，该方法包括：
步骤701：在对随机访问存储器进行读操作和写操作的过程中，读地址产生电路将产生的多个读地址信号发送给地址比较逻辑电路，写地址产生电路将产生的写指示信号发送给延迟线电路，该写指示信号是基于写地址产生电路产生的至少两个写地址产生，且该写指示信号在写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平。
其中，在对随机访问存储器进行读操作的过程中，每当读地址产生电路检测到读时钟信号的一个上升沿时，产生一个读地址信号，该读地址信号中携带读地址，也即是，读地址产生电路可以在读时钟信号的每个周期内产生一个读地址信号。同时，在对随机访问存储器进行写操作的过程中，写地址产生电路可以产生写指示信号和多个写地址信号，每个写地址信号中携带写地址，且当 写地址产生电路检测到产生的写地址为指定写地址时，可以将该写指示信号从第一逻辑电平跳变为第二逻辑电平。
需要说明的是，指定写地址可以预先设置，如该指定写地址可以为7、8、9等等，本发明实施例对此不做具体限定。
另外，第一逻辑电平的状态与第二逻辑电平的状态相反，如当第一逻辑电平为0时，第二逻辑电平可以为1；当第一逻辑电平为1时，第二逻辑电平可以为0，本发明实施例对此不做具体限定。
再者，写地址产生电路还可以在检测到产生的写地址为指定写地址之外的任一写地址时，将该写指示信号从第二逻辑电平跳变为第一逻辑电平，本发明实施例对此不做具体限定。
需要说明的是，随机访问存储器用于存储数据；读地址产生电路用于产生多个读地址信号，每个读地址信号中携带读地址；写地址产生电路用于产生多个写地址信号和写指示信号，每个写地址信号中携带写地址，该写指示信号是基于写地址产生电路产生的至少两个写地址产生，且该写指示信号在写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平；地址比较逻辑电路用于基于写指示信号和读地址信号，确定读写地址差，该读写地址差为当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差；延迟线电路用于对输入延迟线电路的写指示信号进行延迟。
步骤702：处理器通过读地址产生电路、延迟线电路、同步逻辑电路和地址比较逻辑电路，基于该写指示信号、该多个读地址信号和读时钟产生电路产生的读时钟信号，获取N个读写地址差，该N个读写地址差与延迟线电路中的N个预设时延一一对应，该N为大于1的自然数。
需要说明的是，N个预设时延可以预先设置，本发明实施例对此不做具体限定。另外，优选地，由于小数时延为读时钟信号与写时钟信号之间的相位差所引入的时延，且该小数时延小于一个时钟周期，因此，为了保证后续可以基于该N个预设时延，确定小数时延，该N个预设时延中的最小预设时延可以为0，该N个预设时延中的最大预设时延可以大于或等于一个时钟周期。其中，时钟周期为读时钟信号或者写时钟信号的周期，且读时钟信号与写时钟信号的周期相等。
具体地，延迟线电路包括N-1个延迟节和N个抽头，N个抽头与N个预设时延一一对应，处理器通过读地址产生电路、延迟线电路、同步逻辑电路和 地址比较逻辑电路，基于该写指示信号、该多个读地址信号和读时钟产生电路产生的读时钟信号，获取N个读写地址差的操作可以包括如下步骤(1)-(3)：
(1)、当延迟线电路检测到写指示信号时，将该写指示信号延迟N个抽头中第i个抽头对应的预设时延后通过同步逻辑电路发送给地址比较逻辑电路，i大于或等于1且小于或等于N-1。
需要说明的是，N-1个延迟节中的每个延迟节用于对输入该延迟节的写指示信号进行延迟。
其中，延迟线电路将该写指示信号延迟N个抽头中第i个抽头对应的预设时延后通过同步逻辑电路发送给地址比较逻辑电路的操作可以为：延迟线电路通过该N个抽头中第i个抽头将该写指示信号延迟该第i个抽头对应的预设时延后发送给同步逻辑电路；当同步逻辑电路接收到该写指示信号时，将该写指示信号延迟第一数值个时钟周期后发送给地址比较逻辑电路。
需要说明的是，第一数值为同步逻辑电路包括的触发器的个数减1所得的数值。
由于N个抽头中各个抽头与写地址产生电路之间的延迟节的个数是固定的，且每个延迟节可以将输入该延迟节的写指示信号进行固定时间的延迟，所以，该N个抽头与N个预设时延一一对应。因此，延迟线电路可以通过该N个抽头中第i个抽头将该写指示信号延迟该第i个抽头对应的预设时延后发送给同步逻辑电路。
其中，同步逻辑电路包括多个串联的触发器，当同步逻辑电路接收到该写指示信号时，将该写指示信号延迟第一数值个时钟周期后发送给地址比较逻辑电路的操作可以为：同步逻辑电路包括的多个触发器中的第一级触发器在读时钟信号的上升沿接收该写指示信号，并将该写指示信号发送给第二级触发器，第二级触发器在读时钟信号的上升沿接收该写指示信号，并将该写指示信号发送给第三级触发器，如此，直至将该写指示信号发送给同步逻辑电路包括的第m级触发器，第m级触发器在读时钟信号的上升沿接收该写指示信号，并将该写指示信号发送给地址比较逻辑电路，m为自然数，且m大于等于2。
需要说明的是，该多个触发器中的第一级触发器至第m级触发器是按照该多个触发器的串联顺序确定得到，也即是，可以将该多个触发器中与延迟线电路连接的触发器确定为第一级触发器，将第一级触发器之后的触发器依次确定为第二级触发器、第三级触发器……第m级触发器。
由于同步逻辑电路包括的多个触发器中每个触发器是在读时钟信号的上升沿接收写指示信号，并将该写指示信号发送给下一个触发器的，因此，当该写指示信号被一个触发器发送给下一个触发器，并被下一个触发器再次发送时，该写指示信号被延迟了一个时钟周期，因此，同步逻辑电路可以将该写指示信号延迟第一数值个时钟周期。
需要说明的是，当同步逻辑电路接收到该写指示信号时，将该写指示信号延迟第一数值个时钟周期后发送给地址比较逻辑电路的操作还可以参考相关技术，本发明实施例对此不再进行详细阐述。
(2)、当地址比较逻辑电路在读时钟信号的上升沿检测到该写指示信号由第一逻辑电平跳变为第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，基于指定写地址和获取的读地址，确定第i个抽头对应的读写地址差，并将该第i个抽头对应的读写地址差发送给处理器。
其中，地址比较逻辑电路基于指定写地址和获取的读地址，确定第i个抽头对应的读写地址差的操作可以为：地址比较逻辑电路确定指定写地址与获取的读地址之间的地址差；地址比较逻辑电路将同步逻辑电路包括的触发器的个数减1，得到第一数值；地址比较逻辑电路将确定的地址差和第一数值相加，得到第i个抽头对应的读写地址差。
由于写指示信号是在写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平的，且该写指示信号是被同步逻辑电路延迟第一数值个时钟周期后发送给地址比较逻辑电路，因此，在地址比较逻辑电路检测到该写指示信号由第一逻辑电平跳变为第二逻辑电平时，写地址产生电路在产生该指定写地址后又产生了第一数值个写地址，所以当前对随机访问存储器进行写操作的写地址与指定写地址之间的地址差为第一数值。又由于地址比较逻辑电路用于确定同一时刻对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差，且地址比较逻辑电路当前接收到的读地址信号是直接发送给地址比较逻辑电路的，并没有进行延迟，因此，当地址比较逻辑电路基于该指定写地址和获取的读地址，确定第i个抽头对应的读写地址差时，需要将该指定写地址与获取的读地址之间的地址差和第一数值相加。
例如，地址比较逻辑电路确定该指定写地址与获取的读地址之间的地址差为6，同步逻辑电路包括的触发器的个数为3，则将同步逻辑电路包括的触发器的个数3减1，得到第一数值为2，将确定的地址差6和第一数值2相加， 得到第i个抽头对应的读写地址差为8。
其中，地址比较逻辑电路确定该指定写地址与获取的读地址之间的地址差的操作可以为：当该指定写地址大于获取的读地址时，将该指定写地址减去获取的读地址得到第二数值，将第二数值确定为该指定写地址与获取的读地址之间的地址差；当该指定写地址小于获取的读地址时，将获取的读地址减去该指定写地址得到第三数值，将随机访问存储器包括的地址总个数减去第三数值，得到第四数值，将第四数值确定为该指定写地址与获取的读地址之间的地址差；当该指定写地址等于获取的读地址时，如果该指定写地址的写次数与获取的读地址的读次数相同，则将该指定写地址与获取的读地址之间的地址差确定为0，如果该指定写地址的写次数与获取的读地址的读次数不相同，则将随机访问存储器包括的地址总个数确定为该指定写地址与获取的读地址之间的地址差。其中，该指定写地址的写次数为该指定写地址被写入数据的次数，获取的读地址的读次数为获取的读地址被读出数据的次数。
其中，随机访问存储器包括的多个地址中的每个地址上可以标记有该地址的读次数和写次数，该写次数为该地址被写入数据的次数，该读次数为该地址被读出数据的次数，本发明实施例对此不做具体限定。
例如，该指定写地址为8，获取的读地址为7，由于8大于7，则将该指定写地址8减去获取的读地址7，得到第二数值为1，并将第二数值1确定为该指定写地址与获取的读地址之间的地址差。
再例如，该指定写地址为2，获取的读地址为7，由于2小于7，则将获取的读地址减去该指定写地址，得到第三数值为5，假设随机访问存储器包括的地址总个数为10，则将随机访问存储器包括的地址总个数10减去第三数值5，得到第四数值为5，将第四数值5确定为该指定写地址与获取的读地址之间的地址差。
又例如，该指定写地址为7，获取的读地址为7，由于该指定写地址等于获取的读地址，则可以确定该指定写地址的写次数和获取的读地址的读次数，假设该指定写地址的写次数为2，获取的读地址的读次数为1，确定该指定写地址的写次数与获取的读地址的读次数不相同，假设随机访问存储器包括的地址总个数为10，则可以将随机访问存储器包括的地址总个数10确定为该指定写地址与获取的读地址之间的地址差。
需要说明的是，地址比较逻辑电路确定该指定写地址与获取的读地址之间 的地址差的操作还可以参考相关技术，本发明实施例对此不再进行详细阐述。
(3)、当处理器接收到该第i个抽头对应的读写地址差时，令i＝i+1，返回步骤(1)中将该写指示信号延迟N个抽头中第i个抽头对应的预设时延后通过同步逻辑电路发送给地址比较逻辑电路的步骤。
需要说明的是，本发明实施例中通过循环操作，可以保证获取到N个抽头中每个抽头对应的读写地址差，也即是，可以保证获取到N个预设时延中每个预设时延对应的读写地址差，从而可以保证后续处理器基于该N个读写地址差确定小数时延时的准确性。
步骤703：处理器基于该N个读写地址差和布线时延，确定小数时延，布线时延为写地址产生电路与同步逻辑电路之间的布线所引入的时延，小数时延为读时钟信号与写时钟信号之间的相位差所引入的时延。
进一步地，处理器基于该N个读写地址差和布线时延，确定小数时延之前，处理器还可以从存储的后端布线报告中获取写地址产生电路与同步逻辑电路之间的布线所引入的最大时延和最小时延，并将最大时延与最小时延的平均值确定为布线时延，后端布线报告用于记录异步FIFO电路包括的所有布线所引入的时延。
例如，处理器从后端布线报告中获取的写地址产生电路与同步逻辑电路之间的布线所引入的最大时延为0.6ns(纳秒)，最小时延为0.2ns，则处理器可以将最大时延0.6ns与最小时延0.2ns的平均值0.4ns确定为布线时延。
需要说明的是，由于写地址产生电路与同步逻辑电路的位置会对布线时延造成影响，因此，本发明实施例可以在进行该异步FIFO电路的布线时，约束写地址产生电路与同步逻辑电路的位置尽可能接近，以使写地址产生电路与同步逻辑电路之间的布线所引入的最大时延和最小时延的变化最小，以便基于该最大时延和该最小时延确定的布线时延尽可能的小而稳定，从而保证处理器基于该布线时延确定小数时延时的准确性。
具体地，处理器基于该N个读写地址差和布线时延，确定小数时延时，处理器可以基于该N个读写地址差，从该N个预设时延中确定第一时延，并将第一时延与布线时延之和确定为小数时延。
其中，处理器基于该N个读写地址差，从该N个预设时延中确定第一时延的操作可以为：处理器基于该N个预设时延，对该N个读写地址差进行排序，得到该N个读写地址差的顺序；处理器基于该N个读写地址差的顺序， 从该N个读写地址差中获取第一读写地址差，第一读写地址差为基于该N个读写地址差中跳变的读写地址差确定得到，该跳变的读写地址差为与前一位读写地址差不同的读写地址差；处理器将第一读写地址差对应的预设时延确定为第一时延。
需要说明的是，处理器基于该N个预设时延，对该N个读写地址差进行排序时，可以按照该N个预设时延由小到大的顺序，对该N个读写地址差进行排序，当然，也可以按照该N个预设时延由大到小的顺序，对该N个读写地址差进行排序，本发明实施例对此不做具体限定。
例如，该N个预设时延为5ns、1ns、2ns、4ns、3ns，该N个读写地址差为6、7、7、6、7，其中，5ns对应的读写地址差为6、1ns对应的读写地址差为7、2ns对应的读写地址差为7、4ns对应的读写地址差为6、3ns对应的读写地址差为7，则处理器可以按照该N个预设时延由小到大的顺序，对该N个读写地址差进行排序，得到该N个读写地址差的顺序为7、7、7、6、6。
再例如，该N个预设时延为5ns、1ns、2ns、4ns、3ns，该N个读写地址差为6、7、7、6、7，其中，5ns对应的读写地址差为6、1ns对应的读写地址差为7、2ns对应的读写地址差为7、4ns对应的读写地址差为6、3ns对应的读写地址差为7，则处理器可以按照该N个预设时延由大到小的顺序，对该N个读写地址差进行排序，得到该N个读写地址差的顺序为6、6、7、7、7。
其中，处理器基于该N个读写地址差的顺序，从该N个读写地址差中获取第一读写地址差的操作可以为：当该N个读写地址差的顺序为按照该N个预设时延由小到大的顺序排序得到时，处理器从N个读写地址差中获取首个跳变的读写地址差，将获取的读写地址差确定为第一读写地址差；当N个读写地址差的顺序为按照该N个预设时延由大到小的顺序排序得到时，处理器从N个读写地址差中确定最后一个跳变的读写地址差，并将该最后一个跳变的读写地址差的前一位读写地址差确定为第一读写地址差。
例如，该N个读写地址差的顺序为7、7、7、6、6，且该N个读写地址差的顺序为按照该N个预设时延由小到大的顺序排序得到，则处理器可以从该N个读写地址差中获取首个跳变的读写地址差为6，将6确定为第一读写地址差。
再例如，该N个读写地址差的顺序为6、6、7、7、7，且该N个读写地址差的顺序为按照该N个预设时延由大到小的顺序排序得到，则处理器可以从该N个读写地址差中确定最后一个跳变的读写地址差为7，并将最后一个跳变的 读写地址差的前一位读写地址差6确定为第一读写地址差。
进一步地，结合具体的实例，对处理器基于N个读写地址差，从N个预设时延中确定第一时延，并将第一时延与布线时延之和确定为小数时延的原理进行说明：
图8是本发明实施例提供的一种延迟线电路对写指示信号进行延迟的示意图。参考图8，小数时延为写时钟信号与读时钟信号之间的相位差所引入的时延；写地址产生电路产生写指示信号，且写指示信号在写时钟信号的上升沿a由第一逻辑电平0跳变为第二逻辑电平1；延迟线电路中的N个预设时延为预设时延1、预设时延2……预设时延f-1、预设时延f……预设时延n，且预设时延1＜预设时延2＜……＜预设时延f-1＜预设时延f＜……＜预设时延n。
如图8所示，当延迟线电路将写指示信号分别延迟预设时延1、预设时延2……预设时延f-1后发送给同步逻辑电路时，读时钟信号的上升沿c均位于写指示信号的第二逻辑电平1。而当延迟线电路将写指示信号延迟预设时延f后发送给同步逻辑电路时，读时钟信号的上升沿c正好位于写指示信号的第一逻辑电平0向第二逻辑电平1跳变的跳变点。
由于写地址产生电路与同步逻辑电路之间的布线会引入布线时延，因此，当读时钟信号的上升沿c位于写指示信号的第一逻辑电平0向第二逻辑电平1跳变的跳变点时，写指示信号不但被延迟线电路延迟了预设时延f，还被写地址产生电路与同步逻辑电路之间的布线延迟了布线时延。由图8可知，当写指示信号被写地址产生电路发送给延迟线电路时，写指示信号的第一逻辑电平0向第二逻辑电平1跳变的跳变点处于写时钟信号的上升沿a，而当写指示信号被延迟预设时延f和布线时延后，写指示信号的第一逻辑电平0向第二逻辑电平1跳变的跳变点处于读时钟信号的上升沿c。由于小数时延由写时钟信号与读时钟信号之间的相位差所引入，也即是，小数时延为图8中写时钟信号的上升沿a与读时钟信号的上升沿c之间的时延，因此，可以将预设时延f和布线时延之和确定为小数时延。
由于当延迟线电路将写指示信号延迟预设时延1、预设时延2……预设时延f-1后发送给同步逻辑电路时，读时钟信号的上升沿c均处于写指示信号的第二逻辑电平1，并且由于同步逻辑电路只在读时钟信号的上升沿对写指示信号进行接收，因此，如图9(a)所示，当延迟线电路将写指示信号延迟预设时延1、预设时延2……预设时延f-1后发送给同步逻辑电路时，同步逻辑电路可 以在读时钟信号的上升沿c检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1。假设同步逻辑电路包括三个触发器，也即是同步逻辑电路可以将写指示信号延迟两个时钟周期，则此时地址比较逻辑电路可以在读时钟信号的上升沿e检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1，地址比较逻辑电路获取的读地址为在读时钟信号的上升沿e接收到的读地址。由于读写地址差是地址比较逻辑电路基于指定写地址和在检测到写指示信号由第一逻辑电平跳变为第二逻辑电平时获取的读地址确定得到，因此，预设时延1、预设时延2……预设时延f-1对应的读写地址差相等，例如，在如下表1所示的预设时延与读写地址差之间的对应关系中，预设时延1、预设时延2……预设时延f对应的读写地址差均为E。
由于延迟线电路将写指示信号延迟预设时延f后发送给同步逻辑电路时，读时钟信号的上升沿c正好处于写指示信号的第一逻辑电平0向第二逻辑电平1跳变的跳变点，读时钟信号的上升沿c之后的上升沿d处于写指示信号的第二逻辑电平1，并且由于同步逻辑电路只在读时钟信号的上升沿对写指示信号进行接收，因此，如图9(b)所示，当延迟线电路将写指示信号延迟预设时延f后发送给同步逻辑电路时，同步逻辑电路可以在读时钟信号的上升沿d检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1。假设同步逻辑电路包括三个触发器，也即是同步逻辑电路可以将写指示信号延迟两个时钟周期，则此时地址比较逻辑电路可以在读时钟信号的上升沿e之后的上升沿f检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1，地址比较逻辑电路获取的读地址为在读时钟信号的上升沿f接收到的读地址。而由于读地址产生电路在读时钟信号的上升沿f产生的读地址与在读时钟信号的上升沿e产生的读地址之间的地址差为1，因此，预设时延f对应的读写地址差会跳变为预设时延1、预设时延2……预设时延f-1中任一预设时延对应的地址差减1所得的地址差，例如，在如下表1所示的预设时延与读写地址差之间的对应关系中，预设延迟f对应的读写地址差跳变为E-1。
表1
需要说明的是，在本发明实施例中，仅以上述表1所示的预设时延与读写地址差之间的对应关系为例进行说明，上述表1并不对本发明实施例构成限定。
因此，当该N个读写地址差的顺序为按照该N个预设时延由小到大的顺序排序得到时，预设时延f为该N个读写地址差中首个跳变的读写地址差对应的预设时延，也即是，预设时延f为第一时延。
而当该N个读写地址差的顺序为按照该N个预设时延由大到小的顺序排序得到时，该N个读写地址差中最后一个跳变的读写地址差的前一位读写地址差与上述首个跳变的读写地址差相同。因此，当该N个读写地址差的顺序为按照该N个预设时延由大到小的顺序排序得到时，预设时延f为该N个读写地址差中最后一个跳变的读写地址差的前一位读写地址差对应的预设时延，也即是，预设时延f为第一时延。
因此，处理器基于该N个读写地址差和布线时延，确定小数时延时，可以基于该N个读写地址差，从该N个预设时延中确定第一时延，并将第一时延与布线时延之和确定为小数时延。
进一步地，处理器基于该N个读写地址差和布线时延，确定小数时延之后，处理器还可以基于第一时延，确定第二时延，第二时延为能够消除同步逻辑电路的亚稳态的时延；处理器基于第一时延和第二时延，通过地址比较逻辑电路对读地址产生电路产生的读地址进行重置。
其中，处理器基于第一时延，确定第二时延的操作可以为：当第一时延小于或等于信号稳定时间时，将第一时延与第一预设时延之和确定为第二时延，第一预设时延大于信号稳定时间且小于第三时延，信号稳定时间为第一级触发器的建立时间与保持时间之和，第一级触发器为同步逻辑电路包括的多个触发器中与延迟线电路连接的触发器，第三时延为时钟周期与信号稳定时间之间的差值，信号稳定时间小于第三时延；或者，当第一时延大于信号稳定时间且小于第三时延时，将第一时延减去第二预设时延，得到第二时延，第二预设时延大于信号稳定时间且小于或等于小数时延；或者，当第一时延大于或等于第三时延时，将第一时延减去第一预设时延，得到第二时延。
需要说明的是，第一预设时延和第二预设时延均可以预先设置，且第一预设时延可以为在大于信号稳定时间且小于第三时延的范围内的任一时延，第二预设时延可以为在大于信号稳定时间且小于或等于小数时延的范围内的任一 时延，本发明实施例对此不做具体限定。
另外，在本发明实施例中，可以从后端布线报告中获取第一级触发器的建立时间与保持时间，将该建立时间与保持时间之和确定为信号稳定时间，当然，实际应用中，也可以以其它方式获取信号稳定时间，本发明实施例对此不做具体限定。
由于同步逻辑电路中的第一级触发器是在读时钟信号的上升沿接收延迟线电路发送的写指示信号，因此，为了保证第一级触发器可以在读时钟信号的上升沿接收到稳定的写指示信号，该写指示信号应该在读时钟信号的上升沿到来之前的第一指定时间内稳定不变，并在该读时钟信号的上升沿到来之后的第二指定时间内稳定不变，否则第一级触发器接收到的写指示信号会不稳定，导致同步逻辑电路发生亚稳态。
需要说明的是，第一指定时间可以大于或等于第一级触发器的建立时间，，第二指定时间可以大于或等于第一级触发器的保持时间，本发明实施例对此不做具体限定。
由于当延迟线电路将写指示信号延迟第一时延后发送给同步逻辑电路时，读时钟信号的上升沿会正好位于写指示信号的跳变点，因此，为了消除同步逻辑电路的亚稳态，保证同步逻辑电路接收到的写指示信号比较稳定，可以基于第一时延，确定第二时延，进而延迟线电路可以将写指示信号延迟第二时延后发送给同步逻辑电路，以保证读时钟信号的上升沿位于写指示信号的稳定点，进而保证同步逻辑电路在读时钟信号的上升沿可以接收到稳定的写指示信号。
如图10(a)所示，信号稳定时间为t，当第一时延小于或等于信号稳定时间时，可以将第一时延与第一预设时延之和确定为第二时延，此时，延迟线电路将写指示信号延迟第二时延后发送给同步逻辑电路时，读时钟信号的上升沿c正好位于该写指示信号的稳定区域A，从而保证同步逻辑电路在读时钟信号的上升沿可以接收到稳定的写指示信号，避免了亚稳态的发生。
如图10(b)所示，信号稳定时间为t，当第一时延大于信号稳定时间且小于第三时延时，可以将第一时延减去第二预设时延，得到第二时延，此时，延迟线电路将写指示信号延迟第二时延后发送给同步逻辑电路时，读时钟信号的上升沿c正好位于该写指示信号的稳定区域B，从而保证同步逻辑电路在读时钟信号的上升沿可以接收到稳定的写指示信号，避免了亚稳态的发生。
如图10(c)所示，信号稳定时间为t，当第一时延大于或等于第三时延时， 可以将第一时延减去第一预设时延，得到第二时延，此时，延迟线电路将写指示信号延迟第二时延后发送给同步逻辑电路时，读时钟信号的上升沿c正好位于该写指示信号的稳定区域B，从而保证同步逻辑电路在读时钟信号的上升沿可以接收到稳定的写指示信号，避免了亚稳态的发生。
其中，处理器基于第一时延和第二时延，通过地址比较逻辑电路对读地址产生电路产生的读地址进行重置的操作可以包括如下两种方式：
第一种方式：处理器将第一时延发送给地址比较逻辑电路，并将延迟线电路的时延设置为第二时延；当延迟线电路检测到写指示信号时，将该写指示信号通过同步逻辑电路发送给地址比较逻辑电路；当地址比较逻辑电路在读时钟信号的上升沿检测到该写指示信号由第一逻辑电平跳变为第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，基于指定写地址和获取的读地址，确定第二读写地址差，第二读写地址差为第二时延对应的读写地址差；当地址比较逻辑电路接收到第一时延时，基于指定写地址、第一时延、第二读写地址差和指定读写地址差，对读地址产生电路当前产生的读地址进行重置。
需要说明的是，指定读写地址差可以预先设置，如该指定读写地址差可以为7、8等等，本发明实施例对此不做具体限定。
由于异步FIFO电路的时延包括整数时延和小数时延，且小数时延是读时钟信号与写时钟信号之间的相位差所引入的时延，因此，同一异步FIFO电路的小数时延是固定的。为了保证异步FIFO电路的时延固定，需要保证同一时刻对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差为指定读写地址差，从而保证同一异步FIFO电路的整数时延固定。而由于某些不可测因素的影响，可能会导致读地址产生电路产生的读地址有误，此时同一时刻对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差不为指定读写地址差，从而导致此时基于该指定读写地址差确定的异步FIFO电路的时延有误。因此，在异步FIFO电路工作的过程中，可以实时确定当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差，并当检测到该地址差不为指定读写地址差时，通过地址比较逻辑电路对读地址产生电路产生的读地址进行重置，以保证同一时刻对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差为指定读写地址差，从而保证基于指定读写地址差确定的该异步FIFO电路的时延的准确性。
由于地址比较逻辑电路用于基于同步逻辑电路发送的写指示信号和读地 址产生电路发送的读地址信号，确定当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的读写地址差，并当该读写地址差不等于指定读写地址差时对读地址产生电路产生的读地址进行重置。当同步逻辑电路发生亚稳态时，同步逻辑电路接收到的写指示信号可能不准确，从而影响地址比较逻辑电路确定的读写地址差的准确性，进而导致地址比较逻辑电路对读地址产生电路产生的读地址重置有误。又由于第二时延能够消除同步逻辑电路的亚稳态，因此，处理器可以将延迟线电路的时延设置为第二时延，此时同步逻辑电路可以接收到稳定的写指示信号，从而可以保证地址比较逻辑电路确定的读写地址差的准确性，进而保证地址比较逻辑电路可以对读地址产生电路产生的读地址进行正确重置。
由于地址比较逻辑电路对读地址产生电路产生的读地址进行重置的目的是为了使当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差为指定读写地址差。因此，在处理器将延迟线电路设置为第二时延后，当延迟线电路检测到写指示信号时，可以通过同步逻辑电路将该写指示信号发送给地址比较逻辑电路，以便地址比较逻辑电路可以在检测到该写指示信号由第一逻辑电平跳变为第二逻辑电平时，基于指定写地址、第一时延、第二读写地址差和指定读写地址差，对读地址产生电路当前产生的读地址进行重置。
需要说明的是，当该N个预设时延中不包括第二时延时，此时该N个读写地址差中不包括第二时延对应的读写地址差，所以，需要对第二时延对应的读写地址差进行确定；而当该N个预设时延中包括第二时延时，为了保证确定的第二读写地址差的准确性，也可以对第二时延对应的读写地址差再次进行确定。因此，无论该N个预设时延中是否包括第二时延，在处理器将延迟线电路的时延设置为第二时延后，地址比较逻辑电路都可以通过延迟线电路、同步逻辑电路和读地址产生电路，确定第二时延对应的读写地址差，也即是，确定第二读写地址差。
另外，当地址比较逻辑电路在读时钟信号的上升沿检测到该写指示信号由第一逻辑电平跳变为第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，基于指定写地址和获取的读地址，确定第二读写地址差的操作与上述步骤702中步骤(2)的操作类似，本发明实施例对此不再赘述。
第二种方式：当N个预设时延中包括第二时延时，处理器从N个读写地 址差中，获取第二读写地址差，第二读写地址差为第二时延对应的读写地址差；处理器将第一时延和第二读写地址差发送给地址比较逻辑电路，并将延迟线电路的时延设置为第二时延；当延迟线电路检测到写指示信号时，将写指示信号通过同步逻辑电路发送给地址比较逻辑电路；当地址比较逻辑电路在读时钟信号的上升沿检测到写指示信号由第一逻辑电平跳变为第二逻辑电平且接收到第一时延和第二读写地址差时，基于指定写地址、第一时延、第二读写地址差和指定读写地址差，对读地址产生电路当前产生的读地址进行重置。
需要说明的是，当该N个预设时延中包括第二时延时，此时该N个读写地址差中包括第二时延对应的读写地址差，因此，处理器可以从该N个读写地址差中直接获取第二时延对应的读写地址差，并将该第二时延对应的读写地址差发送给地址比较逻辑电路，此时地址比较逻辑电路无需通过延迟线电路、同步逻辑电路和读地址产生电路对第二时延对应的读写地址差进行再一次确定，从而节省了异步FIFO电路中的处理资源。
其中，在上述第一种方式和第二种方式中，地址比较逻辑电路基于指定写地址、第一时延、第二读写地址差和指定读写地址差，对读地址产生电路当前产生的读地址进行重置的操作可以包括如下方式(1)和方式(2)中的一种：
(1)、当第一时延小于或等于信号稳定时间且第二读写地址差加1所得的地址差不等于指定读写地址差时，地址比较逻辑电路基于指定写地址和同步逻辑电路包括的触发器的个数，确定第一地址，并将读地址产生电路当前产生的读地址设置为第一地址。
当第一时延小于或等于信号稳定时间时，如图10(a)所示，延迟线电路将写指示信号延迟第二时延后发送给同步逻辑电路时，读时钟信号的上升沿c位于写指示信号的第一逻辑电平0的稳定区域A，读时钟信号的上升沿c之后的上升沿d位于写指示信号的第二逻辑电平1的稳定区域B。由于同步逻辑电路只在读时钟信号的上升沿对写指示信号进行接收，因此，同步逻辑电路可以在读时钟信号的上升沿d检测到写指示信号由第一逻辑电0跳变为第二逻辑电平1。如图9(b)所示，假设同步逻辑电路包括三个触发器，则此时地址比较逻辑电路可以在读时钟信号的上升沿e之后的上升沿f检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1，此时地址比较逻辑电路获取的读地址为在读时钟信号的上升沿f接收到的读地址。
当当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之 间的地址差为指定读写地址差时，地址比较逻辑电路基于在读时钟信号的上升沿e接收到的读地址确定的读写地址差应该为指定读写地址差，由于读地址产生电路在读时钟信号的上升沿f产生的读地址与在读时钟信号的上升沿e产生的读地址之间的地址差为1，因此，当延迟线电路将写指示信号延迟第二时延时，地址比较逻辑电路基于在读时钟信号的上升沿f接收到的读地址确定的第二读写地址差比指定读写地址差小1。因此，当第一时延小于或等于信号稳定时间且第二读写地址差加1所得的地址差不等于指定读写地址差时，可以确定当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差不为指定读写地址差。此时地址比较逻辑电路可以基于指定写地址和同步逻辑电路包括的触发器的个数，确定第一地址，并将读地址产生电路当前产生的读地址设置为第一地址。
其中，地址比较逻辑电路基于指定写地址和同步逻辑电路包括的触发器的个数，确定第一地址的操作可以为：地址比较逻辑电路基于指定写地址和同步逻辑电路包括的触发器的个数，确定当前对随机访问存储器进行写操作的写地址，基于该写地址和指定读写地址差，确定第一地址，该写地址与第一地址之间的地址差为指定读写地址差。
其中，地址比较逻辑电路基于指定写地址和同步逻辑电路包括的触发器的个数，确定当前对随机访问存储器进行写操作的写地址的操作可以为：地址比较逻辑电路将同步逻辑电路包括的触发器的个数减1得到第一数值，将第一数值加1得到第五数值，基于指定写地址和第五数值，确定与该指定写地址之间的地址差为第五数值的地址，将确定的地址确定为当前对随机访问存储器进行写操作的写地址。
当第一时延小于或等于信号稳定时间时，如图9(b)所示，写地址产生电路产生的写指示信号在写时钟信号的上升沿a由第一逻辑电平0跳变为第二逻辑电平1，延迟线电路将该写指示信号延迟第二时延后，同步逻辑电路在读时钟信号的上升沿d检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1。由于读时钟信号的上升沿d在写时钟信号的上升沿b之后，写时钟的上升沿b在写时钟的上升沿a之后，因此，从写指示信号在写时钟信号的上升沿a发生跳变到同步逻辑电路在读时钟信号的上升沿d检测到该写指示信号的跳变的时间段内，写地址产生电路可以在写时钟信号的上升沿b产生一个写地址。而在同步逻辑电路将写指示信号发送给地址比较逻辑电路的过程中，由于同步逻辑 电路会将写指示信号延迟第一数值个时钟周期，因此，写地址产生电路在该过程中会产生第一数值个写地址。也即是，当地址比较逻辑电路检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1时，写地址产生电路在产生指定写地址之后又产生了第一数值加1个写地址，而第五数值正是第一数值加1后确定得到的，因此，当前对随机访问存储器进行写操作的写地址与指定写地址之间的地址差为第五数值，所以可以将与指定写地址之间的地址差为第五数值的地址确定为当前对随机访问存储器进行写操作的写地址。
其中，基于当前对随机访问存储器进行写操作的写地址和指定读写地址差，确定第一地址的操作可以参考相关技术，本公开实施例对此不进行详细阐述。
例如，指定读写地址差为8，指定写地址为9，同步逻辑电路包括的触发器的个数为3，则将同步逻辑电路包括的触发器的个数3减1得到第一数值为2，将第一数值加1得到第五数值为3，则当前对随机访问存储器进行写操作的写地址为与指定写地址9之间的地址差为第五数值3的写地址12。由于指定读写地址差为8，因此，可以基于该写地址12和指定读写地址差8，确定第一地址为4，之后，地址比较逻辑电路可以将读地址产生电路当前产生的读地址设置为第一地址4。
(2)、当第一时延大于信号稳定时间且第二读写地址差不等于指定读写地址差时，地址比较逻辑电路基于指定写地址和同步逻辑电路包括的触发器的个数，确定第二地址，并将读地址产生电路当前产生的读地址设置为第二地址。
当第一时延大于信号稳定时间时，如图10(b)或者图10(c)所示，延迟线电路将写指示信号延迟第二时延后发送给同步逻辑电路时，读时钟信号的上升沿c位于写指示信号的第二逻辑电平1的稳定区域B。由于同步逻辑电路只在读时钟信号的上升沿对写指示信号进行接收，因此，同步逻辑电路可以在读时钟信号的上升沿c检测到写指示信号由第一逻辑电0跳变为第二逻辑电平1。如图9(a)所示，假设同步逻辑电路包括三个触发器，则此时地址比较逻辑电路可以在读时钟信号的上升沿e检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1，地址比较逻辑电路获取的读地址为在读时钟信号的上升沿e接收到的读地址。
当当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差为指定读写地址差时，地址比较逻辑电路基于在读时钟信号的上升 沿e接收到的读地址确定的读写地址差应该为指定读写地址差，因此，当第一时延大于信号稳定时间且第二读写地址差不等于指定读写地址差时，可以确定当前对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差不为指定读写地址差。此时地址比较逻辑电路可以基于指定写地址和同步逻辑电路包括的触发器的个数，确定第二地址，并将读地址产生电路当前产生的读地址设置为第二地址。
其中，地址比较逻辑电路基于指定写地址和同步逻辑电路包括的触发器的个数，确定第二地址的操作可以为：地址比较逻辑电路基于指定写地址和同步逻辑电路包括的触发器的个数，确定当前对随机访问存储器进行写操作的写地址，基于该写地址和指定读写地址差，确定第二地址，该写地址与第二地址之间的地址差为指定读写地址差。
其中，地址比较逻辑电路基于指定写地址和同步逻辑电路包括的触发器的个数，确定当前对随机访问存储器进行写操作的写地址的操作可以为：地址比较逻辑电路将同步逻辑电路包括的触发器的个数减1，得到第一数值，基于指定写地址，确定与指定写地址之间的地址差为第一数值的地址，将确定的地址确定为当前对随机访问存储器进行写操作的写地址。
当第一时延大于信号稳定时间时，如图9(a)所示，写地址产生电路产生的写指示信号在写时钟信号的上升沿a由第一逻辑电平0跳变为第二逻辑电平1，延迟线电路将该写指示信号延迟第二时延后，同步逻辑电路在读时钟信号的上升沿c检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1。由于读时钟信号的上升沿c在写时钟信号的上升沿a之后，因此，从写指示信号在写时钟信号的上升沿a发生跳变到同步逻辑电路在读时钟信号的上升沿c检测到该写指示信号的跳变的时间段内，写地址产生电路不会产生写地址。而在同步逻辑电路将写指示信号发送给地址比较逻辑电路的过程中，由于同步逻辑电路会将写指示信号延迟第一数值个时钟周期，因此，写地址产生电路在该过程中会产生第一数值个写地址。也即是，当地址比较逻辑电路检测到写指示信号由第一逻辑电平0跳变为第二逻辑电平1时，写地址产生电路在产生指定写地址之后又产生了第一数值个写地址，所以，当前对随机访问存储器进行写操作的写地址与指定写地址之间的地址差为第一数值，因此，可以将与指定写地址之间的地址差为第一数值的地址确定为当前对随机访问存储器进行写操作的写地址。
其中，基于当前对随机访问存储器进行写操作的写地址和指定读写地址差，确定第二地址的操作可以参考相关技术，本公开实施例对此不进行详细阐述。
例如，指定读写地址差为8，指定写地址为9，同步逻辑电路包括的触发器的个数为3，将同步逻辑电路包括的触发器的个数3减1得到第一数值为2，则当前对随机访问存储器进行写操作的写地址为与指定写地址9之间的地址差为第一数值2的写地址11，由于指定读写地址差为8，因此，可以基于该写地址11和指定读写地址差8，确定第二地址为3，之后，地址比较逻辑电路可以将读地址产生电路当前产生的读地址设置为第二地址3。
步骤704：处理器基于小数时延，确定异步FIFO电路的时延。
具体地，处理器获取整数时延，并将小数时延和整数时延之和确定为异步FIFO电路的时延，整数时延为同一时刻对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差所引入的时延。
其中，处理器获取整数时延时，可以将指定读写地址差与时钟周期的乘积确定为整数时延，当然，实际应用中，处理器也可以通过其它方式获取整数时延，本发明实施例对此不做具体限定。
例如，指定读写地址差为8，时钟周期为10ns，则处理器可以将指定读写地址差8与时钟周期10ns相乘，得到整数时延为80ns，
进一步地，当处理器接收到复位设置指令时，将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，第三地址与第四地址的地址差为指定读写地址差，写地址上电复位值为上电时写地址产生电路产生的初始写地址，读地址上电复位值为上电时读地址产生电路产生的初始读地址。
需要说明的是，复位设置指令用于对写地址上电复位值和读地址上电复位值进行设置。
另外，在本发明实施例中，将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，且第三地址与第四地址的地址差为指定读写地址差，可以保证异步FIFO电路在上电刚开始工作时，对随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差为指定读写地址差，从而保证该异步FIFO电路在整个工作过程中的时延均相同，保证确定的异步FIFO电路的时延的准确性。
需要说明的是，本发明实施例中，当确定异步FIFO电路的时延后，可以 将该确定时延的异步FIFO电路应用于无线通信系统中基站的数字信号收发信机中，例如，可以应用于基站的MIMO(Multi-Input Multi-Output，多输入多输出)或者massive MIMO多天线系统中的数字信号收发信机中，以保证各天线对空口信号的收发定时同步，提高基站的定时同步精度。当然，该确定时延的异步FIFO电路还可以应用于同步传输网络中，例如，可以应用于使用IEEE-1588协议的以太网中，以保证IEEE-1588协议中时间戳在网络中的准确传递，提高网络结点间的时钟同步精度。
在本发明实施例中，在对随机访问存储器进行读操作和写操作的过程中，读地址产生电路将产生的多个读地址信号发送给地址比较逻辑电路，写地址产生电路将产生的写指示信号发送给延迟线电路，处理器通过读地址产生电路、延迟线电路、同步逻辑电路和地址比较逻辑电路，基于该写指示信号、该多个读地址信号和读时钟产生电路产生的读时钟信号，获取与延迟线电路中的N个预设时延一一对应的N个读写地址差，之后，处理器基于该N个读写地址差和布线时延，确定小数时延，并基于该小数时延，确定异步FIFO电路的时延，从而实现对异步FIFO电路的时延的准确确定。另外，在本发明实施例中，处理器还可以基于第一时延，确定第二时延，并基于第一时延和第二时延，通过地址比较逻辑电路对读地址产生电路产生的读地址进行重置，由于第二时延能够消除同步逻辑电路的亚稳态，因此，可以保证地址比较逻辑电路对读地址产生电路产生的读地址进行正确重置。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

  1. 一种异步先入先出队列FIFO电路，其特征在于，所述异步FIFO电路包括：写时钟产生电路、读时钟产生电路、写地址产生电路、读地址产生电路、随机访问存储器、延迟线电路、同步逻辑电路、地址比较逻辑电路和处理器；
    所述写时钟产生电路的输出端与所述写地址产生电路的输入端连接，所述写地址产生电路的第一输出端与所述随机访问存储器的第一输入端连接，所述写地址产生电路的第二输出端与所述延迟线电路的第一输入端连接，所述延迟线电路的第二输入端与所述处理器的第一输出端连接，所述延迟线电路的输出端与所述同步逻辑电路的第一输入端连接，所述同步逻辑电路的输出端与所述地址比较逻辑电路的第一输入端连接，所述同步逻辑电路的第二输入端和所述地址比较逻辑电路的第二输入端分别与所述读时钟产生电路的输出端连接；
    所述读时钟产生电路的输出端还与所述读地址产生电路的输入端连接，所述读地址产生电路的输出端与所述随机访问存储器的第二输入端连接，所述读地址产生电路的输出端还与所述地址比较逻辑电路的第三输入端连接，所述地址比较逻辑电路的第一输出端与所述处理器的输入端连接。
  2. 如权利要求1所述的异步FIFO电路，其特征在于，
    所述地址比较逻辑电路的第二输出端与所述读地址产生电路的置位端连接。
  3. 如权利要求1或2所述的异步FIFO电路，其特征在于，
    所述处理器的第二输出端与所述写地址产生电路的复位端连接，所述处理器的第三输出端与所述读地址产生电路的复位端连接。
  4. 如权利要求1-3任一权利要求所述的异步FIFO电路，其特征在于，所述延迟线电路包括：N-1个延迟节和N个抽头，所述N为大于1的自然数；
    所述N-1个延迟节串联连接，所述N-1个延迟节中第i个延迟节的一端与所述N个抽头中第i个抽头连接，所述N-1个延迟节中第i个延迟节的另一端与所述N个抽头中第i+1个抽头连接，所述i大于或等于1且小于或等于N-1。
  5. 如权利要求1-4任一权利要求所述的异步FIFO电路，其特征在于，所述同步逻辑电路包括多个串联的触发器，所述多个串联的触发器中每个触发器用于在所述读时钟产生电路产生的读时钟信号的上升沿接收写指示信号。
  6. 如权利要求4所述的异步FIFO电路，其特征在于，
    所述读地址产生电路，用于将产生的多个读地址信号发送给所述地址比较逻辑电路；
    所述写地址产生电路，用于将产生的写指示信号发送给所述延迟线电路，所述写指示信号是基于所述写地址产生电路产生的至少两个写地址产生，且所述写指示信号在所述写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平；
    所述处理器，用于通过所述读地址产生电路、所述延迟线电路、所述同步逻辑电路和所述地址比较逻辑电路，基于所述写指示信号、所述多个读地址信号和所述读时钟产生电路产生的读时钟信号，获取N个读写地址差，所述N个读写地址差与所述延迟线电路中的N个预设时延一一对应；
    所述处理器，还用于基于所述N个读写地址差和布线时延，确定小数时延，并基于所述小数时延，确定所述异步FIFO电路的时延，所述布线时延为所述写地址产生电路与所述同步逻辑电路之间的布线所引入的时延，所述小数时延为所述读时钟信号与所述写时钟产生电路产生的写时钟信号之间的相位差所引入的时延。
  7. 如权利要求6所述的异步FIFO电路，其特征在于，
    所述延迟线电路，用于当检测到所述写指示信号时，将所述写指示信号延迟所述N个抽头中第i个抽头对应的预设时延后通过所述同步逻辑电路发送给所述地址比较逻辑电路，所述N个抽头与所述N个预设时延一一对应；
    所述地址比较逻辑电路，用于当在所述读时钟信号的上升沿检测到所述写指示信号由所述第一逻辑电平跳变为所述第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，并基于所述指定写地址和获取的读地址，确定所述第i个抽头对应的读写地址差，将所述第i个抽头对应的读写地址差发送给所述处理器；
    所述处理器，用于当接收到所述第i个抽头对应的读写地址差时，令所述 i＝i+1，重新通过所述延迟线电路将所述写指示信号延迟所述N个抽头中第i个抽头对应的预设时延后通过所述同步逻辑电路发送给所述地址比较逻辑电路。
  8. 一种时延确定方法，应用于上述权利要求1-7任一权利要求所述的异步FIFO电路中，其特征在于，所述方法包括：
    在对所述随机访问存储器进行读操作和写操作的过程中，所述读地址产生电路将产生的多个读地址信号发送给所述地址比较逻辑电路，所述写地址产生电路将产生的写指示信号发送给所述延迟线电路，所述写指示信号是基于所述写地址产生电路产生的至少两个写地址产生，且所述写指示信号在所述写地址产生电路产生指定写地址时由第一逻辑电平跳变为第二逻辑电平；
    所述处理器通过所述读地址产生电路、所述延迟线电路、所述同步逻辑电路和所述地址比较逻辑电路，基于所述写指示信号、所述多个读地址信号和所述读时钟产生电路产生的读时钟信号，获取N个读写地址差，所述N个读写地址差与所述延迟线电路中的N个预设时延一一对应，所述N为大于1的自然数；
    所述处理器基于所述N个读写地址差和布线时延，确定小数时延，所述布线时延为所述写地址产生电路与所述同步逻辑电路之间的布线所引入的时延，所述小数时延为所述读时钟信号与所述写时钟产生电路产生的写时钟信号之间的相位差所引入的时延；
    所述处理器基于所述小数时延，确定所述异步FIFO电路的时延。
  9. 如权利要求8所述的方法，其特征在于，所述延迟线电路包括N-1个延迟节和N个抽头，所述N个抽头与所述N个预设时延一一对应；
    所述处理器通过所述读地址产生电路、所述延迟线电路、所述同步逻辑电路和所述地址比较逻辑电路，基于所述写指示信号、所述多个读地址信号和所述读时钟产生电路产生的读时钟信号，获取N个读写地址差，包括：
    当所述延迟线电路检测到所述写指示信号时，将所述写指示信号延迟所述N个抽头中第i个抽头对应的预设时延后通过所述同步逻辑电路发送给所述地址比较逻辑电路，所述i大于或等于1且小于或等于N-1；
    当所述地址比较逻辑电路在所述读时钟信号的上升沿检测到所述写指示信号由所述第一逻辑电平跳变为所述第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，基于所述指定写地址和获取的读地址，确定所述第i个抽 头对应的读写地址差，并将所述第i个抽头对应的读写地址差发送给所述处理器；
    当所述处理器接收到所述第i个抽头对应的读写地址差时，令所述i＝i+1，返回所述将所述写指示信号延迟所述N个抽头中第i个抽头对应的预设时延后通过所述同步逻辑电路发送给所述地址比较逻辑电路的步骤。
  10. 如权利要求9所述的方法，其特征在于，所述地址比较逻辑电路基于指定写地址和获取的读地址，确定所述第i个抽头对应的读写地址差，包括：
    所述地址比较逻辑电路确定所述指定写地址与获取的读地址之间的地址差；
    所述地址比较逻辑电路将所述同步逻辑电路包括的触发器的个数减1，得到第一数值；
    所述地址比较逻辑电路将确定的地址差和所述第一数值相加，得到所述第i个抽头对应的读写地址差。
  11. 如权利要求8-10任一权利要求所述的方法，其特征在于，所述处理器基于所述N个读写地址差和布线时延，确定小数时延之前，还包括：
    所述处理器从存储的后端布线报告中获取所述写地址产生电路与所述同步逻辑电路之间的布线所引入的最大时延和最小时延，所述后端布线报告用于记录所述异步FIFO电路包括的所有布线所引入的时延；
    所述处理器将所述最大时延与所述最小时延的平均值确定为所述布线时延。
  12. 如权利要求8-11任一权利要求所述的方法，其特征在于，所述处理器基于所述N个读写地址差和布线时延，确定小数时延，包括：
    所述处理器基于所述N个读写地址差，从所述N个预设时延中确定第一时延；
    所述处理器将所述第一时延与所述布线时延之和确定为所述小数时延。
  13. 如权利要求12所述的方法，其特征在于，所述处理器基于所述N个读写地址差，从所述N个预设时延中确定第一时延，包括：
    所述处理器基于所述N个预设时延，对所述N个读写地址差进行排序，得到所述N个读写地址差的顺序；
    所述处理器基于所述N个读写地址差的顺序，从所述N个读写地址差中获取第一读写地址差，所述第一读写地址差为基于所述N个读写地址差中跳变的读写地址差确定得到，所述跳变的读写地址差为与前一位读写地址差不同的读写地址差；
    所述处理器将所述第一读写地址差对应的预设时延确定为所述第一时延。
  14. 如权利要求12或13所述的方法，其特征在于，所述处理器基于所述N个读写地址差和布线时延，确定小数时延之后，还包括：
    所述处理器基于所述第一时延，确定第二时延，所述第二时延为能够消除所述同步逻辑电路的亚稳态的时延；
    所述处理器基于所述第一时延和所述第二时延，通过所述地址比较逻辑电路对所述读地址产生电路产生的读地址进行重置。
  15. 如权利要求14所述的方法，其特征在于，所述处理器基于所述第一时延，确定第二时延，包括：
    当所述第一时延小于或等于信号稳定时间时，所述处理器将所述第一时延与第一预设时延之和确定为所述第二时延，所述第一预设时延大于所述信号稳定时间且小于第三时延，所述信号稳定时间为第一级触发器的建立时间与保持时间之和，所述第一级触发器为所述同步逻辑电路包括的多个触发器中与所述延迟线电路连接的触发器，所述第三时延为时钟周期与所述信号稳定时间之间的差值，所述时钟周期为所述读时钟信号或者所述写时钟信号的周期，所述读时钟信号与所述写时钟信号的周期相等，所述信号稳定时间小于所述第三时延；或者，
    当所述第一时延大于所述信号稳定时间且小于所述第三时延时，所述处理器将所述第一时延减去第二预设时延，得到所述第二时延，所述第二预设时延大于所述信号稳定时间且小于或等于所述小数时延；或者，
    当所述第一时延大于或等于所述第三时延时，所述处理器将所述第一时延减去所述第一预设时延，得到所述第二时延。
  16. 如权利要求14或15所述的方法，其特征在于，所述处理器基于所述第一时延和所述第二时延，通过所述地址比较逻辑电路对所述读地址产生电路产生的读地址进行重置，包括：
    所述处理器将所述第一时延发送给所述地址比较逻辑电路；
    所述处理器将所述延迟线电路的时延设置为所述第二时延；
    当所述延迟线电路检测到所述写指示信号时，将所述写指示信号通过所述同步逻辑电路发送给所述地址比较逻辑电路；
    当所述地址比较逻辑电路在读时钟信号的上升沿检测到所述写指示信号由所述第一逻辑电平跳变为所述第二逻辑电平时，获取当前接收到的读地址信号中携带的读地址，基于所述指定写地址和获取的读地址，确定第二读写地址差，所述第二读写地址差为所述第二时延对应的读写地址差；
    当所述地址比较逻辑电路接收到所述第一时延时，基于所述指定写地址、所述第一时延、所述第二读写地址差和指定读写地址差，对所述读地址产生电路当前产生的读地址进行重置。
  17. 如权利要求14或15所述的方法，其特征在于，所述处理器基于所述第一时延和所述第二时延，通过地址比较逻辑电路对所述读地址产生电路产生的读地址进行重置，包括：
    当所述N个预设时延中包括所述第二时延时，所述处理器从所述N个读写地址差中，获取第二读写地址差，所述第二读写地址差为所述第二时延对应的读写地址差；
    所述处理器将所述第一时延和所述第二读写地址差发送给所述地址比较逻辑电路；
    所述处理器将所述延迟线电路的时延设置为所述第二时延；
    当所述延迟线电路检测到所述写指示信号时，将所述写指示信号通过所述同步逻辑电路发送给所述地址比较逻辑电路；
    当所述地址比较逻辑电路在所述读时钟信号的上升沿检测到所述写指示信号由所述第一逻辑电平跳变为所述第二逻辑电平且接收到所述第一时延和所述第二读写地址差时，基于所述指定写地址、所述第一时延、所述第二读写地址差和指定读写地址差，对所述读地址产生电路当前产生的读地址进行重置。
  18. 如权利要求16或17所述的方法，其特征在于，所述地址比较逻辑电路基于所述指定写地址、所述第一时延、所述第二读写地址差和指定读写地址差，对所述读地址产生电路当前产生的读地址进行重置，包括：
    当所述第一时延小于或等于信号稳定时间且所述第二读写地址差加1所得的地址差不等于所述指定读写地址差时，所述地址比较逻辑电路基于所述指定写地址和所述同步逻辑电路包括的触发器的个数，确定第一地址，并将所述读地址产生电路当前产生的读地址设置为所述第一地址；或者，
    当所述第一时延大于所述信号稳定时间且所述第二读写地址差不等于所述指定读写地址差时，所述地址比较逻辑电路基于所述指定写地址和所述同步逻辑电路包括的触发器的个数，确定第二地址，并将所述读地址产生电路当前产生的读地址设置为所述第二地址。
  19. 如权利要求8-18任一权利要求所述的方法，其特征在于，所述处理器基于所述小数时延，确定所述异步FIFO电路的时延，包括：
    所述处理器获取整数时延，所述整数时延为同一时刻对所述随机访问存储器进行写操作的写地址与进行读操作的读地址之间的地址差所引入的时延；
    所述处理器将所述小数时延和所述整数时延之和确定为所述异步FIFO电路的时延。
  20. 如权利要求8-19任一权利要求所述的方法，其特征在于，所述方法还包括：
    当所述处理器接收到复位设置指令时，将写地址上电复位值设置为第三地址，将读地址上电复位值设置为第四地址，所述第三地址与所述第四地址的地址差为指定读写地址差，所述写地址上电复位值为上电时所述写地址产生电路产生的初始写地址，所述读地址上电复位值为上电时所述读地址产生电路产生的初始读地址。
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