WO2017190425A1 - Circuit de zone de sortie de ventilateur côté électrode de grille - Google Patents

Circuit de zone de sortie de ventilateur côté électrode de grille Download PDF

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Publication number
WO2017190425A1
WO2017190425A1 PCT/CN2016/089741 CN2016089741W WO2017190425A1 WO 2017190425 A1 WO2017190425 A1 WO 2017190425A1 CN 2016089741 W CN2016089741 W CN 2016089741W WO 2017190425 A1 WO2017190425 A1 WO 2017190425A1
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WO
WIPO (PCT)
Prior art keywords
gate
circuit
chip
side fan
source
Prior art date
Application number
PCT/CN2016/089741
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English (en)
Chinese (zh)
Inventor
黄笑宇
Original Assignee
深圳市华星光电技术有限公司
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Publication of WO2017190425A1 publication Critical patent/WO2017190425A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention generally relates to the field of liquid crystal panel display, and more particularly to a gate side fan-out area circuit.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD uses an active component such as a thin film transistor (TFT) to control the turning on and off of each pixel unit, and controls the transmittance of the liquid crystal material according to the image signal to display an image.
  • the liquid crystal display is provided with a display panel including a pixel array and a driving circuit for driving the liquid crystal display panel.
  • the display panel is provided with a plurality of parallel data lines and scan lines. The data lines and the scan lines are vertically interlaced with each other, and a pixel unit and a thin film transistor switch for controlling the pixel unit are disposed at the interlaced portion.
  • the driving circuit includes a source driver and a gate driver, the source driver provides a signal related to the display image, and the gate driver provides a signal for the scan line to turn on or off the thin film transistor.
  • FIG. 1 it is a schematic diagram of a TFT-LCD driving structure in the prior art.
  • the main driving principle of the existing TFT-LCD includes: the system motherboard passes the R/G/B signal, the control signal and the power through the wire and the PCB board 1 The connectors are connected, and the PCB board passes through S-COF (Source-Chip on Film) chip 2 and G-COF (Gate-Chip on Film) chip 3 The display area 4 is connected so that the LCD obtains the required power and signals.
  • S-COF Source-Chip on Film
  • G-COF Gate-Chip on Film
  • a fan out area 5 is a portion where the signal line of the display area 4 is connected to the driving chip, and the gate signal line and the source data line are connected to the S-COF chip 2 and G via the fan-out area 5.
  • the COF chip 3, the fan-out region 5 on the side of the gate drive chip G-COF chip 3, may be referred to as a gate side fan-out region.
  • the object of the present invention is to provide a gate side fan-out area circuit to solve the defects of the current PCB management cost and manufacturing cost, and can not meet the current requirements of reducing management costs and manufacturing costs.
  • An exemplary embodiment of the present invention provides a gate side fan-out area circuit including a gate chip group and a circuit module group, the gate chip group including N gate chips, wherein N is greater than or equal to a positive integer; the circuit module group generates and outputs a corresponding output signal according to an input signal provided by the N gate chips.
  • the timing controller of the display device detects an output signal generated from the circuit module group and controls a display mode of the display device based on the detected output signal.
  • the circuit module group includes N parallel circuit modules, each circuit module generates and outputs a corresponding output signal according to an input signal provided by a corresponding gate chip, wherein the N gate chips and the The N parallel circuit modules are in one-to-one correspondence.
  • each circuit module outputs the generated output signal to a corresponding source chip in the source chipset of the source side fan-out area, wherein the source chip set includes N source chips, the N The source chips are in one-to-one correspondence with the N parallel circuit modules.
  • the timing controller of the display device detects an output signal received by the source chip from the circuit module, and controls a display mode of the display device based on the detected output signal.
  • each of the N circuit modules is a switch, wherein each switch is turned on or off in response to an input signal provided by a corresponding gate chip.
  • the switch is an NMOS transistor.
  • the display device has N display modes.
  • each of the N gate chips is a gate chip on a thin film.
  • each of the N source chips is a thin film upper source chip.
  • the gate side fan-out area circuit provided by the exemplary embodiment of the present invention, not only the display mode of the display device can be automatically adjusted, but also the management cost and the manufacturing cost of the PCB are effectively reduced.
  • FIG. 1 is a schematic view showing the structure of a thin film transistor liquid crystal display in the prior art
  • FIG. 2 is a schematic structural view of a prior art heteromorphic thin film transistor liquid crystal display
  • FIG. 3 is a schematic structural view of another prior art heteromorphic thin film transistor liquid crystal display
  • FIG. 4 illustrates a block diagram of a gate side fanout area circuit in accordance with an exemplary embodiment of the present invention
  • FIG. 5 illustrates an example of a gate side fan-out region circuit in accordance with an exemplary embodiment of the present invention
  • FIG. 6 illustrates a schematic diagram of signals detected by a timing controller in one cycle, according to an exemplary embodiment of the present invention
  • FIG. 7 illustrates another example of a gate side fan-out region circuit according to an exemplary embodiment of the present invention.
  • FIG. 8 illustrates an example of a gate side fan-out region circuit in accordance with another exemplary embodiment of the present invention
  • FIG. 9 illustrates an example of a gate side fan-out region circuit in accordance with another exemplary embodiment of the present invention.
  • FIG. 4 illustrates a block diagram of a gate side fan-out region circuit in accordance with an exemplary embodiment of the present invention.
  • a gate side fan-out area circuit includes a gate chip group 10 and a circuit module group 20, wherein the gate chip group 10 includes N gate chips, wherein , N is a positive integer greater than or equal to 2.
  • the gate chip group 10 includes N gate chips, wherein , N is a positive integer greater than or equal to 2.
  • each of the N gate chips is a thin film on-film chip.
  • the circuit module group 20 generates and outputs a corresponding output signal according to an input signal provided by the N gate chips. The output signal can be used to control the display mode of the display device.
  • the timing controller disposed on the PCB of the display device can detect the slave circuit module group. 20 generating an output signal and controlling a display mode of the display device based on the detected output signal.
  • FIG. 5 illustrates an example of a gate side fan-out region circuit in accordance with an exemplary embodiment of the present invention.
  • the gate chip group 10 included in the gate side fan-out area circuit includes three gate chips (such as G-COF1 - G-COF3 in FIG. 5), and the circuit module group 20 may include A wire A and a resistor R, wherein the wire A is a trace of the gate side fan-out area, and one end of the wire A passes through the source chip of the source side fan-out area (for example, a thin film on the source chip) and timing The controllers are connected, the other end of the wire A is grounded via a resistor R, and the output pins a, b and c of the gate chip G-COF1 - G-COF3 are respectively connected to the wire A.
  • the gate chip group 10 may include not only three gate chips but also more or less, but at least two.
  • the output pins a, b, and c of the G-COF1 - G-COF3 simultaneously output the vertical scanning signal and the gate chip G-COF1 -
  • the output of the G-COF3 is turned on to the display area, where the vertical scan signal is the same as the turn-on signal of the display area.
  • the circuit module group 20 can generate and output a corresponding output signal according to a signal provided by the gate chip G-COF1 - G-COF3, and the timing controller T-CON can be based on an output signal generated from the circuit module group 20 received via the source chip. To control the display mode of the display device.
  • the signal output from the wire A to the timing controller in one scanning period is as shown in (a) of FIG. 6, that is, three in one scanning period.
  • the square wave output (for example, three 33V square waves), at this time, the timing controller sets the display mode of the display device to the normal display mode based on the detected three square wave signals.
  • the signal output from the wire A to the timing controller in one scanning period is as shown in (b) of FIG. 6, and the wire A is in one scanning cycle.
  • There are two square wave outputs for example, two 33V square waves).
  • the timing controller T-CON sets the display mode of the display device to the vertical resolution based on the detected two square wave signals. Reduce to the original one-third of the alien display mode.
  • the signal output from the wire A to the timing controller in one scanning period is as shown in (c) of FIG. 6, and the wire A is in one scanning cycle.
  • a square wave output for example, a 33V square wave.
  • the timing controller T-CON sets the display mode of the display device to the vertical resolution based on the detected square wave signal. Two-thirds of the alien display mode.
  • the timing controller can set different display modes accordingly based on the detected number of high-voltage square wave signals, so that the architectures of the plurality of display devices can share the same PCB, thereby improving the PCB.
  • the commonality reduces management costs.
  • FIG. 7 illustrates an example of a gate side fan-out region circuit in accordance with another exemplary embodiment of the present invention.
  • the gate chip group 10 included in the gate side fan-out area circuit includes three gate chips (such as G-COF1 - G-COF3 in FIG. 7), and the circuit module group 20 may include Two wires A and B and two resistors R1 and R2 of the same resistance, wherein wires A and B are traces of the fan-side fan-out region, and one ends of wires A and B pass through the source-side fan-out region
  • the source chip is connected to the timing controller on the PCB board (not shown in FIG. 7), the other end of the wire A is connected to the output pin b of the gate chip G-COF2, and the output of the gate chip G-COF1 is cited.
  • the pin a is connected in series with the resistor R1 to the wire A, and the other end of the wire B is grounded via the resistor R2.
  • the gate chip group 10 according to the present example may include not only three gate chips but also more or less, but at least two.
  • the circuit module group 20 can generate and output a corresponding output signal according to a signal provided by the gate chip G-COF1 - G-COF3, and the timing controller T-CON can be based on the slave circuit module group 20 received via the source chip.
  • the resulting output signal controls the display mode of the display device.
  • the timing controller when the architecture of the thin film transistor liquid crystal display is as shown in FIG. 1, when the output signal generated by the timing controller via the source chip is a low level signal and a high level signal, the timing controller is based on The detected low level signal and high level signal will display the display mode of the device Set to normal display mode.
  • the timing controller when the architecture of the thin film transistor liquid crystal display is as shown in FIG. 2, when the output signal generated by the timing controller via the source chip from the circuit module 20 is two low level signals, the timing controller is based on The two low-level signals detected set the display mode of the display device to a profile display mode in which the vertical resolution is reduced to one-third of the original.
  • the timing controller sets the display mode of the display device to a profile display mode in which the vertical resolution is reduced to two-thirds of the original based on the detected high level signal and low level signal.
  • the timing controller can set different display modes accordingly based on the output signals generated by the detected circuit module group 20, so that the architectures of the plurality of display devices can share the same PCB. Improve PCB sharing and reduce management costs.
  • FIG. 8 illustrates an example of a gate side fan-out region circuit in accordance with another exemplary embodiment of the present invention.
  • the gate chip group 10 included in the gate side fan-out area circuit includes three gate chips (such as G-COF1 - G-COF3 in FIG. 8), and the circuit module group 20 may include Three wires A, B and C and resistors R1, R2 and R3 in series with wires A, B and C, respectively, wherein wires A, B and C are traces of the fan-side fan-out area, wires A, B and C One end of each of the wires is connected to the timing controller on the PCB (not shown in FIG. 8) through the source chip of the source side fan-out area, and the other ends of the wires A, B, and C are respectively connected in series with each of the wires.
  • the resistor is grounded.
  • the output pin a of the gate chip G-COF1 is connected to the wire A
  • the output pin b of the gate chip G-COF2 is connected to the wire B
  • the output pin c of the gate chip G-COF3 is connected to the wire C.
  • the gate chip group 10 according to the present example may include not only three gate chips but also more or less, but at least two.
  • the circuit module group 20 can generate and output a corresponding output signal according to an output signal provided by the gate chip G-COF1 - G-COF3, and the timing controller can be generated based on the slave circuit module group 20 received via the source chip.
  • the output signal is used to control the display mode of the display device.
  • the timing controller when the architecture of the thin film transistor liquid crystal display is as shown in FIG. 1 , when the output signal generated by the timing controller via the source chip from the circuit module 20 is three high level signals, the timing controller is based on detecting The three high level signals set the display mode of the display device to the normal display mode.
  • the output signals generated from the circuit module 20 received by the timing controller via the source chip are a high level signal, a high level signal, and a low level.
  • the timing controller sets the display mode of the display device to a profile display mode in which the vertical resolution is reduced to one-third of the original based on the detected high level signal, high level signal, and low level signal.
  • the timing controller when the architecture of the thin film transistor liquid crystal display is as shown in FIG. 3, when the timing controller generates an output signal from the circuit module group 20 via the source chip as three low level signals, the timing controller Setting the display mode of the display device to be vertical based on the detected three low level signals Straight resolution is reduced to the original two-thirds of the alien display mode.
  • the timing controller can set different display modes accordingly based on the output signals generated by the detected circuit module group 20, so that the architectures of the plurality of display devices can share the same PCB. Improve PCB sharing and reduce management costs.
  • the circuit module group includes N parallel circuit modules, each circuit module generates and outputs a corresponding output signal according to an input signal provided by a corresponding gate chip, wherein the N gates The chip has a one-to-one correspondence with the N parallel circuit modules.
  • each circuit module generates and outputs a corresponding output signal according to an input signal provided by a corresponding gate chip.
  • each of the gate chips in the gate chip set is a thin film on-film chip
  • each of the N circuit modules is a switch, wherein each switch is responsive to a corresponding gate
  • the input signal provided by the chip is turned on or off.
  • the output signal can be output to a source chipset for controlling a display mode of the display device.
  • the source chipset may include N source chips, where each of the N source chips may be a thin film source chip.
  • the N source chips are in one-to-one correspondence with the N parallel circuit modules, and each circuit module can output the generated output signals to corresponding source chips in the source chip group of the source side fan-out area.
  • the timing controller of the display device detects an output signal received by the source chip from the circuit module, and controls a display mode of the display device based on the detected output signal.
  • the display device may have N display modes.
  • the circuit module can generate and output a corresponding output signal according to the input signal, thereby causing the timing controller to set a display mode that matches the current display device architecture based on the output signal.
  • FIG. 9 illustrates an example of a gate side fan-out region circuit in accordance with an exemplary embodiment of the present invention.
  • each circuit module in the circuit module group may be a switch
  • each switch can be turned on or off in response to an input signal provided by its corresponding gate chip, for example, when the switch is an NMOS transistor, when the input signal is a high level signal, the NMOS transistor Turn on.
  • the circuit module group 20 includes three parallel circuit modules, and of course, more or less, but at least two or more. Those skilled in the art will appreciate that other circuit modules that can perform similar functions are also suitable for use in the present invention. Further, as an example, the three gate chips and three switches one-to-one corresponding to the three gate chips may be disposed in a gate-side fan-out region of the liquid crystal display device.
  • the gates a1-a3 of each of the switches are respectively connected to the output pins A1-A3 of the corresponding gate chip G-COF1_G-COF3, for example, the gate chip G-COF1
  • the A1 output pin is connected to the gate a1 of the switch M1 corresponding to the gate chip G-COF1
  • the gate chip G-COF2 The A2 output pin is connected to the gate a2 of the switch M2 corresponding to the gate chip G-COF2
  • the A3 output pin of the gate chip G-COF3 is connected to the gate a3 of the switch M3 corresponding to the gate chip G-COF3.
  • the sources b1-b3 of the switches M1-M3 are respectively connected to corresponding source chips in the source chipset of the source fan-out region, for example, the source b1 of the switch M1 is connected to the source chip S-COF1.
  • the input pin d1, the source b2 of the switch M1 is connected to the input pin d2 of the source chip S-COF2, and the source b3 of the switch M3 is connected to the input pin d3 of the source chip S-COF3.
  • the input pin k of the timing controller T-CON is connected to the output pins e1-e3 of the source chip S-COF1_S-COF3, respectively, and the drains c1-c3 of the switches M1-M3 are grounded.
  • the resistor R in FIG. 9 is an equivalent resistance when the NMOS is turned on.
  • the gate chip can send an input signal to the corresponding switch, the switch is turned on or off according to the input signal sent by the gate chip, and outputs the generated corresponding output signal to the source of the source side fan-out area.
  • the chip, the timing controller of the display device detects the output signal received by the source chip from the switch, and sets a display mode suitable for the current liquid crystal display device architecture based on the detected output signal.
  • FIG. 1 the architecture of a standard thin film transistor liquid crystal display in the prior art is shown in FIG. 1.
  • the gate chip G-COF1 passes through the output pin A1 to the gate of the switch M1.
  • the pole a1 sends a high level signal
  • the G-COF2 sends a high level signal to the gate a2 of the switch M2 through the output pin A2
  • the G-COF3 sends a high level signal to the gate a3 of the switch M3 through the output pin A3.
  • the output signals transmitted to the source chips S-COF1, S-COF2, and S-COF3 through the sources b1-b3 are a low level signal, a low level signal, and a low level signal.
  • the timing controller T-CON detects three low-level signals received from the switches M1, M2, and M3, and sets the display mode of the display device to the normal display mode based on the detected three signals.
  • the gate chip G-COF1 sends a high level signal to the gate a1 of the switch M1 through the output pin A1, and the G-COF2 passes through the output pin.
  • A2 sends a high level signal to the gate a2 of the switch M2, and the gate a3 of M3 does not receive the input signal, then the switches M1, M2 are turned on, and M3 is turned off, and then transmitted to the source chip S through the source b1-b3.
  • the output signals of COF1, S-COF2 and S-COF3 are low level signal, low level signal and high level signal.
  • the timing controller T-CON detects low voltage received from switches M1, M2 and M3.
  • the flat signal, the low level signal, and the high level signal, and based on the detected three signals, the display mode of the display device is set to a vertical display mode in which the vertical resolution is reduced to one-third of the original.
  • the gate chip G-COF1 transmits a high level signal, a gate a2 of M2 and M3 to the gate a1 of the switch M1 through the output pin A1. And a3 does not receive the input signal, then the switch M1 is turned on, and M2 and M3 are turned off, then the output signals transmitted to the source chips S-COF1, S-COF2 and S-COF3 through the sources b1-b3 are low-level signals. High level signal and high level signal.
  • the display mode is set to reduce the vertical resolution to the original two-thirds of the alien display mode.
  • the gate side fan-out area circuit can not only automatically adjust the display mode of the display device, but also effectively reduce the management cost and manufacturing cost of the PCB.

Abstract

L'invention concerne un circuit de zone de sortie de ventilateur côté électrode de grille, comprenant un groupe de puces d'électrode de grille (10) et un groupe de modules de circuit (20), le groupe de puces d'électrode de grille (10) comprenant N puces d'électrode de grille, N étant un nombre entier supérieur ou égal à 2. Le groupe de modules de circuit (20), sur la base d'un signal d'entrée fourni par les N puces d'électrode de grille, génère et émet un signal de sortie correspondant. L'interopérabilité d'une carte de circuit imprimé PCB peut être améliorée sur la base du circuit selon l'invention, ce qui réduit les coûts de gestion.
PCT/CN2016/089741 2016-05-05 2016-07-12 Circuit de zone de sortie de ventilateur côté électrode de grille WO2017190425A1 (fr)

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CN201610292187.6 2016-05-05

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CN106157917B (zh) * 2016-08-31 2019-02-12 深圳市华星光电技术有限公司 一种能够降低功耗的显示器驱动装置及其驱动方法
CN109581766A (zh) * 2018-12-21 2019-04-05 惠科股份有限公司 驱动电路、驱动方法及显示设备

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CN101540147A (zh) * 2008-03-20 2009-09-23 奇信电子股份有限公司 具有独立电压转换单元的液晶显示器驱动装置
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