WO2017185247A1 - Procédé et dispositif de test de puce - Google Patents

Procédé et dispositif de test de puce Download PDF

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Publication number
WO2017185247A1
WO2017185247A1 PCT/CN2016/080315 CN2016080315W WO2017185247A1 WO 2017185247 A1 WO2017185247 A1 WO 2017185247A1 CN 2016080315 W CN2016080315 W CN 2016080315W WO 2017185247 A1 WO2017185247 A1 WO 2017185247A1
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WIPO (PCT)
Prior art keywords
signal
chip
electrical signal
test
excitation
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PCT/CN2016/080315
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English (en)
Chinese (zh)
Inventor
杨炼
覃伟和
宋海宏
管洲
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2016/080315 priority Critical patent/WO2017185247A1/fr
Priority to CN201680000577.XA priority patent/CN105934681A/zh
Publication of WO2017185247A1 publication Critical patent/WO2017185247A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • Embodiments of the present invention relate to a chip testing technique, and in particular, to a chip testing method and apparatus.
  • Fingerprints are unique features of the human body and their complexity is sufficient to provide sufficient features for authentication. Therefore, fingerprint recognition technology is applied to security, smart phones, attendance, access control, secure payment and other fields. Among them, fingerprint recognition chip is the core device in fingerprint recognition technology, which realizes fingerprint image acquisition, feature extraction, feature comparison, etc. . The fingerprint identification chip needs to be strictly tested before it leaves the factory to ensure that the chip that reaches the client can be used normally.
  • the fingerprint identification chip is usually shipped in the form of a substrate, as shown in FIG. 12, which is a schematic structural view of the chip disposed on the substrate in the prior art; m*n chip, first behavior D(0,0)...D(0,n-1),...mth behavior D(m-1,0)...D(m-1,n-1 ), where n ⁇ an integer.
  • m*n chip first behavior D(0,0)...D(0,n-1),...mth behavior D(m-1,0)...D(m-1,n-1 ), where n ⁇ an integer.
  • Each chip on the substrate needs to be tested during chip testing.
  • FIG. 13 it is a schematic diagram of testing a fingerprint identification chip in the prior art; a pressing module is generally used to simulate finger pressing, and the pressing module generally has good electrical conductivity and softness, such as conductive adhesive.
  • the pressing module can be disposed on the chip, and then the chip is placed on the socket of the carrier board, or the chip is first set on the carrier board, and then the pressing module is disposed on the chip. Since there are usually multiple test sockets on the carrier board, each test socket can correspond to a design under test (DUT), so that multiple chips can be measured at a time.
  • the pins in each socket correspond to the pins of each chip under test and are connected to an Automatic Test Equipment (ATE).
  • ATE Automatic Test Equipment
  • the pressing module When the pressing module is pressed on the chip to be tested, the pressing module forms a capacitance C with the sensing area on the chip under test; when testing, the ATE controls the TX pin of the tested chip to output an AC excitation signal to the pressing module. Since the capacitor is "on AC, DC-blocking", the AC excitation signal is coupled into the chip under test. The part is processed by the internal circuit of the tested chip, integrated, etc. Finally, the analog-to-digital converter (ADC) converts the analog signal into a digital signal and then transmits it to the ATE through a specific interface. The data is analyzed and finally determines whether the chip under test is good or bad.
  • ADC analog-to-digital converter
  • the existing test technology has the following defects: when the pressing module directly connects the excitation signal, the wire is taken out from the corresponding excitation signal TX pin on the carrier socket, so that the excitation electric signal TX can be connected to the pressing module, and the realization cost of the system Higher.
  • the excitation signal is susceptible to external interference.
  • an embodiment of the present invention provides a chip testing apparatus, including: a pressing module, a voltage control module, and a test host; and the pressing module is configured to simulate a gesture of the chip under test.
  • the electrical connection has a constant electrical signal;
  • the test host controls the measured chip to output a dynamically changing excitation electrical signal;
  • the voltage control module is configured to dynamically change according to the excitation electrical signal and the normal operation of the tested chip a rated electrical signal, dynamically adjusting a test electrical signal of the tested chip to obtain an equivalent fluctuation state of the excitation electrical signal, wherein the test host is in accordance with an equivalent fluctuation state of the excited electrical signal of the tested chip
  • the data obtained from the work is determined by the test results.
  • the number of the pressing modules is one, the pressing module is electrically connected to a constant electrical signal; the number of the voltage control modules is plural, and the pressing module corresponds to a plurality of Each of the tested chips has a one-to-one correspondence with the tested chip.
  • the number of the pressing modules is plural, and the plurality of pressing modules are all provided with the same constant electrical signal, and the number of the voltage control modules is plural,
  • the pressing module has a one-to-one correspondence with the tested chip, and the tested chip has a one-to-one correspondence with the voltage control module.
  • the chip under test has a first signal end and a second signal end
  • the voltage control module operates according to the dynamic change of the excitation electrical signal and the tested chip works normally.
  • the rated electrical signal dynamically adjusts the test electrical signals of the first signal end and the second signal end.
  • the first signal end of the tested chip is electrically connected to the digital high level signal
  • the second signal end of the tested chip is electrically connected to the digital low level signal.
  • the test electrical signal includes the digital high level signal and the digital low level signal.
  • a voltage difference between the digital high level signal and the digital low level signal is equal to a rated voltage value of the normal operation of the tested chip, and the rated electrical signal The rated voltage value is included.
  • the digital high level signal is a digital power signal
  • the digital low level signal is a digital ground signal
  • the testing device further includes a socket module, and the tested chip is mounted on the socket module for testing.
  • the testing device further comprises a carrier module, the socket module is disposed on the carrier module; and/or the voltage control module It is disposed on the carrier module.
  • an embodiment of the present invention provides a chip testing method, including:
  • the data obtained by operating the test chip under the equivalent fluctuation state of the excitation electric signal is transmitted to determine the test result.
  • the pressing module corresponds to a plurality of tested chips
  • the dynamic adjustment of the test electrical signal of the tested chip according to the dynamic change of the excitation electrical signal of the tested chip and the rated electrical signal of the tested chip includes: dynamic change according to the excitation electrical signal of each tested chip and each The rated electrical signals of the tested chips work normally, and dynamically adjust the test electrical signals of each tested chip.
  • the plurality of pressing modules are all connected with the same constant electrical signal
  • the obtaining an equivalent fluctuation state of the excitation electrical signal includes: obtaining each of the pressing modules Describe the equivalent fluctuation state of the excitation electrical signal;
  • the dynamic adjustment of the test electrical signal of the tested chip according to the dynamic change of the excitation electrical signal of the tested chip and the rated electrical signal of the tested chip includes: dynamic change according to the excitation electrical signal of each tested chip and each The rated electrical signals of the tested chips work normally, and dynamically adjust the test electrical signals of each tested chip.
  • the dynamic change of the excitation electrical signal according to the tested chip and the normal operation of the tested chip comprises: dynamically adjusting the first signal end according to a dynamic change of the excitation electrical signal of the tested chip and a rated electrical signal of the normal operation of the tested chip The test signal of the second signal end.
  • dynamically adjusting the test electrical signals of the first signal end and the second signal end according to the dynamic change of the excitation electrical signal of the tested chip comprises: according to the tested chip
  • the dynamic change of the excitation electrical signal dynamically adjusts the digital high level signal of the first signal end and the digital low level signal of the second signal end.
  • a voltage difference between the digital high level signal and the digital low level signal is equal to a rated voltage value of the normal operation of the tested chip, and the rated electrical signal The rated voltage value is included.
  • the digital high level signal is a digital power signal
  • the digital low level signal is a digital ground signal
  • the voltage control module dynamically adjusts the dynamic signal according to the dynamic change of the excitation electrical signal and the rated electrical signal of the tested chip to work normally.
  • the test electrical signal of the tested chip obtains the equivalent fluctuation state of the excitation electrical signal with reference to the adjusted test electrical signal.
  • the pressing module since the pressing module directly connects the constant electrical signal, such as a common reference ground, No incentive The signal TX pin leads the wire, saving system cost. In addition, since the pressing module directly shares the reference ground, its signal is relatively stable and is not interfered by external signals.
  • the constant electrical signal such as a common reference ground
  • FIG. 1 is a schematic structural diagram of a chip testing device according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing the circuit structure of the testing device in the embodiment of FIG. 1;
  • FIG. 3 is a schematic diagram showing changes of an excitation signal and a test electrical signal in the embodiment of FIG. 1;
  • FIG. 4 is a schematic diagram showing changes in signals on a pressing module and a chip under test in the embodiment of FIG. 1;
  • FIG. 5 is a schematic diagram showing changes in signals on a pressing module and a chip under test in the prior art
  • FIG. 6 is a schematic structural diagram of a chip testing device according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic structural diagram of a three-chip test apparatus according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a four-chip test apparatus according to an embodiment of the present invention.
  • FIG. 9 is a schematic flowchart of a five-chip test method according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a six-chip test method according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a seven-chip test method according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural view of a chip disposed on a substrate in the prior art
  • FIG. 13 is a schematic diagram of testing a fingerprint recognition chip in the prior art.
  • FIG. 1 is a schematic structural diagram of a chip testing device according to an embodiment of the present invention; as shown in FIG. 1 , in this embodiment, a chip test is taken as an example for description.
  • the testing device includes: a pressing module 101, a voltage control module 103, and an automatic test host 104; the pressing module 101 is used to simulate a gesture operation on the test under test 102 (DUT).
  • the electrical connection has a constant electrical signal; the automatic test host 104 controls the output of the test chip 102 to dynamically change the excitation power
  • the signal control module 103 is configured to dynamically adjust the test electrical signal of the tested chip 102 according to the dynamic change of the excitation electrical signal and the rated electrical signal of the tested chip 102 to obtain the equivalent fluctuation state of the excitation electrical signal, automatically
  • the test host 104 Automatic Test Equipment, ATE for short determines the test result based on the equivalent fluctuation state of the data excitation electric signal obtained by the test chip operating under the equivalent fluctuation state of the excitation electric signal.
  • the pressing module 101 is directly electrically connected to the common reference ground GND.
  • the pressing module 101 can be actually connected to other constant electrical signals, and is not particularly limited to the common reference ground GND.
  • the automatic test host 104 is connected to the chip under test 102 through SPI or I2C to control the equivalent fluctuation state of the excitation signal output by the test chip 102.
  • the pressing module 101 can be made using an electric conductor.
  • a capacitor is formed between the pressing module 101 and the fingerprint identification chip.
  • the capacitance changes, thereby affecting the output of the fingerprint identification chip for chip testing.
  • the pressing module 101 can form a capacitor with the chip under test 102, that is, the effective detecting areas of the pressing module 101 and the tested chip 102 respectively correspond to the two plates of the capacitor, and the AC is exchanged according to the capacitance.
  • the principle of DC blocking is to add an equivalent AC excitation signal to the conductor, and the excitation signal can be transmitted to the effective detection area of the chip under test 102, also called the sensor area.
  • the pressing module 101 may be made of non-conductive.
  • the pressing module 101 may be composed of an array of wires.
  • the pressing module 101 can be directly attached to the back surface of the chip under test 102.
  • the tested chip 102 has an excitation electrical signal TX output end, a first signal end, and a second signal end, and the voltage control module 103 dynamically changes according to the dynamic change of the excitation electrical signal and the rated electrical signal of the tested chip.
  • the test electrical signals of the first signal end and the second signal end are adjusted.
  • the first signal end of the tested chip 102 is electrically connected to the digital high level signal
  • the second signal end of the tested chip 102 is electrically connected to the digital low level signal
  • the test electrical signal includes a digital high level signal and a digital signal. Low level signal.
  • the voltage difference between the digital high level signal and the digital low level signal is equal to the rated voltage value of the normal operation of the tested chip 102, and the rated electrical signal includes the rated voltage value.
  • the normal working voltage of a chip is 5V, then the second signal terminal can be connected to the 3V level, and the first signal terminal can be connected to the 8V level.
  • the digital high level signal is the digital power signal SVCC of the chip under test 102
  • the digital low level signal is the digital ground signal SGND of the chip under test 102.
  • the corresponding pin TX, SVCC, and SGND 105 are further provided corresponding to the excitation electric signal TX, the first signal end SVCC signal, and the second signal end SGND signal.
  • the excitation electrical signal may be a square wave.
  • the excitation electrical signal can also be a sine wave, a triangular wave, etc., and the frequency can be flexibly set according to test requirements.
  • FIG. 2 is a schematic diagram showing the circuit structure of the test device in the embodiment of FIG. 1.
  • the voltage control module 103 is electrically connected to a common ground
  • the automatic test host 104 is electrically connected to the tested chip 102 through the SPI bus to control the chip under test.
  • 102 outputs a dynamically changing excitation electrical signal, and receives data from the tested chip 102 for test result determination;
  • the tested chip is connected to the voltage control module 103 through the first signal terminal SVCC, the second signal terminal SGND, and the excitation signal output terminal TX.
  • the excitation electrical signal is transmitted to the voltage control module 103, and the voltage control module 103 adjusts the level change of the first signal terminal SVCC and the second signal terminal SGND according to the adjustment of the excitation electrical signal, so that the first signal terminal SVCC and the second signal
  • the voltage difference at the terminal SGND is equal to or close to the voltage value at which the chip under test 102 operates normally.
  • FIG. 3 is a schematic diagram showing changes of an excitation signal and a test electrical signal in the embodiment of FIG. 1.
  • the first signal terminal SVCC and the second of the tested chip 102 are The difference in level amplitude of the signal terminal SGND is a.
  • the level amplitude of the first signal terminal SVCC periodically changes between a-2a
  • the level amplitude of the second signal terminal SGND is between 0-a. Change, its level amplitude difference is actually still a.
  • the level amplitude of the excitation electrical signal TX periodically changes from 0-2a. When the excitation electrical signal TX is at a low level, its output logic is 0, the excitation electrical signal TX is at a high level, and its output logic is 1. The following is described in detail in conjunction with FIG. 3;
  • the level of the TX initially coincides with the level of the second signal terminal SGND, that is, when the excitation electrical signal TX outputs a logic 1, the level of the TX remains with the first signal terminal SVCC. Consistent. The specific process is: in the initial state S0, TX output logic 0, SGND level is 0, SVCC is a; enter S1, TX output logic 1, when the level of TX changes from 0 to a instant, the voltage control module 103 quickly puts SGNG is pulled up to a.
  • the TX signal Also instantaneously changes from a to 2a; enters S3, TX outputs logic 0, when the TX level changes from 2a to a, the voltage control module 103 quickly pulls SGND from a to 0, because SVCC and SGND need to maintain the voltage difference Is a, so SVCC pulls back from 2a to a, and the TX level needs to be consistent with SGND, so the TX signal also instantaneously changes from a to 0.
  • the second signal terminal SGND changes in accordance with the TX change.
  • FIG. 4 is a schematic diagram showing changes in signals on the pressing module 101 and the chip under test 102 in the embodiment of FIG. 1.
  • the signals on the sensor area of the pressing module 101 and the chip under test 102 are common to the electrical conductor and the system.
  • the ground GND is connected and remains constant, and the second signal terminal SGND of the tested chip 102 can fluctuate with the excitation telecommunication TX signal. Therefore, at the signal processing level, the second signal terminal SGND can be used as a reference, between GND and SGND.
  • the signal fluctuation is equivalent to the common ground GND of the conductor follows the TX signal fluctuation, that is, the equivalent fluctuation state of the TX signal is obtained, and the signal on the conductor is transmitted through the capacitor to the sensor region for a phase delay of 90 degrees.
  • FIG. 5 is a schematic diagram of changes in signals on the pressing module 101 and the chip under test 102 in the prior art; in the prior art, after the excitation signal is output by the tested chip 102, the signals on the conductor and the sensor area are as shown in FIG. 5 . Since the pressing module 101 directly connects the excitation electrical signal TX of the device under test 102, the signal on the electrical conductor is the excitation signal of the TX output, and the excitation signal flows through the capacitor to the sensor region of the device under test 102 with a phase delay of 90 degrees. . In the prior art, since the pressing module 101 directly receives the excitation electrical signal, the electrical signal changes in real time, and in the embodiment of the present invention, the pressing module 101 directly receives the substantially constant common ground signal GND.
  • the signal is substantially constant, except that during signal processing, by using the signal of the second signal terminal SGND as a reference, since the signal of the second signal terminal SGND adjusts the floating variation according to the excitation electrical signal TX, the equivalent
  • the signal of the analog pressing module 101 changes dynamically. Moreover, the signal of the second signal terminal SGND does not directly affect the common ground signal GND.
  • the pressing module 101 directly connects the excitation signal, the wire is taken out from the corresponding excitation signal TX pin on the carrier socket to connect the excitation electrical signal TX to the pressing module.
  • the excitation signal TX pin is not required to lead the wire, thereby saving the cost of the system.
  • the pressing module 101 directly shares the reference ground, its signal is relatively stable and is not interfered by external signals.
  • FIG. 6 is a schematic structural diagram of a chip testing device according to an embodiment of the present invention. As shown in FIG. 6 , in this embodiment, the number of pressing modules 101 is one, which can cover all the tested chips 102, and the pressing module 101 corresponds to multiple
  • the test chip 102 has a plurality of voltage control modules 103, and the voltage control module 103 has a one-to-one correspondence with the test chip 102.
  • One voltage control module 103 corresponds to one test chip 102.
  • the pressing module 101 has a one-to-many relationship with the chip under test 102 and the voltage control module 103, respectively. Therefore, for all of the chips 102 under test, the pressing modules 101 are the same and have a constant electrical signal.
  • a plurality of devices under test 102 are arranged on a substrate, such as m*n chips on the substrate, and the first row D(0, 0)...D (0, n-1), ..., the mth line D(m-1, 0)...D(m-1, m-1), where n ⁇ 1 is an integer.
  • each chip has a set of SPI interfaces, and the SPI interface of each chip is connected to the automatic test host 104, which is equivalent to the automatic test host 104 can communicate with each chip independently.
  • the host is automatically tested.
  • 104 can simultaneously control the output excitation signal of the plurality of tested chips, and at the same time, since each chip is separately provided with a voltage control module 103, the signal for the first signal terminal SVCC and the signal of the second signal terminal SGND are separately used. Control is performed so that testing of all chips on the substrate 106 can be achieved.
  • the pressing module is electrically connected to the common reference ground GND, it is substantially constant for all the chips to be tested, and therefore, the pressing modules can be completely shared.
  • the pressing module is directly connected to the excitation electric signal, the timing and amplitude of the excitation signal TX output excitation signal of each chip may be different, in order to avoid interference of the excitation signals between different chips.
  • the pressing module attached to the chip under test must be independent.
  • the pressing module needs to be replaced, it can be replaced by a new pressing module, and if it is a plurality of pressing modules, it is necessary to perform troubleshooting on the pressing modules one by one and replace them one by one.
  • the operation is cumbersome.
  • FIG. 7 is a schematic structural diagram of a three-chip test apparatus according to an embodiment of the present invention. As shown in FIG. 7 , in the embodiment, the number of the pressing modules 101 is multiple, and the plurality of pressing modules 101 are all provided with the same constant electrical signal, and the voltage control is performed.
  • the number of modules 103 is plural, and the pressing module 101 and the chip under test 102 are Correspondingly, the tested chip 102 has a one-to-one correspondence with the voltage control module 103.
  • one pressing module 101 corresponds to one tested chip 102
  • one tested chip 102 corresponds to one voltage control module 103.
  • the constant signal electrically connected to each of the pressing modules 101 is the same, such as the common reference ground GND, the technique is functionally equivalent to the setting of one pressing module 101 in FIG. 2 described above.
  • the pressing module when each pressing module is connected to the common reference ground GND, the pressing module may be grouped in a certain row or a column, and the group of pressing modules share the same common reference ground GND.
  • FIG. 8 is a schematic structural diagram of a four-chip test apparatus according to an embodiment of the present invention. As shown in FIG. 8, in the embodiment, based on the foregoing embodiment of FIG. 1, the test apparatus further includes a socket module 107, and the tested chip 102 is installed in the socket module. 107 for testing.
  • the testing device further includes a carrier module 108, the socket module is disposed on the carrier module, and the voltage control module 103 is disposed on the carrier module 108.
  • socket module and/or the carrier module may be added to the embodiment of FIG. 6 or FIG. 7 described above, and the detailed description of the drawings is omitted.
  • FIG. 9 is a schematic flowchart of a five-chip test method according to an embodiment of the present invention. As shown in FIG. 9, corresponding to the test device of the embodiment of FIG. 1, the embodiment of the present invention uses one test chip, one voltage control module, and one press.
  • the module implementation is described as an example, which includes:
  • the voltage control module dynamically adjusts the test electrical signal of the tested chip according to the dynamic change of the excitation electrical signal of the tested chip and the rated electrical signal of the normal operation of the tested chip;
  • the voltage control module transmits the excitation wave signal, the test electrical signal, and the equivalent fluctuation state of the excitation electrical signal to the test host;
  • the test host determines the test result according to data obtained by operating the tested chip under the equivalent fluctuation state of the excitation electrical signal, including an excitation wave signal, a test electrical signal, and an equivalent fluctuation state of the excitation electrical signal.
  • the chip under test when the chip under test has the first signal end and the second signal end, dynamically adjusting according to the dynamic change of the excitation electrical signal of the tested chip and the rated electrical signal of the normal operation of the tested chip.
  • the test electrical signal of the tested chip includes: excitation telecommunications according to the tested chip
  • the dynamic change of the number and the rated electrical signal of the normal operation of the tested chip dynamically adjust the test electrical signals of the first signal end and the second signal end.
  • dynamically adjusting the test electrical signals of the first signal end and the second signal end according to the dynamic change of the excitation electrical signal of the tested chip comprises: according to the excitation electrical signal of the tested chip Dynamically changing, dynamically adjusting the digital high level signal of the first signal end and the digital low level signal of the second signal end.
  • the voltage difference between the digital high level signal and the digital low level signal is equal to the rated voltage value of the normal operation of the tested chip, and the rated electrical signal includes the rated voltage value.
  • the digital high level signal is a digital power signal
  • the digital low level signal is a digital ground signal
  • dynamically adjusting the test electrical signal of the tested chip according to the dynamic change of the excitation electrical signal of the tested chip and the rated electrical signal of the tested chip including: according to the excitation electrical signal
  • the dynamic changes and the rated electrical signals of the tested chip are dynamically adjusted to dynamically adjust the digital power signal and the digital ground signal.
  • FIG. 10 is a schematic structural diagram of a six-chip test method according to an embodiment of the present invention; in this embodiment, a test device corresponding to the foregoing embodiment of FIG. 6 has a press module covering a plurality of tested chips, a plurality of tested chips, and a plurality of test modules.
  • a voltage control module is taken as an example for description.
  • a voltage control module corresponds to a chip under test. Specifically, it includes:
  • Each voltage control module dynamically adjusts a test electrical signal of the tested chip according to the dynamic change of the excitation electrical signal and the rated electrical signal of the normal operation;
  • Each voltage control module transmits an equivalent fluctuation state of the excitation electric signal, the test electrical signal, and the excitation electric signal corresponding to the tested chip to the test host;
  • the data obtained by the test host operating under the equivalent fluctuation state of the excitation electrical signal includes at least an excitation wave signal, a test electrical signal, and an equivalent fluctuation state of the excitation electrical signal to determine each tested chip. Test results.
  • FIG. 11 is a schematic structural diagram of a method for testing a chip according to an embodiment of the present invention; in this embodiment, corresponding The testing device of the embodiment of FIG. 7 is described by taking a plurality of pressing modules, a plurality of voltage control modules, and a plurality of tested chips as an example.
  • One pressing module corresponds to one voltage control module
  • one voltage control module corresponds to one tested chip. Specifically, it may include:
  • Each voltage control module dynamically adjusts a test electrical signal of the tested chip according to the dynamic change of the excitation electrical signal and the rated electrical signal of the normal operation;
  • Each voltage control module transmits an equivalent fluctuation state of the excitation electric signal, the test electrical signal, and the excitation electric signal corresponding to the tested chip to the test host;
  • the data obtained by the test host operating under the equivalent fluctuation state of the excitation electrical signal includes at least an excitation wave signal, a test electrical signal, and an equivalent fluctuation state of the excitation electrical signal, and each of the tested is determined to be tested. Test results of the chip.
  • the apparatus provided by the embodiments of the present application can be implemented by a computer program.
  • Those skilled in the art should be able to understand that the foregoing unit and module division manners are only one of a plurality of division manners. If the division is other units or modules or does not divide the blocks, as long as the information object has the above functions, it should be in the present application. Within the scope of protection.
  • embodiments of the present application can be provided as a method, apparatus (device), or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the computer readable memory is stored in the computer readable memory.
  • the instructions in the production result include an article of manufacture of the instruction device that implements the functions specified in one or more blocks of the flowchart or in a flow or block of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

La présente invention concerne un procédé et un dispositif de test de puce. Le dispositif de test de puce comprend: un module de pressage (101), un module de commande de tension (103) et un hôte de test (104). Le module de pressage (101) est utilisé pour simuler une opération de mouvement sur une puce testée (102), et est connecté électriquement à un signal électrique constant; l'hôte de test (104) commande la puce testée (102) pour produire un signal électrique d'excitation qui change de manière dynamique; le module de commande de tension (103) est utilisé pour ajuster de manière dynamique un signal électrique de test de la puce testée (102) sur la base du changement dynamique du signal électrique d'excitation et d'un signal électrique nominal de la puce testée (102) pendant un fonctionnement normal, de façon à obtenir un état de fluctuation équivalent du signal électrique d'excitation; et l'hôte de test (104) détermine un résultat de test sur la base de l'état de fluctuation équivalent. Le module de pressage (101) est directement connecté à un signal électrique constant sans qu'il soit nécessaire d'utiliser un fil de sortie de broche TX de signal d'excitation, ce qui réduit les coûts du système. Le module de pressage (101) est directement connecté à une masse de référence commune, et possède donc un signal relativement stable et ne subit aucune interférence provenant de signaux externes.
PCT/CN2016/080315 2016-04-27 2016-04-27 Procédé et dispositif de test de puce WO2017185247A1 (fr)

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PCT/CN2016/080315 WO2017185247A1 (fr) 2016-04-27 2016-04-27 Procédé et dispositif de test de puce
CN201680000577.XA CN105934681A (zh) 2016-04-27 2016-04-27 芯片测试方法及装置

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CN111965526A (zh) * 2020-08-24 2020-11-20 深圳市华力宇电子科技有限公司 带假手指机构的指纹芯片测试装置
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CN113009318A (zh) * 2021-02-25 2021-06-22 合肥宏晶微电子科技股份有限公司 视频处理芯片的测试设备及测试方法
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CN115825702A (zh) * 2023-02-06 2023-03-21 镇江矽佳测试技术有限公司 一种指纹芯片抗干扰测试装置
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CN117310454B (zh) * 2023-11-30 2024-03-15 珠海市芯动力科技有限公司 芯片测试方法及相关装置

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