WO2017181469A1 - 在olb区绑定引脚的方法 - Google Patents

在olb区绑定引脚的方法 Download PDF

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Publication number
WO2017181469A1
WO2017181469A1 PCT/CN2016/082674 CN2016082674W WO2017181469A1 WO 2017181469 A1 WO2017181469 A1 WO 2017181469A1 CN 2016082674 W CN2016082674 W CN 2016082674W WO 2017181469 A1 WO2017181469 A1 WO 2017181469A1
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Prior art keywords
pins
pin
layer
olb
binding
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Ceased
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PCT/CN2016/082674
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English (en)
French (fr)
Inventor
叶岩溪
林永伦
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/109,124 priority Critical patent/US10032805B2/en
Publication of WO2017181469A1 publication Critical patent/WO2017181469A1/zh
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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for binding pins in an OLB area.
  • a liquid crystal display panel consists of a color filter substrate (CF), a thin film transistor substrate (TFT, Thin Film Transistor), a liquid crystal (LC) sandwiched between a color filter substrate and a thin film transistor substrate, and a sealant ( Sealant); its working principle is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the two glass substrates, and refract the light of the backlight module to produce a picture.
  • CF color filter substrate
  • TFT Thin Film Transistor
  • LC liquid crystal sandwiched between a color filter substrate and a thin film transistor substrate
  • Sealant Sealant
  • Twisted Nematic TN
  • STN Super Twisted Nematic
  • IPS plane conversion
  • VA Vertical Alignment
  • the LCD screen of the TV is limited by the size, and the display technology of the VA mode is generally used, and the IPS display mode is rarely used.
  • the substrate on which the thin film transistor has been formed needs to be covered with an organic film (PFA) as a planarization layer (Planarization, PLN) to change the flatness of the underlying film surface, prevent the electric field from interfering with each other, and flatten.
  • PFA organic film
  • PLN planarization layer
  • the layer is usually an optically active material.
  • Ordinary VA display mode, whether it is PVA, MVA, or HVA will not use the organic film to play a flattening role, but if it is a combination of VA display technology and other technologies, it is possible to use an organic film to achieve flatness.
  • the IPS display mode requires the use of an organic film to planarize.
  • a COF chip on film
  • OLB outer lead bonding
  • the OLB region includes a base substrate, a plurality of first pins 110 arranged side by side on the base substrate, and the base substrate and the plurality of first pins are formed on the substrate a gate insulating layer on 110, a plurality of second pins 120 formed on the gate insulating layer opposite to the plurality of first pins 110, formed on the gate insulating layer and a plurality of second a passivation layer on the pin 120 and a planarization layer 200 formed on the passivation layer; in the fabrication process, first, all the portions of the planarization layer 200 on the corresponding OLB region are dug out, in the planarization layer 200 Forming a blank area 210 thereon, and then as shown in FIG.
  • each connecting wire 130 connects the first pin 110 and the second pin 120 in the blank region 210, and then is used for It is connected to a metal pin on the COF so that the signal integrated into the IC on the COF is transmitted to the display through the OLB area.
  • the specific implementation step of patterning the ITO conductive layer is: coating a photoresist on the ITO conductive layer, exposing and developing the photoresist through a photomask to form a photoresist pattern, and then using the remaining photoresist For occlusion, the ITO conductive layer is etched, and the remaining photoresist is stripped to obtain a plurality of connecting wires 130.
  • the edge of the blank region 210 has a certain taper angle, so after the exposure process for patterning the ITO conductive layer, it will be at the taper angle of the blank region 210.
  • There is a certain photoresist residue which will eventually lead to ITO residue 131 in the corner of the taper. As shown in Figure 2, the ITO residue 131 will cause the metal traces to be connected together and short-circuited.
  • the object of the present invention is to provide a method for binding a pin in an OLB region, which improves the via design of the planarization layer in the OLB region, and avoids residual conductive material at the bottom of the via hole due to residual photoresist material, thereby causing The circuit is shorted and the display is poor.
  • the present invention provides a method of binding a pin in an OLB area, comprising the following steps:
  • Step 1 providing a TFT substrate, the TFT substrate includes a display area, and an OLB area;
  • the OLB region includes a base substrate, a plurality of first pins arranged side by side on the base substrate, a gate insulating layer formed on the base substrate and the plurality of first leads, and formed on the a plurality of second pins disposed on the gate insulating layer corresponding to the plurality of first pins, and a passivation layer formed on the gate insulating layer and the plurality of second pins;
  • Step 2 forming an organic film on the TFT substrate to obtain a planarization layer
  • Step 3 forming at least one first via hole corresponding to each of the first pins on the planarization layer, the passivation layer, and the gate insulating layer, corresponding to each of the planarization layer and the passivation layer Forming at least one second via hole above a second pin;
  • Step 4 forming a conductive layer on the planarization layer, and patterning the conductive layer to obtain a plurality of connecting wires corresponding to the plurality of first pins and the plurality of second pins, each connecting wire passing through The first via is connected to the corresponding first pin, and is connected to the corresponding second pin through the second via, thereby connecting the corresponding first pin and the second pin.
  • the organic film formed in the step 2 is a photoresist material.
  • the thickness of the organic film formed in the step 2 is 1.5 to 3.5 ⁇ m.
  • a first via hole is formed above each of the first pins, and a second via hole is formed above each of the second pins.
  • step 3 two first via holes are formed above each of the first pins, and two second via holes are formed above each of the second pins.
  • the materials of the gate insulating layer and the passivation layer are all silicon nitride.
  • the step 3 specifically includes the following implementation steps:
  • Step 31 Providing a photomask, the photomask includes a first pattern and a second pattern corresponding to the plurality of first vias and the plurality of second vias, respectively, wherein the planarization layer is exposed by using the photomask Developing, forming a plurality of organic film via holes on the planarization layer corresponding to the first pattern and the second pattern;
  • Step 32 etching the gate insulating layer and the passivation layer with the planarization layer as a shielding layer to obtain a first via hole and a second via hole.
  • the material of the conductive layer formed in the step 4 is ITO.
  • the step of patterning the conductive layer in the step 4 includes etching the conductive layer by a wet etching process.
  • the connecting wires are used to connect the flip chip.
  • the invention also provides a method for binding a pin in an OLB area, comprising the following steps:
  • Step 1 providing a TFT substrate, the TFT substrate includes a display area, and an OLB area;
  • the OLB region includes a base substrate, a plurality of first pins arranged side by side on the base substrate, a gate insulating layer formed on the base substrate and the plurality of first leads, and formed on the a plurality of second pins disposed on the gate insulating layer opposite to the plurality of first pins, and a passivation layer formed on the gate insulating layer and the plurality of second pins;
  • Step 2 forming an organic film on the TFT substrate to obtain a planarization layer
  • Step 3 forming at least one first via hole corresponding to each of the first pins on the planarization layer, the passivation layer, and the gate insulating layer, corresponding to each of the planarization layer and the passivation layer Forming at least one second via hole above a second pin;
  • Step 4 forming a conductive layer on the planarization layer, and patterning the conductive layer to obtain a plurality of connecting wires corresponding to the plurality of first pins and the plurality of second pins, each connecting wire passing through The first via is connected to the corresponding first pin, and is connected to the corresponding second pin through the second via, thereby connecting the corresponding first pin and the second pin;
  • the organic film formed in the step 2 is a photoresist material
  • the thickness of the organic film formed in the step 2 is 1.5-3.5 ⁇ m
  • the step 3 specifically includes the following implementation steps:
  • Step 31 Providing a photomask, the photomask includes a first pattern and a second pattern corresponding to the plurality of first vias and the plurality of second vias, respectively, wherein the planarization layer is exposed by using the photomask Display Forming a plurality of organic film via holes on the planarization layer corresponding to the first pattern and the second pattern;
  • Step 32 etching the gate insulating layer and the passivation layer with the planarization layer as a shielding layer to obtain a first via hole and a second via hole.
  • the method for binding a pin in an OLB region of the present invention has a separate opening for each pin on a flattening layer of the OLB region, and a subsequently formed connecting wire passes through a via and a lead above the pin.
  • the pins are connected, and the corresponding pins are connected together through the connecting wires. Since the connecting wires completely cover the through holes above the pins, there is no problem of residual conductive material in the via holes in the process of forming the connecting wires, as opposed to
  • the existing method of opening a large area on the planarization layer of the OLB region avoids short circuit and poor display caused by the conductive material remaining at the bottom of the via hole of the planarization layer.
  • FIG. 1 is a schematic diagram of a large-area opening corresponding to an OLB area on a planarization layer in a method for binding a pin in an OLB area;
  • FIG. 2 is a schematic view showing the formation of a connecting wire in the OLB area of FIG. 1;
  • FIG. 3 is a schematic flow chart of a method for binding a pin in an OLB area according to the present invention.
  • step 2 is a schematic diagram of step 2 of a method for binding a pin in an OLB area according to the present invention
  • step 3 is a schematic diagram of step 3 in a first embodiment of a method for binding a pin in an OLB area according to the present invention
  • FIG. 6 is a schematic diagram of step 3 in a second embodiment of a method for binding a pin in an OLB area according to the present invention.
  • step 4 is a schematic diagram of step 4 in a first embodiment of a method for binding a pin in an OLB area according to the present invention
  • Fig. 8 is a schematic cross-sectional view taken along line A-A' of Fig. 7.
  • the present invention provides a method for binding a pin in an OLB area, including the following steps:
  • Step 1 providing a TFT substrate, the TFT substrate includes a display area, and an OLB area;
  • the OLB region includes a base substrate 11 , a plurality of first pins 12 arranged side by side on the base substrate 11 , and the base substrate and the plurality of first pins are formed on the base substrate 11 .
  • a gate insulating layer 13 on 12 a plurality of second leads 14 formed on the gate insulating layer 13 opposite to the plurality of first leads 12, and a gate insulating layer 13 and A plurality of passivation layers 15 on the second pin 14.
  • the materials of the gate insulating layer 13 and the passivation layer 15 are all silicon nitride (SiNx).
  • Step 2 As shown in FIG. 4, an organic film is formed on the TFT substrate to obtain a planarization layer 16.
  • the organic film formed in the step 2 is a photoresist material and has a thickness of 1.5-3.5 ⁇ m, preferably 2.5 ⁇ m.
  • Step 3 as shown in FIG. 5, a first via 51 is formed on the planarization layer 16, the passivation layer 15, and the gate insulating layer 13 corresponding to each of the first leads 12, A second via 52 is formed on the planarization layer 16 and the passivation layer 15 corresponding to each of the second leads 14 .
  • the step 3 specifically includes the following implementation steps:
  • Step 31 Providing a photomask, the photomask includes a first pattern and a second pattern corresponding to the plurality of first vias 51 and the plurality of second vias 52, respectively, by using the mask to the planarization layer 16 Performing exposure and development to form a plurality of organic film via holes on the planarization layer 16 corresponding to the first pattern and the second pattern;
  • Step 32 The gate insulating layer 13 and the passivation layer 15 are etched by using the planarization layer 16 as a shielding layer to obtain a first via 51 and a second via 52.
  • Step 4 as shown in FIG. 7-8, forming a conductive layer on the planarization layer 16, and patterning the conductive layer to obtain a plurality of first pins 12 and a plurality of second pins 14 a plurality of connecting wires 17, each connecting wire 17 being connected to the corresponding first pin 12 through the first via 51, and connected to the corresponding second pin 14 through the second via 52, thereby correspondingly The first pin 12 is connected to the second pin 14.
  • the step of patterning the conductive layer in step 4 is: applying a photoresist on the conductive layer, exposing and developing the photoresist through a photomask to form a photoresist pattern, and then The remaining photoresist is occluded, the conductive layer is etched, and the remaining photoresist is stripped to obtain a plurality of connecting wires 17.
  • the connecting wires 17 are directly connected to the chip-on-film (COF) chip, so that the signal on the chip-on-film chip is transmitted to the TFT substrate through the OLB region, and then transmitted to the entire display panel.
  • COF chip-on-film
  • the material of the conductive layer formed in the step 4 is indium tin oxide (ITO); and the step 4 etches the conductive layer by a wet etching process.
  • ITO indium tin oxide
  • the connecting wire 17 is connected to the corresponding first pin 12 through the first via 51, and is connected to the corresponding second pin 14 through the second via 52, thereby The corresponding first pin 12 is connected to the second pin 14 . Since the connecting wire 17 completely covers the first via 51 and the second via 52 , it does not exist in the process of patterning the conductive layer to form the connecting wire 17 . The problem of residual conductive material in the via hole avoids the short circuit and display of the conductive material remaining at the bottom of the via hole of the planarization layer relative to the existing large-area opening on the planarization layer of the OLB region. bad.
  • a first via 51 is formed corresponding to each of the first pins 12 in the step 3, corresponding to each second pin.
  • a second via 52 is formed above the 14 .
  • a plurality of first via holes 51 may be formed above each of the first pins 12, corresponding to each of the first
  • a plurality of second vias 52 are formed above the two pins 14; as shown in FIG. 6, in the second embodiment of the present invention, two firsts are formed above the corresponding first pins 12 in the step 3.
  • the via 51 has two second vias 52 formed corresponding to each of the second leads 14.
  • the method for binding a pin in the OLB area of the present invention separately opens a hole corresponding to each pin on the flattening layer of the OLB area, and the subsequently formed connecting wire passes through the via hole and the pin above the pin.
  • the connection is made, and the corresponding pins are connected together through the connecting wires. Since the connecting wires completely cover the through holes above the pins, there is no problem of residual conductive material in the via holes in the process of forming the connecting wires, as opposed to the present
  • Some ways of opening a large area on the flattening layer of the OLB area avoid circuit short circuit and poor display caused by the conductive material remaining at the bottom of the via hole of the planarization layer.

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Abstract

一种在OLB区绑定引脚的方法，在OLB区的平坦化层（16）上对应每一引脚（12、14）单独开孔（51、52），后续形成的连接导线（17）通过引脚（12、14）上方的过孔（51、52）与引脚（12、14）进行连接，进而对应的引脚（12、14）通过连接导线（17）连接在一起，由于连接导线（17）全面覆盖引脚（12、14）上方的过孔（51、52），因此在形成连接导线（17）的过程中不存在在过孔（51、52）内残留导电材料的问题，相对于现有的在OLB区的平坦化层上大面积开孔的方式，避免了导电材料在平坦化层的过孔底部残留而造成的电路短路及显示不良。

Description

在OLB区绑定引脚的方法 技术领域
本发明涉及显示技术领域，尤其涉及一种在OLB区绑定引脚的方法。
背景技术
主动式薄膜晶体管液晶显示器(Thin Film Transistor-LCD，TFT-LCD)近年来得到了飞速的发展和广泛的应用。通常液晶显示面板由彩膜基板(CF，Color Filter)、薄膜晶体管基板(TFT，Thin Film Transistor)、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封框胶(Sealant)组成；其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
就目前主流市场上的TFT-LCD显示面板而言，可分为三种类型，分别是扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted Nematic，STN)型，平面转换(In-Plane Switching，IPS)型、及垂直配向(Vertical Alignment，VA)型。电视的液晶显示屏幕受限于尺寸过大，一般使用的是VA模式的显示技术，少部分使用IPS显示模式。
在液晶显示面板的制作过程中，已经形成薄膜晶体管的基板上需要覆盖一层有机膜(PFA)作为平坦化层(Planarization，PLN)，以改变下层膜表面的平整性，防止电场互相干扰，平坦化层通常为感旋光材料。普通的VA显示模式，无论是PVA，MVA，或者HVA都不会使用到有机膜来起到平坦化的作用，但是如果是VA显示技术和其他技术相结合，则可能使用到有机膜来实现平坦化。而IPS显示模式是需要使用到有机膜来起到平坦化作用的。
液晶显示面板在正常显示时，需要使用COF(chip on film，覆晶薄膜)通过引线连接到面板的外引脚贴合(Outer Lead Bonding，OLB)区域，从而使得集成于COF上IC的信号通过OLB区导通到面板中。具体的，如图1所示，该OLB区包括衬底基板、形成于衬底基板上的数个并列排布的第一引脚110、形成于所述衬底基板及数个第一引脚110上的栅极绝缘层、形成于所述栅极绝缘层上的与数个第一引脚110相对设置的数个第二引脚120、形成于所述栅极绝缘层及数个第二引脚120上的钝化层、及形成于钝化层上的平坦化层200；在制作过程中，首先，将平坦化层200在对应OLB区上的部分全部挖掉，在平坦化层200上形成一空白区210，然后如图2所 示，然后在基板上形成ITO导电层并图案化，得到数个连接导线130，每一连接导线130在空白区210内把第一引脚110与第二引脚120连接在一起，之后用于和COF上的金属针状引脚(pin)连接在一起，从而使得集成在COF上IC的信号通过OLB区传到显示屏。其中对ITO导电层进行图案化处理的具体实施步骤为：在ITO导电层上涂覆光阻，通过一道光罩对所述光阻进行曝光、显影，形成光阻图形，然后以剩余的光阻为遮挡，对所述ITO导电层进行蚀刻，并剥离剩余的光阻，得到数个连接导线130。然而由于平坦化层200的厚度较大，在空白区210的边缘具有一定的斜坡(taper)角度，所以在对ITO导电层进行图案化的曝光工序后，会在空白区210的taper角的地方有一定的光阻残留，最后会导致在taper角的地方会有ITO残留131，如图2所示，该ITO残留131会使得金属走线之间连接在一起而短路。
发明内容
本发明的目的在于提供一种在OLB区绑定引脚的方法，改善平坦化层在OLB区的过孔设计，避免因光阻材料残留而导致过孔底部的导电材料残留，进而因此造成的电路短路及显示不良。
为实现上述目的，本发明提供一种在OLB区绑定引脚的方法，包括如下步骤：
步骤1、提供一TFT基板，所述TFT基板包括显示区、及OLB区；
所述OLB区包括衬底基板、形成于衬底基板上的数个并列排布的第一引脚、形成于所述衬底基板及数个第一引脚上的栅极绝缘层、形成于所述栅极绝缘层上的与数个第一引脚对应设置的数个第二引脚、及形成于所述栅极绝缘层及数个第二引脚上的钝化层；
步骤2、在所述TFT基板上涂布形成一层有机膜，得到平坦化层；
步骤3、在所述平坦化层、钝化层、及栅极绝缘层上对应每一第一引脚的上方形成至少一个第一过孔，在所述平坦化层及钝化层上对应每一第二引脚的上方形成至少一个第二过孔；
步骤4、在所述平坦化层上形成导电层，对所述导电层进行图案化处理，得到对应数个第一引脚及数个第二引脚的数个连接导线，每一连接导线通过第一过孔与对应的第一引脚相连接，通过第二过孔与对应的第二引脚相连接，从而将相对应的第一引脚与第二引脚相连接。
所述步骤2中形成的有机膜为光阻材料。
所述步骤2中形成的有机膜的厚度为1.5-3.5μm。
所述步骤3中对应每一第一引脚的上方形成一个第一过孔，对应每一第二引脚的上方形成一个第二过孔。
所述步骤3中对应每一第一引脚的上方形成两个第一过孔，对应每一第二引脚的上方形成两个第二过孔。
所述栅极绝缘层及钝化层的材料均为氮化硅。
所述步骤3具体包括以下实施步骤：
步骤31、提供一光罩，所述光罩包括分别对应数个第一过孔及数个第二过孔的第一图案及第二图案，利用该光罩对所述平坦化层进行曝光、显影，对应所述第一图案及第二图案在所述平坦化层上形成数个有机膜过孔；
步骤32、以平坦化层为遮蔽层，对所述栅极绝缘层及钝化层进行蚀刻，得到第一过孔及第二过孔。
所述步骤4中形成的导电层的材料为ITO。
所述步骤4对所述导电层进行图案化处理包括采用湿法蚀刻制程对所述导电层进行蚀刻。
所述连接导线用于连接覆晶薄膜芯片。
本发明还提供一种在OLB区绑定引脚的方法，包括如下步骤：
步骤1、提供一TFT基板，所述TFT基板包括显示区、及OLB区；
所述OLB区包括衬底基板、形成于衬底基板上的数个并列排布的第一引脚、形成于所述衬底基板及数个第一引脚上的栅极绝缘层、形成于所述栅极绝缘层上的与数个第一引脚相对设置的数个第二引脚、及形成于所述栅极绝缘层及数个第二引脚上的钝化层；
步骤2、在所述TFT基板上涂布形成一层有机膜，得到平坦化层；
步骤3、在所述平坦化层、钝化层、及栅极绝缘层上对应每一第一引脚的上方形成至少一个第一过孔，在所述平坦化层及钝化层上对应每一第二引脚的上方形成至少一个第二过孔；
步骤4、在所述平坦化层上形成导电层，对所述导电层进行图案化处理，得到对应数个第一引脚及数个第二引脚的数个连接导线，每一连接导线通过第一过孔与对应的第一引脚相连接，通过第二过孔与对应的第二引脚相连接，从而将相对应的第一引脚与第二引脚相连接；
其中，所述步骤2中形成的有机膜为光阻材料；
其中，所述步骤2中形成的有机膜的厚度为1.5-3.5μm；
其中，所述步骤3具体包括以下实施步骤：
步骤31、提供一光罩，所述光罩包括分别对应数个第一过孔及数个第二过孔的第一图案及第二图案，利用该光罩对所述平坦化层进行曝光、显 影，对应所述第一图案及第二图案在所述平坦化层上形成数个有机膜过孔；
步骤32、以平坦化层为遮蔽层，对所述栅极绝缘层及钝化层进行蚀刻，得到第一过孔及第二过孔。
本发明的有益效果：本发明的在OLB区绑定引脚的方法，在OLB区的平坦化层上对应每一引脚单独开孔，后续形成的连接导线通过引脚上方的过孔与引脚进行连接，进而对应的引脚通过连接导线连接在一起，由于连接导线全面覆盖引脚上方的过孔，因此在形成连接导线的过程中不存在在过孔内残留导电材料的问题，相对于现有的在OLB区的平坦化层上大面积开孔的方式，避免了导电材料在平坦化层的过孔底部残留而造成的电路短路及显示不良。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有一种在OLB区绑定引脚的方法中在平坦化层上对应OLB区大面积开孔的示意图；
图2为在图1的OLB区形成连接导线的示意图；
图3为本发明在OLB区绑定引脚的方法的流程示意图；
图4为本发明在OLB区绑定引脚的方法的步骤2的示意图；
图5为本发明在OLB区绑定引脚的方法的第一实施例中步骤3的示意图；
图6为本发明在OLB区绑定引脚的方法的第二实施例中步骤3的示意图；
图7为本发明在OLB区绑定引脚的方法的第一实施例中步骤4的示意图；
图8为沿图7中A-A’剖面线的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明提供一种在OLB区绑定引脚的方法，包括如下步骤：
步骤1、提供一TFT基板，所述TFT基板包括显示区、及OLB区；
如图8所示，所述OLB区包括衬底基板11、形成于衬底基板11上的数个并列排布的第一引脚12、形成于所述衬底基板及数个第一引脚12上的栅极绝缘层13、形成于所述栅极绝缘层13上的与数个第一引脚12相对设置的数个第二引脚14、及形成于所述栅极绝缘层13及数个第二引脚14上的钝化层15。
具体的，所述栅极绝缘层13及钝化层15的材料均为氮化硅(SiNx)。
步骤2、如图4所示，在所述TFT基板上涂布形成一层有机膜，得到平坦化层16。
具体的，所述步骤2中形成的有机膜为光阻材料，厚度为1.5-3.5μm，优选为2.5μm。
步骤3、如图5所示，在所述平坦化层16、钝化层15、及栅极绝缘层13上对应每一第一引脚12的上方形成一个第一过孔51，在所述平坦化层16及钝化层15上对应每一第二引脚14的上方形成一个第二过孔52。
其中，所述步骤3具体包括以下实施步骤：
步骤31、提供一光罩，所述光罩包括分别对应数个第一过孔51及数个第二过孔52的第一图案及第二图案，利用该光罩对所述平坦化层16进行曝光、显影，对应所述第一图案及第二图案在所述平坦化层16上形成数个有机膜过孔；
步骤32、以平坦化层16为遮蔽层，对所述栅极绝缘层13及钝化层15进行蚀刻，得到第一过孔51及第二过孔52。
步骤4、如图7-8所示，在所述平坦化层16上形成导电层，对所述导电层进行图案化处理，得到对应数个第一引脚12及数个第二引脚14的数个连接导线17，每一连接导线17通过第一过孔51与对应的第一引脚12相连接，通过第二过孔52与对应的第二引脚14相连接，从而将相对应的第一引脚12与第二引脚14相连接。
具体的，步骤4对导电层进行图案化处理的具体实施步骤为：在所述导电层上涂覆光阻，通过一道光罩对所述光阻进行曝光、显影，形成光阻图形，然后以剩余的光阻为遮挡，对所述导电层进行蚀刻，并剥离剩余的光阻，得到数个连接导线17。后续制程中，所述连接导线17直接连接覆晶薄膜(COF)芯片，从而将覆晶薄膜芯片上的信号通过OLB区传递给TFT基板，进而传递给整个显示面板。
具体的，所述步骤4中形成的导电层的材料为氧化铟锡(Indium tin oxide，ITO)；所述步骤4采用湿法蚀刻制程对所述导电层进行蚀刻。
值得一提的是，本发明中，连接导线17通过第一过孔51与对应的第一引脚12相连接，通过第二过孔52与对应的第二引脚14相连接，从而将相对应的第一引脚12与第二引脚14相连接，由于连接导线17全面覆盖第一过孔51与第二过孔52，因此在图案化导电层以形成连接导线17的过程中不存在在过孔内残留导电材料的问题，相对于现有的在OLB区的平坦化层上大面积开孔的方式，避免了导电材料在平坦化层的过孔底部残留而造成的电路短路及显示不良。
如图5与图8所示，在上述本发明的第一实施例中，所述步骤3中对应每一第一引脚12的上方形成一个第一过孔51，对应每一第二引脚14的上方形成一个第二过孔52。
然而，为减少每一连接导线17与第一引脚12、第二引脚14的连接电阻，可以在对应每一第一引脚12的上方形成多个第一过孔51，对应每一第二引脚14的上方形成多个第二过孔52；如图6所示，本发明的第二实施例中，所述步骤3中对应每一第一引脚12的上方形成两个第一过孔51，对应每一第二引脚14的上方形成两个第二过孔52，其他其他与本发明前述的第一实施例均相同，在此不再赘述。
综上所述，本发明的在OLB区绑定引脚的方法，在OLB区的平坦化层上对应每一引脚单独开孔，后续形成的连接导线通过引脚上方的过孔与引脚进行连接，进而对应的引脚通过连接导线连接在一起，由于连接导线全面覆盖引脚上方的过孔，因此在形成连接导线的过程中不存在在过孔内残留导电材料的问题，相对于现有的在OLB区的平坦化层上大面积开孔的方式，避免了导电材料在平坦化层的过孔底部残留而造成的电路短路及显示不良。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (17)

  1. 一种在OLB区绑定引脚的方法，包括如下步骤：
    步骤1、提供一TFT基板，所述TFT基板包括显示区、及OLB区；
    所述OLB区包括衬底基板、形成于衬底基板上的数个并列排布的第一引脚、形成于所述衬底基板及数个第一引脚上的栅极绝缘层、形成于所述栅极绝缘层上的与数个第一引脚相对设置的数个第二引脚、及形成于所述栅极绝缘层及数个第二引脚上的钝化层；
    步骤2、在所述TFT基板上涂布形成一层有机膜，得到平坦化层；
    步骤3、在所述平坦化层、钝化层、及栅极绝缘层上对应每一第一引脚的上方形成至少一个第一过孔，在所述平坦化层及钝化层上对应每一第二引脚的上方形成至少一个第二过孔；
    步骤4、在所述平坦化层上形成导电层，对所述导电层进行图案化处理，得到对应数个第一引脚及数个第二引脚的数个连接导线，每一连接导线通过第一过孔与对应的第一引脚相连接，通过第二过孔与对应的第二引脚相连接，从而将相对应的第一引脚与第二引脚相连接。
  2. 如权利要求1所述的在OLB区绑定引脚的方法，其中，所述步骤2中形成的有机膜为光阻材料。
  3. 如权利要求2所述的在OLB区绑定引脚的方法，其中，所述步骤2中形成的有机膜的厚度为1.5-3.5μm。
  4. 如权利要求1所述的在OLB区绑定引脚的方法，其中，所述步骤3中对应每一第一引脚的上方形成一个第一过孔，对应每一第二引脚的上方形成一个第二过孔。
  5. 如权利要求1所述的在OLB区绑定引脚的方法，其中，所述步骤3中对应每一第一引脚的上方形成两个第一过孔，对应每一第二引脚的上方形成两个第二过孔。
  6. 如权利要求1所述的在OLB区绑定引脚的方法，其中，所述栅极绝缘层及钝化层的材料均为氮化硅。
  7. 如权利要求1所述的在OLB区绑定引脚的方法，其中，所述步骤3具体包括以下实施步骤：
    步骤31、提供一光罩，所述光罩包括分别对应数个第一过孔及数个第二过孔的第一图案及第二图案，利用该光罩对所述平坦化层进行曝光、显影，对应所述第一图案及第二图案在所述平坦化层上形成数个有机膜过孔； 步骤32、以平坦化层为遮蔽层，对所述栅极绝缘层及钝化层进行蚀刻，得到第一过孔及第二过孔。
  8. 如权利要求1所述的在OLB区绑定引脚的方法，其中，所述步骤4中形成的导电层的材料为ITO。
  9. 如权利要求8所述的在OLB区绑定引脚的方法，其中，所述步骤4对所述导电层进行图案化处理包括采用湿法蚀刻制程对所述导电层进行蚀刻。
  10. 如权利要求1所述的在OLB区绑定引脚的方法，其中，所述连接导线用于连接覆晶薄膜芯片。
  11. 一种在OLB区绑定引脚的方法，包括如下步骤：
    步骤1、提供一TFT基板，所述TFT基板包括显示区、及OLB区；
    所述OLB区包括衬底基板、形成于衬底基板上的数个并列排布的第一引脚、形成于所述衬底基板及数个第一引脚上的栅极绝缘层、形成于所述栅极绝缘层上的与数个第一引脚相对设置的数个第二引脚、及形成于所述栅极绝缘层及数个第二引脚上的钝化层；
    步骤2、在所述TFT基板上涂布形成一层有机膜，得到平坦化层；
    步骤3、在所述平坦化层、钝化层、及栅极绝缘层上对应每一第一引脚的上方形成至少一个第一过孔，在所述平坦化层及钝化层上对应每一第二引脚的上方形成至少一个第二过孔；
    步骤4、在所述平坦化层上形成导电层，对所述导电层进行图案化处理，得到对应数个第一引脚及数个第二引脚的数个连接导线，每一连接导线通过第一过孔与对应的第一引脚相连接，通过第二过孔与对应的第二引脚相连接，从而将相对应的第一引脚与第二引脚相连接；
    其中，所述步骤2中形成的有机膜为光阻材料；
    其中，所述步骤2中形成的有机膜的厚度为1.5-3.5μm；
    其中，所述步骤3具体包括以下实施步骤：
    步骤31、提供一光罩，所述光罩包括分别对应数个第一过孔及数个第二过孔的第一图案及第二图案，利用该光罩对所述平坦化层进行曝光、显影，对应所述第一图案及第二图案在所述平坦化层上形成数个有机膜过孔；
    步骤32、以平坦化层为遮蔽层，对所述栅极绝缘层及钝化层进行蚀刻，得到第一过孔及第二过孔。
  12. 如权利要求11所述的在OLB区绑定引脚的方法，其中，所述步骤3中对应每一第一引脚的上方形成一个第一过孔，对应每一第二引脚的上方形成一个第二过孔。
  13. 如权利要求11所述的在OLB区绑定引脚的方法，其中，所述步骤3中对应每一第一引脚的上方形成两个第一过孔，对应每一第二引脚的上方形成两个第二过孔。
  14. 如权利要求11所述的在OLB区绑定引脚的方法，其中，所述栅极绝缘层及钝化层的材料均为氮化硅。
  15. 如权利要求11所述的在OLB区绑定引脚的方法，其中，所述步骤4中形成的导电层的材料为ITO。
  16. 如权利要求15所述的在OLB区绑定引脚的方法，其中，所述步骤4对所述导电层进行图案化处理包括采用湿法蚀刻制程对所述导电层进行蚀刻。
  17. 如权利要求11所述的在OLB区绑定引脚的方法，其中，所述连接导线用于连接覆晶薄膜芯片。
PCT/CN2016/082674 2016-04-20 2016-05-19 在olb区绑定引脚的方法 Ceased WO2017181469A1 (zh)

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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108550580B (zh) * 2018-04-27 2019-10-11 武汉华星光电技术有限公司 Tft阵列基板
CN110109300B (zh) * 2019-04-23 2021-12-03 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示面板的制作方法
CN110136589B (zh) * 2019-06-28 2021-09-21 武汉天马微电子有限公司 一种显示面板、其制作方法及显示装置
CN111090201B (zh) 2020-03-22 2020-06-23 深圳市华星光电半导体显示技术有限公司 显示面板及电子装置
US12219831B2 (en) 2020-10-14 2025-02-04 Samsung Display Co., Ltd. Display apparatus
CN112366220B (zh) * 2020-11-10 2024-02-27 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
KR20220069160A (ko) 2020-11-19 2022-05-27 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
CN112596313A (zh) * 2020-12-07 2021-04-02 Tcl华星光电技术有限公司 阵列基板
CN116449616A (zh) * 2023-04-23 2023-07-18 京东方科技集团股份有限公司 一种显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020088450A (ko) * 2001-05-17 2002-11-29 주식회사 현대 디스플레이 테크놀로지 액정표시장치 어레이 기판
TW565815B (en) * 2002-10-17 2003-12-11 Chi Mei Optoelectronics Corp Liquid crystal display panel
KR100780573B1 (ko) * 2006-08-22 2007-11-30 (주)아이디에스 플라스틱 ｌｃｄ의 ｉｔｏ단과 연성인쇄회로기판의 ｏｌｂ단의 정렬 부착 구조
CN101145565A (zh) * 2006-09-15 2008-03-19 龙腾光电（控股）有限公司 多倒角薄膜晶体管阵列基板及液晶显示装置
CN102103284A (zh) * 2009-12-21 2011-06-22 三星电子株式会社 显示装置和制造显示装置的方法
CN103365009A (zh) * 2012-03-29 2013-10-23 乐金显示有限公司 玻璃上布线型液晶显示器件及其制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5019834B2 (ja) * 2006-09-26 2012-09-05 インフォビジョン オプトエレクトロニクス ホールデングズ リミティッド 表示装置用基板及び表示装置
CN101442060B (zh) * 2008-12-25 2011-04-20 友达光电股份有限公司 像素阵列及其制造方法
US8629965B2 (en) * 2009-06-17 2014-01-14 Hitachi Displays, Ltd. Display device
CN104142588B (zh) * 2014-07-30 2017-01-25 深圳市华星光电技术有限公司 液晶显示面板以及液晶显示器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020088450A (ko) * 2001-05-17 2002-11-29 주식회사 현대 디스플레이 테크놀로지 액정표시장치 어레이 기판
TW565815B (en) * 2002-10-17 2003-12-11 Chi Mei Optoelectronics Corp Liquid crystal display panel
KR100780573B1 (ko) * 2006-08-22 2007-11-30 (주)아이디에스 플라스틱 ｌｃｄ의 ｉｔｏ단과 연성인쇄회로기판의 ｏｌｂ단의 정렬 부착 구조
CN101145565A (zh) * 2006-09-15 2008-03-19 龙腾光电（控股）有限公司 多倒角薄膜晶体管阵列基板及液晶显示装置
CN102103284A (zh) * 2009-12-21 2011-06-22 三星电子株式会社 显示装置和制造显示装置的方法
CN103365009A (zh) * 2012-03-29 2013-10-23 乐金显示有限公司 玻璃上布线型液晶显示器件及其制造方法

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