WO2017175480A1

WO2017175480A1 - Sheet for producing three-dimensional integrated laminated circuit and method for producing three-dimensional integrated laminated circuit

Info

Publication number: WO2017175480A1
Application number: PCT/JP2017/005141
Authority: WO
Inventors: 裕介根津; 貴志杉野
Original assignee: リンテック株式会社
Priority date: 2016-04-05
Filing date: 2017-02-13
Publication date: 2017-10-12
Also published as: KR102571295B1; TWI701800B; KR20180131528A; TW201803080A

Abstract

This sheet 1 for producing a three-dimensional integrated laminated circuit, which is interposed between a plurality of semiconductor chips having through-electrodes and is used to adhere the semiconductor chips to each other and obtain a three-dimensional integrated laminated circuit, is provided with at least a curable adhesive layer 13, wherein the material that constitutes the adhesive layer 13 has a pre-curing melt viscosity at 90 °C of 1.0×10⁰-5.0×10⁵ Pa·s, and the cured product has an average linear expansion coefficient at 0-130 °C of 45 ppm or less. This sheet 1 for producing a three-dimensional integrated laminated circuit can be used to produce a three-dimensional integrated laminated circuit in which connection resistance between the semiconductor chips does not easily change and which is highly reliable.

Description

Sheet for manufacturing three-dimensional integrated multilayer circuit and method for manufacturing three-dimensional integrated multilayer circuit

The present invention relates to a sheet suitable for manufacturing a three-dimensional integrated multilayer circuit, and a method for manufacturing a three-dimensional integrated multilayer circuit using the sheet.

In recent years, development of a three-dimensional integrated stacked circuit (hereinafter sometimes referred to as “laminated circuit”) in which a plurality of semiconductor chips are three-dimensionally stacked is progressing from the viewpoint of increasing the capacity and functionality of electronic circuits. In such a laminated circuit, a semiconductor chip having a through electrode (TSV) penetrating from the circuit formation surface to the opposite surface is used for miniaturization and high functionality. In this case, the stacked semiconductor chips are electrically connected to each other through contact between through electrodes (or bumps provided at end portions of the through electrodes) provided in the respective semiconductor chips.

When manufacturing such a laminated circuit, in order to ensure the electrical connection and mechanical strength described above, the semiconductor chip is bonded to each other while electrically connecting the through electrodes with the resin composition. Is done. For example, Patent Document 1 proposes a method in which semiconductor chips are bonded to each other by interposing a film-like adhesive generally called NCF (Non-Conductive Film) between the semiconductor chips.

By the way, such an adhesive is required to have high reliability such that the connection resistance between the semiconductor chips does not change even under a temperature cycle test.

JP 2010-010368 A

However, conventional adhesives have a problem that good results cannot always be secured in the temperature cycle test.

The present invention has been made in view of such a situation, and it is difficult to change the connection resistance between semiconductor chips, and it is possible to manufacture a highly reliable three-dimensional integrated multilayer circuit. The purpose is to provide a sheet for use. Another object of the present invention is to provide a method for manufacturing such a three-dimensional integrated laminated circuit.

In order to achieve the above object, first, the present invention is interposed between a plurality of semiconductor chips having through electrodes, and is used to bond the plurality of semiconductor chips to each other to form a three-dimensional integrated stacked circuit. A sheet for manufacturing a three-dimensional integrated circuit, wherein the sheet for manufacturing a three-dimensional integrated circuit includes at least a curable adhesive layer, and the material constituting the adhesive layer is 90 ° C. before curing. The melt viscosity is 1.0 × 10 ⁰ to 5.0 × 10 ⁵ Pa · s, and the average linear expansion coefficient at 0 to 130 ° C. of the cured product is 45 ppm or less. A production sheet is provided (Invention 1).

In the sheet for manufacturing a three-dimensional integrated laminated circuit according to the invention (Invention 1), since the melt viscosity at 90 ° C. before the adhesive layer is cured is in the above range, the adhesive layer is interposed between the semiconductor chips. In addition, the adhesive layer satisfactorily follows irregularities due to the through electrodes or bumps on the semiconductor chip surface. Further, since the average linear expansion coefficient of the cured product of the adhesive layer is 45 ppm or less, the difference in the linear expansion coefficient with the semiconductor chip is reduced, and the stress that can be generated between the adhesive layer and the semiconductor chip is reduced. be able to. Therefore, the sheet for manufacturing a three-dimensional integrated laminated circuit according to the above invention (Invention 1) can have high connection reliability between semiconductor chips.

In the above invention (Invention 1), the cured material of the material constituting the adhesive layer preferably has a glass transition temperature of 150 ° C. or more and 350 ° C. or less (Invention 2).

In the above inventions (Inventions 1 and 2), the cured material of the material constituting the adhesive layer preferably has a 5% mass reduction temperature of 350 ° C. or more by thermogravimetry (Invention 3).

In the above inventions (Inventions 1 to 3), the standard deviation of the thickness (T2) of the adhesive layer is preferably 2.0 μm or less (Invention 4).

In the above inventions (Inventions 1 to 4), the storage elastic modulus at 23 ° C. after curing of the adhesive layer is preferably 1.0 × 10 ² MPa or more and 1.0 × 10 ⁵ MPa or less (Invention). 5).

In the above inventions (Inventions 1 to 5), the adhesive layer has an exothermic onset temperature (TS) measured by differential scanning calorimetry at a heating rate of 10 ° C./min within a range of 70 ° C. to 150 ° C. The exothermic peak temperature (TP) is preferably TS + 5 to 60 ° C. (Invention 6).

In the above inventions (Inventions 1 to 6), the material constituting the adhesive layer preferably contains a thermosetting component, a high molecular weight component, a curing agent and a curing catalyst (Invention 7).

In the above inventions (Inventions 1 to 7), the material constituting the adhesive layer preferably contains a flux component (Invention 8).

In the above inventions (Inventions 1 to 8), the material constituting the adhesive layer preferably contains an inorganic filler (Invention 9).

In the above inventions (Inventions 1 to 9), the sheet for manufacturing a three-dimensional integrated laminated circuit is opposite to the adhesive layer laminated on one side of the adhesive layer and the adhesive layer in the adhesive layer. It is preferable to further include a base material laminated on the surface side (Invention 10).

In the said invention (invention 10), ratio (T2 / T1) of the thickness (T2) of the said adhesive bond layer with respect to the thickness (T1) of the said base material is 0.01 or more and 1.5 or less. Preferred (Invention 11).

In the said invention (invention 10 and 11), it is preferable that the storage elastic modulus in 23 degreeC of the said adhesive layer is 1 * 10 < ³ > Pa or more and 1 * 10 < ⁹ > Pa or less (invention 12).

In the above inventions (Inventions 10 to 12), the base material preferably has a tensile elastic modulus at 23 ° C. of 100 MPa or more and 5000 MPa or less (Invention 13).

In the above inventions (Inventions 10 to 13), the laminate comprising the pressure-sensitive adhesive layer and the substrate is preferably a dicing sheet (Invention 14).

Second, the present invention relates to one side of the adhesive layer of the sheet for manufacturing a three-dimensional integrated circuit (Invention 1 to 9) or the adhesive layer of the sheet for manufacturing a three-dimensional integrated circuit (Invention 10 to 14). Bonding the surface opposite to the pressure-sensitive adhesive layer and at least one surface of a semiconductor wafer provided with through electrodes, and bonding the semiconductor wafer to the adhesive layer of the sheet for producing a three-dimensional integrated multilayer circuit And dicing together into a semiconductor chip with an adhesive layer, and dividing the plurality of semiconductor chips with an adhesive layer into electrical connection between the through electrodes and the adhesive layer and the semiconductor chip A step of obtaining a semiconductor chip laminate by stacking a plurality of semiconductor chips so as to be alternately arranged, and curing the adhesive layer in the semiconductor chip laminate to constitute the semiconductor chip laminate. Said to provide a method of manufacturing a three-dimensional integrated multilayer circuit, characterized in that it comprises a step of bonding the semiconductor chips to (invention 15).

According to the sheet for manufacturing a three-dimensional integrated multilayer circuit of the present invention, it is possible to manufacture a three-dimensional integrated multilayer circuit having a high reliability in which the connection resistance between the semiconductor chips hardly changes. Moreover, according to the manufacturing method of the present invention, such a three-dimensional integrated laminated circuit can be manufactured.

It is sectional drawing of the sheet | seat for three-dimensional integrated laminated circuit manufacture which concerns on the 1st Embodiment of this invention. It is sectional drawing of the sheet | seat for three-dimensional integrated laminated circuit manufacture which concerns on the 2nd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described.
[Three-dimensional integrated laminated circuit manufacturing sheet]
FIG. 1 shows a cross-sectional view of a sheet 1 for manufacturing a three-dimensional integrated laminated circuit according to the first embodiment. As shown in FIG. 1, a sheet 1 for manufacturing a three-dimensional integrated laminated circuit according to the present embodiment (hereinafter sometimes referred to as “manufacturing sheet 1”) includes an adhesive layer 13 and at least the adhesive layer 13. And a release sheet 14 laminated on one surface. Note that the release sheet 14 may be omitted.

FIG. 2 is a cross-sectional view of the sheet 2 for manufacturing a three-dimensional integrated multilayer circuit according to the second embodiment. As shown in FIG. 2, the sheet 2 for manufacturing a three-dimensional integrated laminated circuit according to the present embodiment (hereinafter, also referred to as “manufacturing sheet 2”) includes a base material 11 and at least one surface of the base material 11. The adhesive layer 12 laminated | stacked on the side and the adhesive bond layer 13 laminated | stacked on the surface side on the opposite side to the base material 11 in the adhesive layer 12 are provided. A release sheet 14 may be laminated on the surface of the adhesive layer 13 opposite to the pressure-sensitive adhesive layer 12.

In the sheet 2 for manufacturing a three-dimensional integrated laminated circuit according to the second embodiment, the laminate composed of the base material 11 and the pressure-sensitive adhesive layer 12 may be a dicing sheet. In this case, the manufacturing sheet 2 is It becomes a dicing sheet integrated adhesive sheet. The laminate may be a back grind sheet. In this case, the production sheet 2 is a back grind sheet integrated adhesive sheet.

The three-dimensional integrated multilayer

circuit manufacturing sheets

1 and 2 according to the present embodiment are interposed between a plurality of semiconductor chips having through electrodes, and are bonded to each other to form a three-dimensional integrated multilayer circuit. It is used for this purpose. One or both ends of the through electrode may protrude from the surface of the semiconductor chip. Further, the semiconductor chip may further include a bump, and in this case, the bump may be provided at one end or both ends of the through electrode.

1. Adhesive Layer (1) Physical Properties In the three-dimensional integrated laminated

circuit manufacturing sheets

1 and 2 according to this embodiment, the adhesive layer 13 has curability. Here, having the curability means that the adhesive layer 13 can be cured by heating or the like. That is, the adhesive layer 13 is uncured in the state where the

manufacturing sheets

1 and 2 are configured. The adhesive layer 13 may be thermosetting or energy ray curable. However, the adhesive layer 13 is preferably thermosetting from the viewpoint that curing can be satisfactorily performed when the

production sheets

1 and 2 are used in a method for producing a laminated circuit. Specifically, when the

manufacturing sheets

1 and 2 are used in a method for manufacturing a laminated circuit, the adhesive layer 13 is separated into pieces in a state of being attached to a semiconductor wafer, as will be described later. Thereby, the laminated body of the semiconductor chip and the adhesive layer 13 separated into pieces is obtained. In the laminated body, the adhesive layer 13 side surface is stuck on the laminated body of the semiconductor chips, and the adhesive layer 13 is cured in this state. In general, a semiconductor chip often does not have a permeability to energy rays or has a very low permeability. Even in such a case, the adhesive layer 13 has a thermosetting property. In this case, the adhesive layer 13 can be quickly cured.

(1-1) Melt Viscosity In the

sheets

1 and 2 for manufacturing a three-dimensional integrated laminated circuit according to this embodiment, the material constituting the adhesive layer 13 is melt viscosity at 90 ° C. (hereinafter referred to as “90 ° C.”) before curing. The upper limit is 5.0 × 10 ⁵ Pa · s or less, preferably 1.0 × 10 ⁵ Pa · s or less, and particularly preferably 5.0 × 10 5. ⁴ Pa · s or less. When the 90 ° C. melt viscosity is less than or equal to the above upper limit, when the adhesive layer 13 is interposed between the electrodes, the semiconductor chip adheres well to the unevenness caused by the through electrodes or bumps on the surface of the semiconductor chip. Generation of voids at the interface with the agent layer 13 can be prevented. The 90 ° C. melt viscosity is 1.0 × 10 ⁰ Pa · s or more as a lower limit, preferably 1.0 × 10 ¹ Pa · s or more, and particularly preferably 1.0 × 10 ² Pa · s. s or more. When the 90 ° C. melt viscosity is not less than the above lower limit value, the material constituting the adhesive layer 13 does not flow excessively, and contamination of the apparatus can be prevented when the adhesive layer 13 is stuck or when semiconductor chips are stacked. it can. Therefore, the

sheets

1 and 2 for manufacturing a three-dimensional integrated multilayer circuit according to the present embodiment have high reliability when the constituent material has a 90 ° C. melt viscosity in the above range.

Here, the 90 ° C. melt viscosity of the material constituting the adhesive layer 13 is a value measured using a flow tester, and the details of the test method are as shown in Examples described later.

(1-2) Average Linear Expansion Coefficient In the present embodiment, the material constituting the adhesive layer 13 is sometimes referred to as an average linear expansion coefficient at 0 to 130 ° C. of the cured product (hereinafter simply referred to as “average linear expansion coefficient”). .) Is 45 ppm or less as an upper limit, preferably 35 ppm or less, and particularly preferably 25 ppm or less. When the average linear expansion coefficient is not more than the above upper limit value, the difference in linear expansion coefficient between the adhesive layer 13 made of a cured product and the semiconductor chip becomes small, and the adhesive layer 13 and the semiconductor chip are based on the difference. The stress that can be generated can be reduced. Thereby, the

sheets

1 and 2 for manufacturing a three-dimensional integrated circuit according to the present embodiment can have high connection reliability between semiconductor chips, and particularly high connection reliability in the temperature cycle test shown in the examples. Will be shown.

On the other hand, the lower limit value of the average linear expansion coefficient is not particularly limited, but is preferably 5 ppm or more and more preferably 10 ppm or more from the viewpoint of film formability.

Here, the average linear expansion coefficient of the material constituting the adhesive layer 13 is a value measured using a thermomechanical analyzer, and details of the test method are as shown in Examples described later.

(1-3) Glass Transition Temperature In this embodiment, the material constituting the adhesive layer 13 is preferably such that the glass transition temperature (Tg) of the cured product is 150 ° C. or higher as the lower limit, and is 200 ° C. or higher. More preferably, it is particularly preferably 240 ° C. or higher. It is preferable for the glass transition temperature of the cured product to be equal to or higher than the above lower limit value because the cured product is not deformed during the temperature cycle test and stress is hardly generated. On the other hand, the upper limit value of the glass transition temperature of the cured product is not particularly limited, but is preferably 350 ° C. or less and more preferably 300 ° C. or less from the viewpoint of suppressing embrittlement of the cured product.

Here, the glass transition temperature of the cured material of the material constituting the adhesive layer 13 was measured using a dynamic viscoelasticity measuring instrument (manufactured by TA Instruments, DMA Q800), with a frequency of 11 Hz, an amplitude of 10 μm, and an increase. This is the temperature at the maximum point of tan δ (loss elastic modulus / storage elastic modulus) when the viscoelasticity in the tensile mode is measured by raising the temperature from 0 ° C. to 300 ° C. at a temperature rate of 3 ° C./min. The details of the glass transition temperature test method are as shown in Examples described later.

(1-4) 5% mass reduction temperature In the

sheets

1 and 2 for manufacturing a three-dimensional integrated multilayer circuit according to this embodiment, the cured product of the material constituting the adhesive layer 13 is a 5% mass reduction temperature by thermogravimetry. However, it is preferable that it is 350 degreeC or more, and it is especially preferable that it is 360 degreeC or more. When the 5% mass reduction temperature is 350 ° C. or higher, the cured product of the adhesive layer 13 has excellent resistance to high temperatures. Therefore, even when the cured product is exposed to a high temperature in the production of a laminated circuit, the generation of volatile components accompanying the decomposition of the components contained in the cured product is suppressed, and the performance of the laminated circuit is improved. Maintained. In addition, although it does not specifically limit as the upper limit of the said 5% mass reduction | decrease temperature, It is preferable that the said 5% mass reduction | decrease temperature is 500 degrees C or less normally. The measuring method of the 5% mass reduction temperature is as shown in the test examples described later.

(1-5) Storage Elasticity In the

sheets

1 and 2 for manufacturing a three-dimensional integrated laminated circuit according to this embodiment, the storage elastic modulus at 23 ° C. after the adhesive layer 13 is cured is 1.0 × 10 ² MPa or more. It is preferable that it is 1.0 * 10 < ³ > MPa or more especially. Further, the storage elastic modulus is preferably 1.0 × 10 ⁵ MPa or less, and particularly preferably 1.0 × 10 ⁴ MPa or less. When the storage elastic modulus is in the above range, when a laminated circuit is manufactured, a laminated body in which semiconductor chips and separated adhesive layers 13 are alternately laminated has good strength. Become. As a result, even when semiconductor chips are further laminated or when the laminated body is handled, the laminated state can be maintained well, and a laminated circuit having excellent quality can be manufactured. In addition, the measuring method of the said storage elastic modulus is as showing to the test example mentioned later.

(1-6) Heat generation start temperature and heat generation peak temperature by differential scanning calorimetry In the three-dimensional integrated

circuit manufacturing sheets

1 and 2 according to this embodiment, the adhesive layer 13 before curing is subjected to differential scanning calorimetry ( The exothermic onset temperature (TS) measured at a rate of temperature increase of 10 ° C./min by the DSC method is preferably in the range of 70 ° C. to 150 ° C., particularly in the range of 100 ° C. to 150 ° C. More preferably, it is in the range of 120 ° C to 150 ° C. When the heat generation start temperature (TS) is in the above range, the adhesive layer 13 can be cured at an unintended stage, for example, when receiving heat generated when a semiconductor wafer is diced by a dicing blade. In addition to being suppressed, the storage stability of the

production sheets

1 and 2 is excellent. In particular, when a plurality of adhesive layers 13 existing between semiconductor chips are cured at once after a plurality of semiconductor chips are stacked in order to produce a stacked circuit, an unintended stage before the completion of stacking of semiconductor chips is completed. It can suppress that the adhesive bond layer 13 hardens.

In the

sheets

1 and 2 for manufacturing a three-dimensional integrated laminated circuit according to this embodiment, the adhesive layer 13 before curing is an exothermic peak temperature measured at a heating rate of 10 ° C./min by a differential scanning calorimetry (DSC) method. (TP) is preferably exothermic onset temperature (TS) +5 to 60 ° C., particularly preferably TS + 5 to 50 ° C., and more preferably TS + 10 to 40 ° C. When the exothermic peak temperature (TP) is in the above range, when the adhesive layer 13 is cured, the time from the start to the completion of the curing is relatively short. Generally, when a laminated circuit is manufactured using an adhesive such as NCF, it takes time to cure the adhesive. Therefore, the tact time in the production of the laminated circuit is often defined by the time for curing the adhesive. Therefore, the time until the adhesive layer 13 is cured is short as described above, so that the tact time can be effectively shortened. In particular, when manufacturing a laminated circuit, there may be a case where a plurality of semiconductor chips are stacked (temporarily placed), and then a plurality of adhesive layers 13 existing between the semiconductor chips are finally cured at once in order to improve the process efficiency. is there. Even in such a case, if the exothermic peak temperature (TP) is in the above-mentioned range, it exists between the semiconductor chips stacked at the beginning of the process in an unintended stage such as before the stacking of the semiconductor chips is completed. Curing of the adhesive layer 13 to be performed can be suppressed.

In addition, the measuring method of the exothermic start temperature and the exothermic peak temperature by the differential scanning calorimetry is as shown in the test examples described later.

(1-7) Thickness of Adhesive Layer, etc. In the three-dimensional integrated laminated

circuit manufacturing sheets

1 and 2 according to this embodiment, the thickness (T2) of the adhesive layer 13 is preferably 2 μm or more, In particular, it is preferably 5 μm or more, more preferably 10 μm or more. The thickness (T2) is preferably 500 μm or less, particularly preferably 300 μm or less, and more preferably 100 μm or less. When the thickness (T2) of the adhesive layer 13 is 2 μm or more, it is possible to satisfactorily embed through electrodes or bumps existing in the semiconductor chip in the adhesive layer 13. Moreover, when the thickness (T2) of the adhesive layer 13 is 500 μm or less, when the semiconductor chip having the through electrode is bonded via the adhesive layer 13, the adhesive layer 13 oozes out to the side surface. Therefore, a highly reliable semiconductor device can be manufactured. In addition, let the thickness (T2) of the adhesive bond layer 13 be an average value at the time of measuring a total of 100 points | pieces at 50 mm space | interval in the sheet | seat 1 for manufacture.

In the

sheets

1 and 2 for manufacturing a three-dimensional integrated laminated circuit according to the present embodiment, the standard deviation of the thickness (T2) of the adhesive layer 13 is preferably 2.0 μm or less, and particularly 1.8 μm or less. It is preferable that it is 1.6 μm or less. When the standard deviation is 2.0 μm or less, the generation of voids can be more reliably prevented when the through-electrodes or bumps of the semiconductor wafer are embedded in the adhesive layer 13 using the

manufacturing sheets

1 and 2. Therefore, it is possible to effectively manufacture a laminated circuit having a uniform thickness and good quality. In particular, since the laminated circuit is obtained by laminating a plurality of semiconductor chips, it is difficult to make the thickness of the laminated circuit uniform, but the standard deviation of the thickness of the adhesive layer 13 is in the above range. By using the

sheets

1 and 2, voids can be more reliably prevented when embedding through electrodes or bumps of a semiconductor wafer in the adhesive layer 13, and a laminated circuit having a uniform thickness can be easily obtained. Become. In addition, the measuring method of the standard deviation of the thickness (T2) of the adhesive layer 13 is as shown in a test example described later.

In the sheet 2 for manufacturing a three-dimensional integrated laminated circuit according to the second embodiment including the base material 11, the ratio (T2 / T1) of the thickness (T2) of the adhesive layer 13 to the thickness (T1) of the base material 11 Is preferably 0.01 or more, particularly preferably 0.1 or more, and further preferably 0.4 or more. The ratio (T2 / T1) is preferably 1.5 or less, particularly preferably 1.0 or less, and more preferably 0.9 or less. When the ratio (T2 / T1) is in the above range, the thickness balance between the base material 11 and the adhesive layer 13 is good, and the handling property when the manufacturing sheet 2 is stuck to a semiconductor wafer is improved. In addition to being excellent, it becomes easy to adjust the applicability of application at the time of application. As a result, the pasting can be performed satisfactorily, and a laminated circuit having excellent quality can be manufactured. In particular, when the ratio (T2 / T1) is 0.01 or more, the relative thickness of the base material 11 in the manufacturing sheet 1 is relatively small, and the relative rigidity of the manufacturing sheet 1 is compared. Can be kept low. As a result, when the manufacturing sheet 1 is affixed to the semiconductor wafer, the through electrodes or bumps present on the semiconductor wafer can be easily embedded in the adhesive layer 13. On the other hand, when the ratio (T2 / T1) is 1.5 or less, the relative thickness of the base material 11 in the manufacturing sheet 1 is relatively large, and the relative rigidity of the manufacturing sheet 1 is compared. Highly maintained. As a result, the handling property of the manufacturing sheet 1 is excellent, and the manufacturing sheet 1 is easily attached to the semiconductor wafer. In addition, let the thickness (T1) of the base material 11 be the average value at the time of measuring a total of 100 points at intervals of 50 mm in the manufacturing sheet 1.

(2) Material In the three-dimensional integrated laminated

circuit manufacturing sheets

1 and 2 according to the present embodiment, the adhesive layer 13 is made of a material that satisfies the 90 ° C. melt viscosity and the average linear expansion coefficient described above.

(2-1) Thermosetting component The material constituting the adhesive layer 13 preferably contains a thermosetting component. The thermosetting component is not particularly limited as long as it is an adhesive component usually used for connecting semiconductor chips. Specific examples include epoxy resins, phenol resins, melamine resins, urea resins, polyester resins, urethane resins, acrylic resins, polyimide resins, benzoxazine resins, phenoxy resins, and the like. A combination of the above can be used. Among these, from the viewpoint of adhesiveness and the like, an epoxy resin and a phenol resin are preferable, and an epoxy resin is particularly preferable.

Epoxy resin has the property of forming a three-dimensional network upon heating and forming a hardened product. As such an epoxy resin, various conventionally known epoxy resins are used. Specifically, glycidyl ethers of phenols such as bisphenol A, bisphenol F, resorcinol, phenyl novolac, cresol novolac; butanediol, Glycidyl ether of alcohols such as polyethylene glycol and polypropylene glycol; Glycidyl ether of carboxylic acid such as phthalic acid, isophthalic acid and tetrahydrophthalic acid; Glycidyl type in which active hydrogen bonded to nitrogen atom such as aniline isocyanurate is substituted with glycidyl group Or an alkyl glycidyl type epoxy resin; vinylcyclohexane diepoxide, 3,4-epoxycyclohexylmethyl-3,4-dicyclohexanecarboxylate, 2- (3,4- Poxy) cyclohexyl-5,5-spiro (3,4-epoxy) cyclohexane-m-dioxane or the like, so-called alicyclic in which epoxy is introduced by, for example, oxidizing a carbon-carbon double bond in the molecule Mention may be made of type epoxides. In addition, an epoxy resin having a biphenyl skeleton, a dicyclohexadiene skeleton, a naphthalene skeleton, or the like can also be used. These epoxy resins can be used alone or in combination of two or more.

The content of the thermosetting component in the material constituting the adhesive layer 13 is preferably a lower limit of 5% by mass or more, based on the total amount of the materials constituting the adhesive layer 13, and 10% by mass. More preferably, it is the above. The upper limit of the content of the thermosetting component is preferably 75% by mass or less, and more preferably 55% by mass or less. When the content of the thermosetting component is within the above range, the above-described heat generation start temperature and heat generation peak temperature can be easily adjusted to the above range.

(2-2) Curing Agent / Curing Catalyst When the material constituting the adhesive layer 13 contains the thermosetting component described above, the material preferably further contains a curing agent and a curing catalyst.

Although it does not specifically limit as a hardening | curing agent, Phenolics, amines, thiols, etc. are mentioned, According to the kind of thermosetting component mentioned above, it can select suitably. For example, when an epoxy resin is used as the curable component, phenols are preferable from the viewpoint of reactivity with the epoxy resin.

Examples of phenols include bisphenol A, tetramethyl bisphenol A, diallyl bisphenol A, biphenol, bisphenol F, diallyl bisphenol F, triphenylmethane type phenol, tetrakisphenol, novolac type phenol, cresol novolac resin, and the like. Can be used singly or in combination of two or more.

Further, the curing catalyst is not particularly limited, and examples thereof include imidazole-based, phosphorus-based, and amine-based, and can be appropriately selected according to the type of the thermosetting component described above. In addition, it is preferable to use a latent curing catalyst that does not activate under a predetermined condition and activates when heated to a temperature equal to or higher than the high pressure temperature for melting the solder. Further, the latent curing catalyst is preferably used as a microencapsulated latent curing catalyst.

For example, when using an epoxy resin as a curable component, use an imidazole-based curing catalyst as a curing catalyst from the viewpoint of reactivity with the epoxy resin, storage stability, physical properties of the cured product, curing speed, etc. Is preferred. A known catalyst can be used as the imidazole-based curing catalyst, but an imidazole catalyst having a triazine skeleton is preferable from the viewpoint of excellent curability, storage stability, and connection reliability. These may be used alone or in combination of two or more. These may be used as a microencapsulated latent curing catalyst. The melting point of the imidazole-based curing catalyst is preferably 200 ° C. or higher, particularly preferably 250 ° C. or higher, from the viewpoint of excellent curability, storage stability, and connection reliability.

In this embodiment, the lower limit of the content of the curing catalyst in the material constituting the adhesive layer 13 is preferably 0.1% by mass or more based on the total amount of the materials constituting the adhesive layer 13. The content is more preferably 0.2% by mass or more, and particularly preferably 0.4% by mass or more. The upper limit of the content of the curing catalyst is preferably 10% by mass or less, more preferably 5% by mass or less, and particularly preferably 3% by mass or less. If the content of the curing catalyst in the material constituting the adhesive layer 13 is equal to or higher than the lower limit, the thermosetting component can be sufficiently cured. On the other hand, when the content of the curing catalyst is not more than the above upper limit value, the storage stability of the adhesive layer 13 becomes good.

(2-3) High molecular weight component The material constituting the adhesive layer 13 preferably contains a high molecular weight component other than the thermosetting component described above. By containing the high molecular weight component, the 90 ° C. melt viscosity and the average linear expansion coefficient of the material can easily satisfy the numerical range described above.

Examples of the high molecular weight component include (meth) acrylic resin, phenoxy resin, polyester resin, polyurethane resin, polyimide resin, polyamideimide resin, siloxane-modified polyimide resin, polybutadiene resin, polypropylene resin, and styrene-butadiene-styrene copolymer. , Styrene-ethylene-butylene-styrene copolymer, polyacetal resin, polyvinyl acetal resin including polyvinyl butyral resin, butyl rubber, chloroprene rubber, polyamide resin, acrylonitrile-butadiene copolymer, acrylonitrile-butadiene-acrylic acid copolymer , Acrylonitrile-butadiene-styrene copolymer, polyvinyl acetate, nylon, etc., can be used alone or in combination of two or more.

In addition, “(meth) acrylic acid” in this specification means both acrylic acid and methacrylic acid. The same applies to other similar terms such as “(meth) acrylic resin”.

Among the high molecular weight components described above, it is preferable to use one or more selected from the group consisting of polyvinyl acetal resins, polyester resins, and phenoxy resins. The material constituting the production sheet contains these high molecular weight components, so that the 90 ° C. melt viscosity and the average linear expansion coefficient are both low, and as a result, these values are within the above-described numerical range. It becomes easy.

Here, the polyvinyl acetal resin is obtained by acetalizing polyvinyl alcohol obtained by saponifying polyvinyl acetate with aldehyde. Examples of the aldehyde used for acetalization include n-butyraldehyde, n-hexyl aldehyde, n-valeraldehyde and the like. As the polyvinyl acetal resin, it is also preferable to use a polyvinyl butyral resin acetalized with n-butyraldehyde.

Examples of polyester resins include polyester resins obtained by polycondensation of dicarboxylic acid components and diol components such as polyethylene terephthalate resin, polybutylene terephthalate resin, and polyethylene oxalate resin; urethane modification obtained by reacting these with a polyisocyanate compound Examples thereof include modified polyester resins such as polyester resins; polyester resins grafted with acrylic resins and / or vinyl resins, and the like can be used alone or in combination of two or more.

Further, when the material constituting the adhesive layer 13 contains a polyvinyl acetal resin or a polyester resin as the high molecular weight component, it is particularly preferable to further contain a phenoxy resin. When the phenoxy resin is further contained, the material constituting the adhesive layer 13 is more likely to satisfy the numerical range described above in terms of 90 ° C. melt viscosity and average linear expansion coefficient.

The phenoxy resin is not particularly limited, and examples thereof include bisphenol A type, bisphenol F type, bisphenol A / bisphenol F copolymer type, biphenol type, and biphenyl type.

The lower limit value of the softening point of the high molecular weight component is preferably 50 ° C. or higher, more preferably 100 ° C. or higher, and particularly preferably 120 ° C. or higher. Moreover, the upper limit value of the softening point of the high molecular weight component is preferably 200 ° C. or less, more preferably 180 ° C. or less, and particularly preferably 150 ° C. or less. By containing a high molecular weight component having a softening point equal to or higher than the lower limit, the average linear expansion coefficient of the material constituting the adhesive layer 13 can be reduced, and the above-described numerical range is easily satisfied. Moreover, the embrittlement of the adhesive bond layer 13 can be suppressed as a softening point is below the said upper limit. The softening point is a value measured based on ASTM D1525.

The lower limit of the glass transition temperature of the high molecular weight component is preferably 50 ° C. or higher, more preferably 60 ° C. or higher, and particularly preferably 80 ° C. or higher. The high molecular weight component preferably has an upper limit of glass transition temperature of 250 ° C. or lower, more preferably 200 ° C. or lower, and particularly preferably 180 ° C. or lower. By including a high molecular weight component having a glass transition temperature equal to or higher than the lower limit, the average linear expansion coefficient of the material constituting the adhesive layer 13 can be reduced, and the above-described numerical range is easily satisfied. Moreover, it becomes what was excellent in compatibility with another material as a glass transition temperature is below the said upper limit. In addition, the glass transition temperature of a high molecular weight component is the value measured using the differential scanning calorimeter, and a specific measuring method is shown in the Example mentioned later.

The high molecular weight component preferably has a weight average molecular weight of 10,000 or more, more preferably 30,000 or more, and particularly preferably 50,000 or more. Further, the upper limit is preferably 1,000,000 or less, more preferably 700,000 or less, and particularly preferably 500,000 or less. It is preferable for the weight average molecular weight to be not less than the above lower limit value, since the film viscosity can be maintained and the melt viscosity can be lowered. Moreover, since a compatibility with low molecular weight components, such as a thermosetting component, improves that a weight average molecular weight is below the said upper limit, it is preferable. In addition, the weight average molecular weight in this specification is the value of standard polystyrene conversion measured by the gel permeation chromatography (GPC) method.

The content of the high molecular weight component in the material constituting the adhesive layer 13 is preferably a lower limit of 3% by mass or more, preferably 5% by mass or more, based on the total amount of the materials constituting the adhesive layer 13. More preferably, it is particularly preferably 7% by mass or more. The upper limit of the content of the high molecular weight component is preferably 95% by mass or less, more preferably 90% by mass or less, and particularly preferably 80% by mass or less. When the content of the high molecular weight component is equal to or higher than the lower limit, the 90 ° C. melt viscosity of the material constituting the adhesive layer 13 can be further reduced, and the above numerical range is easily satisfied. On the other hand, when the content of the high molecular weight component is not more than the above upper limit value, the average linear expansion coefficient of the material constituting the adhesive layer 13 can be further reduced, and the above-described numerical range is easily satisfied.

(2-4) Inorganic filler The material constituting the adhesive layer 13 preferably contains an inorganic filler. Since the material constituting the adhesive layer 13 contains an inorganic filler, the average linear expansion coefficient becomes a low value. Therefore, when the

sheets

1 and 2 for manufacturing a three-dimensional integrated multilayer circuit according to this embodiment are used. The connection reliability between the semiconductor chips can be made high.

The inorganic filler that can be used in the present embodiment is not particularly limited, but silica, alumina, glass, titanium oxide, mica, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, oxidation Examples include calcium, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whisker, boron nitride, crystalline silica, amorphous silica, mullite, cordierite and other complex oxides, montmorillonite, smectite, etc. Can be used singly or in combination of two or more. Among these, silica filler is preferable. The shape of the silica filler is preferably spherical.

In addition, the inorganic filler is preferably surface-modified with a silane coupling agent or the like. When the inorganic filler is surface-modified, a bond can be formed between the filler and other components. As a result, the material constituting the adhesive layer 13 can be prevented from being thickened, and the melt viscosity is low. And the average linear expansion coefficient of the material can be further reduced. As the silane coupling agent, a silane coupling agent having a hydrophobic functional group such as an alkyl group, a vinyl group, an acryloyl group, a methacryloyl group, a phenyl group or an aminophenyl group is preferable from the viewpoint of easily reducing the melt viscosity. .

The lower limit of the average particle size of the inorganic filler is preferably 10 nm or more, more preferably 20 nm or more, and particularly preferably 30 nm or more. The average particle size of the inorganic filler is preferably 200 nm or less, more preferably 150 nm or less, and particularly preferably 100 nm or less. When the average particle size of the inorganic filler is not less than the above lower limit, both the transparency of the sheet and the low melt viscosity can be achieved. Moreover, 90 degreeC melt viscosity in the material which comprises the adhesive bond layer 13 can be maintained to a low value as the average particle diameter of an inorganic filler is below the said upper limit.

The maximum particle size of the inorganic filler is preferably 1000 nm or less, and more preferably 500 nm or less. When the maximum particle size of the inorganic filler is 1000 nm or less, it becomes easy to fill the adhesive layer 13 with the inorganic filler, and as a result, the average linear expansion coefficient of the material constituting the adhesive layer 13 satisfies the numerical range described above. It is easy to satisfy, and it is possible to achieve both the transparency of the sheet and the low melt viscosity. Further, since the maximum particle diameter of the inorganic filler is 1000 nm or less, the through electrodes (or bumps provided at the end portions of the through electrodes) in the laminated circuit are easily electrically connected to each other, and the laminated layer has high reliability. A circuit can be effectively manufactured.

Further, the content of the inorganic filler in the material constituting the adhesive layer 13 is preferably 35% by mass or more, and 40% by mass or more, based on the total amount of the materials constituting the adhesive layer 13. More preferably, it is particularly preferably 50% by mass or more. The upper limit of the content of the inorganic filler is preferably 64% by mass or less, more preferably 60% by mass or less, and particularly preferably 56% by mass or less. When the content of the inorganic filler in the material constituting the adhesive layer 13 is equal to or more than the above lower limit value, the average linear expansion coefficient of the material can be further reduced, and the above-described numerical range is easily satisfied. On the other hand, when the content of the inorganic filler is not more than the above upper limit value, the 90 ° C. melt viscosity of the material can be maintained at a low value, and the above-described numerical range is easily satisfied.

(2-5) Component having a flux function In this embodiment, when the through electrode or bump of the semiconductor chip is joined by solder, the material constituting the adhesive layer 13 is a component having a flux function (hereinafter referred to as “flux component”). It is preferable that it contains. The flux component has an action of removing the metal oxide film formed on the electrode surface, makes the electrical connection between the electrodes by solder more reliable, and can improve the connection reliability at the solder joint. .

Although it does not specifically limit as a flux component, It is preferable that it is a component which has a phenolic hydroxyl group and / or a carboxyl group, and it is especially preferable that it is a component which has a carboxyl group. The component having a carboxyl group has a flux function and also has a function as a curing agent when an epoxy resin described later is used as a thermosetting component. For this reason, the component having a carboxyl group reacts and is consumed as a curing agent after the solder bonding is completed, so that it is possible to suppress problems caused by excessive flux components.

Specific flux components include, for example, glutaric acid, 2-methylglutaric acid, orthoanisic acid, diphenolic acid, adipic acid, acetylsalicylic acid, benzoic acid, benzylic acid, azelaic acid, benzylbenzoic acid, malonic acid, 2, 2-bis (hydroxymethyl) propionic acid, salicylic acid, o-methoxybenzoic acid, m-hydroxybenzoic acid, succinic acid, 2,6-dimethoxymethylparacresol, benzoic hydrazide, carbohydrazide, malonic dihydrazide, succinic dihydrazide , Glutaric acid dihydrazide, salicylic acid hydrazide, iminodiacetic acid dihydrazide, itaconic acid dihydrazide, citric acid trihydrazide, thiocarbohydrazide, benzophenone hydrazone, 4,4'-oxybisbenzenesulfonylhydrazide, adipine Dihydrazide, rosin derivatives and the like, which may be used alone or in admixture.

Examples of rosin derivatives include gum rosin, tall rosin, wood rosin, polymerized rosin, hydrogenated rosin, formylated rosin, rosin ester, rosin modified maleic resin, rosin modified phenolic resin, rosin modified alkyd resin, and the like.

Among these, it is particularly preferable to use at least one selected from 2-methylglutaric acid, adipic acid and rosin derivatives. Since 2-methylglutaric acid and adipic acid have two carboxyl groups in the molecule in the material constituting the adhesive layer 13 even though the molecular weight is relatively small, the flux function is excellent even when added in a small amount. In this embodiment, it can be particularly preferably used. Since the rosin derivative has a high softening point and can impart a flux property while maintaining a low linear expansion coefficient, it can be used particularly suitably in this embodiment.

At least one of the melting point and softening point of the flux component is preferably 80 ° C. or higher, more preferably 110 ° C. or higher, and further preferably 130 ° C. or higher. It is preferable that at least one of the melting point and the softening point of the flux component is in the above range because a more excellent flux function can be obtained and outgas can be reduced. In addition, although the upper limit of melting | fusing point and softening point of a flux component is not specifically limited, What is necessary is just to be below melting | fusing point of solder, for example.

In the present embodiment, the content of the flux component in the material constituting the adhesive layer 13 is preferably such that the lower limit is 1% by mass or more based on the total amount of the materials constituting the adhesive layer 13. The content is more preferably at least 5% by mass, and particularly preferably at least 5% by mass. The upper limit of the content of the flux component is preferably 20% by mass or less, more preferably 15% by mass or less, and particularly preferably 10% by mass or less. When the content of the flux component in the material constituting the adhesive layer 13 is not less than the above lower limit value, the electrical connection between the electrodes by solder is made more reliable, and the connection reliability at the solder joint is further improved. Can do. On the other hand, when the content of the flux component is not more than the above upper limit value, it is possible to prevent problems such as ion migration due to an excessive flux component.

(2-6) Other components The adhesive layer 13 further includes a plasticizer, a stabilizer, a tackifier, a colorant, a coupling agent, an antistatic agent, an antioxidant as a material constituting the adhesive layer 13. An agent, conductive particles and the like may be contained.

For example, when the material constituting the adhesive layer 13 contains conductive particles or the like, and anisotropic conductivity is imparted to the

sheets

1 and 2 for manufacturing a three-dimensional integrated laminated circuit, the embodiment complements the solder joint. Alternatively, the semiconductor chips can be electrically bonded to each other in a mode different from solder bonding.

2. Pressure-sensitive adhesive layer (1) material In the sheet 2 for manufacturing a three-dimensional integrated laminated circuit according to the second embodiment including the pressure-sensitive adhesive layer 12, the pressure-sensitive adhesive layer 12 may be composed of a non-curable pressure-sensitive adhesive, or You may be comprised from a curable adhesive. As will be described later, when the sheet 2 for producing a three-dimensional integrated laminated circuit according to the present embodiment is used in a method for producing a laminated circuit, the adhesive layer 13 is peeled from the laminate of the base material 11 and the pressure-sensitive adhesive layer 12. The Therefore, from the viewpoint of easily performing the peeling, the pressure-sensitive adhesive layer 12 is preferably composed of a curable pressure-sensitive adhesive, and the pressure-sensitive adhesive strength is reduced by curing.

When the pressure-sensitive adhesive layer 12 is composed of a curable pressure-sensitive adhesive, the pressure-sensitive adhesive may be an energy ray-curable pressure-sensitive adhesive or a thermosetting pressure-sensitive adhesive. Here, since the adhesive layer 12 and the adhesive layer 13 are cured at different stages, when the adhesive layer 13 has thermosetting properties, the adhesive layer 12 is made of an energy ray curable adhesive. Preferably, the adhesive layer 13 is composed of a thermosetting adhesive when the adhesive layer 13 has energy ray curability. However, since the adhesive layer 13 preferably has thermosetting properties for the reasons described above, the pressure-sensitive adhesive layer 12 is preferably composed of an energy ray-curable pressure-sensitive adhesive.

As the non-curable pressure-sensitive adhesive, those having desired adhesive strength and removability are preferable, for example, acrylic pressure-sensitive adhesive, rubber-based pressure-sensitive adhesive, silicone-based pressure-sensitive adhesive, urethane-based pressure-sensitive adhesive, polyester-based pressure-sensitive adhesive, A polyvinyl ether-based pressure-sensitive adhesive or the like can be used. Among these, an acrylic pressure-sensitive adhesive is preferable from the viewpoint of effectively suppressing peeling at the interface between the pressure-sensitive adhesive layer 12 and the adhesive layer 13 in an unintended stage such as a dicing process.

The energy beam curable pressure-sensitive adhesive may be mainly composed of a polymer having energy beam curable properties, or at least one of a non-energy beam curable polymer (a polymer not having energy beam curable properties). The main component may be a mixture of the monomer and / or oligomer having the above energy ray-curable group. Further, it may be a mixture of a polymer having energy ray curable properties and a non-energy ray curable polymer, a polymer having energy ray curable properties and a monomer having at least one energy ray curable group and / or It may be a mixture with an oligomer or a mixture of these three.

The polymer having energy ray curability is preferably a (meth) acrylic acid ester (co) polymer in which a functional group having energy ray curability (energy ray curable group) is introduced into a side chain. This polymer is preferably obtained by reacting an acrylic copolymer having a functional group-containing monomer unit with an unsaturated group-containing compound having a functional group bonded to the functional group.

As the monomer and / or oligomer having at least one energy ray-curable group, for example, an ester of a polyhydric alcohol and (meth) acrylic acid or the like can be used.

As the non-energy ray curable polymer component, for example, an acrylic copolymer having the functional group-containing monomer unit described above can be used.

(2) Physical Properties, etc. In the sheet 2 for manufacturing a three-dimensional integrated laminated circuit according to the present embodiment, the storage elastic modulus at 23 ° C. of the pressure-sensitive adhesive layer 12 is preferably 1 × 10 ³ Pa or more, particularly 1 × 10. It is preferable that it is ⁴ Pa or more. The storage elastic modulus is preferably 1 × 10 ⁹ Pa or less, and particularly preferably 1 × 10 ⁸ Pa or less. In addition, the said storage elastic modulus shall say the storage elastic modulus before hardening, when the adhesive layer 12 is comprised from a curable adhesive. Since the storage elastic modulus at 23 ° C. of the pressure-sensitive adhesive layer 12 is in the above range, when the manufacturing sheet 2 is affixed to the semiconductor wafer, the penetrating electrodes or bumps existing on the semiconductor wafer are satisfactorily applied to the adhesive layer 13. It becomes possible to embed. Further, when the

manufacturing sheet

1 or 2 is used to back grind the surface of the semiconductor wafer where the bumps are not formed, warpage or dimple generation of the semiconductor wafer can be suppressed. In addition, the measuring method of the storage elastic modulus in 23 degreeC of the adhesive layer 12 is as showing to the test example mentioned later.

Although the thickness of the pressure-sensitive adhesive layer 12 is not particularly limited, for example, it is preferably 1 μm or more, and particularly preferably 10 μm or more. The thickness is preferably, for example, 100 μm or less, and particularly preferably 50 μm or less. When the thickness of the pressure-sensitive adhesive layer 12 is 1 μm or more, the pressure-sensitive adhesive layer 12 can exhibit good adhesive force. Moreover, when the said thickness is 100 micrometers or less, it becomes possible to suppress that the adhesive layer 12 becomes unnecessary thickness, and it becomes possible to reduce cost.

3. Base Material (1) Material In the sheet 2 for manufacturing a three-dimensional integrated laminated circuit according to the second embodiment including the base material 11, the material constituting the base material 11 is not particularly limited. However, when the manufacturing sheet 2 is a dicing sheet integrated adhesive sheet, the material constituting the base material 11 is preferably a material generally used for the base material constituting the dicing sheet. For example, the material of the base material 11 is polyethylene, polypropylene, polybutene, polybutadiene, polymethylpentene, polyvinyl chloride, vinyl chloride copolymer, polyethylene terephthalate, polybutylene terephthalate, polyurethane, ethylene vinyl acetate copolymer. , Ionomer, ethylene / (meth) acrylic acid copolymer, ethylene / (meth) acrylic acid ester copolymer, polystyrene, vinyl polyisoprene, polycarbonate, polyolefin, etc., one or more of these Can be used.

Further, when the production sheet 2 is a back grind sheet integrated adhesive sheet, the material constituting the base material 11 is preferably a material generally used for the base material constituting the back grind sheet. For example, as a material of such a base material 11, what consists of resin, such as a polyethylene terephthalate, polyethylene, a polypropylene, an ethylene-vinyl acetate copolymer, is mentioned, The mixture of 1 type, or 2 or more types of these is used. Can be used.

The surface on the pressure-sensitive adhesive layer 12 side of the substrate 11 may be subjected to surface treatment such as primer treatment, corona treatment, plasma treatment, etc., in order to improve the adhesion with the pressure-sensitive adhesive layer 12.

(2) Physical properties etc. In the sheet 2 for producing a three-dimensional integrated laminated circuit according to the present embodiment, the tensile modulus of elasticity of the substrate 11 at 23 ° C. is preferably 100 MPa or more, particularly preferably 200 MPa or more, Furthermore, it is preferable that it is 300 MPa or more. Further, the tensile elastic modulus is preferably 5000 MPa or less, particularly preferably 1000 MPa or less, and further preferably 400 MPa or less. Since the tensile elastic modulus at 23 ° C. of the base material 11 is within the above range, when the manufacturing sheet 2 is affixed to the semiconductor wafer, the through electrodes or bumps existing on the semiconductor wafer are satisfactorily applied to the adhesive layer 13. It becomes possible to embed. Moreover, when making the manufacturing sheet 2 into a dicing sheet integrated adhesive sheet, the manufacturing sheet 2 is expanded and the space | interval of semiconductor chips is because the tensile elasticity modulus in 23 degreeC of the base material 11 exists in the said range. It is preferable because the base material 11 is less likely to break when expanding. In addition, the measuring method of the tensile elasticity modulus in 23 degreeC of the base material 11 is as showing to the test example mentioned later.

Although the thickness (T1) of the base material 11 is not particularly limited, for example, it is preferably 10 μm or more, and particularly preferably 15 μm or more. Further, the thickness (T1) is, for example, preferably 500 μm or less, and particularly preferably 100 μm or less. Since the thickness (T1) of the base material 11 is within the above range, the value of the ratio (T2 / T1) of the thickness (T2) of the adhesive layer 12 to the thickness (T1) of the base material 11 described above is set. It becomes easy to set the above-mentioned range, and the handling property when sticking the

manufacturing sheets

1 and 2 to the semiconductor wafer becomes excellent. As a result, it is possible to effectively manufacture a laminated circuit having excellent quality.

4). Release Sheet The configuration of the release sheet 14 is arbitrary, and examples thereof include a plastic film such as a polyester film such as polyethylene terephthalate, polybutylene terephthalate, and polyethylene naphthalate, and a polyolefin film such as polypropylene and polyethylene. It is preferable that a peeling process is performed on these peeling surfaces (surfaces in contact with the adhesive layer 13). Examples of the release agent used for the release treatment include silicone-based, fluorine-based, and long-chain alkyl-based release agents.

Although there is no restriction | limiting in particular about the thickness of a peeling sheet, Usually, they are 20 micrometers or more and 250 micrometers or less.

5. Method for Manufacturing Sheet for Manufacturing 3D Integrated Layered Circuit A sheet 1 for manufacturing a 3D integrated layered circuit according to the first embodiment can be manufactured in the same manner as a sheet for manufacturing a conventional 3D integrated layered circuit. For example, when manufacturing the sheet 1 for manufacturing a three-dimensional integrated laminated circuit including the release sheet 14, a material for forming the adhesive layer 13 and, if desired, a coating liquid further containing a solvent or a dispersion medium is prepared, and the release sheet is prepared. The coating sheet is formed by applying the coating liquid on the release surface of No. 14 with a die coater, curtain coater, spray coater, slit coater, knife coater, etc., and drying the coating film. Can be manufactured. The properties of the coating liquid are not particularly limited as long as it can be applied, and may contain a component for forming the adhesive layer 13 as a solute or a dispersoid. . The release sheet 14 may be peeled off as a process material, or may protect the adhesive layer 13 until being attached to the semiconductor wafer.

Moreover, as a manufacturing method of the laminated body in which the two release sheets 14 are respectively laminated on both surfaces of the sheet 1 for manufacturing a three-dimensional integrated laminated circuit, a coating liquid is applied on the release surface of the release sheet 14 described above. A coating film is formed and dried to form a laminate composed of the adhesive layer 13 and the release sheet 14, and the other side of the adhesive layer 13 of the laminate opposite to the release sheet 14 is provided as another release sheet. It can affix on the 14 peeling surface, and can obtain the laminated body which consists of peeling sheet 14 / adhesive layer 13 / release sheet 14. FIG. The release sheet 14 in this laminate may be peeled off as a process material, or the adhesive layer 13 may be protected until being attached to a semiconductor wafer.

The three-dimensional integrated circuit manufacturing sheet 2 according to the second embodiment can be manufactured in the same manner as the conventional three-dimensional integrated circuit manufacturing sheet 2. For example, a laminate of the adhesive layer 13 and the release sheet 14 and a laminate of the pressure-sensitive adhesive layer 12 and the base material 11 are respectively produced, and the lamination is performed so that the adhesive layer 13 and the pressure-sensitive adhesive layer 12 are in contact with each other. The sheet | seat 2 for manufacture can be obtained by bonding a body.

The laminate of the adhesive layer 13 and the release sheet 14 is prepared by preparing the above-described coating liquid for forming the adhesive layer 13 and applying the coating liquid onto the release surface of the release sheet 14 by the application method described above. It can be obtained by forming a film and drying the coating film.

Examples of the solvent include organic solvents such as toluene, ethyl acetate, and methyl ethyl ketone. By blending these organic solvents to obtain a solution with an appropriate solid content concentration, variation in the thickness (T2) of the adhesive layer 13 can be suppressed, and adhesion having the above-described standard deviation with respect to the thickness (T2). It becomes easy to form the agent layer 13. In particular, the solid content concentration of the coating solution is preferably 5% by mass or more, and particularly preferably 10% by mass or more from the viewpoint of uniformly coating the coating solution. From the same viewpoint, the solid content concentration is preferably 55% by mass or less, and preferably 50% by mass or less. When the solid content concentration is 5% by mass or more, occurrence of repellency or the like is suppressed when forming a coating film, and the solvent can be easily dried, resulting in variations in the thickness and physical properties of the adhesive layer 13. It becomes easier to suppress. Moreover, aggregation of the filler in a coating liquid is suppressed because the said solid content concentration is 55 mass% or less, it becomes easy to send a coating liquid, and it generate | occur | produces continuously in the direction perpendicular | vertical to an application direction. Generation | occurrence | production of the coating nonuniformity (horizontal step nonuniformity) is suppressed, and generation | occurrence | production of the dispersion | variation in the thickness of the adhesive bond layer 13 can be suppressed more. The viscosity at 25 ° C. of the coating solution measured with a B-type viscometer is preferably 20 mPa · s or more, and particularly preferably 25 mPa · s or more. The viscosity is preferably 500 mPa · s or less, and particularly preferably 100 mPa · s or less.

The laminate of the pressure-sensitive adhesive layer 12 and the base material 11 is prepared by preparing a coating liquid containing a material constituting the pressure-sensitive adhesive layer 12 and, if desired, further a solvent or a dispersion medium. It can be obtained by coating on one side to form a coating film and drying the coating film. Moreover, as another production method of the laminate of the pressure-sensitive adhesive layer 12 and the base material 11, the pressure-sensitive adhesive layer 12 is formed on the release surface of the process release sheet, and then the pressure-sensitive adhesive layer 12 is formed on the base material 11. The laminate of the pressure-sensitive adhesive layer 12 and the substrate 11 may be obtained by transferring to one side and peeling the process release sheet from the pressure-sensitive adhesive layer 12.

[Method of manufacturing three-dimensional integrated laminated circuit]
A three-dimensional integrated multilayer circuit can be manufactured using the

sheets

1 and 2 for manufacturing a three-dimensional integrated multilayer circuit according to the present embodiment. Below, the example of the manufacturing method is demonstrated.

First, the three-dimensional integrated laminated

circuit manufacturing sheets

1 and 2 according to this embodiment are attached to one side of a semiconductor wafer having through electrodes. Specifically, the surface on the adhesive layer 13 side of the three-dimensional integrated laminated

circuit manufacturing sheets

1 and 2 is attached to one side of the semiconductor wafer. Here, the

sheets

1 and 2 for manufacturing a three-dimensional integrated circuit according to this embodiment have a 90 ° C. melt viscosity of 1.0 × 10 ⁰ to 5.0 × 10 before the material constituting the adhesive layer 13 is cured. ^Since it is ⁵ Pa · s, it is possible to satisfactorily follow the unevenness caused by the through electrodes of the semiconductor wafer, and to suppress the generation of voids at the interface between the adhesive layer 13 and the semiconductor wafer.

Note that a semiconductor wafer having a through electrode may be weak in strength. Therefore, the semiconductor wafer may be reinforced by fixing to a support such as support glass via a temporary fixing material. In this case, the surface of the laminated body on the semiconductor wafer side and the three-dimensional integrated laminated

circuit manufacturing sheets

1 and 2 are bonded together, and then the support is peeled off together with the temporary fixing material.

When using the three-dimensional integrated laminated circuit manufacturing sheet 1 according to the first embodiment, a dicing sheet is further laminated. In this case, the dicing sheet may be attached to the semiconductor wafer first, and the manufacturing sheet 1 may be attached to the surface of the semiconductor wafer opposite to the dicing sheet. Alternatively, the manufacturing sheet 1 may be attached to the semiconductor wafer first, and the dicing sheet may be attached to the surface of the semiconductor wafer opposite to the manufacturing sheet 1. Or you may affix a dicing sheet on the surface at the side of the manufacturing sheet 1 of the laminated body obtained by sticking the manufacturing sheet 1 with respect to a semiconductor wafer. On the other hand, when using the 3D integrated laminated circuit manufacturing sheet 2 according to the second embodiment, it is not necessary to further stack the dicing sheet, and the following dicing process can be performed on the manufacturing sheet 2.

Next, the semiconductor wafer is cut into individual chips (dicing process). At this time, the adhesive layer 13 is also cut together with the semiconductor wafer. The method for cutting the wafer is not particularly limited, and it is performed by various conventionally known dicing methods. For example, there is a method of cutting a semiconductor wafer using a dicing blade. Also, other dicing methods such as laser dicing may be employed.

After the dicing process, pick up the semiconductor chip. At this time, the semiconductor chip is picked up with the adhesive layer 13 separated into pieces. That is, the semiconductor chip to which the adhesive layer 13 is attached is peeled from the pressure-sensitive adhesive layer of the dicing sheet or the pressure-sensitive adhesive layer 12 of the sheet 2 for manufacturing a three-dimensional integrated laminated circuit. In addition, when the adhesive layer 12 is comprised from an energy-beam curable adhesive, it is preferable to irradiate an energy ray with respect to the adhesive layer 12 before a pick-up. As a result, the adhesive strength of the pressure-sensitive adhesive is reduced, so that the semiconductor chip can be easily picked up. If necessary, the interval between the semiconductor chips may be expanded by expanding the dicing sheet or the sheet 2 for manufacturing a three-dimensional integrated laminated circuit before the pickup.

Subsequently, the semiconductor chip with an adhesive layer is placed on the circuit board. The semiconductor chip with an adhesive layer is positioned on the circuit board so that the electrodes on the semiconductor chip side and the electrodes on the circuit board face each other.

Further, the semiconductor chip with an adhesive layer and the circuit board are heated and pressurized, and then cooled. As a result, the semiconductor chip and the circuit board are bonded via the adhesive layer 13, and the electrode of the semiconductor chip and the electrode of the chip mounting portion on the circuit board are electrically connected via the solder bumps formed on the semiconductor chip. To be joined. The soldering conditions depend on the metal composition to be used. For example, in the case of Sn—Ag, it is preferable to heat at 200 to 300 ° C. for 1 to 30 seconds.

When the solder bonding is performed, the adhesive layer 13 interposed between the semiconductor chip and the circuit board is cured. Curing can be performed, for example, by heating at 100 to 200 ° C. for 1 to 120 minutes. Moreover, you may perform this hardening process on pressurization conditions. Further, such a curing step may be omitted when the curing of the adhesive layer 13 is completed in the above-described solder bonding step.

Subsequently, a new semiconductor chip with an adhesive layer is stacked on the semiconductor chip bonded onto the circuit board as described above. At this time, the surface on the adhesive layer 13 side of the new semiconductor chip with an adhesive layer and the surface of the semiconductor chip laminated on the circuit board opposite to the circuit board are in contact with each other, and the two semiconductor chips Lamination is performed so that the through electrodes are electrically connected to each other. Thereafter, solder bonding is performed between the penetrating electrode of the newly stacked semiconductor chip and the penetrating electrode of the semiconductor chip stacked on the circuit board, and an adhesive layer 13 interposed between the semiconductor chips is further formed. Harden. The solder bonding and the curing of the adhesive layer 13 at this time can be performed by the method and conditions described above. Thereby, a laminated body in which two semiconductor chips are laminated on the circuit board is obtained.

By repeating the procedure of laminating the semiconductor chip with the adhesive layer on the semiconductor chip laminated on the circuit board and curing the solder joint and the adhesive layer 13 as described above, the plurality of semiconductor chips become adhesive layers. A laminated circuit bonded with 13 cured products can be obtained. In such a laminated circuit, since the average linear expansion coefficient of the cured product of the adhesive layer 13 is 45 ppm or less, the generation of stress between the semiconductor chip and the cured product of the adhesive layer 13 is suppressed. Therefore, for example, even after being subjected to a long-term reliability test such as a temperature cycle test, the connection resistance at the connection portion hardly changes and has high reliability.

In the method for manufacturing a laminated circuit described above, each time one semiconductor chip is laminated, the solder bonding and the adhesive layer 13 are cured, but a plurality of semiconductor chips are laminated for process efficiency. After that, the solder bonding between these semiconductor chips and the curing of the adhesive layer 13 interposed between these semiconductor chips may be finally performed collectively.

The embodiment described above is described for facilitating understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

Hereinafter, the present invention will be described in more detail by showing examples and test examples, but the present invention is not limited to the following test examples.

[Examples 1 to 5, Comparative Example 1]
A composition containing the constituent components shown in Table 1 was diluted with methyl ethyl ketone so that the solid content concentration was 40% by mass to obtain a coating solution. It was 50 mPa * s when the viscosity at 25 degrees C of the said coating liquid was measured using the B-type viscosity meter. The coating liquid is applied onto a silicone-treated release film (SP-PET 381031 manufactured by Lintec Corporation), and the resulting coating film is dried in an oven at 100 ° C. for 1 minute, thereby bonding to a thickness of 45 μm. The 1st laminated body which consists of an agent layer and a peeling film was obtained.

100 parts by mass of acrylic copolymer (weight average molecular weight: 700,000) obtained by copolymerizing 80 parts by mass of 2-ethylhexyl acrylate, 10 parts by mass of methyl acrylate and 10 parts by mass of 2-hydroxyethyl acrylate (in terms of solid content; below) The same) and 10 parts by mass of an isocyanate-based crosslinking agent (Polyurethane Industry Co., Ltd., Coronate L) were mixed to prepare an adhesive composition.

The pressure-sensitive adhesive composition obtained as described above was applied to one side of an ethylene-methacrylic acid copolymer (EMAA) film (thickness: 100 μm) as a base material to form a coating film. Thereafter, the coating film was dried at 100 ° C. for 1 minute. This obtained the 2nd laminated body which consists of a 10-micrometer-thick adhesive layer and a base material.

Then, the sheet | seat for three-dimensional integrated laminated circuit manufacture was obtained by bonding the surface by the side of the adhesive layer in a 1st laminated body, and the surface by the side of the adhesive layer in a 2nd laminated body.

Example 6
A first laminate is prepared using a composition containing the constituents shown in Table 1, and a three-dimensional integrated laminate is obtained in the same manner as in Example 1 except that polyethylene terephthalate (thickness: 100 μm) is used as a base material. A circuit manufacturing sheet was manufactured.

Example 7
A composition containing the constituent components shown in Table 1 was diluted with methyl ethyl ketone so that the solid content concentration was 40% by mass to obtain a coating solution. It was 150 mPa * s when the viscosity at 25 degrees C of the said coating liquid was measured using the B-type viscosity meter. A sheet for producing a three-dimensional integrated laminated circuit was prepared in the same manner as in Example 1 except that an adhesive layer was formed using the coating solution and the thickness of the base material was changed as described in Table 2. Obtained.

[Comparative Example 2]
A composition containing the components shown in Table 1 was diluted with methyl ethyl ketone so that the solid content concentration became 55% by mass to obtain a coating solution. It was 150 mPa * s when the viscosity at 25 degrees C of the said coating liquid was measured using the B-type viscosity meter. A sheet for producing a three-dimensional integrated laminated circuit was obtained in the same manner as in Example 1 except that the adhesive layer was formed using the coating solution.

[Comparative Example 3]
A composition containing the components shown in Table 1 was diluted with methyl ethyl ketone so that the solid content concentration became 55% by mass to obtain a coating solution. It was 150 mPa * s when the viscosity at 25 degrees C of the said coating liquid was measured using the B-type viscosity meter. A sheet for producing a three-dimensional integrated laminated circuit was prepared in the same manner as in Example 1 except that an adhesive layer was formed using the coating solution and the thickness of the base material was changed as described in Table 2. Obtained.

Here, the detail of the component shown in Table 1 is as follows.
High molecular weight component , polyvinyl acetal resin: glass transition temperature 86 ° C., weight average molecular weight 130,000, polyvinyl butyral resin: glass transition temperature 71 ° C., weight average molecular weight 110,000, polyester resin: glass transition temperature 83 ° C., weight average molecular weight 40,000 Bisphenol A (BisA) type phenoxy resin: glass transition temperature 84 ° C., weight average molecular weight 60,000Bisphenol A (BPA) / bisphenol F (BPF) copolymerization type phenoxy resin: manufactured by Tohto Kasei Co., Ltd., product name “ZX-1356 -2 ", glass transition temperature 71 ° C, weight average molecular weight 60,000, polyacrylate: glass transition temperature -28 ° C, weight average molecular weight 800,000
Thermosetting component / Bisphenol A (BisA) type epoxy resin: Epoxy equivalent 180-190 g / eq
・ Epoxy resin 1: Tris (hydroxyphenyl) methane type solid epoxy resin, manufactured by Japan Epoxy Resin Co., Ltd., product name “E1032H60”, 5% weight loss temperature 350 ° C., solid, melting point 60 ° C.
Epoxy resin 2: Bis-F type liquid epoxy resin, manufactured by Japan Epoxy Resin, product name “YL-983U”, epoxy equivalent 184
Epoxy resin 3: long-chain Bis-F modified epoxy resin, manufactured by Japan Epoxy Resin, product name “YL-7175”
Triphenylmethane type epoxy resin: Triphenylmethane type epoxy resin, manufactured by Nippon Kayaku Co., Ltd., product name “EPPN-502H”, epoxy equivalent 168
Curing catalyst 2PHZ-PW: 2-phenyl-4,5-dihydroxymethylimidazole, manufactured by Shikoku Kasei Kogyo Co., Ltd., product name “2PHZ-PW”, melting point 230 ° C.
2MZA-PW: 2,4-diamino-6- [2′-methylimidazolyl- (1 ′)]-ethyl-s-triazine, manufactured by Shikoku Kasei Kogyo Co., Ltd., product name “2MZA-PW”, melting point 250 ° C.
Flux component 2-methylglutaric acid: Wako Pure Chemical Industries, melting point 80-82 ° C
・ Adipic acid: Wako Pure Chemical Industries, melting point 152 ° C
Rosin derivative: Arakawa Chemical Industries, softening point 124-134 ° C
Inorganic filler / Surface-modified silica filler: manufactured by Admatechs, product name “Admanano”, average particle size 100 nm, maximum particle size 450 nm

Here, the glass transition temperature (Tg) of the high molecular weight component was measured with a temperature profile of −70 ° C. to 150 ° C. using a DSC (PYRIS Diamond DSC) manufactured by PerkinElmer Co., Ltd. at a heating / cooling rate of 10 ° C./min. In practice, the inflection point was confirmed and the glass transition temperature was determined. Further, the weight average molecular weight (Mw) of the above component is a weight average molecular weight in terms of standard polystyrene measured (GPC measurement) using a gel permeation chromatograph (manufactured by Tosoh Corporation, HLC-8020) under the following conditions. .

<GPC measurement conditions>
Column: “TSK guard column HXL-L”, “TSK gel G2500HXL”, “TSK gel G2000HXL”, “TSK gel G1000HXL” (all manufactured by Tosoh Corporation) • Column temperature: 40 ° C.
・ Developing solvent: Tetrahydrofuran ・ Flow rate: 1.0 mL / min
・ Detector: Differential refractometer ・ Standard sample: Polystyrene

Test Example 1 Measurement of 90 ° C. Melt Viscosity A sample for measurement having a thickness of 15 mm was prepared by laminating a plurality of adhesive layers using the first laminate produced in Examples and Comparative Examples. The melt viscosity of the obtained measurement sample was measured using a flow tester (manufactured by Shimadzu Corporation, CFT-100D) under the conditions of a load of 50 kgf, a temperature range of 50 to 120 ° C., and a temperature increase rate of 10 ° C./min. The melt viscosity values at 90 ° C. are shown in Table 2.

[Test Example 2] Measurement of average linear expansion coefficient The first laminates produced in the examples and comparative examples were cut into 15 x 4.5 mm and used as measurement samples. The obtained adhesive layer was cured by treating the obtained sample at 160 ° C. for 1 hour. Using the thermomechanical analyzer (manufactured by Bruker Ax, TMA4030SA), the coefficient of linear expansion was measured under the conditions of a load of 2 g, a temperature range of 0 to 300 ° C., and a heating rate of 5 ° C./min. did. From the obtained results, the average linear expansion coefficient at 0 to 130 ° C. was calculated. The results are shown in Table 2.

[Test Example 3] Measurement of glass transition temperature of cured product The first laminates produced in Examples and Comparative Examples were cut into 5 x 20 mm to obtain measurement samples. The obtained adhesive layer was cured by treating the obtained sample at 160 ° C. for 1 hour. About the obtained hardened | cured material, using a dynamic viscoelasticity measuring apparatus (The product made from TA instrument company, DMA Q800), frequency 11Hz, amplitude 10micrometer, and the temperature increase rate of 3 degree-C / min, 0 to 300 degreeC The viscoelasticity in the tensile mode when the temperature was raised to ° C. was measured, and the temperature at the maximum point of tan δ (loss elastic modulus / storage elastic modulus) obtained by this measurement was defined as the glass transition temperature (Tg). The measurement results are shown in Table 2.

[Test Example 4] Measurement of 5% mass reduction temperature The first laminates produced in the examples and comparative examples were cut into 15 x 4.5 mm and used as measurement samples. The obtained adhesive layer was cured by treating the obtained sample at 160 ° C. for 1 hour. With respect to the obtained cured product, in accordance with JIS K7120: 1987, using a differential thermal and thermogravimetric simultaneous measurement device (DTG-60, manufactured by Shimadzu Corporation), the inflow gas is nitrogen, the gas inflow rate is 100 ml / min, Thermogravimetry was performed by raising the temperature from 40 ° C. to 550 ° C. at a rate of temperature increase of 20 ° C./min. Based on the obtained thermogravimetric curve, the temperature at which the mass decreased by 5% relative to the mass at a temperature of 100 ° C. (5% mass reduction temperature) was determined. The results are shown in Table 2.

[Test Example 5] Measurement of the thickness of the adhesive layer and the standard deviation of the thickness For the first laminates produced in the examples and comparative examples, the thickness (T2) of the adhesive layer was totaled at intervals of 50 mm. 100 points were measured. Based on the measurement results, the average value (μm) of the thickness (T2) and the standard deviation (μm) of the thickness (T2) were calculated. The results are shown in Table 2.

[Test Example 6] Measurement of storage elastic modulus at 23 ° C after curing of adhesive layer From the measurement result of viscoelasticity of the adhesive layer after curing in Test Example 3, storage at 23 ° C after curing of the adhesive layer The elastic modulus (MPa) was read. The results are shown in Table 2.

[Test Example 7] Measurement of storage elastic modulus of adhesive layer at 23 ° C The adhesive compositions prepared in Examples and Comparative Examples were applied on a silicone-treated release sheet film (SP-PET 381031 manufactured by Lintec Corporation). And the adhesive layer was formed by drying the obtained coating film. Then, the laminated body of the 800-micrometer-thick adhesive layer was obtained by laminating | stacking two or more formed adhesive layers. The laminate of the pressure-sensitive adhesive layer was punched into a circle having a diameter of 10 mm and used as a measurement sample.

Using a dynamic viscoelasticity measuring device (A Instruments, ARES), the storage elastic modulus (Pa) was measured under the conditions of a frequency of 1 Hz, a measurement temperature range of −50 to 150 ° C., and a temperature increase rate of 3 ° C./min. It was measured. The results are shown in Table 2.

[Test Example 8] Measurement of tensile elastic modulus at 23 ° C. of base material The base materials used in Examples and Comparative Examples were cut into test pieces of 15 mm × 140 mm, and tensile at 23 ° C. in accordance with JIS K7127: 1999. The elastic modulus was measured. Specifically, the above test piece was set to a chuck distance of 100 mm with a tensile tester (manufactured by Shimadzu Corporation, Autograph AG-IS 500N), and then a tensile test was performed at a speed of 200 mm / min. The elastic modulus (MPa) was measured. The results are shown in Table 2.

[Test Example 9] Measurement of exothermic onset temperature and exothermic peak temperature by differential scanning calorimetry Using the first laminates produced in Examples and Comparative Examples, the thickness was determined by laminating a plurality of adhesive layers. A 15 mm measurement sample was prepared. The obtained measurement sample was heated from room temperature to 300 ° C. at a temperature rising rate of 10 ° C./min using a differential scanning calorimeter (TA Instruments, Q2000). From the DSC curve thus obtained, the temperature at which heat generation starts (heat generation start temperature) (TS) and the heat generation peak temperature (TP) were determined. The results are shown in Table 2.

[Test Example 10] Temperature cycle test A wafer for evaluation having a bump formed on one surface and a pad formed on the other surface was prepared, and a fully automatic multi-wafer mounter (RAD-2700F / 12, manufactured by Lintec Corporation). The three-dimensional integrated circuit manufacturing sheets manufactured in Examples and Comparative Examples were attached to the surface of the evaluation wafer on which the bumps were formed, and further fixed to the ring frame.

Subsequently, the evaluation wafer was diced together with the adhesive layer using a full auto dicing saw (DFD651, manufactured by Disco Corporation), and diced into chips having a size of 7.3 mm × 7.3 mm in plan view.

Next, using a flip chip bonder (manufactured by Toray Engineering Co., Ltd., FC3000W), the chip was picked up together with the separated adhesive layer, and then flip chip bonded to the substrate. Thereafter, the second-stage chip with the adhesive layer was flip-chip bonded onto the first-stage chip temporarily placed on the substrate. This procedure was repeated to produce a semiconductor device in which a total of five stages of chips were stacked on the substrate.

A temperature cycle test was performed in which the obtained semiconductor device was subjected to 1000 cycles in an environment in which −55 ° C., 10 minutes and 125 ° C., 10 minutes was one cycle. For the semiconductor devices before and after the test, the connection resistance value between the semiconductor chips was measured with a digital multimeter, and the change rate of the connection resistance value in the semiconductor device after the test with respect to the connection resistance value in the semiconductor device before the test was measured. And connection reliability was evaluated according to the following evaluation criteria. The results are shown in Table 2.
A: The change rate of the connection resistance value is 20% or less.
X: The change rate of the connection resistance value exceeds 20%.

[Test Example 11] Evaluation of Embeddability A plurality of semiconductor devices were manufactured by the method described in Test Example 10. The four sides of five semiconductor devices randomly selected from these semiconductor devices are observed with a digital microscope to confirm the presence or absence of cracks in the bumps and the state of embedding the bumps in the adhesive layer. The thickness in the stacking direction on the surface was measured. Based on these results, the embedding property of the bumps in the three-dimensional integrated laminated circuit manufacturing sheets obtained in Examples and Comparative Examples was evaluated according to the following evaluation criteria. The results are shown in Table 2.
○: In all the five semiconductor devices, no crack was generated in the bump, the bump was satisfactorily embedded in the adhesive layer, and the thickness in the stacking direction was the same between the four side surfaces.
X: Among five semiconductor devices, there are cracks in the bumps, insufficient embedding of the bumps in the adhesive layer, or thicknesses in the stacking direction that are not the same between the four side surfaces .

As can be seen from Table 2, the sheet for manufacturing the three-dimensional integrated laminated circuit obtained in the examples had good results of the temperature cycle test and had high connection reliability. In addition, the sheet for producing a three-dimensional integrated laminated circuit obtained in the example was excellent in the embedding property of the bumps.

The sheet for manufacturing a three-dimensional integrated laminated circuit according to the present invention has high connection reliability when semiconductor chips are connected to each other, and therefore can be suitably used for joining various semiconductor chips.

DESCRIPTION OF

SYMBOLS

1, 2 ... Sheet | seat for three-dimensional integrated laminated circuit manufacture 11 ... Base material 12 ... Adhesive layer 13 ... Adhesive layer 14 ... Release sheet

Claims

A sheet for manufacturing a three-dimensional integrated multilayer circuit, which is interposed between a plurality of semiconductor chips having through electrodes, and is used to bond the plurality of semiconductor chips to each other to form a three-dimensional integrated multilayer circuit,
The sheet for manufacturing a three-dimensional integrated laminated circuit includes at least a curable adhesive layer,
The material constituting the adhesive layer has a melt viscosity of 1.0 × 10 0 to 5.0 × 10 5 Pa · s at 90 ° C. before curing, and the average linear expansion of the cured product at 0 to 130 ° C. A sheet for producing a three-dimensional integrated laminated circuit, wherein the coefficient is 45 ppm or less.
The sheet for manufacturing a three-dimensional integrated laminated circuit according to claim 1, wherein the cured material of the material constituting the adhesive layer has a glass transition temperature of 150 ° C or higher and 350 ° C or lower.
The sheet for manufacturing a three-dimensional integrated laminated circuit according to claim 1 or 2, wherein the cured material of the material constituting the adhesive layer has a 5% mass reduction temperature of 350 ° C or higher by thermogravimetry.
The sheet for manufacturing a three-dimensional integrated multilayer circuit according to any one of claims 1 to 3, wherein a standard deviation of the thickness (T2) of the adhesive layer is 2.0 µm or less.
5. The storage elastic modulus at 23 ° C. after curing of the adhesive layer is 1.0 × 10 2 MPa or more and 1.0 × 10 5 MPa or less. A sheet for producing a three-dimensional integrated laminated circuit according to 1.
The adhesive layer has an exothermic start temperature (TS) measured by differential scanning calorimetry at a heating rate of 10 ° C./min within a range of 70 ° C. to 150 ° C., and an exothermic peak temperature (TP) The sheet for producing a three-dimensional integrated laminated circuit according to any one of claims 1 to 5, wherein TS + 5 to 60 ° C.
The three-dimensional integrated laminated circuit according to any one of claims 1 to 6, wherein the material constituting the adhesive layer contains a thermosetting component, a high molecular weight component, a curing agent, and a curing catalyst. Production sheet.
The sheet for manufacturing a three-dimensional integrated laminated circuit according to any one of claims 1 to 7, wherein the material constituting the adhesive layer contains a flux component.
The sheet for manufacturing a three-dimensional integrated multilayer circuit according to any one of claims 1 to 8, wherein the material constituting the adhesive layer contains an inorganic filler.
The sheet for manufacturing a three-dimensional integrated laminated circuit includes a pressure-sensitive adhesive layer laminated on one side of the adhesive layer, and a base material laminated on the surface side opposite to the adhesive layer in the pressure-sensitive adhesive layer. The sheet for manufacturing a three-dimensional integrated laminated circuit according to any one of claims 1 to 9, further comprising:
The ratio (T2 / T1) of the thickness (T2) of the adhesive layer to the thickness (T1) of the base material is 0.01 or more and 1.5 or less. Sheet for manufacturing three-dimensional integrated laminated circuits.
The sheet for manufacturing a three-dimensional integrated laminated circuit according to claim 10 or 11, wherein the pressure-sensitive adhesive layer has a storage elastic modulus at 23 ° C of 1 x 10 3 Pa or more and 1 x 10 9 Pa or less.
The sheet for manufacturing a three-dimensional integrated laminated circuit according to any one of claims 10 to 12, wherein the base material has a tensile elastic modulus at 23 ° C of 100 MPa or more and 5000 MPa or less.
The sheet for producing a three-dimensional integrated laminated circuit according to any one of claims 10 to 13, wherein the laminate comprising the pressure-sensitive adhesive layer and the substrate is a dicing sheet.
The sheet for manufacturing a three-dimensional integrated multilayer circuit according to any one of claims 10 to 14, or one side of the adhesive layer of the sheet for manufacturing a three-dimensional integrated multilayer circuit according to any one of claims 1 to 9. Bonding the surface of the adhesive layer opposite to the pressure-sensitive adhesive layer and at least one surface of a semiconductor wafer provided with a through electrode,
Dicing the semiconductor wafer together with the adhesive layer of the sheet for manufacturing a three-dimensional integrated laminated circuit, and singulating into semiconductor chips with an adhesive layer;
A plurality of semiconductor chips with an adhesive layer separated into a plurality of pieces are stacked so that the through electrodes are electrically connected to each other and the adhesive layers and the semiconductor chips are alternately arranged. A step of obtaining a chip laminate, and a step of curing the adhesive layer in the semiconductor chip laminate to bond the semiconductor chips constituting the semiconductor chip laminate together. Circuit manufacturing method.