WO2017171890A1 - Systèmes, procédés et appareils pour réduire une erreur de modèle d'opc par l'intermédiaire d'un algorithme d'apprentissage automatique - Google Patents

Systèmes, procédés et appareils pour réduire une erreur de modèle d'opc par l'intermédiaire d'un algorithme d'apprentissage automatique Download PDF

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WO2017171890A1
WO2017171890A1 PCT/US2016/025780 US2016025780W WO2017171890A1 WO 2017171890 A1 WO2017171890 A1 WO 2017171890A1 US 2016025780 W US2016025780 W US 2016025780W WO 2017171890 A1 WO2017171890 A1 WO 2017171890A1
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mask
features
physical
contours
semi
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PCT/US2016/025780
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English (en)
Inventor
Hyungjin MA
Vasudev LAL
Seongtae Jeong
Erik N. HOGGAN
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Intel Corporation
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Priority to PCT/US2016/025780 priority Critical patent/WO2017171890A1/fr
Publication of WO2017171890A1 publication Critical patent/WO2017171890A1/fr

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness

Definitions

  • HVM high volume manufacturing
  • Figure 1 depicts an exemplary Artificial Neural Network (ANN) machine learning algorithm in accordance with described embodiments
  • Figure 2 depicts an exemplary modeling flow utilizing the Artificial Neural
  • Figure 3 depicts a contour shifting scheme based upon image map distortion in accordance with described embodiments
  • Figure 4 depicts an intensity profile and corresponding resist threshold depicting a step-like function in accordance with described embodiments
  • Figure 5 depicts several SEM image representations showing the model prediction of resist pattern utilizing the described techniques in comparison to conventional models
  • Figure 6 is a flow diagram illustrating a method for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm in accordance with described embodiments;
  • OPC Optical Proximity Correction
  • Figure 7 illustrates a computing device in accordance with described embodiments.
  • Figure 8 illustrates an interposer that includes one or more described embodiments.
  • OPC Optical Proximity Correction
  • the described techniques result in significant improvements in OPC model prediction based on the described machine learning algorithm and provide for a flexible way to combine the influence of optical image parameters as well as geometric parameters to predict lithographic processes, which are complicated phenomenon originated from optical, chemical and physical effects. This flexibility is realized in a model form which is easy to calibrate from fabrication process data. Moreover, the resulting model is fast enough to deploy in high volume full chip correction by guiding the model generation through non-linear parametric regression and classification.
  • Optical Proximity Correction (OPC) models require accurate mask layout dimensions as input parameters. The greater the accuracy, the more useful and accurate the resulting model will be for the semiconductor manufacturing processes.
  • Resist patterns generated by lithographic processes are the results of complicated optical, chemical and physical phenomenon, which can be modeled based on optical image parameters and geometric parameters. Model predictions, which are represented in the form of contours, are generated based on the distorted image maps, which are numerically stable and efficient enough to be used for high volume manufacturing.
  • machine learning algorithms such as Artificial Neural Network (ANN) algorithms are employed in accordance with certain embodiments.
  • Rule based model error compensation has also been conventionally utilized for known problematic configurations. However, such a technique is only feasible for a very limited set of geometries, and it is therefore infeasible to generate the requisite rules for all possible configurations in the circuit partem. Moreover, use of rule based model error compensation introduces unnecessary and undesirable complexity into the tapeout flow, which in turn translates to increased costs in terms of the engineering resources necessary to characterize, specify, code, and validate such rules as well as computational resources required to then calculate the models.
  • the existing modeling software for OPC is deficient in terms of the accuracy when new lithographic systems having tighter margins and dimensions are utilized, resulting in unworkable errors inhibiting the newer technologies from being successfully scaled to high volume manufacturing.
  • Conventional OPC models simply cannot predict with sufficient accuracy and precision to the smaller feature size and feature geometries associated new technologies.
  • Improvements to the existing OPC models are needed such that the OPC models which drive manufacturing may be successfully utilized to attain sufficiently accurate pattern fidelity on the mask and on the manufactured silicon wafers.
  • the conventional OPC models need further adjustment and correction or contour shifting so as to move these printed features into the correct position with a greater degree of precision. Such improvements ensure functionally operable silicon and thus improve manufacturing yields and profitability for any given product.
  • embodiments further include various operations which are described below.
  • the operations described in accordance with such embodiments may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the operations.
  • the operations may be performed by a combination of hardware and software.
  • any of the disclosed embodiments may be used alone or together with one another in any combination. Although various embodiments may have been partially motivated by deficiencies with conventional techniques and approaches, some of which are described or alluded to within the specification, the embodiments need not necessarily address or solve any of these deficiencies, but rather, may address only some of the deficiencies, address none of the deficiencies, or be directed toward different deficiencies and problems which are not directly discussed.
  • Figure 1 depicts an exemplary Artificial Neural Network (ANN) 100 machine learning algorithm in which the input variables predict the deterministic model error or process driven changes in critical dimension.
  • ANN Artificial Neural Network
  • an initial OPC contour 120 represented by the bold line and outermost ellipse and then a second contour is further depicted via the inner ellipse showing the Scanning Electron Microscope (SEM) contour 125 representing fabrication data as taken from an SEM image.
  • SEM Scanning Electron Microscope
  • a neural network 105 having as input several input image parameters 110 which are calculated using an OPC model and the resulting output from the neural network is a contour shift prediction 115.
  • the image input parameters 110 used to train the neural network 105 are simulated optical parameters representing the entirety of the feature set for use as the input image parameters 110.
  • any specific layout will have a deterministic OPC model error.
  • Neural networks such as Artificial Neural Network (ANN) 100, are able to approximate any arbitrary formula. Therefore, in accordance with described embodiments, the neural network 105 is trained to describe the relationship between the layout and the respective OPC model error, using the image input parameters 110 to enable the neural network 105 to learn about the layout. A sufficient quantity of image input parameters 110 are provided so as to enable such learning.
  • ANN Artificial Neural Network
  • a simulated optical image from conventional OPC models is obtained from the convolution of the layout and an optical transfer function.
  • image parameters are defined via optical images that capture information about the layout which is then used to train the neural network 105 to describe the deterministic relationship between the layout and conventional OPC model error.
  • geometric information from the layout is additionally utilized to directly train the neural network to predict the amount of model error associated with the geometry.
  • the neural network 105 provides a more accurate model which can then be implemented by shifting the initial OPC contour 120 by an amount predicted by neural network 105.
  • the OPC model provides a forward function which connects what is on the mask to what is on the wafer.
  • Software algorithms provide a basic physics solution to this problem, but the solution requires many approximations which thus operates as a source of inaccuracies. Described embodiments therefore reformulate the problem in such a way that a list of features are provided to the neural network for the purposes of training.
  • the neural network learns what adaptations are necessary to conform the base OPC models to known physical models.
  • These adaptations are output as the contour shift predictions 115 and result in a semi-physical model which permits formulas and corrections by which the trained neural network 105 describes the differences between the incoming base OPC model and the observed physical realities.
  • the neural network 105 predicts the deterministic model error or process driven changes in critical dimensions for the size and position of features.
  • the neural network provides contour fitting to the SEM contour 125 image representing the actually observed physical outputs from a fabrication process utilizing the base OPC model which provides the initial OPC contour 120.
  • the initial OPC contour 120 is a result of the software algorithms which provides a prediction of the physical space via a semi-physical model. According to such an embodiment, SEM image data is then collected for the patterns to generate or determine the SEM contour 125 representing the fab data for actual physical samples of fabricated physical silicon wafers generated using the initial OPC base model.
  • the delta between the initial OPC contour 120 and the SEM contour 125 is the determined model error of the base OPC model.
  • the neural network 105 is trained to be able to predict the determined model error of the base OPC model so as to output an improved model using the contour shift prediction 115 provided by the trained neural network 105.
  • Figure 2 depicts an exemplary modeling flow 200 utilizing the Artificial Neural Network (ANN) machine learning algorithm in accordance with described embodiments.
  • ANN Artificial Neural Network
  • block 205 means for sampling data collection for model building when then proceeds to block 210 where a base OPC model (e.g., an initial contour such as the initial OPC contour depicted by element 120 at Figure 1) is provided.
  • a base OPC model e.g., an initial contour such as the initial OPC contour depicted by element 120 at Figure 1
  • the processing advances to block 215 where a correction engine for mask design applies the contour as rendered by the base OPC model.
  • described embodiments provide further correction and improvement over the base OPC model via the contour shift as predicted by the trained neural network.
  • the processing instead advances into the newly introduced elements of the modeling flow 200 depicted by the dashed line in which processing from block 210 advances to next to block 220 where a model error and lithographic process characterization is applied.
  • contour shifting 225 is applied utilizing the contour shift as predicted by the trained neural network.
  • processing then advances to block 230 where the final model or the final contour is provided as a result of the contour shifting 225 applied using the contour shift as predicted by the neural network.
  • processing then returns to block 215 where a correction engine for the mask design applies the appropriate correction as benefitted from the contour shifting 225 operation.
  • the trained neural network output providing the contour shift prediction results in a third contour, one between the initial OPC contour 120 and the SEM contour 125, which is a predicted contour as output by applying the contour shift prediction 115 of the trained neural network as a correction for the base OPC model, thus yielding an improved contour fit between the improved prediction and reality.
  • the contour shifting 225 operation produces from the input base OPC model's initial contour at block 210 the final model's final contour at block 230, and it is this final contour which is then utilized by the correction engine for the mask design at block 215.
  • the combination of the semi-physical model and the output of the trained neural network would exactly equal the physical data which equates the observed measurements from the SEM imagery data.
  • significant improvement is attained as described below, but the predicted final contour 230 is not exactly identical, but it is sufficiently accurate for the smaller feature size dimensions and positions utilized by the newer technologies, and thus, appropriate for scaling up silicon wafer production in high volume manufacturing.
  • the predicted final contour rendered by the final model at block 230 is much closer to the actually observed SEM data and the contour shifting 225 as provided by the contour shift prediction 115 from Figure 1 is thus usable to better predict a wide array of structures and how they will behave, which may then compared to new SEM imagery for such features. Moreover, iterative training of the neural network further improves the predictive capability and thus improves the eventual final model and final contour 230 for any mask structures and features.
  • the final model 230 is then re-applied via OPC correction to modify the mask such that features and structures are positioned in the correct location such that when a next silicon wafer is fabricated through the manufacturing process, all the structures and features will be in the correct location and the resulting silicon die will be functional and operate correctly according to design specifications.
  • Figure 3 depicts a contour shifting scheme 300 based upon image map distortion in accordance with described embodiments.
  • Implementation of the contour shift scheme utilizes a predicted model from the trained neural network.
  • the amount of contour shift is given as a function of input variables including, for example, optical image parameters, geometrical parameters, density, pseudo-critical dimensions (pseudo-CDs), and so forth.
  • contour crossing at a given location X is calculated locally. Since the location X' is unknown, training input at location X' is calculated iteratively, which is described by the equation
  • the OPC base model generates a contour with specified optical intensities resulting from light originating at the beginning of the imager or the imaging tool.
  • the intensities vary and are generally nonlinear. By systematically processing these intensities it is possible to develop many points on the contour location to establish the shape of the pattern.
  • a correction is made to the initial contour 315 using an initial guess 330 and then iteratively the correction made to the initial contour 315, with the correction being represented at Figure 3 by location "X" 325, is shifted over and over to improve the resulting prediction, ultimately resulting in a point on the final contour 320 corresponding to the known SEM contour.
  • an equation is applied to cause a shift to the depth mask such that the final contour 320 is closer to the actual measured contour based on the SEM contour (element 125 from Figure 1) of an SEM image from wafer fabrication.
  • the equations may continually be manipulated and adjusted by the neural network until the adaptation to the initial contour 315 is sufficiently close or equal to the final contour 320 sought.
  • the neural network Because the basic physics are known from the base OPC model, it is possible for the neural network to continuously attempt to draw contours to approximate the final contour 320 utilizing the base OPC model until the desired shift is attained for every point on the contour sought. It is the shift in the intensity map as represented by the initial intensity map 310 and the shifted intensity map 305 which is algorithmically manipulated through the iterations of the neural network to ultimately render a new model (e.g., a neural network model) contour which matches the final contour 320 provided by the SEM image.
  • a new model e.g., a neural network model
  • the neural network determines how the shifted intensity map 305 will be translated into a physical feature within a polymer photoresist as part of predicting the final contour 320.
  • the initial intensity map 310 is created from the initial OPC model, which is a semi-physical modeling tool, and the shifts are then applied through the initial OPC model to the initial intensity map 310 to render the shifted intensity map 305.
  • Figure 4 depicts an intensity profile and corresponding resist threshold depicting a step-like function in accordance with described embodiments.
  • a step-like function 401 is depicted on the left and on the right there are depicted various input variables for a non- linear resist threshold classification including iMax at element 405, threshold 415, iMin 410, and neighboring intensity with an exemplary 6nm step up to +/- 12nm at element 420.
  • the final contour may instead be described by modulating the resist threshold, which is the intensity at the boundaries after the development of the model.
  • regularization is accomplished by classifying shifted locations from the boundaries as inside or outside of the contours, forming a step-like function 401 threshold form, which can be fit by the neural network's predicted model.
  • the model contour is generated where the threshold crosses the intensity which is pinpointed on the exemplary graph at element 415. In such a way, it is possible to bypass or eliminate the iterative operation for finding the initial contour location which may therefore yield a regularized model in faster time due to less computationally intensive processing.
  • both image parameters as well as geometric density of dot negative Sub-Resolution Assisting Features are utilized as inputs for training the neural network to generate the improved model.
  • the trained neural network smoothly combines the provided geometric parameters with the image parameters to compensate for the focus shift effect induced by dot negative SRAFs inputs.
  • the demonstrated range of error for various geometries is reduced from 12nm utilizing conventional methodologies down to 5nm utilizing the techniques as described herein.
  • such criteria are checked at the full chip level to ensure a stable contour generation.
  • a damping term may additionally be added to the iteration.
  • regularization is applied during the training of the neural network to ensure stable models are achieved.
  • Two reasons for application of such a regularization technique are for the sake of spatial stability and also to prevent over-fitting.
  • the neural network is trained to predict the contour shift at the contour locations.
  • the entire two dimensional image map is distorted to achieve the contour shift in the new model. Consequently, it is important for the contour shift prediction to exhibit stability via characteristics such as slowly varying and varying within bounds, at spatial locations away from the contours. Otherwise, the contour shift prediction could result in a seemingly chaotic result which may be mathematically accurate but pragmatically unrealistic for the application of the prediction to the corrected OPC base model.
  • neural networks especially those of high complexity, are prone to over-fitting. It is therefore in accordance with certain embodiments that a safeguard is provided against over-fitting by the trained neural network by imposing a physical condition mandating within the model that any contour shift prediction must be a slowly varying function of space.
  • any target variable to the contour location is a determination of best fit for vector length from an OPC base model predicted contour to the SEM contour representing the actual fabrication result. The delta between these two points represents the shift from the predicted result to the determined reality corresponding to the physical measurements from SEM images. Determining the length of the vector for every one of a series of points making up the contour thus establishes the shift to the contour to attain the final result.
  • both the contour and the shifted contour represent a 2D quantity and the regularization process applies a smoothing function to the shifted contour to avoid problems such as over fitting. Otherwise, the shifting of the contour may provide a result which is not useful.
  • the input parameters are provided for only target locations
  • additional points are additionally extrapolated to nearby pseudo target points, distinct from the actual target locations provided.
  • the resulting shift is smoothed.
  • the contour shifting for the model error is determined on the basis of the delta from the initial contour to not just the actually measured points of the SEM image input into the neural network, but additionally based on the delta to the pseudo target locations extrapolated as nearby points to the actually measured points of the SEM image.
  • the predicted contour represents an intermediate result and a final contour is generated through the smoothing function by fitting the contour to both the SEM contour points and also the extrapolated pseudo nearby points.
  • the neural network generates the intermediate contour using preferential locations for each of the points on the contour which are best possible matches without regard to over-fitting problems or model stability and the final contour is regularized to enhance model stability and remove or smooth out over-fitting of the contour to the measured SEM contour points.
  • Figure 5 depicts several SEM image representations 501, 502, and 503 showing the model prediction of resist pattern utilizing the described techniques in comparison to conventional models.
  • the outer bold line at elements 510 and 515 represent the improved model prediction results for a resist partem using the exemplary fit of a conventional model depicted by the non-bolded interior lines at the elements 510 and 515.
  • the overall fit of the model calibration dataset has been improved for a particular manufacturing process known to suffer from thick resist effects.
  • SEM image representation 502 represents a different manufacturing process, again in which during testing there was a demonstrated reduction in error observed for a manufacturing process having one of the strictest process margins.
  • the outer bold line at each of elements 520 and 525 depict the improved model prediction results versus those of the conventional model depicted by the non-bolded interior lines at the elements 520 and 525.
  • SEM image representation 503 represents a corner-to-corner configuration.
  • Use of the trained neural network results in superior predictability of the models especially in regard to tight comer-to-comer configurations as depicted by element 530, which is a critical feature in the manufacturability of certain semiconductor products in accordance with reliability and yield targets. Improvements in the model's predictive capability thus translates directly into significant improvements of lithographic processes which in turn enables the capability of optimizing manufacturing yield, which directly determines the profitability silicon products produced.
  • Figure 6 is a flow diagram illustrating a method 600 for reducing Optical
  • Proximity Correction model error via a machine learning algorithm in accordance with described embodiments.
  • Some of the blocks and/or operations listed below are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from method 600 may be utilized in a variety of combinations.
  • the method for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm begins with creating a mask via a lithography process.
  • OPC Optical Proximity Correction
  • the method includes fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask.
  • the method includes creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask.
  • the method includes capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer.
  • SEM Scanning Electron Microscope
  • the method includes quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images.
  • the method includes shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.
  • method 600 further includes:
  • shifting the contours of the plurality of features of the mask distorts a two dimensional (2D) quantity representing the semi-physical model of the mask; and in which the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.
  • method 600 further includes: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model.
  • training the neural network includes: inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network; and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.
  • training the neural network includes: inputting SEM images of the physical silicon wafer fabricated using the mask into the neural network; and generating smoothed shifted contours of the plurality of features of the mask via a regularization process; and inputting the smoothed shifted contours of the plurality of features into the neural network.
  • training the neural network includes: inputting image input parameters based on the SEM images collected, in which the image input parameters are simulated optical parameters describing the physical parameters of the lithography process used to create the mask.
  • training the neural network includes: inputting a simulated optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model and an optical transfer function; and in which the trained neural network generates a deterministic relationship between the layout of the contours of the plurality of features of the mask as specified by the semi- physical model and the quantified differences.
  • OPC Optical Proximity Correction
  • training the neural network includes: inputting geometric information from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model to directly train the neural network to predict an amount of model error observed in the semi-physical model associated with the input geometric information based on the quantified differences.
  • the trained neural network performs contour fitting of the contours of the plurality of features of the mask as specified by the semi-physical model to the plurality of features embodied within the physical silicon wafer represented within the captured SEM images.
  • the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi -physical model based on the quantified differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and in which the neural network generates a new model of the mask specifying the contours of the plurality of features of the mask shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.
  • the neural network performs a regularization process to smooth the shifted contour, in which the neural network is trained against over-fitting of the shifted contour by imposing a physical condition mandate upon the trained neural network within the new model of the mask requiring that any contour shift prediction be a slowly varying function of space.
  • method 600 further includes: using the new model generated by the trained neural network to predict new mask features based on a predicted contour shift generated by the trained neural network to contours of the new mask features as determined by the semi-physical model.
  • the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model to each of a plurality of targets corresponding to points on the features embodied within the physical silicon wafer represented by the SEM images; and in which the neural network smoothes the shift of the contours of the plurality of features of the mask through a regularization process by obtaining values of the contour shift to each of the plurality of targets by a distance- weighted sum of a determined contour shift at other nearby targets within a threshold distance of each target.
  • any target variable to the contour target location is a determination of best fit for vector length from a predicted contour of an Optical Proximity Correction (OPC) base model to a measured contour from the SEM images representing fabrication results for the plurality of features embodied within the physical silicon wafer.
  • OPC Optical Proximity Correction
  • quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images includes: collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the mask as specified by the semi-physical model to determine the differences.
  • quantifying differences includes: measuring critical dimensions of the features embodied by the physical silicon wafer from thousands of the SEM images captured, in which the measuring of the critical dimensions includes measuring at each of a plurality of target points along the contours of the plurality of features of the mask as specified by the semi-physical model and comparing to the plurality of features embodied by the physical silicon wafer to generate millions of data points quantifying the differences between the SEM images and the semi-physical model.
  • method 600 further includes:
  • method 600 further includes: applying correction to the contour generated via the semi-physical model with specified optical intensities, in which the correction includes an initial guess; and iteratively shifting the correction made to the contour via the initial guess to improve the correction until the iterative shifting of the correction made to the contour results in a point on a targeted contour of one of the plurality of features embodied within the physical silicon wafer corresponding to the SEM images.
  • a non-transitory computer readable storage medium having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for reducing Optical Proximity Correction (OPC) model error, in which operations include: creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi- physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality
  • OPC Optical Proximity Correction
  • a system having means by which to reduce Optical Proximity Correction (OPC) model error in which such an exemplary system includes: a mask created via a lithography process; a physical silicon wafer having been fabricated using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; a semi-physical model of the mask created using physical parameters of the lithography process used to create the mask, the semi-physical model to specify contours of the plurality of features of the mask; storage to capture Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; an analysis unit to quantify differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and the analysis unit to shift the contours of the plurality of features of the mask as specified by the semi-physical model based
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials.
  • any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the described embodiments.
  • a plurality of transistors such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate.
  • MOSFET metal-oxide-semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (SiC ) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlay er dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or
  • polytetrafluoroethylene fluorosilicate glass (FSG)
  • organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • FIG. 7 illustrates a computing device 700 in accordance with described embodiments.
  • the computing device 700 houses a board 702.
  • the board 702 may include a number of components, including but not limited to a processor 704 and at least one
  • the processor 704 is physically and electrically coupled to the board 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.
  • computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a
  • the communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless
  • Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704.
  • the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with described embodiments.
  • the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 706 also includes an integrated circuit die packaged within the communication chip 706.
  • the integrated circuit die of the communication chip includes one or more devices, such as MOS- FET transistors built in accordance with described embodiments.
  • another component housed within the computing device 700 may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with described embodiments.
  • the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • FIG 8 illustrates an interposer 800 that includes one or more described embodiments.
  • the interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804.
  • the first substrate 802 may be, for instance, an integrated circuit die.
  • the second substrate 804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804.
  • BGA ball grid array
  • first and second substrates 802/804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800.
  • the interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 812.
  • the interposer 800 may further include embedded devices 814, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800.
  • RF radio- frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.
  • a method for reducing Optical Proximity Correction (OPC) model error comprises: creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi- physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.
  • OPC Optical Proximity Correction
  • the method further includes: performing a regularization operation to smooth the shifting of the contours of the plurality of features of the mask.
  • shifting the contours of the plurality of features of the mask distorts a two dimensional (2D) quantity representing the semi-physical model of the mask; and wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.
  • the method further includes: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model.
  • training the neural network comprises: inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network; and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.
  • training the neural network comprises: inputting SEM images of the physical silicon wafer fabricated using the mask into the neural network; and generating smoothed shifted contours of the plurality of features of the mask via a regularization process; and inputting the smoothed shifted contours of the plurality of features into the neural network.
  • training the neural network comprises: inputting image input parameters based on the SEM images collected, wherein the image input parameters are simulated optical parameters describing the physical parameters of the lithography process used to create the mask.
  • training the neural network comprises: inputting a simulated optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model and an optical transfer function; and wherein the trained neural network generates a deterministic relationship between the layout of the contours of the plurality of features of the mask as specified by the semi-physical model and the quantified differences.
  • OPC Optical Proximity Correction
  • training the neural network comprises: inputting geometric information from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model to directly train the neural network to predict an amount of model error observed in the semi-physical model associated with the input geometric information based on the quantified differences.
  • the trained neural network performs contour fitting of the contours of the plurality of features of the mask as specified by the semi-physical model to the plurality of features embodied within the physical silicon wafer represented within the captured SEM images.
  • the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and wherein the neural network generates a new model of the mask specifying the contours of the plurality of features of the mask shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.
  • the neural network performs a regularization process to smooth the shifted contour, wherein the neural network is trained against over-fitting of the shifted contour by imposing a physical condition mandate upon the trained neural network within the new model of the mask requiring that any contour shift prediction be a slowly varying function of space.
  • the method further includes: using the new model generated by the trained neural network to predict new mask features based on a predicted contour shift generated by the trained neural network to contours of the new mask features as determined by the semi-physical model.
  • the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model to each of a plurality of targets corresponding to points on the features embodied within the physical silicon wafer represented by the SEM images; and wherein the neural network smoothes the shift of the contours of the plurality of features of the mask through a regularization process by obtaining values of the contour shift to each of the plurality of targets by a distance-weighted sum of a determined contour shift at other nearby targets within a threshold distance of each target.
  • any target variable to the contour target location is a determination of best fit for vector length from a predicted contour of an Optical Proximity Correction (OPC) base model to a measured contour from the SEM images representing fabrication results for the plurality of features embodied within the physical silicon wafer.
  • OPC Optical Proximity Correction
  • quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images comprises: collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the mask as specified by the semi-physical model to determine the differences.
  • quantifying differences comprises: measuring critical dimensions of the features embodied by the physical silicon wafer from thousands of the SEM images captured, wherein the measuring of the critical dimensions comprises measuring at each of a plurality of target points along the contours of the plurality of features of the mask as specified by the semi-physical model and comparing to the plurality of features embodied by the physical silicon wafer to generate millions of data points quantifying the differences between the SEM images and the semi-physical model.
  • the method further includes: generating a contour via the semi -physical model with specified optical intensities resulting from light originating at an imager which illuminates the mask, wherein the intensities vary and are nonlinear; and systematically processing the optical intensities to develop a plurality of points on the contour to establish a shape for each of the plurality of features of the mask as specified by the semi- physical model.
  • the method further includes: applying correction to the contour generated via the semi-physical model with specified optical intensities, wherein the correction comprises an initial guess; and iteratively shifting the correction made to the contour via the initial guess to improve the correction until the iterative shifting of the correction made to the contour results in a point on a targeted contour of one of the plurality of features embodied within the physical silicon wafer corresponding to the SEM images.
  • a system to reduce Optical Proximity Correction (OPC) model error comprising: a mask created via a lithography process; a physical silicon wafer having been fabricated using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; a semi-physical model of the mask created using physical parameters of the lithography process used to create the mask, the semi-physical model to specify contours of the plurality of features of the mask; storage to capture Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; an analysis unit to quantify differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and the analysis unit to shift the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.
  • OPC Optical Proximity Correction
  • the analysis unit is to further perform a regularization operation to smooth the shifting of the contours of the plurality of features of the mask; wherein shifting the contours of the plurality of features of the mask distorts a two dimensional (2D) quantity representing the semi-physical model of the mask; and wherein the regularization operation is to smooth the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.
  • a regularization operation to smooth the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.
  • the analysis unit is to further train a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model; wherein training the neural network comprises: inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.
  • non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for reducing Optical Proximity Correction (OPC) model error, wherein operations comprise: creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality of features of the mask as
  • OPC Optical Prox
  • the instructions cause the processor to perform operations further comprising: performing a regularization operation to smooth the shifting of the contours of the plurality of features of the mask; wherein shifting the contours of the plurality of features of the mask distorts a two dimensional (2D) quantity representing the semi-physical model of the mask; and wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.
  • the instructions cause the processor to perform operations further comprising: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model; inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network; and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

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Abstract

Des modes de réalisation de l'invention concernent des procédés, des systèmes et des appareils pour réduire une erreur de modèle de correction de proximité optique (OPC) par l'intermédiaire d'un algorithme d'apprentissage automatique. Un exemple de mode de réalisation comprend des moyens pour créer un masque par l'intermédiaire d'un processus de lithographie ; fabriquer une galette en silicium physique à l'aide du masque, la galette en silicium physique ayant une pluralité de fonctionnalités incorporées dans celle-ci telles qu'elles sont définies par le masque ; créer un modèle semi-physique du masque en utilisant les paramètres physiques du processus de lithographie utilisé pour créer le masque, le modèle semi-physique spécifiant les contours de la pluralité de fonctionnalités du masque ; capturer des images de microscope électronique à balayage (SEM) de la pluralité de fonctionnalités incorporées dans la galette en silicium physique ; quantifier les différences entre (a) les contours de la pluralité de fonctionnalités du masque telles que spécifiées par le modèle semi-physique et (b) la pluralité de fonctionnalités incorporées dans la galette en silicium physique telles qu'elles sont capturées par les images de SEM ; et décaler les contours de la pluralité de fonctionnalités du masque comme spécifié par le modèle semi-physique sur la base des différences quantifiées. L'invention concerne également d'autres modes de réalisation associés.
PCT/US2016/025780 2016-04-02 2016-04-02 Systèmes, procédés et appareils pour réduire une erreur de modèle d'opc par l'intermédiaire d'un algorithme d'apprentissage automatique WO2017171890A1 (fr)

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