WO2017166660A1

WO2017166660A1 - Secure digital card communication method and circuit

Info

Publication number: WO2017166660A1
Application number: PCT/CN2016/097025
Authority: WO
Inventors: 常琪
Original assignee: 乐视控股（北京）有限公司; 乐视致新电子科技（天津）有限公司
Priority date: 2016-03-31
Filing date: 2016-08-26
Publication date: 2017-10-05
Also published as: CN105893895A

Abstract

The invention relates to the field of electronic data storing and processing. An embodiment of the invention relates to a secure digital card communication method and circuit. The secure digital card communication method comprises: using an internal clock signal to perform sampling and holding on a feedback signal on a signal line of a secure digital card so as to generate an internal feedback signal; performing inversion on the original clock signal to generate an inverted clock signal; and using the inverted clock signal to trigger reading of the internal feedback signal.

Description

Safety digital card communication method and circuit

The present application claims priority to Chinese Patent Application No. 2016101957387, the entire disclosure of which is hereby incorporated by reference. Combined in this application.

Technical field

The embodiments of the present application relate to the field of electronic data storage processing, for example, to a communication method and circuit for a secure digital card.

Background technique

The Secure Digital (SD) card is a storage device based on semiconductor flash memory. The SD card was first developed jointly by Japan's Matsushita, Toshiba and the United States' SanDisk Company in August 1999. In 2000, the three companies initiated the establishment of the SD Association (Secure Digital Association, SDA), a strong lineup, attracted a large number of internationally renowned manufacturers to participate. These include IBM, Microsoft, Motorola, NEC, Samsung, and others. Driven by these leading manufacturers, SD cards have become the most widely used memory card in consumer digital devices.

Those skilled in the art will appreciate that in order to maintain efficient communication with the SD card, the SD controller (SD host) needs to maintain a communication connection with the SD card. On an actual printed circuit board (PCB), the above communication connection is generally a PCB trace. The lengths of the wires used to connect the SD controller to the SD card are different due to different layouts of components on different PCBs. This causes a signal to be transmitted from the SD controller to the SD card, or when an SD card is transmitted to the SD controller, a certain phase delay (Phase delay) is generated. Referring to Figure 1, there is a phase delay t between the original clock signal of the SD card and the external clock signal. The original clock signal of the SD card is a clock signal received by the SD card. The external clock signal is a clock signal sent by the SD card controller. Due to the existence of such a phase delay, the feedback signal on the signal line cannot be accurately read on the SD controller side. Once the feedback signal is erroneously read, it causes an incompatibility between the SD card and the entire system.

Summary of the invention

For the above technical problem, the embodiment of the present application provides a communication method and a power of a secure digital card. Road to effectively prevent the occurrence of incompatible digital card.

In a first aspect, an embodiment of the present application provides a communication method for a secure digital card, where the method includes:

Using a internal clock signal to sample and hold a feedback signal on a signal line of the secure digital card to generate an internal feedback signal;

Inverting the original clock signal to generate an inverted clock signal;

The reading of the internal feedback signal is triggered using the inverted clock signal.

Optionally, the signal line includes: a command signal line.

Optionally, the internal clock signal is used to sample and hold the feedback signal on the signal line of the secure digital card to generate an internal feedback signal, including:

Taking the internal clock signal as an input clock signal, the feedback signal is sampled and held by the first D flip-flop to generate the internal feedback signal.

Optionally, the first D flip-flop is a sustain blocking D flip-flop.

Optionally, triggering the reading of the internal feedback signal by using the inverted clock signal includes:

The internal feedback signal is sampled by a second D flip-flop with the inverted clock signal as an input clock signal.

Optionally, the second D flip-flop triggers reading of the internal feedback signal when a rising edge of the inverted clock signal arrives.

Optionally, the second D flip-flop is a sustain blocking D flip-flop.

Optionally, the feedback signal is a feedback signal obtained when a single data block read command or a plurality of data block read commands are executed.

In a second aspect, the embodiment of the present application further provides a communication circuit for a secure digital card, where the circuit includes:

a first D flip-flop, configured to sample and hold a feedback signal on a signal line of the secure digital card using an internal clock signal to generate an internal feedback signal;

An inverter configured to invert an original clock signal to generate an inverted clock signal;

A second D flip-flop is arranged to trigger reading of the internal feedback signal using the inverted clock signal.

Optionally, the first D flip-flop and the second D flip-flop are both maintaining a blocking D flip-flop.

Optionally, the signal line includes: a command signal line.

Optionally, the second D flip-flop triggers when a rising edge of the inverted clock signal arrives The reading of the internal feedback signal.

The application also provides a non-transitory computer storage medium storing computer executable instructions for causing the computer to perform the method of any of the above.

The application also provides an electronic device, including:

At least one processor; and,

a memory communicatively coupled to the at least one processor; wherein

The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the method of any of the above.

The application also provides a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions, when the program instructions are executed by a computer, Having the computer perform the method of any of the above.

A communication method and circuit for a secure digital card provided by an embodiment of the present application, by using an internal clock signal to sample and hold a feedback signal on a signal line of the secure digital card, and using the inverted clock signal to trigger the internal The reading of the feedback signal ensures accurate reading of the feedback signal through timing control, and effectively avoids the occurrence of incompatible digital card.

BRIEF abstract

The one or more embodiments are exemplified by the accompanying drawings in the accompanying drawings, and FIG. The figures in the drawings do not constitute a scale limitation unless otherwise stated.

1 is a timing chart of signals in communication with an SD card in the related art;

2 is a flowchart of a method for communicating a secure digital card according to a first embodiment of the present application;

3 is a signal timing diagram of a plurality of signals when the communication method of the secure digital card is provided in the first embodiment of the present application;

4 is a structural block diagram of a communication circuit of a secure digital card according to a second embodiment of the present application.

FIG. 5 is a schematic diagram showing the hardware structure of an apparatus for performing a communication method of a secure digital card according to a fourth embodiment of the present application.

Implementation

The present application will be described in detail below with reference to the accompanying drawings and embodiments. It is to be understood that the embodiments described herein are merely illustrative of the application and are not intended to be limiting. In addition, it should be noted that, for the convenience of description, only some but not all of the structures related to the present application are shown in the drawings, and the features in the following embodiments may be arbitrarily combined without conflict.

First embodiment

This embodiment provides a technical solution for a communication method of a secure digital card. The communication method of the secure digital card is performed by an SD controller.

Referring to FIG. 2, the communication method of the secure digital card includes:

In S21, the feedback signal on the signal line of the secure digital card is sampled and held using an internal clock signal to generate an internal feedback signal.

The internal clock signal is a clock signal formed inside the SD card after the SD controller receives an external clock signal when communicating with the SD card. On the signal waveform, the internal clock signal is the same as the waveform of the external clock signal, and is a rectangular square wave. In the timing relationship, the internal clock signal has a certain time delay compared to the external clock signal.

The signal line refers to a signal line of the SD card controller that is connected to a command (Command, CMD) line of the SD card. According to the definition of a plurality of pins of the SD card, the signal line should be a bidirectional signal line. That is, on the signal line, either the signal from the SD card to the SD card controller or the signal from the SD card controller to the SD card can be transmitted.

Since the signal line is a bidirectional signal line, it can be understood that when the SD card controller sends a command to the SD card, the SD card can acquire a corresponding feedback signal through the signal line. In this embodiment, the feedback signal is a feedback signal obtained by executing a single data block read command or a plurality of data block read commands, that is, CMD17 or CMD18 commands.

In this embodiment, after receiving the feedback signal, the SD card controller samples and holds the feedback signal by using a first D flip-flop. And, the clock signal input to the first D flip-flop is the internal clock signal described above. The first D flip-flop is a sustain blocking D flip-flop.

In S22, the original clock signal is inverted to generate an inverted clock signal.

The original clock signal is a clock signal received by an SD card.

Typically, the SD card controller employs an inverter to perform the inverting process of the original clock signal. Moreover, optionally, the inverter may be a NOT circuit.

In S23, the reading of the internal feedback signal is triggered using the inverted clock signal.

In this embodiment, a second D flip-flop is employed to trigger the reading of the internal feedback signal. The internal feedback signal of the signal input to the signal input of the second D flip-flop, and the signal input to the clock input of the second D flip-flop is the inverted clock signal. The second D flip-flop is a sustain blocking D flip-flop.

FIG. 3 shows the timing relationship of a plurality of signals when the communication method of the secure digital card provided by the embodiment is performed. Referring to Figure 3, t ₁ is the phase delay between the external clock signal and the original clock signal of the SD card, and t ₂ is the phase delay between the external clock signal and the internal clock signal of the SD card controller. The sum of t ₁ and t ₂ described above is already close to the half cycle duration of the clock signal. That is, the phase delay between the original clock signal of the SD card and the internal clock signal of the SD card controller is close to half a cycle. Therefore, if the clock signal of the SD card is used to trigger the reading of the internal feedback signal, the problem that the feedback time establishment time is insufficient will still be solved, and the problem of incompatibility of the SD card cannot be completely solved. Therefore, it is necessary to trigger the reading of the internal feedback signal by using a clock signal of the inverted SD card to ensure that the internal feedback signal has sufficient settling time.

In this embodiment, the feedback signal on the signal line of the secure digital card is sampled and held by using an internal clock signal, the original clock signal is inverted to generate an inverted clock signal, and the inverted clock signal is used to trigger the pair. The reading of the internal feedback signal effectively avoids the occurrence of a situation in which the secure digital card is incompatible.

Second embodiment

This embodiment provides a technical solution of a communication circuit of a secure digital card. In this technical solution, the secure digital card is integrated in an SD controller.

Referring to FIG. 4, the communication circuit of the secure digital card includes a first D flip-flop 41, an inverter 42, and a second D flip-flop 43.

The signal input end of the first D flip-flop 41 is connected to a feedback signal on the signal line, and the clock input end is connected to an internal clock signal of the SD card controller, and is configured to generate an internal feedback signal of the SD card controller. That is, the first D flip-flop 41 is arranged to sample and hold the feedback signal on the signal line of the secure digital card using an internal clock signal to generate an internal feedback signal.

Exemplarily, the signal line may be a CMD signal line of the SD card.

The inverter 42 is arranged to invert the original clock signal. The inverter 42 outputs an inverted clock signal after inversion of the original clock signal.

Optionally, the inverter 42 can be a logic NOT circuit.

The signal input end of the second D flip-flop 43 is connected to the internal feedback signal generated by the first D flip-flop 41, and the clock input terminal is connected to the inverted external clock signal. So configured, the second D flip-flop 43 can trigger the reading of the internal feedback signal and ensure that the SD card is not compatible.

Optionally, the second D flip-flop 43 may trigger the reading of the internal feedback signal when a rising edge of the inverted clock signal arrives.

In the embodiment of the present application, the first D flip-flop 41 and the second D flip-flop 43 are both maintaining a blocking D flip-flop.

In this embodiment, through the mutual connection between the first D flip-flop, the inverter, and the second D flip-flop, the feedback signal of the signal line of the secure digital card is sampled and held by the first D flip-flop, and the anti- The phase detector inverts the internal clock signal and triggers reading of the internal feedback signal through the second D flip-flop, thereby effectively preventing the occurrence of an SD card incompatibility.

Third embodiment

The present application also provides a non-transitory computer storage medium storing computer executable instructions for causing the computer to perform the methods described in the above embodiments.

Fourth embodiment

FIG. 5 is a schematic diagram showing the hardware structure of an apparatus for performing a communication method of a secure digital card according to a fourth embodiment of the present application. As shown in Figure 5, the device includes:

One or more processors 51 and a memory 52 are exemplified by a processor 51 in FIG.

The apparatus may also include an input device 53 and an output device 54.

The processor 51, the memory 52, the input device 53, and the output device 54 may be connected by a bus or other means, as exemplified by a bus connection in FIG.

The memory 52 is used as a non-transitory computer readable storage medium, and can be used for storing non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions corresponding to the communication method of the secure digital card in the embodiment of the present application. / Module (for example, the first D flip-flop 41, the inverter 42 and the second D flip-flop 43 shown in FIG. 4). The processor 51 executes various functional applications and data processing of the server by running non-transitory software programs, instructions, and modules stored in the memory 52, that is, the communication method of the secure digital card of the above method embodiment.

The memory 52 can include a storage program area and a storage data area, wherein the storage program area can store operations The system, the application required for at least one function; the storage data area can store data created according to the use of the communication device of the secure digital card, and the like. Moreover, memory 52 can include high speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 52 may optionally include memory remotely located relative to processor 51, which may be connected to the communication device of the secure digital card via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 53 can receive the input digital or character information and generate a key signal input related to user settings and function control of the communication device of the secure digital card. Output device 54 may include a display device such as a display screen.

The one or more modules are stored in the memory 52, and when executed by the one or more processors 51, perform a communication method of the secure digital card in any of the above method embodiments.

The above-mentioned products can be implemented in the method provided by the embodiments of the present application, and the functional modules and the beneficial effects of the method are not described in detail in the embodiments.

Finally, it should be understood that those skilled in the art can understand that all or part of the process of implementing the above embodiments can be completed by a computer program to instruct related hardware, and the program can be stored in a computer readable. In the storage medium, when the program is executed, the flow of the embodiments of the above methods may be included. The storage medium may be a magnetic disk, an optical disk, a read only memory (ROM), or a random access memory (RAM).

The above description is only an optional embodiment of the present application, and is not intended to limit the present application. Many changes and modifications may be made to the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application are intended to be included within the scope of the present application.

Industrial applicability

Claims

A communication method for a secure digital card, comprising:

Using a internal clock signal to sample and hold a feedback signal on a signal line of the secure digital card to generate an internal feedback signal;

Inverting the original clock signal to generate an inverted clock signal;

The reading of the internal feedback signal is triggered using the inverted clock signal.
The method of communicating a secure digital card according to claim 1, wherein said signal line comprises: a command signal line.
The communication method of the secure digital card according to claim 1 or 2, wherein the sampling and holding of the feedback signal on the signal line of the secure digital card using the internal clock signal to generate the internal feedback signal comprises:

Taking the internal clock signal as an input clock signal, the feedback signal is sampled and held by the first D flip-flop to generate the internal feedback signal.
The method of communicating a secure digital card according to claim 3, wherein said first D flip-flop is a sustain blocking D flip-flop.
The method of communicating a secure digital card according to claim 1 or 2, wherein the triggering the reading of the internal feedback signal using the inverted clock signal comprises:

The internal feedback signal is sampled by a second D flip-flop with the inverted clock signal as an input clock signal.
The method of communicating a secure digital card according to claim 5, wherein said second D flip-flop triggers reading of said internal feedback signal when a rising edge of said inverted clock signal arrives.
The secure digital card communication method according to claim 6, wherein said second D flip-flop is a sustain blocking D flip-flop.
The communication method of the secure data card according to claim 1 or 2, wherein the feedback signal is a feedback signal obtained when a single data block read command or a plurality of data block read commands are executed.
A communication circuit for a secure digital card, comprising:

a first D flip-flop, configured to sample and hold a feedback signal on a signal line of the secure digital card using an internal clock signal to generate an internal feedback signal;

An inverter configured to invert an original clock signal to generate an inverted clock signal;

A second D flip-flop is arranged to trigger reading of the internal feedback signal using the inverted clock signal.
A communication circuit for a secure digital card according to claim 9, wherein said first D touch Both the transmitter and the second D flip-flop are sustain blocking D flip-flops.
A communication circuit for a secure digital card according to claim 9, wherein said signal line comprises: a command signal line.
A communication circuit for a secure digital card according to claim 9, wherein said second D flip-flop triggers reading of said internal feedback signal when a rising edge of said inverted clock signal arrives.
A communication circuit for a secure digital card according to claim 9, wherein said feedback signal is a feedback signal obtained when a single block read command or a plurality of block read commands are executed.
A non-transitory computer storage medium storing computer executable instructions for causing the computer to perform the method of any of claims 1-8.
An electronic device comprising:

At least one processor; and,

a memory communicatively coupled to the at least one processor; wherein

The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the method of any of claims 1-8 method.
A computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to execute The method of any of claims 1-8.