CN103050144A - Power supply transmission circuit of memory card - Google Patents
Power supply transmission circuit of memory card Download PDFInfo
- Publication number
- CN103050144A CN103050144A CN2012105855859A CN201210585585A CN103050144A CN 103050144 A CN103050144 A CN 103050144A CN 2012105855859 A CN2012105855859 A CN 2012105855859A CN 201210585585 A CN201210585585 A CN 201210585585A CN 103050144 A CN103050144 A CN 103050144A
- Authority
- CN
- China
- Prior art keywords
- circuit
- cpu
- resistance
- power delivery
- storage card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Power Sources (AREA)
- Logic Circuits (AREA)
- Credit Cards Or The Like (AREA)
Abstract
The invention provides a power supply transmission circuit of a memory card. The power supply transmission circuit comprises a waveform tidying circuit and a time sequence adjusting circuit, wherein the waveform tidying circuit is serially connected between an SD card and a CPU to adjust the transmission signal between the SD card and the CPU to meet preset threshold value, and the capacity of resisting disturbance is improved; the time sequence adjusting circuit is connected with the waveform tidying circuit and is used for adjusting the time sequence of an SDIO (Secure Digital Input Output) bus so as to enable waveform of transmission signals to perform time delay, and the problem of slow card reading speed caused by transmission data is solved.
Description
Technical field
The present invention relates to circuit field, relate in particular a kind of storage card power delivery circuit.
Background technology
Along with the development of science and technology, electronic product becomes the requisite part of daily life.Usually, the quality of Quality of electronic products can be judged by a plurality of factors such as CPU frequency, storage space, resolution.And storage space can be divided into internal memory and external memory.External memory can show as flash card (Flash Card), and it is to utilize flash memory (Flash Memory) technology to reach the storer of storage of electronic information.
According to different production firms and different application, flash card can be divided into SM card (SmartMedia), CF card (Compact Flash), mmc card (MultiMediaCard), SD card (Secure Digital), memory stick (Memory Stick), XD card (XD-Picture Card) and micro harddisk (MICRODRIVE) etc.Although these flash card outward appearances, specification difference, know-why is almost identical.Because the plurality of advantages of flash card and the application of flash card, flash card has replaced traditional storage medium gradually, is widely used in other electronic equipments such as digital camera and mobile phone.
In the prior art, adopt CPU is directly linked to each other with the SD card, and carry out the data of SD card are read and write operation in the mode that an end of SD card adds phasmajector ground connection, as shown in Figure 1.But when the cabling between SD card and the CPU is very long (usually being defined as greater than 12cm), can cause the signal skew transmitted between CPU and the SD card, increase the bit error rate of SD card, and cause card reading speed slack-off.Except this, when there is static in the external world, also may pass to CPU by some static, cause CPU to damage.
Summary of the invention
In view of this, the invention provides a kind of storage card power delivery circuit, effectively solved high, the slow problem of reading speed of the long SD card bit error rate that causes of cabling in the prior art.
For achieving the above object, the invention provides following technical scheme:
A kind of storage card power delivery circuit comprises:
Be serially connected between SD card and the CPU, be used for regulating the waveform finishing circuit that satisfies default threshold value of signal transmission between described SD card and the described CPU;
Link to each other with described waveform finishing circuit, be used for to regulate the sequential of SDIO bus, make the waveform of described signal transmission carry out the time sequence adjusting circuit of time delay.
Preferably, also comprise:
Link to each other with described waveform finishing circuit, for the electrostatic discharge protection circuit of the static of eliminating described signal transmission.
Preferably, described waveform finishing circuit comprises at least one regulating circuit,
Described regulating circuit comprises: the first resistance, the second resistance, pull-up resistor and operational amplifier,
The data input pin of described regulating circuit links to each other with the inverting input of described operational amplifier, the first end of described the first resistance links to each other respectively at the first end of external voltage Vcc and described pull-up resistor, the second end of described the first resistance links to each other with the in-phase input end of described operational amplifier and the first end of described the second resistance respectively, the second end ground connection of described the second resistance, the output terminal of described operational amplifier links to each other with the second end of described pull-up resistor, and as the data output end of described regulating circuit.
Preferably, CLK line and data line all are serially connected with described regulating circuit.
Preferably, described time sequence adjusting circuit comprises: the 3rd resistance and the first electric capacity,
Described the 3rd resistance string is connected between the inverting input of the data input pin of described regulating circuit and described operational amplifier, and described the first capacitance series is between the inverting input and ground of described operational amplifier.
Preferably, described electrostatic discharge protection circuit comprises:
Be serially connected in the data output end of described regulating circuit and the voltage dependent resistor (VDR) between the CPU.
Preferably, described electrostatic discharge protection circuit comprises:
Be serially connected in data output end and the pipe of the TVS between the CPU of described regulating circuit.
Preferably, described electrostatic discharge protection circuit comprises:
Be serially connected in data output end and the pipe of the ESD between the CPU of described regulating circuit.
Via above-mentioned technical scheme as can be known, compared with prior art, the invention provides a kind of storage card power delivery circuit, comprise: waveform finishing circuit and time sequence adjusting circuit, wherein, the waveform finishing circuit is serially connected between SD card and the CPU, and the signal transmission of regulating between described SD card and the described CPU satisfies default threshold value, has improved antijamming capability.Time sequence adjusting circuit links to each other with described waveform finishing circuit, is used for regulating the sequential of SDIO bus, makes the waveform of described signal transmission carry out time delay, has solved the slack-off problem of card reading speed that causes because of the transmission of data.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is embodiments of the invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to the accompanying drawing that provides other accompanying drawing.
Fig. 1 is in the prior art, the structural representation that the SD card is connected with CPU;
Fig. 2 is the structural representation of a kind of storage card power delivery circuit provided by the invention;
Fig. 3 is the another structural representation of a kind of storage card power delivery circuit provided by the invention;
Fig. 4 is the structural representation of regulating circuit in a kind of storage card power delivery circuit provided by the invention;
Fig. 5 is the structural representation of time sequence adjusting circuit in a kind of storage card power delivery circuit provided by the invention;
Fig. 6 is oscillogram in a kind of storage card power delivery circuit provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
See also Fig. 1, in prior art, the structural representation that the SD card is connected with CPU wherein, directly links to each other CPU with the SD card, and carries out the data of SD card are read and write operation in the mode that an end of SD card adds phasmajector ground connection.But when the cabling between SD card and the CPU is very long (usually being defined as greater than 12cm), can cause the signal skew transmitted between CPU and the SD card, increase the bit error rate of SD card, and cause card reading speed slack-off.Except this, when there is static in the external world, also may pass to CPU by some static, cause CPU to damage.
Embodiment one
For addressing the above problem, the embodiment of the invention provides a kind of storage card power delivery circuit, please participate in Fig. 2, comprising: waveform finishing circuit 101 and time sequence adjusting circuit 102, wherein,
See also Fig. 4 and Fig. 5, wherein, Fig. 4 is the structural representation of regulating circuit in a kind of storage card power delivery circuit provided by the invention, and Fig. 5 is the structural representation of time sequence adjusting circuit in a kind of storage card power delivery circuit provided by the invention.
Concrete, described waveform finishing circuit 101 comprises at least one regulating circuit 1011, as shown in Figure 4, described regulating circuit 1011 comprises: the first resistance R 1, the second resistance R 2, pull-up resistor R244 and operational amplifier U21A.
The annexation of each device is:
The data input pin Datain of described regulating circuit 1011 links to each other with the inverting input of described operational amplifier U21A (being 2 ends among Fig. 4).The first end of described the first resistance R 1 links to each other respectively at the first end of external voltage Vcc and described pull-up resistor R244, the second end of described the first resistance R 1 links to each other with in-phase input end (4 3 ends among the figure) and the first end of described the second resistance R 2 of described operational amplifier U21A respectively, the second end ground connection of described the second resistance R 2, the output terminal of described operational amplifier U21A (1 end among Fig. 4) links to each other with the second end of described pull-up resistor R244, and as the data output end Dataout of described regulating circuit 1011.
The principle of work of this regulating circuit 1011 is: when signal transmits, because signal is affected by external factor, the phenomenon of signal skew can occur.Operational amplifier in this circuit is placed on the end near the SD card, utilizes the characteristic of amplifier, can only export high level or low level.And by regulating the ratio of R1 and R2, can determine to export high level and low level threshold values.And then raising antijamming capability.
Here need to prove that in actual applications, CLK line and data line all are serially connected with described regulating circuit 1011, so that its signal transmission meets the digital circuit standard.
Concrete, seeing also Fig. 5, described time sequence adjusting circuit 102 comprises: the 3rd resistance R 3 and the first capacitor C 1.
The annexation of each device is:
Described the 3rd resistance R 3 is serially connected between the inverting input of the data input pin Datain of described regulating circuit 1011 and described operational amplifier U21A, and described the first capacitor C 1 is serially connected between the inverting input and ground of described operational amplifier U21A.
The principle of work of this time sequence adjusting circuit is:
By adjusting the size of the 3rd resistance R 3 and the first capacitor C 1, make the waveform of described signal transmission carry out time delay, as shown in Figure 6.Fig. 6 is oscillogram in a kind of storage card power delivery circuit provided by the invention.
Embodiment two
See also Fig. 3, be the another structural representation of a kind of storage card power delivery circuit provided by the invention, this embodiment is on the basis of embodiment one, has also set up electrostatic discharge protection circuit 103.
Wherein, described electrostatic discharge protection circuit 103 links to each other with described waveform finishing circuit 101, is used for eliminating the static of described signal transmission.
Preferably, described electrostatic discharge protection circuit can for voltage dependent resistor (VDR), TVS pipe and/or ESD pipe, not done concrete restriction at this.Need to prove that described voltage dependent resistor (VDR), TVS pipe or ESD pipe all are serially connected between the data output end and CPU of described regulating circuit
To sum up, the invention provides a kind of storage card power delivery circuit, comprise: waveform finishing circuit and time sequence adjusting circuit, wherein, the waveform finishing circuit is serially connected between SD card and the CPU, the signal transmission of regulating between described SD card and the described CPU satisfies default threshold value, has improved antijamming capability.Time sequence adjusting circuit links to each other with described waveform finishing circuit, is used for regulating the sequential of SDIO bus, makes the waveform of described signal transmission carry out time delay, has solved the slack-off problem of card reading speed that causes because of the transmission of data.
Each embodiment adopts the mode of going forward one by one to describe in this instructions, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For the device that embodiment provides, because it is corresponding with the method that embodiment provides, so description is fairly simple, relevant part partly illustrates referring to method and gets final product.
Above-mentioned explanation to the embodiment that provides makes this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but principle and the features of novelty the widest consistent scope that provides with this paper will be provided.
Claims (8)
1. a storage card power delivery circuit is characterized in that, comprising:
Be serially connected between SD card and the CPU, be used for regulating the waveform finishing circuit that satisfies default threshold value of signal transmission between described SD card and the described CPU;
Link to each other with described waveform finishing circuit, be used for to regulate the sequential of SDIO bus, make the waveform of described signal transmission carry out the time sequence adjusting circuit of time delay.
2. storage card power delivery circuit according to claim 1 is characterized in that, also comprises:
Link to each other with described waveform finishing circuit, for the electrostatic discharge protection circuit of the static of eliminating described signal transmission.
3. storage card power delivery circuit according to claim 1 is characterized in that, described waveform finishing circuit comprises at least one regulating circuit,
Described regulating circuit comprises: the first resistance, the second resistance, pull-up resistor and operational amplifier,
The data input pin of described regulating circuit links to each other with the inverting input of described operational amplifier, the first end of described the first resistance links to each other respectively at the first end of external voltage Vcc and described pull-up resistor, the second end of described the first resistance links to each other with the in-phase input end of described operational amplifier and the first end of described the second resistance respectively, the second end ground connection of described the second resistance, the output terminal of described operational amplifier links to each other with the second end of described pull-up resistor, and as the data output end of described regulating circuit.
4. storage card power delivery circuit according to claim 3 is characterized in that CLK line and data line all are serially connected with described regulating circuit.
5. storage card power delivery circuit according to claim 1 is characterized in that described time sequence adjusting circuit comprises: the 3rd resistance and the first electric capacity,
Described the 3rd resistance string is connected between the inverting input of the data input pin of described regulating circuit and described operational amplifier, and described the first capacitance series is between the inverting input and ground of described operational amplifier.
6. storage card power delivery circuit according to claim 2 is characterized in that described electrostatic discharge protection circuit comprises:
Be serially connected in the data output end of described regulating circuit and the voltage dependent resistor (VDR) between the CPU.
7. storage card power delivery circuit according to claim 2 is characterized in that described electrostatic discharge protection circuit comprises:
Be serially connected in data output end and the pipe of the TVS between the CPU of described regulating circuit.
8. storage card power delivery circuit according to claim 2 is characterized in that described electrostatic discharge protection circuit comprises:
Be serially connected in data output end and the pipe of the ESD between the CPU of described regulating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210585585.9A CN103050144B (en) | 2012-12-30 | 2012-12-30 | A kind of storage card power delivery circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210585585.9A CN103050144B (en) | 2012-12-30 | 2012-12-30 | A kind of storage card power delivery circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103050144A true CN103050144A (en) | 2013-04-17 |
| CN103050144B CN103050144B (en) | 2016-05-25 |
Family
ID=48062756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210585585.9A Active CN103050144B (en) | 2012-12-30 | 2012-12-30 | A kind of storage card power delivery circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103050144B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017166660A1 (en) * | 2016-03-31 | 2017-10-05 | 乐视控股（北京）有限公司 | Secure digital card communication method and circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080080254A1 (en) * | 2006-09-29 | 2008-04-03 | Yishai Kagan | Dual Voltage Flash Memory Methods |
| CN101566675A (en) * | 2009-05-25 | 2009-10-28 | 王文新 | Method and device for monitoring working condition of flash lamp |
| CN201754502U (en) * | 2010-07-30 | 2011-03-02 | 曲阜嘉信电气有限公司 | Overcurrent protection device capable of adjusting overcurrent value by software |
| CN102098010A (en) * | 2010-12-28 | 2011-06-15 | 山西太钢不锈钢股份有限公司 | Multifunctional hydraulic servo power amplifier |
| CN202486738U (en) * | 2011-12-31 | 2012-10-10 | 深圳市凌启电子有限公司 | Protecting device and system based on touch screen |
| CN203102871U (en) * | 2012-12-30 | 2013-07-31 | 深圳市凌启电子有限公司 | Power supply transmission circuit for storage card |
-
2012
- 2012-12-30 CN CN201210585585.9A patent/CN103050144B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080080254A1 (en) * | 2006-09-29 | 2008-04-03 | Yishai Kagan | Dual Voltage Flash Memory Methods |
| CN101566675A (en) * | 2009-05-25 | 2009-10-28 | 王文新 | Method and device for monitoring working condition of flash lamp |
| CN201754502U (en) * | 2010-07-30 | 2011-03-02 | 曲阜嘉信电气有限公司 | Overcurrent protection device capable of adjusting overcurrent value by software |
| CN102098010A (en) * | 2010-12-28 | 2011-06-15 | 山西太钢不锈钢股份有限公司 | Multifunctional hydraulic servo power amplifier |
| CN202486738U (en) * | 2011-12-31 | 2012-10-10 | 深圳市凌启电子有限公司 | Protecting device and system based on touch screen |
| CN203102871U (en) * | 2012-12-30 | 2013-07-31 | 深圳市凌启电子有限公司 | Power supply transmission circuit for storage card |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017166660A1 (en) * | 2016-03-31 | 2017-10-05 | 乐视控股（北京）有限公司 | Secure digital card communication method and circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103050144B (en) | 2016-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20140169090A1 (en) | Memory card for storing and transmitting data | |
| US8582388B1 (en) | Serial advanced technology attachment dual in-line memory module (SATA DIMM) capable of preventing data loss | |
| JP2009176136A (en) | Semiconductor storage device | |
| US9852062B2 (en) | Memory controller and accessing system utilizing the same | |
| US10146265B1 (en) | Main board slot power control circuit | |
| CN104008079A (en) | Data read-write circuit capable of being simultaneously inserted into SD card and TF card | |
| US20140082250A1 (en) | EMBEDDED MULTIMEDIA CARD (eMMC), HOST FOR CONTROLLING eMMC, AND METHOD OPERATION FOR eMMC SYSTEM | |
| CN109073699B (en) | Connection cable with voltage level indicator | |
| CN203102871U (en) | Power supply transmission circuit for storage card | |
| CN103050144A (en) | Power supply transmission circuit of memory card | |
| CN202150274U (en) | Anti-lost circuit structure for EEPROM (Electrically Erasable Programmable Read Only Memory) data | |
| CN103123530A (en) | Solid state disk | |
| CN115858426A (en) | Hard disk interface, hard disk and electronic equipment | |
| CN109240957A (en) | M.2 hard-disk interface turns usb circuit and conversion method to one kind | |
| CN209929634U (en) | Multifunctional data line | |
| US9251454B2 (en) | Storage medium, transmittal system and control method thereof | |
| CN201765835U (en) | USB externally connected device | |
| CN205942601U (en) | Electronic equipment interface communication reduces device of consumption | |
| KR102433013B1 (en) | Memory module and solid state disk having the same | |
| CN101089991A (en) | Electronic product with Flash and its software updating method | |
| CN104809091A (en) | Adapter device | |
| CN103780995A (en) | Audio signal output device | |
| US9697893B2 (en) | Driving circuit with adjustable termination resistor | |
| CN212749888U (en) | SMD SD NAND Flash storage IC | |
| CN202551059U (en) | Multifunctional USB (Universal Serial Bus) network card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |