CN203102871U - Power supply transmission circuit for storage card - Google Patents
Power supply transmission circuit for storage card Download PDFInfo
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- CN203102871U CN203102871U CN 201220741371 CN201220741371U CN203102871U CN 203102871 U CN203102871 U CN 203102871U CN 201220741371 CN201220741371 CN 201220741371 CN 201220741371 U CN201220741371 U CN 201220741371U CN 203102871 U CN203102871 U CN 203102871U
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- circuit
- storage card
- cpu
- resistance
- power delivery
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Abstract
The utility model provides a power supply transmission circuit for a storage card. The power supply transmission circuit comprises a waveform arrangement circuit and a time sequence regulation circuit, wherein the waveform arrangement circuit is connected between an SD (Secure Digital) card and a CPU (Central Processing Unit) in series and is used for regulating transmission signals between the SD card and the CPU to meet a preset threshold, thus improving an anti-jamming capability; and the time sequence regulation circuit is connected with the waveform arrangement circuit and is used for regulating time sequences of an SDIO (Secure Digital Input Output) bus to carry out time delay on waveforms of the transmission signals, thus solving the problem that the card reading speed is slowed caused by data transmission.
Description
Technical field
The utility model relates to circuit field, relates to a kind of storage card power delivery circuit in particular.
Background technology
Along with the continuous development of science and technology, electronic product becomes the daily life necessary part.Usually, the quality of electronic product quality can be judged by a plurality of factors such as CPU frequency, storage space, resolution.And storage space can be divided into internal memory and external memory.External memory can show as flash card (Flash Card), and it is to utilize flash memory (Flash Memory) technology to reach the storer of storage of electronic information.
According to different production firms and different application, flash card can be divided into SM card (SmartMedia), CF card (Compact Flash), mmc card (MultiMediaCard), SD card (Secure Digital), memory stick (Memory Stick), XD card (XD-Picture Card) and micro harddisk (MICRODRIVE) etc.Though these flash card outward appearances, specification difference, know-why much at one.Because the plurality of advantages of flash card and the application of flash card, flash card has replaced traditional storage medium gradually, is widely used in other electronic equipments such as digital camera and mobile phone.
In the prior art, adopt CPU is directly linked to each other with the SD card, and carry out data read and write operation, as shown in Figure 1 the SD card in the mode that an end of SD card adds phasmajector ground connection.But when the cabling between SD card and the CPU is very long (being defined as greater than 12cm usually), can cause the signal skew transmitted between CPU and the SD card, increase the bit error rate of SD card, and cause card reading speed slack-off.Remove this, when there is static in the external world, also may pass to CPU by some static, cause CPU to damage.
The utility model content
In view of this, the utility model provides a kind of storage card power delivery circuit, has effectively solved long SD card bit error rate height, the slow problem of reading speed that causes of cabling in the prior art.
For achieving the above object, the utility model provides following technical scheme:
A kind of storage card power delivery circuit comprises:
Be serially connected between SD card and the CPU, be used to regulate the waveform finishing circuit that satisfies preset threshold value of transmission signals between described SD card and the described CPU;
Link to each other with described waveform finishing circuit, be used to regulate the sequential of SDIO bus, make the waveform of described transmission signals carry out the time sequence adjusting circuit of time delay.
Preferably, also comprise:
Link to each other with described waveform finishing circuit, be used to eliminate the electrostatic discharge protection circuit of the static of described transmission signals.
Preferably, described waveform finishing circuit comprises at least one regulating circuit,
Described regulating circuit comprises: first resistance, second resistance, pull-up resistor and operational amplifier,
The data input pin of described regulating circuit links to each other with the inverting input of described operational amplifier, first end of described first resistance links to each other respectively at first end of external voltage Vcc and described pull-up resistor, second end of described first resistance links to each other with the in-phase input end of described operational amplifier and first end of described second resistance respectively, the second end ground connection of described second resistance, the output terminal of described operational amplifier links to each other with second end of described pull-up resistor, and as the data output end of described regulating circuit.
Preferably, CLK line and data line all are serially connected with described regulating circuit.
Preferably, described time sequence adjusting circuit comprises: the 3rd resistance and first electric capacity,
Described the 3rd resistance string is connected between the inverting input of the data input pin of described regulating circuit and described operational amplifier, and described first capacitance series is between the inverting input and ground of described operational amplifier.
Preferably, described electrostatic discharge protection circuit comprises:
Be serially connected in the data output end of described regulating circuit and the voltage dependent resistor (VDR) between the CPU.
Preferably, described electrostatic discharge protection circuit comprises:
Be serially connected in the data output end and the pipe of the TVS between the CPU of described regulating circuit.
Preferably, described electrostatic discharge protection circuit comprises:
Be serially connected in the data output end and the pipe of the ESD between the CPU of described regulating circuit.
Via above-mentioned technical scheme as can be known, compared with prior art, the utility model provides a kind of storage card power delivery circuit, comprise: waveform finishing circuit and time sequence adjusting circuit, wherein, the waveform finishing circuit is serially connected between SD card and the CPU, and the transmission signals of regulating between described SD card and the described CPU satisfies preset threshold value, has improved antijamming capability.Time sequence adjusting circuit links to each other with described waveform finishing circuit, is used to regulate the sequential of SDIO bus, makes the waveform of described transmission signals carry out time delay, has solved the slack-off problem of card reading speed that causes because of the transmission data.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to the accompanying drawing that provides.
Fig. 1 is in the prior art, the structural representation that the SD card is connected with CPU;
The structural representation of a kind of storage card power delivery circuit that Fig. 2 provides for the utility model;
The another structural representation of a kind of storage card power delivery circuit that Fig. 3 provides for the utility model;
The structural representation of regulating circuit in a kind of storage card power delivery circuit that Fig. 4 provides for the utility model;
The structural representation of time sequence adjusting circuit in a kind of storage card power delivery circuit that Fig. 5 provides for the utility model;
Oscillogram in a kind of storage card power delivery circuit that Fig. 6 provides for the utility model.
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
See also Fig. 1, in prior art, the structural representation that the SD card is connected with CPU wherein, directly links to each other CPU with the SD card, and carries out data read and write operation to the SD card in the mode that an end of SD card adds phasmajector ground connection.But when the cabling between SD card and the CPU is very long (being defined as greater than 12cm usually), can cause the signal skew transmitted between CPU and the SD card, increase the bit error rate of SD card, and cause card reading speed slack-off.Remove this, when there is static in the external world, also may pass to CPU by some static, cause CPU to damage.
Embodiment one
For addressing the above problem, the utility model embodiment provides a kind of storage card power delivery circuit, please participate in Fig. 2, comprising: waveform finishing circuit 101 and time sequence adjusting circuit 102, wherein,
See also Fig. 4 and Fig. 5, wherein, the structural representation of time sequence adjusting circuit in a kind of storage card power delivery circuit that the structural representation of regulating circuit in a kind of storage card power delivery circuit that Fig. 4 provides for the utility model, Fig. 5 provide for the utility model.
Concrete, described waveform finishing circuit 101 comprises at least one regulating circuit 1011, as shown in Figure 4, described regulating circuit 1011 comprises: first resistance R 1, second resistance R 2, pull-up resistor R244 and operational amplifier U21A.
The annexation of each device is:
The data input pin Datain of described regulating circuit 1011 links to each other with the inverting input of described operational amplifier U21A (being 2 ends among Fig. 4).First end of described first resistance R 1 links to each other respectively at first end of external voltage Vcc and described pull-up resistor R244, second end of described first resistance R 1 links to each other with in-phase input end (4 3 ends among the figure) and first end of described second resistance R 2 of described operational amplifier U21A respectively, the second end ground connection of described second resistance R 2, the output terminal of described operational amplifier U21A (1 end among Fig. 4) links to each other with second end of described pull-up resistor R244, and as the data output end Dataout of described regulating circuit 1011.
The principle of work of this regulating circuit 1011 is: when signal transmits, because of signal is influenced by external factor, the phenomenon of signal skew can occur.Operational amplifier in this circuit is placed on the end near the SD card, utilizes the characteristic of amplifier, can only export high level or low level.And, can determine to export high level and low level threshold values by regulating the ratio of R1 and R2.And then raising antijamming capability.
Here need to prove that in actual applications, CLK line and data line all are serially connected with described regulating circuit 1011, so that its transmission signals meets the digital circuit standard.
Concrete, seeing also Fig. 5, described time sequence adjusting circuit 102 comprises: the 3rd resistance R 3 and first capacitor C 1.
The annexation of each device is:
Described the 3rd resistance R 3 is serially connected between the inverting input of the data input pin Datain of described regulating circuit 1011 and described operational amplifier U21A, and described first capacitor C 1 is serially connected between the inverting input and ground of described operational amplifier U21A.
The principle of work of this time sequence adjusting circuit is:
By adjusting the size of the 3rd resistance R 3 and first capacitor C 1, make the waveform of described transmission signals carry out time delay, as shown in Figure 6.Oscillogram in a kind of storage card power delivery circuit that Fig. 6 provides for the utility model.
Embodiment two
See also Fig. 3, the another structural representation of a kind of storage card power delivery circuit that provides for the utility model, this embodiment is on the basis of embodiment one, has also set up electrostatic discharge protection circuit 103.
Wherein, described electrostatic discharge protection circuit 103 links to each other with described waveform finishing circuit 101, is used to eliminate the static of described transmission signals.
Preferably, described electrostatic discharge protection circuit can not done concrete qualification at this for voltage dependent resistor (VDR), TVS pipe and/or ESD pipe.Need to prove that described voltage dependent resistor (VDR), TVS pipe or ESD pipe all are serially connected between the data output end and CPU of described regulating circuit
To sum up, the utility model provides a kind of storage card power delivery circuit, comprise: waveform finishing circuit and time sequence adjusting circuit, wherein, the waveform finishing circuit is serially connected between SD card and the CPU, the transmission signals of regulating between described SD card and the described CPU satisfies preset threshold value, has improved antijamming capability.Time sequence adjusting circuit links to each other with described waveform finishing circuit, is used to regulate the sequential of SDIO bus, makes the waveform of described transmission signals carry out time delay, has solved the slack-off problem of card reading speed that causes because of the transmission data.
Each embodiment adopts the mode of going forward one by one to describe in this instructions, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For the device that embodiment provides, because it is corresponding with the method that embodiment provides, so description is fairly simple, relevant part partly illustrates referring to method and gets final product.
Above-mentioned explanation to the embodiment that provided makes this area professional and technical personnel can realize or use the utility model.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined herein General Principle can realize under the situation that does not break away from spirit or scope of the present utility model in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but principle and the features of novelty the wideest corresponding to scope that is provided with this paper will be provided.
Claims (8)
1. a storage card power delivery circuit is characterized in that, comprising:
Be serially connected between SD card and the CPU, be used to regulate the waveform finishing circuit that satisfies preset threshold value of transmission signals between described SD card and the described CPU;
Link to each other with described waveform finishing circuit, be used to regulate the sequential of SDIO bus, make the waveform of described transmission signals carry out the time sequence adjusting circuit of time delay.
2. storage card power delivery circuit according to claim 1 is characterized in that, also comprises:
Link to each other with described waveform finishing circuit, be used to eliminate the electrostatic discharge protection circuit of the static of described transmission signals.
3. storage card power delivery circuit according to claim 1 is characterized in that described waveform finishing circuit comprises at least one regulating circuit,
Described regulating circuit comprises: first resistance, second resistance, pull-up resistor and operational amplifier,
The data input pin of described regulating circuit links to each other with the inverting input of described operational amplifier, first end of described first resistance links to each other respectively at first end of external voltage Vcc and described pull-up resistor, second end of described first resistance links to each other with the in-phase input end of described operational amplifier and first end of described second resistance respectively, the second end ground connection of described second resistance, the output terminal of described operational amplifier links to each other with second end of described pull-up resistor, and as the data output end of described regulating circuit.
4. storage card power delivery circuit according to claim 3 is characterized in that CLK line and data line all are serially connected with described regulating circuit.
5. storage card power delivery circuit according to claim 1 is characterized in that described time sequence adjusting circuit comprises: the 3rd resistance and first electric capacity,
Described the 3rd resistance string is connected between the inverting input of the data input pin of described regulating circuit and described operational amplifier, and described first capacitance series is between the inverting input and ground of described operational amplifier.
6. storage card power delivery circuit according to claim 2 is characterized in that described electrostatic discharge protection circuit comprises:
Be serially connected in the data output end of described regulating circuit and the voltage dependent resistor (VDR) between the CPU.
7. storage card power delivery circuit according to claim 2 is characterized in that described electrostatic discharge protection circuit comprises:
Be serially connected in the data output end and the pipe of the TVS between the CPU of described regulating circuit.
8. storage card power delivery circuit according to claim 2 is characterized in that described electrostatic discharge protection circuit comprises:
Be serially connected in the data output end and the pipe of the ESD between the CPU of described regulating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220741371 CN203102871U (en) | 2012-12-30 | 2012-12-30 | Power supply transmission circuit for storage card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220741371 CN203102871U (en) | 2012-12-30 | 2012-12-30 | Power supply transmission circuit for storage card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203102871U true CN203102871U (en) | 2013-07-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220741371 Expired - Lifetime CN203102871U (en) | 2012-12-30 | 2012-12-30 | Power supply transmission circuit for storage card |
Country Status (1)
| Country | Link |
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| CN (1) | CN203102871U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050144A (en) * | 2012-12-30 | 2013-04-17 | 深圳市凌启电子有限公司 | Power supply transmission circuit of memory card |
-
2012
- 2012-12-30 CN CN 201220741371 patent/CN203102871U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050144A (en) * | 2012-12-30 | 2013-04-17 | 深圳市凌启电子有限公司 | Power supply transmission circuit of memory card |
| CN103050144B (en) * | 2012-12-30 | 2016-05-25 | 深圳市凌启电子有限公司 | A kind of storage card power delivery circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130731 |
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| CX01 | Expiry of patent term |